According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.
"Bits N:0 of the limit register are
decoded by hardware as all 1s."
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials are licensed and made available under\r
the terms and conditions of the BSD License which accompanies this distribution.\r
\r
This program and the accompanying materials are licensed and made available under\r
the terms and conditions of the BSD License which accompanies this distribution.\r
\r
PEI Memory Layout:\r
\r
\r
PEI Memory Layout:\r
\r
- +------------------+ <=============== PHMR.Limit (Top of memory)\r
+ +------------------+ <=============== PHMR.Limit (+ alignment) (Top of memory)\r
| Mem Resource |\r
| |\r
\r
| Mem Resource |\r
| |\r
\r
DMA Buffer | * DMA FREE * |\r
| | -------------- |\r
V | Read/Write Buf |\r
DMA Buffer | * DMA FREE * |\r
| | -------------- |\r
V | Read/Write Buf |\r
- =========== +==================+ <=============== PLMR.Limit\r
+ =========== +==================+ <=============== PLMR.Limit (+ alignment)\r
| PEI allocated |\r
| -------------- | <------- EfiFreeMemoryTop\r
| * PEI FREE * |\r
| PEI allocated |\r
| -------------- | <------- EfiFreeMemoryTop\r
| * PEI FREE * |\r