IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit

According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.

"Bits N:0 of the limit register are
decoded by hardware as all 1s."

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index 7147a19f538a436b59dfef1452cb7ccc1ae52077..8f86d4cd15c0c128a0a7d7f56f037a27c1d8597a 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials are licensed and made available under\r
   the terms and conditions of the BSD License which accompanies this distribution.\r
@@ -60,7 +60,7 @@ typedef struct {
 \r
   PEI Memory Layout:\r
 \r
-              +------------------+ <=============== PHMR.Limit (Top of memory)\r
+              +------------------+ <=============== PHMR.Limit (+ alignment) (Top of memory)\r
               |   Mem Resource   |\r
               |                  |\r
 \r
@@ -72,7 +72,7 @@ typedef struct {
   DMA Buffer  |   * DMA FREE *   |\r
        |      |  --------------  |\r
        V      |  Read/Write Buf  |\r
-  =========== +==================+ <=============== PLMR.Limit\r
+  =========== +==================+ <=============== PLMR.Limit (+ alignment)\r
               |   PEI allocated  |\r
               |  --------------  | <------- EfiFreeMemoryTop\r
               |   * PEI FREE *   |\r