Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35"

This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index b3446ece311a1ede5d86e6ab875cb988eaf72d2d..578fc6c98ec8537b4ea018edf2127a1cbb833b55 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -490,7 +490,10 @@
   # This PCD is used to set the base address of the PCI express hierarchy. It\r
   # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
   # the PCIEXBAR register.\r
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
 \r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r

diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 679d4eb8dd363d95573b989af9edbe33a858303d..eade8f62d3de0e99939756a19ac6653354f8ce92 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -495,7 +495,10 @@
   # This PCD is used to set the base address of the PCI express hierarchy. It\r
   # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
   # the PCIEXBAR register.\r
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
 \r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r

diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 56a9560262aa1df5f7465884e7424fba11cb484b..733a4c9d8a431747d3eb29d16767fae4afbd121a 100644 (file)
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -495,7 +495,10 @@
   # This PCD is used to set the base address of the PCI express hierarchy. It\r
   # is only consulted when OVMF runs on Q35. In that case it is programmed into\r
   # the PCIEXBAR register.\r
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
+  #\r
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
+  # never lets the RAM below 4 GB exceed 2 GB.\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
 \r
 !ifdef $(SOURCE_DEBUG_ENABLE)\r
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index fd8eccaf3e50cc133cfc1acb3adb949afc324fa1..9c013613a1a0b35517bd5b7da039a5ede5c304b8 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -184,13 +184,14 @@ MemMapInitialization (
     PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
       //\r
-      // The 32-bit PCI host aperture is expected to fall between the top of\r
-      // low RAM and the base of the MMCONFIG area.\r
+      // The MMCONFIG area is expected to fall between the top of low RAM and\r
+      // the base of the 32-bit PCI host aperture.\r
       //\r
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
-      ASSERT (PciBase < PciExBarBase);\r
+      ASSERT (TopOfLowRam <= PciExBarBase);\r
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
-      PciSize = (UINT32)(PciExBarBase - PciBase);\r
+      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
+      PciSize = 0xFC000000 - PciBase;\r
     } else {\r
       PciSize = 0xFC000000 - PciBase;\r
     }\r