-
-/** @file
- Processor or Compiler specific defines and types for ARM.
-
- Copyright (c) 2006 - 2009, Intel Corporation
- Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-///
-/// Define the processor type so other code can make processor based choices
-///
-#define MDE_CPU_ARM
-
-//
-// Make sure we are useing the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
- //
- // use Microsoft* C complier dependent interger width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
-#else
- //
- // Assume standard ARM alignment.
- // Need to check portability of long long
- //
- typedef unsigned long long UINT64;
- typedef long long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
-#endif
-
+\r
+/** @file\r
+ Processor or Compiler specific defines and types for ARM.\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation \r
+ Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.\r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef __PROCESSOR_BIND_H__\r
+#define __PROCESSOR_BIND_H__\r
+\r
+///\r
+/// Define the processor type so other code can make processor based choices\r
+///\r
+#define MDE_CPU_ARM\r
+\r
+//\r
+// Make sure we are useing the correct packing rules per EFI specification\r
+//\r
+#ifndef __GNUC__\r
+#pragma pack()\r
+#endif\r
+\r
+#if _MSC_EXTENSIONS \r
+ //\r
+ // use Microsoft* C complier dependent interger width types \r
+ //\r
+ typedef unsigned __int64 UINT64;\r
+ typedef __int64 INT64;\r
+ typedef unsigned __int32 UINT32;\r
+ typedef __int32 INT32;\r
+ typedef unsigned short UINT16;\r
+ typedef unsigned short CHAR16;\r
+ typedef short INT16;\r
+ typedef unsigned char BOOLEAN;\r
+ typedef unsigned char UINT8;\r
+ typedef char CHAR8;\r
+ typedef char INT8;\r
+#else\r
+ //\r
+ // Assume standard ARM alignment. \r
+ // Need to check portability of long long\r
+ //\r
+ typedef unsigned long long UINT64;\r
+ typedef long long INT64;\r
+ typedef unsigned int UINT32;\r
+ typedef int INT32;\r
+ typedef unsigned short UINT16;\r
+ typedef unsigned short CHAR16;\r
+ typedef short INT16;\r
+ typedef unsigned char BOOLEAN;\r
+ typedef unsigned char UINT8;\r
+ typedef char CHAR8;\r
+ typedef char INT8;\r
+#endif\r
+\r
///\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef UINT32 UINTN;
-
+typedef UINT32 UINTN;\r
+\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef INT32 INTN;
-
-//
-// Processor specific defines
-//
+typedef INT32 INTN;\r
+\r
+//\r
+// Processor specific defines\r
+//\r
\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x80000000
-
+#define MAX_BIT 0x80000000\r
+\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
-#define MAX_2_BITS 0xC0000000
-
-///
-/// Maximum legal ARM address
-///
-#define MAX_ADDRESS 0xFFFFFFFF
-
-///
-/// The stack alignment required for ARM
-///
-#define CPU_STACK_ALIGNMENT sizeof(UINT64)
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify thier member functions with EFIAPI.
-//
-#define EFIAPI
-
-#if defined(__GNUC__)
- ///
- /// For GNU assembly code, .global or .globl can declare global symbols.
- /// Define this macro to unify the usage.
- ///
- #define ASM_GLOBAL .globl
-#endif
-
+#define MAX_2_BITS 0xC0000000\r
+\r
+///\r
+/// Maximum legal ARM address\r
+///\r
+#define MAX_ADDRESS 0xFFFFFFFF\r
+\r
+///\r
+/// The stack alignment required for ARM\r
+///\r
+#define CPU_STACK_ALIGNMENT sizeof(UINT64)\r
+\r
+//\r
+// Modifier to ensure that all protocol member functions and EFI intrinsics\r
+// use the correct C calling convention. All protocol member functions and\r
+// EFI intrinsics are required to modify thier member functions with EFIAPI.\r
+//\r
+#define EFIAPI \r
+\r
+#if defined(__GNUC__)\r
+ ///\r
+ /// For GNU assembly code, .global or .globl can declare global symbols.\r
+ /// Define this macro to unify the usage.\r
+ ///\r
+ #define ASM_GLOBAL .globl\r
+#endif\r
+\r
/**\r
Return the pointer to the first instruction of a function given a function pointer.\r
On ARM CPU architectures, these two pointer values are the same, \r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (FunctionPointer)
-
-#endif
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (FunctionPointer)\r
+\r
+#endif\r
functions, and CPU architecture-specific functions.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
-Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#endif // defined (MDE_CPU_EBC)\r
\r
-#if defined (MDE_CPU_ARM)
-
-typedef struct {
- UINT32 R3; ///< Copy of R13
- UINT32 R4;
- UINT32 R5;
- UINT32 R6;
- UINT32 R7;
- UINT32 R8;
- UINT32 R9;
- UINT32 R10;
- UINT32 R11;
- UINT32 R12;
- UINT32 R14;
-} BASE_LIBRARY_JUMP_BUFFER;
-
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
-
-#endif // defined (MDE_CPU_ARM)
-
+#if defined (MDE_CPU_ARM)\r
+\r
+typedef struct {\r
+ UINT32 R3; ///< Copy of R13\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 R14;\r
+} BASE_LIBRARY_JUMP_BUFFER;\r
+\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
+\r
+#endif // defined (MDE_CPU_ARM)\r
+\r
//\r
// String Services\r
//\r
and can be ported easily to any environment.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR> \r
-Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
/// otherwise, the entry remains to be 0.\r
///\r
PHYSICAL_ADDRESS HiiResourceData;\r
- ///
- /// Private storage for implementation specific data.
- ///
- UINT64 Context;
+ ///\r
+ /// Private storage for implementation specific data. \r
+ ///\r
+ UINT64 Context; \r
} PE_COFF_LOADER_IMAGE_CONTEXT;\r
\r
/**\r
processor and handle context save and restore operations.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation<BR> \r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
UINT64 Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
-
-
-///
-/// ARM processor exception types
-///
-#define EXCEPT_ARM_RESET 0
-#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
-#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
-#define EXCEPT_ARM_PREFETCH_ABORT 3
-#define EXCEPT_ARM_DATA_ABORT 4
-#define EXCEPT_ARM_RESERVED 5
-#define EXCEPT_ARM_IRQ 6
-#define EXCEPT_ARM_FIQ 7
-
-///
-/// For coding convenience, define the maximum valid ARM exception.
-///
-#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
-
-///
-/// ARM processor context definition
-///
-typedef struct {
- UINT32 R0;
- UINT32 R1;
- UINT32 R2;
- UINT32 R3;
- UINT32 R4;
- UINT32 R5;
- UINT32 R6;
- UINT32 R7;
- UINT32 R8;
- UINT32 R9;
- UINT32 R10;
- UINT32 R11;
- UINT32 R12;
- UINT32 SP;
- UINT32 LR;
- UINT32 PC;
- UINT32 CPSR;
- UINT32 DFSR;
- UINT32 DFAR;
- UINT32 IFSR;
- UINT32 IFAR;
-} EFI_SYSTEM_CONTEXT_ARM;
-
-///
-/// Universal EFI_SYSTEM_CONTEXT definition
-///
+\r
+\r
+///\r
+/// ARM processor exception types\r
+///\r
+#define EXCEPT_ARM_RESET 0\r
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
+#define EXCEPT_ARM_PREFETCH_ABORT 3\r
+#define EXCEPT_ARM_DATA_ABORT 4\r
+#define EXCEPT_ARM_RESERVED 5\r
+#define EXCEPT_ARM_IRQ 6\r
+#define EXCEPT_ARM_FIQ 7\r
+\r
+///\r
+/// For coding convenience, define the maximum valid ARM exception.\r
+///\r
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
+\r
+///\r
+/// ARM processor context definition\r
+///\r
+typedef struct {\r
+ UINT32 R0;\r
+ UINT32 R1;\r
+ UINT32 R2;\r
+ UINT32 R3;\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 SP;\r
+ UINT32 LR;\r
+ UINT32 PC;\r
+ UINT32 CPSR;\r
+ UINT32 DFSR;\r
+ UINT32 DFAR;\r
+ UINT32 IFSR;\r
+ UINT32 IFAR;\r
+} EFI_SYSTEM_CONTEXT_ARM;\r
+\r
+///\r
+/// Universal EFI_SYSTEM_CONTEXT definition\r
+///\r
typedef union {\r
EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
- IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
- IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED ///< 0x01c2
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED ///< 0x01c2\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
\r
Defines data types and constants introduced in UEFI.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
///\r
#define EFI_IMAGE_MACHINE_X64 0x8664\r
\r
-///
-/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images
-///
-#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
-
+///\r
+/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images\r
+///\r
+#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2\r
+\r
\r
#if defined (MDE_CPU_IA32)\r
\r
\r
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32) \r
\r
-#elif defined (MDE_CPU_ARM)
-
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
- (((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
-
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
-
+#elif defined (MDE_CPU_ARM)\r
+\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
+ (((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) || ((Machine) == EFI_IMAGE_MACHINE_EBC))\r
+\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) \r
+\r
#elif defined (MDE_CPU_EBC)\r
\r
///\r
by this include file.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"\r
\r
#if defined (MDE_CPU_IA32)\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32\r
#elif defined (MDE_CPU_X64)\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64\r
#elif defined (MDE_CPU_EBC)\r
-#elif defined (MDE_CPU_ARM)
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
+#elif defined (MDE_CPU_ARM)\r
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM\r
#else\r
#error Unknown Processor Type\r
#endif\r
# This library assumes there are no chipset dependencies required to maintain caches.\r
#\r
# Copyright (c) 2007 - 2008, Intel Corporation<BR>\r
-# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+# Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
[Sources.EBC]\r
EbcCache.c\r
\r
-[Sources.ARM]
- ArmCache.c
-
+[Sources.ARM]\r
+ ArmCache.c\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
-/** @file
- CpuFlushTlb function for Ia32/X64 GCC.
-
- Copyright (c) 2006 - 2008, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-
-/**
- Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
-
- Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
-
-**/
-VOID
-EFIAPI
-CpuFlushTlb (
- VOID
- )
-{
- __asm__ __volatile__ (
- "movl %%cr3, %0\n\t"
- "movl %0, %%cr3 "
- : "r" // %0
- );
-}
-
+/** @file\r
+ CpuFlushTlb function for Ia32/X64 GCC.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+/**\r
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuFlushTlb (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %%cr3, %0\n\t"\r
+ "movl %0, %%cr3 "\r
+ : "r" // %0\r
+ );\r
+}\r
+\r
-/** @file
- CpuSleep function for Ia32/X64 GCC.
-
- Copyright (c) 2006 - 2008, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-/**
- Places the CPU in a sleep state until an interrupt is received.
-
- Places the CPU in a sleep state until an interrupt is received. If interrupts
- are disabled prior to calling this function, then the CPU will be placed in a
- sleep state indefinitely.
-
-**/
-VOID
-EFIAPI
-CpuSleep (
- VOID
- )
-{
- __asm__ __volatile__ ("hlt"::: "memory");
-}
-
+/** @file\r
+ CpuSleep function for Ia32/X64 GCC.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+/**\r
+ Places the CPU in a sleep state until an interrupt is received.\r
+\r
+ Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+ are disabled prior to calling this function, then the CPU will be placed in a\r
+ sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("hlt"::: "memory");\r
+}\r
+\r
-/** @file
- I/O Library for ARM.
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-//
-// Include common header file for this module.
-//
-#include "BaseIoLibIntrinsicInternal.h"
-
-/**
- Reads an 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-IoRead8 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes an 8-bit I/O port.
-
- Writes the 8-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-IoRead16 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 16-bit I/O port.
-
- Writes the 16-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-IoRead32 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 32-bit I/O port.
-
- Writes the 32-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-IoRead64 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 64-bit I/O port.
-
- Writes the 64-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-MmioRead8 (
- IN UINTN Address
- )
-{
- UINT8 Value;
-
- Value = *(volatile UINT8*)Address;
- return Value;
-}
-
-/**
- Writes an 8-bit MMIO register.
-
- Writes the 8-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- *(volatile UINT8*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-MmioRead16 (
- IN UINTN Address
- )
-{
- UINT16 Value;
-
- ASSERT ((Address & 1) == 0);
- Value = *(volatile UINT16*)Address;
- return Value;
-}
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- ASSERT ((Address & 1) == 0);
- *(volatile UINT16*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-MmioRead32 (
- IN UINTN Address
- )
-{
- UINT32 Value;
-
- ASSERT ((Address & 3) == 0);
- Value = *(volatile UINT32*)Address;
- return Value;
-}
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- ASSERT ((Address & 3) == 0);
- *(volatile UINT32*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-MmioRead64 (
- IN UINTN Address
- )
-{
- UINT64 Value;
-
- ASSERT ((Address & 7) == 0);
- Value = *(volatile UINT64*)Address;
- return Value;
-}
-
-/**
- Writes a 64-bit MMIO register.
-
- Writes the 64-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
- )
-{
- ASSERT ((Address & 7) == 0);
- *(volatile UINT64*)Address = Value;
- return Value;
-}
-
+/** @file\r
+ I/O Library for ARM. \r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "BaseIoLibIntrinsicInternal.h"\r
+\r
+/**\r
+ Reads an 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit I/O port.\r
+\r
+ Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit I/O port.\r
+\r
+ Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit I/O port.\r
+\r
+ Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If Port is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoRead64 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit I/O port.\r
+\r
+ Writes the 64-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If Port is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWrite64 (\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ Reads an 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT8 Value;\r
+\r
+ Value = *(volatile UINT8*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit MMIO register.\r
+\r
+ Writes the 8-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ *(volatile UINT8*)Address = Value;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT16 Value;\r
+\r
+ ASSERT ((Address & 1) == 0);\r
+ Value = *(volatile UINT16*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit MMIO register.\r
+\r
+ Writes the 16-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ *(volatile UINT16*)Address = Value;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ ASSERT ((Address & 3) == 0);\r
+ Value = *(volatile UINT32*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit MMIO register.\r
+\r
+ Writes the 32-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ *(volatile UINT32*)Address = Value;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT64 Value;\r
+\r
+ ASSERT ((Address & 7) == 0);\r
+ Value = *(volatile UINT64*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit MMIO register.\r
+\r
+ Writes the 64-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ *(volatile UINT64*)Address = Value;\r
+ return Value;\r
+}\r
+\r
-#------------------------------------------------------------------------------
-#
-# CpuBreakpoint() for ARM
-#
-# Copyright (c) 2006 - 2009, Intel Corporation<BR>
-# Portions copyright (c) 2008-2009 Apple Inc.<BR>
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-.globl ASM_PFX(CpuBreakpoint)
-
-#/**
-# Generates a breakpoint on the CPU.
-#
-# Generates a breakpoint on the CPU. The breakpoint must be implemented such
-# that code can resume normal execution after the breakpoint.
-#
-#**/
-#VOID
-#EFIAPI
-#CpuBreakpoint (
-# VOID
-# );
-#
-ASM_PFX(CpuBreakpoint):
- swi 0xdbdbdb
- bx lr
+#------------------------------------------------------------------------------ \r
+#\r
+# CpuBreakpoint() for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.align 2\r
+.globl ASM_PFX(CpuBreakpoint)\r
+\r
+#/**\r
+# Generates a breakpoint on the CPU.\r
+#\r
+# Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+# that code can resume normal execution after the breakpoint.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#CpuBreakpoint (\r
+# VOID\r
+# );\r
+#\r
+ASM_PFX(CpuBreakpoint):\r
+ swi 0xdbdbdb \r
+ bx lr\r
-;------------------------------------------------------------------------------
-;
-; CpuBreakpoint() for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT CpuBreakpoint
-
- AREA Cpu_Breakpoint, CODE, READONLY
-
-;/**
-; Generates a breakpoint on the CPU.
-;
-; Generates a breakpoint on the CPU. The breakpoint must be implemented such
-; that code can resume normal execution after the breakpoint.
-;
-;**/
-;VOID
-;EFIAPI
-;CpuBreakpoint (
-; VOID
-; );
-;
-CpuBreakpoint
- swi 0xdbdbdb
- bx lr
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; CpuBreakpoint() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT CpuBreakpoint\r
+\r
+ AREA Cpu_Breakpoint, CODE, READONLY\r
+\r
+;/**\r
+; Generates a breakpoint on the CPU.\r
+;\r
+; Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+; that code can resume normal execution after the breakpoint.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuBreakpoint (\r
+; VOID\r
+; );\r
+;\r
+CpuBreakpoint\r
+ swi 0xdbdbdb\r
+ bx lr\r
+ \r
+ END\r
-;------------------------------------------------------------------------------
-;
-; CpuPause() for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT CpuPause
- AREA cpu_pause, CODE, READONLY
-
-;/**
-; Requests CPU to pause for a short period of time.
-;
-; Requests CPU to pause for a short period of time. Typically used in MP
-; systems to prevent memory starvation while waiting for a spin lock.
-;
-;**/
-;VOID
-;EFIAPI
-;CpuPause (
-; VOID
-; );
-;
-CpuPause
- NOP
- NOP
- NOP
- NOP
- NOP
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; CpuPause() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT CpuPause\r
+ AREA cpu_pause, CODE, READONLY\r
+\r
+;/**\r
+; Requests CPU to pause for a short period of time.\r
+;\r
+; Requests CPU to pause for a short period of time. Typically used in MP\r
+; systems to prevent memory starvation while waiting for a spin lock.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;CpuPause (\r
+; VOID\r
+; );\r
+;\r
+CpuPause\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ NOP\r
+ BX LR\r
+\r
+ END\r
-#------------------------------------------------------------------------------
-#
-# DisableInterrupts() for ARM
-#
-# Copyright (c) 2006 - 2009, Intel Corporation<BR>
-# Portions copyright (c) 2008-2009 Apple Inc.<BR>
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.p2align 2
-.globl ASM_PFX(DisableInterrupts)
-
-#/**
-# Disables CPU interrupts.
-#
-#**/
-#VOID
-#EFIAPI
-#DisableInterrupts (
-# VOID
-# );
-#
-ASM_PFX(DisableInterrupts):
- mrs R0,CPSR
- orr R0,R0,#0x80 @Disable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+#------------------------------------------------------------------------------ \r
+#\r
+# DisableInterrupts() for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+.globl ASM_PFX(DisableInterrupts)\r
+\r
+#/**\r
+# Disables CPU interrupts.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#DisableInterrupts (\r
+# VOID\r
+# );\r
+#\r
+ASM_PFX(DisableInterrupts):\r
+ mrs R0,CPSR\r
+ orr R0,R0,#0x80 @Disable IRQ interrupts\r
+ msr CPSR_c,R0\r
+ bx LR\r
-;------------------------------------------------------------------------------
-;
-; DisableInterrupts() for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT DisableInterrupts
-
- AREA Interrupt_disable, CODE, READONLY
-
-;/**
-; Disables CPU interrupts.
-;
-;**/
-;VOID
-;EFIAPI
-;DisableInterrupts (
-; VOID
-; );
-;
-DisableInterrupts
- MRS R0,CPSR
- ORR R0,R0,#0x80 ;Disable IRQ interrupts
- MSR CPSR_c,R0
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; DisableInterrupts() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT DisableInterrupts\r
+\r
+ AREA Interrupt_disable, CODE, READONLY\r
+\r
+;/**\r
+; Disables CPU interrupts.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;DisableInterrupts (\r
+; VOID\r
+; );\r
+;\r
+DisableInterrupts\r
+ MRS R0,CPSR\r
+ ORR R0,R0,#0x80 ;Disable IRQ interrupts\r
+ MSR CPSR_c,R0\r
+ BX LR\r
+ \r
+ END\r
-#------------------------------------------------------------------------------
-#
-# EnableInterrupts() for ARM
-#
-# Copyright (c) 2006 - 2009, Intel Corporation<BR>
-# Portions copyright (c) 2008-2009 Apple Inc.<BR>
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.p2align 2
-.globl ASM_PFX(EnableInterrupts)
-
-
-#/**
-# Enables CPU interrupts.
-#
-#**/
-#VOID
-#EFIAPI
-#EnableInterrupts (
-# VOID
-# );
-#
-ASM_PFX(EnableInterrupts):
- mrs R0,CPSR
- bic R0,R0,#0x80 @Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
+#------------------------------------------------------------------------------ \r
+#\r
+# EnableInterrupts() for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+.globl ASM_PFX(EnableInterrupts)\r
+\r
+\r
+#/**\r
+# Enables CPU interrupts.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#EnableInterrupts (\r
+# VOID\r
+# );\r
+#\r
+ASM_PFX(EnableInterrupts):\r
+ mrs R0,CPSR\r
+ bic R0,R0,#0x80 @Enable IRQ interrupts\r
+ msr CPSR_c,R0\r
+ bx LR\r
-;------------------------------------------------------------------------------
-;
-; EnableInterrupts() for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT EnableInterrupts
-
- AREA Interrupt_enable, CODE, READONLY
-
-;/**
-; Enables CPU interrupts.
-;
-;**/
-;VOID
-;EFIAPI
-;EnableInterrupts (
-; VOID
-; );
-;
-EnableInterrupts
- MRS R0,CPSR
- BIC R0,R0,#0x80 ;Enable IRQ interrupts
- MSR CPSR_c,R0
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; EnableInterrupts() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT EnableInterrupts\r
+\r
+ AREA Interrupt_enable, CODE, READONLY\r
+\r
+;/**\r
+; Enables CPU interrupts.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;EnableInterrupts (\r
+; VOID\r
+; );\r
+;\r
+EnableInterrupts\r
+ MRS R0,CPSR\r
+ BIC R0,R0,#0x80 ;Enable IRQ interrupts\r
+ MSR CPSR_c,R0\r
+ BX LR\r
+ \r
+ END\r
-/** @file
- GCC inline implementation of BaseLib processor specific functions.
-
- Copyright (c) 2006 - 2007, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseLibInternals.h"
-
-/**
- Requests CPU to pause for a short period of time.
-
- Requests CPU to pause for a short period of time. Typically used in MP
- systems to prevent memory starvation while waiting for a spin lock.
-
-**/
-VOID
-EFIAPI
-CpuPause (
- VOID
- )
-{
- __asm__ __volatile__ (
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- );
-}
-
-VOID
-EFIAPI
-InternalSwitchStackAsm (
- SWITCH_STACK_ENTRY_POINT EntryPoint,
- VOID *Context,
- VOID *Context2,
- VOID *NewStack
- )
-{
- __asm__ __volatile__ (
- "mov lr, %0\n\t"
- "mov sp, %3\n\t"
- "mov %r0, %1\n\t"
- "mov %r1, %2\n\t"
- "bx lr\n\t"
- : /* no output operand */
- : "r" (EntryPoint),
- "r" (Context),
- "r" (Context2),
- "r" (NewStack)
- );
-}
+/** @file\r
+ GCC inline implementation of BaseLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "nop\n\t"\r
+ "nop\n\t"\r
+ "nop\n\t"\r
+ "nop\n\t"\r
+ "nop\n\t"\r
+ );\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+InternalSwitchStackAsm (\r
+ SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ VOID *Context,\r
+ VOID *Context2,\r
+ VOID *NewStack\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov lr, %0\n\t"\r
+ "mov sp, %3\n\t"\r
+ "mov %r0, %1\n\t"\r
+ "mov %r1, %2\n\t"\r
+ "bx lr\n\t"\r
+ : /* no output operand */\r
+ : "r" (EntryPoint),\r
+ "r" (Context),\r
+ "r" (Context2),\r
+ "r" (NewStack)\r
+ );\r
+}\r
-#------------------------------------------------------------------------------
-#
-# GetInterruptState() function for ARM
-#
-# Copyright (c) 2006 - 2009, Intel Corporation<BR>
-# Portions copyright (c) 2008-2009 Apple Inc.<BR>
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.p2align 2
-.globl _GetInterruptState
-
-#/**
-# Retrieves the current CPU interrupt state.
-#
-# Returns TRUE is interrupts are currently enabled. Otherwise
-# returns FALSE.
-#
-# @retval TRUE CPU interrupts are enabled.
-# @retval FALSE CPU interrupts are disabled.
-#
-#**/
-#
-#BOOLEAN
-#EFIAPI
-#GetInterruptState (
-# VOID
-# );
-#
-_GetInterruptState:
- mrs R0, CPSR
- tst R0, #0x80 @Check if IRQ is enabled.
- moveq R0, #1
- movne R0, #0
- bx LR
+#------------------------------------------------------------------------------ \r
+#\r
+# GetInterruptState() function for ARM\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.text\r
+.p2align 2\r
+.globl _GetInterruptState\r
+\r
+#/**\r
+# Retrieves the current CPU interrupt state.\r
+#\r
+# Returns TRUE is interrupts are currently enabled. Otherwise\r
+# returns FALSE.\r
+#\r
+# @retval TRUE CPU interrupts are enabled.\r
+# @retval FALSE CPU interrupts are disabled.\r
+#\r
+#**/\r
+#\r
+#BOOLEAN\r
+#EFIAPI\r
+#GetInterruptState (\r
+# VOID\r
+# );\r
+#\r
+_GetInterruptState:\r
+ mrs R0, CPSR\r
+ tst R0, #0x80 @Check if IRQ is enabled.\r
+ moveq R0, #1\r
+ movne R0, #0\r
+ bx LR\r
-;------------------------------------------------------------------------------
-;
-; GetInterruptState() function for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT GetInterruptState
-
- AREA Interrupt_enable, CODE, READONLY
-
-;/**
-; Retrieves the current CPU interrupt state.
-;
-; Returns TRUE is interrupts are currently enabled. Otherwise
-; returns FALSE.
-;
-; @retval TRUE CPU interrupts are enabled.
-; @retval FALSE CPU interrupts are disabled.
-;
-;**/
-;
-;BOOLEAN
-;EFIAPI
-;GetInterruptState (
-; VOID
-; );
-;
-GetInterruptState
- MRS R0, CPSR
- TST R0, #0x80 ;Check if IRQ is enabled.
- MOVEQ R0, #1
- MOVNE R0, #0
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; GetInterruptState() function for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT GetInterruptState\r
+\r
+ AREA Interrupt_enable, CODE, READONLY\r
+\r
+;/**\r
+; Retrieves the current CPU interrupt state.\r
+;\r
+; Returns TRUE is interrupts are currently enabled. Otherwise\r
+; returns FALSE.\r
+;\r
+; @retval TRUE CPU interrupts are enabled.\r
+; @retval FALSE CPU interrupts are disabled.\r
+;\r
+;**/\r
+;\r
+;BOOLEAN\r
+;EFIAPI\r
+;GetInterruptState (\r
+; VOID\r
+; );\r
+;\r
+GetInterruptState\r
+ MRS R0, CPSR\r
+ TST R0, #0x80 ;Check if IRQ is enabled.\r
+ MOVEQ R0, #1\r
+ MOVNE R0, #0\r
+ BX LR\r
+ \r
+ END\r
-/** @file
- SwitchStack() function for ARM.
-
- Copyright (c) 2006 - 2007, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseLibInternals.h"
-
-/**
- Transfers control to a function starting with a new stack.
-
- Transfers control to the function specified by EntryPoint using the
- new stack specified by NewStack and passing in the parameters specified
- by Context1 and Context2. Context1 and Context2 are optional and may
- be NULL. The function EntryPoint must never return.
- Marker will be ignored on IA-32, x64, and EBC.
- IPF CPUs expect one additional parameter of type VOID * that specifies
- the new backing store pointer.
-
- If EntryPoint is NULL, then ASSERT().
- If NewStack is NULL, then ASSERT().
-
- @param EntryPoint A pointer to function to call with the new stack.
- @param Context1 A pointer to the context to pass into the EntryPoint
- function.
- @param Context2 A pointer to the context to pass into the EntryPoint
- function.
- @param NewStack A pointer to the new stack to use for the EntryPoint
- function.
- @param Marker VA_LIST marker for the variable argument list.
-
-**/
-VOID
-EFIAPI
-InternalSwitchStack (
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
- IN VOID *NewStack,
- IN VA_LIST Marker
- )
-
-{
- //
- // Stack should be aligned with CPU_STACK_ALIGNMENT
- //
- ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
-
- InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);
-}
+/** @file\r
+ SwitchStack() function for ARM.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the\r
+ new stack specified by NewStack and passing in the parameters specified\r
+ by Context1 and Context2. Context1 and Context2 are optional and may\r
+ be NULL. The function EntryPoint must never return.\r
+ Marker will be ignored on IA-32, x64, and EBC.\r
+ IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ the new backing store pointer.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param Marker VA_LIST marker for the variable argument list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalSwitchStack (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ IN VA_LIST Marker\r
+ )\r
+\r
+{\r
+ //\r
+ // Stack should be aligned with CPU_STACK_ALIGNMENT\r
+ //\r
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+\r
+ InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);\r
+}\r
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2006 - 2009, Intel Corporation<BR>
-# Portions copyright (c) 2008-2009 Apple Inc.<BR>
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-.text
-.p2align 2
-
-.globl ASM_PFX(SetJump)
-.globl ASM_PFX(InternalLongJump)
-
-#/**
-# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
-#
-# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
-# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
-# value to be returned by SetJump().
-#
-# If JumpBuffer is NULL, then ASSERT().
-# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
-#
-# @param JumpBuffer A pointer to CPU context buffer.
-#
-#**/
-#
-#UINTN
-#EFIAPI
-#SetJump (
-# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
-# );
-#
-ASM_PFX(SetJump):
- mov r3, r13
- stmia r0, {r3-r12,r14}
- eor r0, r0, r0
- bx lr
-
-#/**
-# Restores the CPU context that was saved with SetJump().#
-#
-# Restores the CPU context from the buffer specified by JumpBuffer.
-# This function never returns to the caller.
-# Instead is resumes execution based on the state of JumpBuffer.
-#
-# @param JumpBuffer A pointer to CPU context buffer.
-# @param Value The value to return when the SetJump() context is restored.
-#
-#**/
-#VOID
-#EFIAPI
-#InternalLongJump (
-# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
-# IN UINTN Value // R1
-# );
-#
-ASM_PFX(InternalLongJump):
- ldmia r0, {r3-r12,r14}
- mov r13, r3
- mov r0, r1
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED()
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+# Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+.text\r
+.p2align 2\r
+\r
+.globl ASM_PFX(SetJump)\r
+.globl ASM_PFX(InternalLongJump)\r
+\r
+#/**\r
+# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#\r
+#\r
+# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial\r
+# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero\r
+# value to be returned by SetJump().\r
+#\r
+# If JumpBuffer is NULL, then ASSERT().\r
+# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+#\r
+# @param JumpBuffer A pointer to CPU context buffer.\r
+#\r
+#**/\r
+#\r
+#UINTN\r
+#EFIAPI\r
+#SetJump (\r
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0\r
+# );\r
+#\r
+ASM_PFX(SetJump):\r
+ mov r3, r13\r
+ stmia r0, {r3-r12,r14}\r
+ eor r0, r0, r0\r
+ bx lr\r
+\r
+#/**\r
+# Restores the CPU context that was saved with SetJump().#\r
+#\r
+# Restores the CPU context from the buffer specified by JumpBuffer.\r
+# This function never returns to the caller.\r
+# Instead is resumes execution based on the state of JumpBuffer.\r
+#\r
+# @param JumpBuffer A pointer to CPU context buffer.\r
+# @param Value The value to return when the SetJump() context is restored.\r
+#\r
+#**/\r
+#VOID\r
+#EFIAPI\r
+#InternalLongJump (\r
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0\r
+# IN UINTN Value // R1\r
+# );\r
+#\r
+ASM_PFX(InternalLongJump):\r
+ ldmia r0, {r3-r12,r14}\r
+ mov r13, r3\r
+ mov r0, r1\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED()\r
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT SetJump
- EXPORT InternalLongJump
-
- AREA BaseLib, CODE, READONLY
-
-;/**
-; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;
-;
-; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
-; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
-; value to be returned by SetJump().
-;
-; If JumpBuffer is NULL, then ASSERT().
-; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
-;
-; @param JumpBuffer A pointer to CPU context buffer.
-;
-;**/
-;
-;UINTN
-;EFIAPI
-;SetJump (
-; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
-; )
-;
-SetJump
- MOV R3, R13
- STM R0, {R3-R12,R14}
- EOR R0, R0
- BX LR
-
-;/**
-; Restores the CPU context that was saved with SetJump().;
-;
-; Restores the CPU context from the buffer specified by JumpBuffer.
-; This function never returns to the caller.
-; Instead is resumes execution based on the state of JumpBuffer.
-;
-; @param JumpBuffer A pointer to CPU context buffer.
-; @param Value The value to return when the SetJump() context is restored.
-;
-;**/
-;VOID
-;EFIAPI
-;InternalLongJump (
-; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
-; IN UINTN Value // R1
-; );
-;
-InternalLongJump
- LDM R0, {R3-R12,R14}
- MOV R13, R3
- MOV R0, R1
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT SetJump\r
+ EXPORT InternalLongJump\r
+\r
+ AREA BaseLib, CODE, READONLY\r
+\r
+;/**\r
+; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;\r
+;\r
+; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial\r
+; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero\r
+; value to be returned by SetJump().\r
+;\r
+; If JumpBuffer is NULL, then ASSERT().\r
+; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+;\r
+; @param JumpBuffer A pointer to CPU context buffer.\r
+;\r
+;**/\r
+;\r
+;UINTN\r
+;EFIAPI\r
+;SetJump (\r
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0\r
+; )\r
+;\r
+SetJump\r
+ MOV R3, R13\r
+ STM R0, {R3-R12,R14}\r
+ EOR R0, R0\r
+ BX LR\r
+\r
+;/**\r
+; Restores the CPU context that was saved with SetJump().;\r
+;\r
+; Restores the CPU context from the buffer specified by JumpBuffer.\r
+; This function never returns to the caller.\r
+; Instead is resumes execution based on the state of JumpBuffer.\r
+;\r
+; @param JumpBuffer A pointer to CPU context buffer.\r
+; @param Value The value to return when the SetJump() context is restored.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;InternalLongJump (\r
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0\r
+; IN UINTN Value // R1\r
+; );\r
+;\r
+InternalLongJump\r
+ LDM R0, {R3-R12,R14}\r
+ MOV R13, R3\r
+ MOV R0, R1\r
+ BX LR\r
+\r
+ END\r
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT InternalSwitchStackAsm
-
- AREA Switch_Stack, CODE, READONLY
-
-;/**
-; This allows the caller to switch the stack and goes to the new entry point
-;
-; @param EntryPoint Pointer to the location to enter
-; @param Context Parameter to pass in
-; @param Context2 Parameter2 to pass in
-; @param NewStack New Location of the stack
-;
-; @return Nothing. Goes to the Entry Point passing in the new parameters
-;
-;**/
-;VOID
-;EFIAPI
-;InternalSwitchStackAsm (
-; SWITCH_STACK_ENTRY_POINT EntryPoint,
-; VOID *Context,
-; VOID *Context2,
-; VOID *NewStack
-; );
-;
-InternalSwitchStackAsm
- MOV LR, R0
- MOV SP, R3
- MOV R0, R1
- MOV R1, R2
- BX LR
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+ \r
+ EXPORT InternalSwitchStackAsm\r
+ \r
+ AREA Switch_Stack, CODE, READONLY\r
+ \r
+;/**\r
+; This allows the caller to switch the stack and goes to the new entry point\r
+;\r
+; @param EntryPoint Pointer to the location to enter\r
+; @param Context Parameter to pass in\r
+; @param Context2 Parameter2 to pass in\r
+; @param NewStack New Location of the stack\r
+;\r
+; @return Nothing. Goes to the Entry Point passing in the new parameters\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;InternalSwitchStackAsm (\r
+; SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+; VOID *Context,\r
+; VOID *Context2,\r
+; VOID *NewStack\r
+; );\r
+;\r
+InternalSwitchStackAsm\r
+ MOV LR, R0\r
+ MOV SP, R3\r
+ MOV R0, R1\r
+ MOV R1, R2\r
+ BX LR\r
+ END\r
-/** @file
- Unaligned access functions of BaseLib for ARM.
-
- volatile was added to work around optimization issues.
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseLibInternals.h"
-
-/**
- Reads a 16-bit value from memory that may be unaligned.
-
- This function returns the 16-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 16-bit value that may be unaligned.
-
- @return The 16-bit value read from Buffer.
-
-**/
-UINT16
-EFIAPI
-ReadUnaligned16 (
- IN CONST UINT16 *Buffer
- )
-{
- volatile UINT8 LowerByte;
- volatile UINT8 HigherByte;
-
- ASSERT (Buffer != NULL);
-
- LowerByte = ((UINT8*)Buffer)[0];
- HigherByte = ((UINT8*)Buffer)[1];
-
- return (UINT16)(LowerByte | (HigherByte << 8));
-}
-
-/**
- Writes a 16-bit value to memory that may be unaligned.
-
- This function writes the 16-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 16-bit value that may be unaligned.
- @param Value 16-bit value to write to Buffer.
-
- @return The 16-bit value to write to Buffer.
-
-**/
-UINT16
-EFIAPI
-WriteUnaligned16 (
- OUT UINT16 *Buffer,
- IN UINT16 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- ((volatile UINT8*)Buffer)[0] = (UINT8)Value;
- ((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
-
- return Value;
-}
-
-/**
- Reads a 24-bit value from memory that may be unaligned.
-
- This function returns the 24-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 24-bit value that may be unaligned.
-
- @return The 24-bit value read from Buffer.
-
-**/
-UINT32
-EFIAPI
-ReadUnaligned24 (
- IN CONST UINT32 *Buffer
- )
-{
- ASSERT (Buffer != NULL);
-
- return (UINT32)(
- ReadUnaligned16 ((UINT16*)Buffer) |
- (((UINT8*)Buffer)[2] << 16)
- );
-}
-
-/**
- Writes a 24-bit value to memory that may be unaligned.
-
- This function writes the 24-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 24-bit value that may be unaligned.
- @param Value 24-bit value to write to Buffer.
-
- @return The 24-bit value to write to Buffer.
-
-**/
-UINT32
-EFIAPI
-WriteUnaligned24 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
- *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
- return Value;
-}
-
-/**
- Reads a 32-bit value from memory that may be unaligned.
-
- This function returns the 32-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 32-bit value that may be unaligned.
-
- @return The 32-bit value read from Buffer.
-
-**/
-UINT32
-EFIAPI
-ReadUnaligned32 (
- IN CONST UINT32 *Buffer
- )
-{
- UINT16 LowerBytes;
- UINT16 HigherBytes;
-
- ASSERT (Buffer != NULL);
-
- LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
- HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
-
- return (UINT32) (LowerBytes | (HigherBytes << 16));
-}
-
-/**
- Writes a 32-bit value to memory that may be unaligned.
-
- This function writes the 32-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 32-bit value that may be unaligned.
- @param Value 32-bit value to write to Buffer.
-
- @return The 32-bit value to write to Buffer.
-
-**/
-UINT32
-EFIAPI
-WriteUnaligned32 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
- WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
- return Value;
-}
-
-/**
- Reads a 64-bit value from memory that may be unaligned.
-
- This function returns the 64-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 64-bit value that may be unaligned.
-
- @return The 64-bit value read from Buffer.
-
-**/
-UINT64
-EFIAPI
-ReadUnaligned64 (
- IN CONST UINT64 *Buffer
- )
-{
- UINT32 LowerBytes;
- UINT32 HigherBytes;
-
- ASSERT (Buffer != NULL);
-
- LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
- HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
-
- return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
-}
-
-/**
- Writes a 64-bit value to memory that may be unaligned.
-
- This function writes the 64-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer Pointer to a 64-bit value that may be unaligned.
- @param Value 64-bit value to write to Buffer.
-
- @return The 64-bit value to write to Buffer.
-
-**/
-UINT64
-EFIAPI
-WriteUnaligned64 (
- OUT UINT64 *Buffer,
- IN UINT64 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
- WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
- return Value;
-}
+/** @file\r
+ Unaligned access functions of BaseLib for ARM.\r
+ \r
+ volatile was added to work around optimization issues.\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Reads a 16-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 16-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 16-bit value that may be unaligned.\r
+\r
+ @return The 16-bit value read from Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+ReadUnaligned16 (\r
+ IN CONST UINT16 *Buffer\r
+ )\r
+{\r
+ volatile UINT8 LowerByte;\r
+ volatile UINT8 HigherByte;\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ LowerByte = ((UINT8*)Buffer)[0];\r
+ HigherByte = ((UINT8*)Buffer)[1];\r
+\r
+ return (UINT16)(LowerByte | (HigherByte << 8));\r
+}\r
+\r
+/**\r
+ Writes a 16-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 16-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 16-bit value that may be unaligned.\r
+ @param Value 16-bit value to write to Buffer.\r
+\r
+ @return The 16-bit value to write to Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+WriteUnaligned16 (\r
+ OUT UINT16 *Buffer,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ ((volatile UINT8*)Buffer)[0] = (UINT8)Value;\r
+ ((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);\r
+\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 24-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 24-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 24-bit value that may be unaligned.\r
+\r
+ @return The 24-bit value read from Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned24 (\r
+ IN CONST UINT32 *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return (UINT32)(\r
+ ReadUnaligned16 ((UINT16*)Buffer) |\r
+ (((UINT8*)Buffer)[2] << 16)\r
+ );\r
+}\r
+\r
+/**\r
+ Writes a 24-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 24-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 24-bit value that may be unaligned.\r
+ @param Value 24-bit value to write to Buffer.\r
+\r
+ @return The 24-bit value to write to Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned24 (\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
+ *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 32-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 32-bit value that may be unaligned.\r
+\r
+ @return The 32-bit value read from Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned32 (\r
+ IN CONST UINT32 *Buffer\r
+ )\r
+{\r
+ UINT16 LowerBytes;\r
+ UINT16 HigherBytes;\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);\r
+ HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);\r
+\r
+ return (UINT32) (LowerBytes | (HigherBytes << 16));\r
+}\r
+\r
+/**\r
+ Writes a 32-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 32-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 32-bit value that may be unaligned.\r
+ @param Value 32-bit value to write to Buffer.\r
+\r
+ @return The 32-bit value to write to Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned32 (\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
+ WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 64-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 64-bit value that may be unaligned.\r
+\r
+ @return The 64-bit value read from Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+ReadUnaligned64 (\r
+ IN CONST UINT64 *Buffer\r
+ )\r
+{\r
+ UINT32 LowerBytes;\r
+ UINT32 HigherBytes;\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);\r
+ HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);\r
+\r
+ return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));\r
+}\r
+\r
+/**\r
+ Writes a 64-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 64-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer Pointer to a 64-bit value that may be unaligned.\r
+ @param Value 64-bit value to write to Buffer.\r
+\r
+ @return The 64-bit value to write to Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+WriteUnaligned64 (\r
+ OUT UINT64 *Buffer,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);\r
+ WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));\r
+ return Value;\r
+}\r
-/** @file
- GCC inline implementation of BaseLib processor specific functions.
-
- Copyright (c) 2006 - 2007, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseLibInternals.h"
-
-
-
-/**
- Used to serialize load and store operations.
-
- All loads and stores that proceed calls to this function are guaranteed to be
- globally visible when this function returns.
-
-**/
-VOID
-EFIAPI
-MemoryFence (
- VOID
- )
-{
- // This is a little bit of overkill and it is more about the compiler that it is
- // actually processor syncronization. This is like the _ReadWriteBarrier
- // Microsft specific intrinsic
- __asm__ __volatile__ ("":::"memory");
-}
-
-
-/**
- Enables CPU interrupts.
-
- Enables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-EnableInterrupts (
- VOID
- )
-{
- __asm__ __volatile__ ("sti"::: "memory");
-}
-
-
-/**
- Disables CPU interrupts.
-
- Disables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-DisableInterrupts (
- VOID
- )
-{
- __asm__ __volatile__ ("cli"::: "memory");
-}
-
-
-
-
-/**
- Requests CPU to pause for a short period of time.
-
- Requests CPU to pause for a short period of time. Typically used in MP
- systems to prevent memory starvation while waiting for a spin lock.
-
-**/
-VOID
-EFIAPI
-CpuPause (
- VOID
- )
-{
- __asm__ __volatile__ ("pause");
-}
-
-
-/**
- Generates a breakpoint on the CPU.
-
- Generates a breakpoint on the CPU. The breakpoint must be implemented such
- that code can resume normal execution after the breakpoint.
-
-**/
-VOID
-EFIAPI
-CpuBreakpoint (
- VOID
- )
-{
- __asm__ __volatile__ ("int $3");
-}
-
-
-
-/**
- Returns a 64-bit Machine Specific Register(MSR).
-
- Reads and returns the 64-bit MSR specified by Index. No parameter checking is
- performed on Index, and some Index values may cause CPU exceptions. The
- caller must either guarantee that Index is valid, or the caller must set up
- exception handlers to catch the exceptions. This function is only available
- on IA-32 and X64.
-
- @param Index The 32-bit MSR index to read.
-
- @return The value of the MSR identified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadMsr64 (
- IN UINT32 Index
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "rdmsr"
- : "=A" (Data) // %0
- : "c" (Index) // %1
- );
-
- return Data;
-}
-
-/**
- Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
- value.
-
- Writes the 64-bit value specified by Value to the MSR specified by Index. The
- 64-bit value written to the MSR is returned. No parameter checking is
- performed on Index or Value, and some of these may cause CPU exceptions. The
- caller must either guarantee that Index and Value are valid, or the caller
- must establish proper exception handlers. This function is only available on
- IA-32 and X64.
-
- @param Index The 32-bit MSR index to write.
- @param Value The 64-bit value to write to the MSR.
-
- @return Value
-
-**/
-UINT64
-EFIAPI
-AsmWriteMsr64 (
- IN UINT32 Index,
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "wrmsr"
- :
- : "c" (Index),
- "A" (Value)
- );
-
- return Value;
-}
-
-
-
-/**
- Reads the current value of the EFLAGS register.
-
- Reads and returns the current value of the EFLAGS register. This function is
- only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
- 64-bit value on X64.
-
- @return EFLAGS on IA-32 or RFLAGS on X64.
-
-**/
-UINTN
-EFIAPI
-AsmReadEflags (
- VOID
- )
-{
- UINTN Eflags;
-
- __asm__ __volatile__ (
- "pushfl \n\t"
- "popl %0 "
- : "=r" (Eflags)
- );
-
- return Eflags;
-}
-
-
-
-/**
- Reads the current value of the Control Register 0 (CR0).
-
- Reads and returns the current value of CR0. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 0 (CR0).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr0 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%cr0,%0"
- : "=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of the Control Register 2 (CR2).
-
- Reads and returns the current value of CR2. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 2 (CR2).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr2 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%cr2, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-/**
- Reads the current value of the Control Register 3 (CR3).
-
- Reads and returns the current value of CR3. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 3 (CR3).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr3 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%cr3, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of the Control Register 4 (CR4).
-
- Reads and returns the current value of CR4. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 4 (CR4).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr4 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%cr4, %0"
- : "=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Writes a value to Control Register 0 (CR0).
-
- Writes and returns a new value to CR0. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr0 The value to write to CR0.
-
- @return The value written to CR0.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr0 (
- UINTN Cr0
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%cr0"
- :
- : "r" (Cr0)
- );
- return Cr0;
-}
-
-
-/**
- Writes a value to Control Register 2 (CR2).
-
- Writes and returns a new value to CR2. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr2 The value to write to CR2.
-
- @return The value written to CR2.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr2 (
- UINTN Cr2
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%cr2"
- :
- : "r" (Cr2)
- );
- return Cr2;
-}
-
-
-/**
- Writes a value to Control Register 3 (CR3).
-
- Writes and returns a new value to CR3. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr3 The value to write to CR3.
-
- @return The value written to CR3.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr3 (
- UINTN Cr3
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%cr3"
- :
- : "r" (Cr3)
- );
- return Cr3;
-}
-
-
-/**
- Writes a value to Control Register 4 (CR4).
-
- Writes and returns a new value to CR4. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr4 The value to write to CR4.
-
- @return The value written to CR4.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr4 (
- UINTN Cr4
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%cr4"
- :
- : "r" (Cr4)
- );
- return Cr4;
-}
-
-
-/**
- Reads the current value of Debug Register 0 (DR0).
-
- Reads and returns the current value of DR0. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 0 (DR0).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr0 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr0, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 1 (DR1).
-
- Reads and returns the current value of DR1. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 1 (DR1).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr1 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr1, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 2 (DR2).
-
- Reads and returns the current value of DR2. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 2 (DR2).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr2 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr2, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 3 (DR3).
-
- Reads and returns the current value of DR3. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 3 (DR3).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr3 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr3, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 4 (DR4).
-
- Reads and returns the current value of DR4. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 4 (DR4).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr4 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr4, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 5 (DR5).
-
- Reads and returns the current value of DR5. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 5 (DR5).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr5 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr5, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 6 (DR6).
-
- Reads and returns the current value of DR6. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 6 (DR6).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr6 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr6, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 7 (DR7).
-
- Reads and returns the current value of DR7. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 7 (DR7).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr7 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "movl %%dr7, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Writes a value to Debug Register 0 (DR0).
-
- Writes and returns a new value to DR0. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr0 The value to write to Dr0.
-
- @return The value written to Debug Register 0 (DR0).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr0 (
- UINTN Dr0
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr0"
- :
- : "r" (Dr0)
- );
- return Dr0;
-}
-
-
-/**
- Writes a value to Debug Register 1 (DR1).
-
- Writes and returns a new value to DR1. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr1 The value to write to Dr1.
-
- @return The value written to Debug Register 1 (DR1).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr1 (
- UINTN Dr1
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr1"
- :
- : "r" (Dr1)
- );
- return Dr1;
-}
-
-
-/**
- Writes a value to Debug Register 2 (DR2).
-
- Writes and returns a new value to DR2. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr2 The value to write to Dr2.
-
- @return The value written to Debug Register 2 (DR2).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr2 (
- UINTN Dr2
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr2"
- :
- : "r" (Dr2)
- );
- return Dr2;
-}
-
-
-/**
- Writes a value to Debug Register 3 (DR3).
-
- Writes and returns a new value to DR3. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr3 The value to write to Dr3.
-
- @return The value written to Debug Register 3 (DR3).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr3 (
- UINTN Dr3
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr3"
- :
- : "r" (Dr3)
- );
- return Dr3;
-}
-
-
-/**
- Writes a value to Debug Register 4 (DR4).
-
- Writes and returns a new value to DR4. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr4 The value to write to Dr4.
-
- @return The value written to Debug Register 4 (DR4).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr4 (
- UINTN Dr4
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr4"
- :
- : "r" (Dr4)
- );
- return Dr4;
-}
-
-
-/**
- Writes a value to Debug Register 5 (DR5).
-
- Writes and returns a new value to DR5. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr5 The value to write to Dr5.
-
- @return The value written to Debug Register 5 (DR5).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr5 (
- UINTN Dr5
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr5"
- :
- : "r" (Dr5)
- );
- return Dr5;
-}
-
-
-/**
- Writes a value to Debug Register 6 (DR6).
-
- Writes and returns a new value to DR6. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr6 The value to write to Dr6.
-
- @return The value written to Debug Register 6 (DR6).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr6 (
- UINTN Dr6
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr6"
- :
- : "r" (Dr6)
- );
- return Dr6;
-}
-
-
-/**
- Writes a value to Debug Register 7 (DR7).
-
- Writes and returns a new value to DR7. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr7 The value to write to Dr7.
-
- @return The value written to Debug Register 7 (DR7).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr7 (
- UINTN Dr7
- )
-{
- __asm__ __volatile__ (
- "movl %0, %%dr7"
- :
- : "r" (Dr7)
- );
- return Dr7;
-}
-
-
-/**
- Reads the current value of Code Segment Register (CS).
-
- Reads and returns the current value of CS. This function is only available on
- IA-32 and X64.
-
- @return The current value of CS.
-
-**/
-UINT16
-EFIAPI
-AsmReadCs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%cs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Data Segment Register (DS).
-
- Reads and returns the current value of DS. This function is only available on
- IA-32 and X64.
-
- @return The current value of DS.
-
-**/
-UINT16
-EFIAPI
-AsmReadDs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%ds, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Extra Segment Register (ES).
-
- Reads and returns the current value of ES. This function is only available on
- IA-32 and X64.
-
- @return The current value of ES.
-
-**/
-UINT16
-EFIAPI
-AsmReadEs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%es, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of FS Data Segment Register (FS).
-
- Reads and returns the current value of FS. This function is only available on
- IA-32 and X64.
-
- @return The current value of FS.
-
-**/
-UINT16
-EFIAPI
-AsmReadFs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%fs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of GS Data Segment Register (GS).
-
- Reads and returns the current value of GS. This function is only available on
- IA-32 and X64.
-
- @return The current value of GS.
-
-**/
-UINT16
-EFIAPI
-AsmReadGs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%gs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Stack Segment Register (SS).
-
- Reads and returns the current value of SS. This function is only available on
- IA-32 and X64.
-
- @return The current value of SS.
-
-**/
-UINT16
-EFIAPI
-AsmReadSs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%ds, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Task Register (TR).
-
- Reads and returns the current value of TR. This function is only available on
- IA-32 and X64.
-
- @return The current value of TR.
-
-**/
-UINT16
-EFIAPI
-AsmReadTr (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "str %0"
- : "=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current Global Descriptor Table Register(GDTR) descriptor.
-
- Reads and returns the current GDTR descriptor and returns it in Gdtr. This
- function is only available on IA-32 and X64.
-
- @param Gdtr Pointer to a GDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86ReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
- )
-{
- __asm__ __volatile__ (
- "sgdt %0"
- : "=m" (*Gdtr)
- );
-}
-
-
-/**
- Writes the current Global Descriptor Table Register (GDTR) descriptor.
-
- Writes and the current GDTR descriptor specified by Gdtr. This function is
- only available on IA-32 and X64.
-
- @param Gdtr Pointer to a GDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
- )
-{
- __asm__ __volatile__ (
- "lgdt %0"
- :
- : "m" (*Gdtr)
- );
-
-}
-
-
-/**
- Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
-
- Reads and returns the current IDTR descriptor and returns it in Idtr. This
- function is only available on IA-32 and X64.
-
- @param Idtr Pointer to a IDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Ldtr
- )
-{
- __asm__ __volatile__ (
- "sldt %0"
- : "=m" (*Ldtr)
- );
-}
-
-
-/**
- Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
-
- Writes the current IDTR descriptor and returns it in Idtr. This function is
- only available on IA-32 and X64.
-
- @param Idtr Pointer to a IDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Ldtr
- )
-{
- __asm__ __volatile__ (
- "lidt %0"
- :
- : "m" (*Ldtr)
- );
-}
-
-
-/**
- Reads the current Local Descriptor Table Register(LDTR) selector.
-
- Reads and returns the current 16-bit LDTR descriptor value. This function is
- only available on IA-32 and X64.
-
- @return The current selector of LDT.
-
-**/
-UINT16
-EFIAPI
-AsmReadLdtr (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "sldt %0"
- : "=g" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Writes the current Local Descriptor Table Register (GDTR) selector.
-
- Writes and the current LDTR descriptor specified by Ldtr. This function is
- only available on IA-32 and X64.
-
- @param Ldtr 16-bit LDTR selector value.
-
-**/
-VOID
-EFIAPI
-AsmWriteLdtr (
- IN UINT16 Ldtr
- )
-{
- __asm__ __volatile__ (
- "lldtw %0"
- :
- : "g" (Ldtr) // %0
- );
-}
-
-
-/**
- Save the current floating point/SSE/SSE2 context to a buffer.
-
- Saves the current floating point/SSE/SSE2 state to the buffer specified by
- Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
- available on IA-32 and X64.
-
- @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
-
-**/
-VOID
-EFIAPI
-InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
- )
-{
- __asm__ __volatile__ (
- "fxsave %0"
- :
- : "m" (*Buffer) // %0
- );
-}
-
-
-/**
- Restores the current floating point/SSE/SSE2 context from a buffer.
-
- Restores the current floating point/SSE/SSE2 state from the buffer specified
- by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
- only available on IA-32 and X64.
-
- @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
-
-**/
-VOID
-EFIAPI
-InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
- )
-{
- __asm__ __volatile__ (
- "fxrstor %0"
- :
- : "m" (*Buffer) // %0
- );
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #0 (MM0).
-
- Reads and returns the current value of MM0. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM0.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm0 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm0, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #1 (MM1).
-
- Reads and returns the current value of MM1. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM1.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm1 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm1, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #2 (MM2).
-
- Reads and returns the current value of MM2. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM2.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm2 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm2, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #3 (MM3).
-
- Reads and returns the current value of MM3. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM3.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm3 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm3, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #4 (MM4).
-
- Reads and returns the current value of MM4. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM4.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm4 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm4, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #5 (MM5).
-
- Reads and returns the current value of MM5. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM5.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm5 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm5, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #6 (MM6).
-
- Reads and returns the current value of MM6. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM6.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm6 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm6, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #7 (MM7).
-
- Reads and returns the current value of MM7. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM7.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm7 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "push %%eax \n\t"
- "push %%eax \n\t"
- "movq %%mm7, (%%esp)\n\t"
- "pop %%eax \n\t"
- "pop %%edx \n\t"
- : "=A" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #0 (MM0).
-
- Writes the current value of MM0. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM0.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm0 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm0" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #1 (MM1).
-
- Writes the current value of MM1. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM1.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm1 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm1" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #2 (MM2).
-
- Writes the current value of MM2. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM2.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm2 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm2" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #3 (MM3).
-
- Writes the current value of MM3. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM3.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm3 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm3" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #4 (MM4).
-
- Writes the current value of MM4. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM4.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm4 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm4" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #5 (MM5).
-
- Writes the current value of MM5. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM5.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm5 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm5" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #6 (MM6).
-
- Writes the current value of MM6. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM6.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm6 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm6" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #7 (MM7).
-
- Writes the current value of MM7. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM7.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm7 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movq %0, %%mm7" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Reads the current value of Time Stamp Counter (TSC).
-
- Reads and returns the current value of TSC. This function is only available
- on IA-32 and X64.
-
- @return The current value of TSC
-
-**/
-UINT64
-EFIAPI
-AsmReadTsc (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "rdtsc"
- : "=A" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of a Performance Counter (PMC).
-
- Reads and returns the current value of performance counter specified by
- Index. This function is only available on IA-32 and X64.
-
- @param Index The 32-bit Performance Counter index to read.
-
- @return The value of the PMC specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmc (
- IN UINT32 Index
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "rdpmc"
- : "=A" (Data)
- : "c" (Index)
- );
-
- return Data;
-}
-
-
-
-
-/**
- Executes a WBINVD instruction.
-
- Executes a WBINVD instruction. This function is only available on IA-32 and
- X64.
-
-**/
-VOID
-EFIAPI
-AsmWbinvd (
- VOID
- )
-{
- __asm__ __volatile__ ("wbinvd":::"memory");
-}
-
-
-/**
- Executes a INVD instruction.
-
- Executes a INVD instruction. This function is only available on IA-32 and
- X64.
-
-**/
-VOID
-EFIAPI
-AsmInvd (
- VOID
- )
-{
- __asm__ __volatile__ ("invd":::"memory");
-
-}
-
-
-/**
- Flushes a cache line from all the instruction and data caches within the
- coherency domain of the CPU.
-
- Flushed the cache line specified by LinearAddress, and returns LinearAddress.
- This function is only available on IA-32 and X64.
-
- @param LinearAddress The address of the cache line to flush. If the CPU is
- in a physical addressing mode, then LinearAddress is a
- physical address. If the CPU is in a virtual
- addressing mode, then LinearAddress is a virtual
- address.
-
- @return LinearAddress
-**/
-VOID *
-EFIAPI
-AsmFlushCacheLine (
- IN VOID *LinearAddress
- )
-{
- __asm__ __volatile__ (
- "clflush (%0)"
- : "+a" (LinearAddress)
- :
- : "memory"
- );
-
- return LinearAddress;
-}
-
-
+/** @file\r
+ GCC inline implementation of BaseLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+\r
+/**\r
+ Used to serialize load and store operations.\r
+\r
+ All loads and stores that proceed calls to this function are guaranteed to be\r
+ globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+ VOID\r
+ )\r
+{\r
+ // This is a little bit of overkill and it is more about the compiler that it is\r
+ // actually processor syncronization. This is like the _ReadWriteBarrier \r
+ // Microsft specific intrinsic\r
+ __asm__ __volatile__ ("":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+ Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("sti"::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+ Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+ VOID\r
+ )\r
+{ \r
+ __asm__ __volatile__ ("cli"::: "memory");\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("pause");\r
+}\r
+\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("int $3");\r
+}\r
+\r
+\r
+\r
+/**\r
+ Returns a 64-bit Machine Specific Register(MSR).\r
+\r
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
+ performed on Index, and some Index values may cause CPU exceptions. The\r
+ caller must either guarantee that Index is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+\r
+ @return The value of the MSR identified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr64 (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT64 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdmsr"\r
+ : "=A" (Data) // %0\r
+ : "c" (Index) // %1\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
+ value.\r
+\r
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The\r
+ 64-bit value written to the MSR is returned. No parameter checking is\r
+ performed on Index or Value, and some of these may cause CPU exceptions. The\r
+ caller must either guarantee that Index and Value are valid, or the caller\r
+ must establish proper exception handlers. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param Value The 64-bit value to write to the MSR.\r
+\r
+ @return Value\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "wrmsr"\r
+ :\r
+ : "c" (Index),\r
+ "A" (Value)\r
+ );\r
+ \r
+ return Value;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the EFLAGS register.\r
+\r
+ Reads and returns the current value of the EFLAGS register. This function is\r
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a\r
+ 64-bit value on X64.\r
+\r
+ @return EFLAGS on IA-32 or RFLAGS on X64.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadEflags (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Eflags;\r
+ \r
+ __asm__ __volatile__ (\r
+ "pushfl \n\t"\r
+ "popl %0 "\r
+ : "=r" (Eflags)\r
+ );\r
+ \r
+ return Eflags;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 0 (CR0).\r
+\r
+ Reads and returns the current value of CR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 0 (CR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%cr0,%0" \r
+ : "=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 2 (CR2).\r
+\r
+ Reads and returns the current value of CR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 2 (CR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%cr2, %0" \r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads the current value of the Control Register 3 (CR3).\r
+\r
+ Reads and returns the current value of CR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 3 (CR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%cr3, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 4 (CR4).\r
+\r
+ Reads and returns the current value of CR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 4 (CR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%cr4, %0"\r
+ : "=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 0 (CR0).\r
+\r
+ Writes and returns a new value to CR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr0 The value to write to CR0.\r
+\r
+ @return The value written to CR0.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr0 (\r
+ UINTN Cr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%cr0"\r
+ :\r
+ : "r" (Cr0)\r
+ );\r
+ return Cr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 2 (CR2).\r
+\r
+ Writes and returns a new value to CR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr2 The value to write to CR2.\r
+\r
+ @return The value written to CR2.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr2 (\r
+ UINTN Cr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%cr2"\r
+ :\r
+ : "r" (Cr2)\r
+ );\r
+ return Cr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 3 (CR3).\r
+\r
+ Writes and returns a new value to CR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr3 The value to write to CR3.\r
+\r
+ @return The value written to CR3.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr3 (\r
+ UINTN Cr3\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%cr3"\r
+ :\r
+ : "r" (Cr3)\r
+ );\r
+ return Cr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 4 (CR4).\r
+\r
+ Writes and returns a new value to CR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr4 The value to write to CR4.\r
+\r
+ @return The value written to CR4.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr4 (\r
+ UINTN Cr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%cr4"\r
+ :\r
+ : "r" (Cr4)\r
+ );\r
+ return Cr4;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 0 (DR0).\r
+\r
+ Reads and returns the current value of DR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr0, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 1 (DR1).\r
+\r
+ Reads and returns the current value of DR1. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr1 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr1, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 2 (DR2).\r
+\r
+ Reads and returns the current value of DR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr2, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 3 (DR3).\r
+\r
+ Reads and returns the current value of DR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr3, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 4 (DR4).\r
+\r
+ Reads and returns the current value of DR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr4, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 5 (DR5).\r
+\r
+ Reads and returns the current value of DR5. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr5 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr5, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 6 (DR6).\r
+\r
+ Reads and returns the current value of DR6. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr6 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr6, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 7 (DR7).\r
+\r
+ Reads and returns the current value of DR7. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr7 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "movl %%dr7, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 0 (DR0).\r
+\r
+ Writes and returns a new value to DR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr0 The value to write to Dr0.\r
+\r
+ @return The value written to Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr0 (\r
+ UINTN Dr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr0"\r
+ :\r
+ : "r" (Dr0)\r
+ );\r
+ return Dr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 1 (DR1).\r
+\r
+ Writes and returns a new value to DR1. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr1 The value to write to Dr1.\r
+\r
+ @return The value written to Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr1 (\r
+ UINTN Dr1\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr1"\r
+ :\r
+ : "r" (Dr1)\r
+ );\r
+ return Dr1;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 2 (DR2).\r
+\r
+ Writes and returns a new value to DR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr2 The value to write to Dr2.\r
+\r
+ @return The value written to Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr2 (\r
+ UINTN Dr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr2"\r
+ :\r
+ : "r" (Dr2)\r
+ );\r
+ return Dr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 3 (DR3).\r
+\r
+ Writes and returns a new value to DR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr3 The value to write to Dr3.\r
+\r
+ @return The value written to Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr3 (\r
+ UINTN Dr3\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr3"\r
+ :\r
+ : "r" (Dr3)\r
+ );\r
+ return Dr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 4 (DR4).\r
+\r
+ Writes and returns a new value to DR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr4 The value to write to Dr4.\r
+\r
+ @return The value written to Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr4 (\r
+ UINTN Dr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr4"\r
+ :\r
+ : "r" (Dr4)\r
+ );\r
+ return Dr4;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 5 (DR5).\r
+\r
+ Writes and returns a new value to DR5. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr5 The value to write to Dr5.\r
+\r
+ @return The value written to Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr5 (\r
+ UINTN Dr5\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr5"\r
+ :\r
+ : "r" (Dr5)\r
+ );\r
+ return Dr5;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 6 (DR6).\r
+\r
+ Writes and returns a new value to DR6. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr6 The value to write to Dr6.\r
+\r
+ @return The value written to Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr6 (\r
+ UINTN Dr6\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr6"\r
+ :\r
+ : "r" (Dr6)\r
+ );\r
+ return Dr6;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 7 (DR7).\r
+\r
+ Writes and returns a new value to DR7. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr7 The value to write to Dr7.\r
+\r
+ @return The value written to Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr7 (\r
+ UINTN Dr7\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movl %0, %%dr7"\r
+ :\r
+ : "r" (Dr7)\r
+ );\r
+ return Dr7;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Code Segment Register (CS).\r
+\r
+ Reads and returns the current value of CS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of CS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadCs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Data Segment Register (DS).\r
+\r
+ Reads and returns the current value of DS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of DS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadDs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Extra Segment Register (ES).\r
+\r
+ Reads and returns the current value of ES. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of ES.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadEs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%es, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of FS Data Segment Register (FS).\r
+\r
+ Reads and returns the current value of FS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of FS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadFs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%fs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of GS Data Segment Register (GS).\r
+\r
+ Reads and returns the current value of GS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of GS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadGs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%gs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Stack Segment Register (SS).\r
+\r
+ Reads and returns the current value of SS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of SS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadSs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Task Register (TR).\r
+\r
+ Reads and returns the current value of TR. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of TR.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadTr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "str %0"\r
+ : "=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Gdtr Pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadGdtr (\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sgdt %0"\r
+ : "=m" (*Gdtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
+\r
+ Writes and the current GDTR descriptor specified by Gdtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Gdtr Pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteGdtr (\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lgdt %0"\r
+ :\r
+ : "m" (*Gdtr)\r
+ );\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Idtr Pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadIdtr (\r
+ OUT IA32_DESCRIPTOR *Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sldt %0"\r
+ : "=m" (*Ldtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Writes the current IDTR descriptor and returns it in Idtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Idtr Pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteIdtr (\r
+ IN CONST IA32_DESCRIPTOR *Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lidt %0"\r
+ :\r
+ : "m" (*Ldtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Local Descriptor Table Register(LDTR) selector.\r
+\r
+ Reads and returns the current 16-bit LDTR descriptor value. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @return The current selector of LDT.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadLdtr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "sldt %0"\r
+ : "=g" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Local Descriptor Table Register (GDTR) selector.\r
+\r
+ Writes and the current LDTR descriptor specified by Ldtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Ldtr 16-bit LDTR selector value.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteLdtr (\r
+ IN UINT16 Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lldtw %0"\r
+ :\r
+ : "g" (Ldtr) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Save the current floating point/SSE/SSE2 context to a buffer.\r
+\r
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
+ available on IA-32 and X64.\r
+\r
+ @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxSave (\r
+ OUT IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxsave %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ ); \r
+}\r
+\r
+\r
+/**\r
+ Restores the current floating point/SSE/SSE2 context from a buffer.\r
+\r
+ Restores the current floating point/SSE/SSE2 state from the buffer specified\r
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxRestore (\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxrstor %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Reads and returns the current value of MM0. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm0 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm0, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Reads and returns the current value of MM1. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm1 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm1, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Reads and returns the current value of MM2. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm2 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm2, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Reads and returns the current value of MM3. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm3 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm3, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Reads and returns the current value of MM4. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm4 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm4, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Reads and returns the current value of MM5. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm5 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm5, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Reads and returns the current value of MM6. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm6 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm6, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Reads and returns the current value of MM7. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm7 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "push %%eax \n\t"\r
+ "push %%eax \n\t"\r
+ "movq %%mm7, (%%esp)\n\t"\r
+ "pop %%eax \n\t"\r
+ "pop %%edx \n\t"\r
+ : "=A" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Writes the current value of MM0. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM0.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm0 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm0" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Writes the current value of MM1. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm1 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm1" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Writes the current value of MM2. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM2.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm2 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm2" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Writes the current value of MM3. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM3.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm3 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm3" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Writes the current value of MM4. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM4.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm4 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm4" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Writes the current value of MM5. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM5.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm5 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm5" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Writes the current value of MM6. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM6.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm6 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm6" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Writes the current value of MM7. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM7.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm7 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movq %0, %%mm7" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Time Stamp Counter (TSC).\r
+\r
+ Reads and returns the current value of TSC. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of TSC\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadTsc (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdtsc"\r
+ : "=A" (Data)\r
+ );\r
+ \r
+ return Data; \r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of a Performance Counter (PMC).\r
+\r
+ Reads and returns the current value of performance counter specified by\r
+ Index. This function is only available on IA-32 and X64.\r
+\r
+ @param Index The 32-bit Performance Counter index to read.\r
+\r
+ @return The value of the PMC specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmc (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT64 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdpmc"\r
+ : "=A" (Data)\r
+ : "c" (Index)\r
+ );\r
+ \r
+ return Data; \r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ Executes a WBINVD instruction.\r
+\r
+ Executes a WBINVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWbinvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("wbinvd":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Executes a INVD instruction.\r
+\r
+ Executes a INVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmInvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("invd":::"memory");\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Flushes a cache line from all the instruction and data caches within the\r
+ coherency domain of the CPU.\r
+\r
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+ This function is only available on IA-32 and X64.\r
+\r
+ @param LinearAddress The address of the cache line to flush. If the CPU is\r
+ in a physical addressing mode, then LinearAddress is a\r
+ physical address. If the CPU is in a virtual\r
+ addressing mode, then LinearAddress is a virtual\r
+ address.\r
+\r
+ @return LinearAddress\r
+**/\r
+VOID *\r
+EFIAPI\r
+AsmFlushCacheLine (\r
+ IN VOID *LinearAddress\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "clflush (%0)"\r
+ : "+a" (LinearAddress) \r
+ : \r
+ : "memory"\r
+ );\r
+ \r
+ return LinearAddress;\r
+}\r
+\r
+\r
-/** @file
- GCC inline implementation of BaseLib processor specific functions.
-
- Copyright (c) 2006 - 2007, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseLibInternals.h"
-
-
-
-
-/**
- Used to serialize load and store operations.
-
- All loads and stores that proceed calls to this function are guaranteed to be
- globally visible when this function returns.
-
-**/
-VOID
-EFIAPI
-MemoryFence (
- VOID
- )
-{
- // This is a little bit of overkill and it is more about the compiler that it is
- // actually processor syncronization. This is like the _ReadWriteBarrier
- // Microsft specific intrinsic
- __asm__ __volatile__ ("":::"memory");
-}
-
-
-/**
- Enables CPU interrupts.
-
- Enables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-EnableInterrupts (
- VOID
- )
-{
- __asm__ __volatile__ ("sti"::: "memory");
-}
-
-
-/**
- Disables CPU interrupts.
-
- Disables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-DisableInterrupts (
- VOID
- )
-{
- __asm__ __volatile__ ("cli"::: "memory");
-}
-
-
-
-
-/**
- Requests CPU to pause for a short period of time.
-
- Requests CPU to pause for a short period of time. Typically used in MP
- systems to prevent memory starvation while waiting for a spin lock.
-
-**/
-VOID
-EFIAPI
-CpuPause (
- VOID
- )
-{
- __asm__ __volatile__ ("pause");
-}
-
-
-/**
- Generates a breakpoint on the CPU.
-
- Generates a breakpoint on the CPU. The breakpoint must be implemented such
- that code can resume normal execution after the breakpoint.
-
-**/
-VOID
-EFIAPI
-CpuBreakpoint (
- VOID
- )
-{
- __asm__ __volatile__ ("int $3");
-}
-
-
-
-/**
- Returns a 64-bit Machine Specific Register(MSR).
-
- Reads and returns the 64-bit MSR specified by Index. No parameter checking is
- performed on Index, and some Index values may cause CPU exceptions. The
- caller must either guarantee that Index is valid, or the caller must set up
- exception handlers to catch the exceptions. This function is only available
- on IA-32 and X64.
-
- @param Index The 32-bit MSR index to read.
-
- @return The value of the MSR identified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadMsr64 (
- IN UINT32 Index
- )
-{
- UINT32 LowData;
- UINT32 HighData;
-
- __asm__ __volatile__ (
- "rdmsr"
- : "=a" (LowData), // %0
- "=d" (HighData) // %1
- : "c" (Index) // %2
- );
-
- return (((UINT64)HighData) << 32) | LowData;
-}
-
-/**
- Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
- value.
-
- Writes the 64-bit value specified by Value to the MSR specified by Index. The
- 64-bit value written to the MSR is returned. No parameter checking is
- performed on Index or Value, and some of these may cause CPU exceptions. The
- caller must either guarantee that Index and Value are valid, or the caller
- must establish proper exception handlers. This function is only available on
- IA-32 and X64.
-
- @param Index The 32-bit MSR index to write.
- @param Value The 64-bit value to write to the MSR.
-
- @return Value
-
-**/
-UINT64
-EFIAPI
-AsmWriteMsr64 (
- IN UINT32 Index,
- IN UINT64 Value
- )
-{
- UINT32 LowData;
- UINT32 HighData;
-
- LowData = (UINT32)(Value);
- HighData = (UINT32)(Value >> 32);
-
- __asm__ __volatile__ (
- "wrmsr"
- :
- : "c" (Index),
- "a" (LowData),
- "d" (HighData)
- );
-
- return Value;
-}
-
-
-
-/**
- Reads the current value of the EFLAGS register.
-
- Reads and returns the current value of the EFLAGS register. This function is
- only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
- 64-bit value on X64.
-
- @return EFLAGS on IA-32 or RFLAGS on X64.
-
-**/
-UINTN
-EFIAPI
-AsmReadEflags (
- VOID
- )
-{
- UINTN Eflags;
-
- __asm__ __volatile__ (
- "pushfq \n\t"
- "pop %0 "
- : "=r" (Eflags) // %0
- );
-
- return Eflags;
-}
-
-
-
-/**
- Reads the current value of the Control Register 0 (CR0).
-
- Reads and returns the current value of CR0. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 0 (CR0).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr0 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%cr0,%0"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of the Control Register 2 (CR2).
-
- Reads and returns the current value of CR2. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 2 (CR2).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr2 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%cr2, %0"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-/**
- Reads the current value of the Control Register 3 (CR3).
-
- Reads and returns the current value of CR3. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 3 (CR3).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr3 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%cr3, %0"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of the Control Register 4 (CR4).
-
- Reads and returns the current value of CR4. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of the Control Register 4 (CR4).
-
-**/
-UINTN
-EFIAPI
-AsmReadCr4 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%cr4, %0"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Writes a value to Control Register 0 (CR0).
-
- Writes and returns a new value to CR0. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr0 The value to write to CR0.
-
- @return The value written to CR0.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr0 (
- UINTN Cr0
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%cr0"
- :
- : "r" (Cr0)
- );
- return Cr0;
-}
-
-
-/**
- Writes a value to Control Register 2 (CR2).
-
- Writes and returns a new value to CR2. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr2 The value to write to CR2.
-
- @return The value written to CR2.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr2 (
- UINTN Cr2
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%cr2"
- :
- : "r" (Cr2)
- );
- return Cr2;
-}
-
-
-/**
- Writes a value to Control Register 3 (CR3).
-
- Writes and returns a new value to CR3. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr3 The value to write to CR3.
-
- @return The value written to CR3.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr3 (
- UINTN Cr3
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%cr3"
- :
- : "r" (Cr3)
- );
- return Cr3;
-}
-
-
-/**
- Writes a value to Control Register 4 (CR4).
-
- Writes and returns a new value to CR4. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Cr4 The value to write to CR4.
-
- @return The value written to CR4.
-
-**/
-UINTN
-EFIAPI
-AsmWriteCr4 (
- UINTN Cr4
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%cr4"
- :
- : "r" (Cr4)
- );
- return Cr4;
-}
-
-
-/**
- Reads the current value of Debug Register 0 (DR0).
-
- Reads and returns the current value of DR0. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 0 (DR0).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr0 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr0, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 1 (DR1).
-
- Reads and returns the current value of DR1. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 1 (DR1).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr1 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr1, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 2 (DR2).
-
- Reads and returns the current value of DR2. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 2 (DR2).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr2 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr2, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 3 (DR3).
-
- Reads and returns the current value of DR3. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 3 (DR3).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr3 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr3, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 4 (DR4).
-
- Reads and returns the current value of DR4. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 4 (DR4).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr4 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr4, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 5 (DR5).
-
- Reads and returns the current value of DR5. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 5 (DR5).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr5 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr5, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 6 (DR6).
-
- Reads and returns the current value of DR6. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 6 (DR6).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr6 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr6, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Debug Register 7 (DR7).
-
- Reads and returns the current value of DR7. This function is only available
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
- X64.
-
- @return The value of Debug Register 7 (DR7).
-
-**/
-UINTN
-EFIAPI
-AsmReadDr7 (
- VOID
- )
-{
- UINTN Data;
-
- __asm__ __volatile__ (
- "mov %%dr7, %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Writes a value to Debug Register 0 (DR0).
-
- Writes and returns a new value to DR0. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr0 The value to write to Dr0.
-
- @return The value written to Debug Register 0 (DR0).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr0 (
- UINTN Dr0
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr0"
- :
- : "r" (Dr0)
- );
- return Dr0;
-}
-
-
-/**
- Writes a value to Debug Register 1 (DR1).
-
- Writes and returns a new value to DR1. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr1 The value to write to Dr1.
-
- @return The value written to Debug Register 1 (DR1).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr1 (
- UINTN Dr1
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr1"
- :
- : "r" (Dr1)
- );
- return Dr1;
-}
-
-
-/**
- Writes a value to Debug Register 2 (DR2).
-
- Writes and returns a new value to DR2. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr2 The value to write to Dr2.
-
- @return The value written to Debug Register 2 (DR2).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr2 (
- UINTN Dr2
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr2"
- :
- : "r" (Dr2)
- );
- return Dr2;
-}
-
-
-/**
- Writes a value to Debug Register 3 (DR3).
-
- Writes and returns a new value to DR3. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr3 The value to write to Dr3.
-
- @return The value written to Debug Register 3 (DR3).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr3 (
- UINTN Dr3
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr3"
- :
- : "r" (Dr3)
- );
- return Dr3;
-}
-
-
-/**
- Writes a value to Debug Register 4 (DR4).
-
- Writes and returns a new value to DR4. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr4 The value to write to Dr4.
-
- @return The value written to Debug Register 4 (DR4).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr4 (
- UINTN Dr4
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr4"
- :
- : "r" (Dr4)
- );
- return Dr4;
-}
-
-
-/**
- Writes a value to Debug Register 5 (DR5).
-
- Writes and returns a new value to DR5. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr5 The value to write to Dr5.
-
- @return The value written to Debug Register 5 (DR5).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr5 (
- UINTN Dr5
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr5"
- :
- : "r" (Dr5)
- );
- return Dr5;
-}
-
-
-/**
- Writes a value to Debug Register 6 (DR6).
-
- Writes and returns a new value to DR6. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr6 The value to write to Dr6.
-
- @return The value written to Debug Register 6 (DR6).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr6 (
- UINTN Dr6
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr6"
- :
- : "r" (Dr6)
- );
- return Dr6;
-}
-
-
-/**
- Writes a value to Debug Register 7 (DR7).
-
- Writes and returns a new value to DR7. This function is only available on
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
-
- @param Dr7 The value to write to Dr7.
-
- @return The value written to Debug Register 7 (DR7).
-
-**/
-UINTN
-EFIAPI
-AsmWriteDr7 (
- UINTN Dr7
- )
-{
- __asm__ __volatile__ (
- "mov %0, %%dr7"
- :
- : "r" (Dr7)
- );
- return Dr7;
-}
-
-
-/**
- Reads the current value of Code Segment Register (CS).
-
- Reads and returns the current value of CS. This function is only available on
- IA-32 and X64.
-
- @return The current value of CS.
-
-**/
-UINT16
-EFIAPI
-AsmReadCs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%cs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Data Segment Register (DS).
-
- Reads and returns the current value of DS. This function is only available on
- IA-32 and X64.
-
- @return The current value of DS.
-
-**/
-UINT16
-EFIAPI
-AsmReadDs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%ds, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Extra Segment Register (ES).
-
- Reads and returns the current value of ES. This function is only available on
- IA-32 and X64.
-
- @return The current value of ES.
-
-**/
-UINT16
-EFIAPI
-AsmReadEs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%es, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of FS Data Segment Register (FS).
-
- Reads and returns the current value of FS. This function is only available on
- IA-32 and X64.
-
- @return The current value of FS.
-
-**/
-UINT16
-EFIAPI
-AsmReadFs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%fs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of GS Data Segment Register (GS).
-
- Reads and returns the current value of GS. This function is only available on
- IA-32 and X64.
-
- @return The current value of GS.
-
-**/
-UINT16
-EFIAPI
-AsmReadGs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%gs, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Stack Segment Register (SS).
-
- Reads and returns the current value of SS. This function is only available on
- IA-32 and X64.
-
- @return The current value of SS.
-
-**/
-UINT16
-EFIAPI
-AsmReadSs (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "mov %%ds, %0"
- :"=a" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of Task Register (TR).
-
- Reads and returns the current value of TR. This function is only available on
- IA-32 and X64.
-
- @return The current value of TR.
-
-**/
-UINT16
-EFIAPI
-AsmReadTr (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "str %0"
- : "=r" (Data)
- );
-
- return Data;
-}
-
-
-/**
- Reads the current Global Descriptor Table Register(GDTR) descriptor.
-
- Reads and returns the current GDTR descriptor and returns it in Gdtr. This
- function is only available on IA-32 and X64.
-
- @param Gdtr Pointer to a GDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86ReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
- )
-{
- __asm__ __volatile__ (
- "sgdt %0"
- : "=m" (*Gdtr)
- );
-}
-
-
-/**
- Writes the current Global Descriptor Table Register (GDTR) descriptor.
-
- Writes and the current GDTR descriptor specified by Gdtr. This function is
- only available on IA-32 and X64.
-
- @param Gdtr Pointer to a GDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
- )
-{
- __asm__ __volatile__ (
- "lgdt %0"
- :
- : "m" (*Gdtr)
- );
-
-}
-
-
-/**
- Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
-
- Reads and returns the current IDTR descriptor and returns it in Idtr. This
- function is only available on IA-32 and X64.
-
- @param Idtr Pointer to a IDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Ldtr
- )
-{
- __asm__ __volatile__ (
- "sldt %0"
- : "=m" (*Ldtr)
- );
-}
-
-
-/**
- Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
-
- Writes the current IDTR descriptor and returns it in Idtr. This function is
- only available on IA-32 and X64.
-
- @param Idtr Pointer to a IDTR descriptor.
-
-**/
-VOID
-EFIAPI
-InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Ldtr
- )
-{
- __asm__ __volatile__ (
- "lidt %0"
- :
- : "m" (*Ldtr)
- );
-}
-
-
-/**
- Reads the current Local Descriptor Table Register(LDTR) selector.
-
- Reads and returns the current 16-bit LDTR descriptor value. This function is
- only available on IA-32 and X64.
-
- @return The current selector of LDT.
-
-**/
-UINT16
-EFIAPI
-AsmReadLdtr (
- VOID
- )
-{
- UINT16 Data;
-
- __asm__ __volatile__ (
- "sldt %0"
- : "=g" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Writes the current Local Descriptor Table Register (GDTR) selector.
-
- Writes and the current LDTR descriptor specified by Ldtr. This function is
- only available on IA-32 and X64.
-
- @param Ldtr 16-bit LDTR selector value.
-
-**/
-VOID
-EFIAPI
-AsmWriteLdtr (
- IN UINT16 Ldtr
- )
-{
- __asm__ __volatile__ (
- "lldtw %0"
- :
- : "g" (Ldtr) // %0
- );
-}
-
-
-/**
- Save the current floating point/SSE/SSE2 context to a buffer.
-
- Saves the current floating point/SSE/SSE2 state to the buffer specified by
- Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
- available on IA-32 and X64.
-
- @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
-
-**/
-VOID
-EFIAPI
-InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
- )
-{
- __asm__ __volatile__ (
- "fxsave %0"
- :
- : "m" (*Buffer) // %0
- );
-}
-
-
-/**
- Restores the current floating point/SSE/SSE2 context from a buffer.
-
- Restores the current floating point/SSE/SSE2 state from the buffer specified
- by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
- only available on IA-32 and X64.
-
- @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.
-
-**/
-VOID
-EFIAPI
-InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
- )
-{
- __asm__ __volatile__ (
- "fxrstor %0"
- :
- : "m" (*Buffer) // %0
- );
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #0 (MM0).
-
- Reads and returns the current value of MM0. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM0.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm0 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm0, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #1 (MM1).
-
- Reads and returns the current value of MM1. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM1.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm1 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm1, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #2 (MM2).
-
- Reads and returns the current value of MM2. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM2.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm2 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm2, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #3 (MM3).
-
- Reads and returns the current value of MM3. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM3.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm3 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm3, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #4 (MM4).
-
- Reads and returns the current value of MM4. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM4.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm4 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm4, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #5 (MM5).
-
- Reads and returns the current value of MM5. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM5.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm5 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm5, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #6 (MM6).
-
- Reads and returns the current value of MM6. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM6.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm6 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm6, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Reads the current value of 64-bit MMX Register #7 (MM7).
-
- Reads and returns the current value of MM7. This function is only available
- on IA-32 and X64.
-
- @return The current value of MM7.
-
-**/
-UINT64
-EFIAPI
-AsmReadMm7 (
- VOID
- )
-{
- UINT64 Data;
-
- __asm__ __volatile__ (
- "movd %%mm7, %0 \n\t"
- : "=r" (Data) // %0
- );
-
- return Data;
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #0 (MM0).
-
- Writes the current value of MM0. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM0.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm0 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm0" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #1 (MM1).
-
- Writes the current value of MM1. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM1.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm1 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm1" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #2 (MM2).
-
- Writes the current value of MM2. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM2.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm2 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm2" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #3 (MM3).
-
- Writes the current value of MM3. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM3.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm3 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm3" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #4 (MM4).
-
- Writes the current value of MM4. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM4.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm4 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm4" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #5 (MM5).
-
- Writes the current value of MM5. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM5.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm5 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm5" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #6 (MM6).
-
- Writes the current value of MM6. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM6.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm6 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm6" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Writes the current value of 64-bit MMX Register #7 (MM7).
-
- Writes the current value of MM7. This function is only available on IA32 and
- X64.
-
- @param Value The 64-bit value to write to MM7.
-
-**/
-VOID
-EFIAPI
-AsmWriteMm7 (
- IN UINT64 Value
- )
-{
- __asm__ __volatile__ (
- "movd %0, %%mm7" // %0
- :
- : "m" (Value)
- );
-}
-
-
-/**
- Reads the current value of Time Stamp Counter (TSC).
-
- Reads and returns the current value of TSC. This function is only available
- on IA-32 and X64.
-
- @return The current value of TSC
-
-**/
-UINT64
-EFIAPI
-AsmReadTsc (
- VOID
- )
-{
- UINT32 LowData;
- UINT32 HiData;
-
- __asm__ __volatile__ (
- "rdtsc"
- : "=a" (LowData),
- "=d" (HiData)
- );
-
- return (((UINT64)HiData) << 32) | LowData;
-}
-
-
-/**
- Reads the current value of a Performance Counter (PMC).
-
- Reads and returns the current value of performance counter specified by
- Index. This function is only available on IA-32 and X64.
-
- @param Index The 32-bit Performance Counter index to read.
-
- @return The value of the PMC specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmc (
- IN UINT32 Index
- )
-{
- UINT32 LowData;
- UINT32 HiData;
-
- __asm__ __volatile__ (
- "rdpmc"
- : "=a" (LowData),
- "=d" (HiData)
- : "c" (Index)
- );
-
- return (((UINT64)HiData) << 32) | LowData;
-}
-
-
-/**
- Sets up a monitor buffer that is used by AsmMwait().
-
- Executes a MONITOR instruction with the register state specified by Eax, Ecx
- and Edx. Returns Eax. This function is only available on IA-32 and X64.
-
- @param Eax The value to load into EAX or RAX before executing the MONITOR
- instruction.
- @param Ecx The value to load into ECX or RCX before executing the MONITOR
- instruction.
- @param Edx The value to load into EDX or RDX before executing the MONITOR
- instruction.
-
- @return Eax
-
-**/
-UINTN
-EFIAPI
-AsmMonitor (
- IN UINTN Eax,
- IN UINTN Ecx,
- IN UINTN Edx
- )
-{
- __asm__ __volatile__ (
- "monitor"
- :
- : "a" (Eax),
- "c" (Ecx),
- "d" (Edx)
- );
-
- return Eax;
-}
-
-
-/**
- Executes an MWAIT instruction.
-
- Executes an MWAIT instruction with the register state specified by Eax and
- Ecx. Returns Eax. This function is only available on IA-32 and X64.
-
- @param Eax The value to load into EAX or RAX before executing the MONITOR
- instruction.
- @param Ecx The value to load into ECX or RCX before executing the MONITOR
- instruction.
-
- @return Eax
-
-**/
-UINTN
-EFIAPI
-AsmMwait (
- IN UINTN Eax,
- IN UINTN Ecx
- )
-{
- __asm__ __volatile__ (
- "mwait"
- :
- : "a" (Eax),
- "c" (Ecx)
- );
-
- return Eax;
-}
-
-
-/**
- Executes a WBINVD instruction.
-
- Executes a WBINVD instruction. This function is only available on IA-32 and
- X64.
-
-**/
-VOID
-EFIAPI
-AsmWbinvd (
- VOID
- )
-{
- __asm__ __volatile__ ("wbinvd":::"memory");
-}
-
-
-/**
- Executes a INVD instruction.
-
- Executes a INVD instruction. This function is only available on IA-32 and
- X64.
-
-**/
-VOID
-EFIAPI
-AsmInvd (
- VOID
- )
-{
- __asm__ __volatile__ ("invd":::"memory");
-
-}
-
-
-/**
- Flushes a cache line from all the instruction and data caches within the
- coherency domain of the CPU.
-
- Flushed the cache line specified by LinearAddress, and returns LinearAddress.
- This function is only available on IA-32 and X64.
-
- @param LinearAddress The address of the cache line to flush. If the CPU is
- in a physical addressing mode, then LinearAddress is a
- physical address. If the CPU is in a virtual
- addressing mode, then LinearAddress is a virtual
- address.
-
- @return LinearAddress
-**/
-VOID *
-EFIAPI
-AsmFlushCacheLine (
- IN VOID *LinearAddress
- )
-{
- __asm__ __volatile__ (
- "clflush (%0)"
- :
- : "r" (LinearAddress)
- : "memory"
- );
-
- return LinearAddress;
-}
-
-
+/** @file\r
+ GCC inline implementation of BaseLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR> \r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+\r
+\r
+/**\r
+ Used to serialize load and store operations.\r
+\r
+ All loads and stores that proceed calls to this function are guaranteed to be\r
+ globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+ VOID\r
+ )\r
+{\r
+ // This is a little bit of overkill and it is more about the compiler that it is\r
+ // actually processor syncronization. This is like the _ReadWriteBarrier \r
+ // Microsft specific intrinsic\r
+ __asm__ __volatile__ ("":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+ Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("sti"::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+ Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+ VOID\r
+ )\r
+{ \r
+ __asm__ __volatile__ ("cli"::: "memory");\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("pause");\r
+}\r
+\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("int $3");\r
+}\r
+\r
+\r
+\r
+/**\r
+ Returns a 64-bit Machine Specific Register(MSR).\r
+\r
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
+ performed on Index, and some Index values may cause CPU exceptions. The\r
+ caller must either guarantee that Index is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+\r
+ @return The value of the MSR identified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr64 (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdmsr"\r
+ : "=a" (LowData), // %0\r
+ "=d" (HighData) // %1\r
+ : "c" (Index) // %2\r
+ );\r
+ \r
+ return (((UINT64)HighData) << 32) | LowData;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
+ value.\r
+\r
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The\r
+ 64-bit value written to the MSR is returned. No parameter checking is\r
+ performed on Index or Value, and some of these may cause CPU exceptions. The\r
+ caller must either guarantee that Index and Value are valid, or the caller\r
+ must establish proper exception handlers. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param Value The 64-bit value to write to the MSR.\r
+\r
+ @return Value\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+\r
+ LowData = (UINT32)(Value);\r
+ HighData = (UINT32)(Value >> 32);\r
+ \r
+ __asm__ __volatile__ (\r
+ "wrmsr"\r
+ :\r
+ : "c" (Index),\r
+ "a" (LowData),\r
+ "d" (HighData)\r
+ );\r
+ \r
+ return Value;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the EFLAGS register.\r
+\r
+ Reads and returns the current value of the EFLAGS register. This function is\r
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a\r
+ 64-bit value on X64.\r
+\r
+ @return EFLAGS on IA-32 or RFLAGS on X64.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadEflags (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Eflags;\r
+ \r
+ __asm__ __volatile__ (\r
+ "pushfq \n\t"\r
+ "pop %0 "\r
+ : "=r" (Eflags) // %0\r
+ );\r
+ \r
+ return Eflags;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 0 (CR0).\r
+\r
+ Reads and returns the current value of CR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 0 (CR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr0,%0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 2 (CR2).\r
+\r
+ Reads and returns the current value of CR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 2 (CR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr2, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads the current value of the Control Register 3 (CR3).\r
+\r
+ Reads and returns the current value of CR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 3 (CR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr3, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 4 (CR4).\r
+\r
+ Reads and returns the current value of CR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 4 (CR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr4, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 0 (CR0).\r
+\r
+ Writes and returns a new value to CR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr0 The value to write to CR0.\r
+\r
+ @return The value written to CR0.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr0 (\r
+ UINTN Cr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr0"\r
+ :\r
+ : "r" (Cr0)\r
+ );\r
+ return Cr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 2 (CR2).\r
+\r
+ Writes and returns a new value to CR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr2 The value to write to CR2.\r
+\r
+ @return The value written to CR2.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr2 (\r
+ UINTN Cr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr2"\r
+ :\r
+ : "r" (Cr2)\r
+ );\r
+ return Cr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 3 (CR3).\r
+\r
+ Writes and returns a new value to CR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr3 The value to write to CR3.\r
+\r
+ @return The value written to CR3.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr3 (\r
+ UINTN Cr3\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr3"\r
+ :\r
+ : "r" (Cr3)\r
+ );\r
+ return Cr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 4 (CR4).\r
+\r
+ Writes and returns a new value to CR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr4 The value to write to CR4.\r
+\r
+ @return The value written to CR4.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr4 (\r
+ UINTN Cr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr4"\r
+ :\r
+ : "r" (Cr4)\r
+ );\r
+ return Cr4;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 0 (DR0).\r
+\r
+ Reads and returns the current value of DR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr0, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 1 (DR1).\r
+\r
+ Reads and returns the current value of DR1. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr1 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr1, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 2 (DR2).\r
+\r
+ Reads and returns the current value of DR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr2, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 3 (DR3).\r
+\r
+ Reads and returns the current value of DR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr3, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 4 (DR4).\r
+\r
+ Reads and returns the current value of DR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr4, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 5 (DR5).\r
+\r
+ Reads and returns the current value of DR5. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr5 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr5, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 6 (DR6).\r
+\r
+ Reads and returns the current value of DR6. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr6 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr6, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 7 (DR7).\r
+\r
+ Reads and returns the current value of DR7. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr7 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr7, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 0 (DR0).\r
+\r
+ Writes and returns a new value to DR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr0 The value to write to Dr0.\r
+\r
+ @return The value written to Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr0 (\r
+ UINTN Dr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr0"\r
+ :\r
+ : "r" (Dr0)\r
+ );\r
+ return Dr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 1 (DR1).\r
+\r
+ Writes and returns a new value to DR1. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr1 The value to write to Dr1.\r
+\r
+ @return The value written to Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr1 (\r
+ UINTN Dr1\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr1"\r
+ :\r
+ : "r" (Dr1)\r
+ );\r
+ return Dr1;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 2 (DR2).\r
+\r
+ Writes and returns a new value to DR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr2 The value to write to Dr2.\r
+\r
+ @return The value written to Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr2 (\r
+ UINTN Dr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr2"\r
+ :\r
+ : "r" (Dr2)\r
+ );\r
+ return Dr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 3 (DR3).\r
+\r
+ Writes and returns a new value to DR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr3 The value to write to Dr3.\r
+\r
+ @return The value written to Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr3 (\r
+ UINTN Dr3\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr3"\r
+ :\r
+ : "r" (Dr3)\r
+ );\r
+ return Dr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 4 (DR4).\r
+\r
+ Writes and returns a new value to DR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr4 The value to write to Dr4.\r
+\r
+ @return The value written to Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr4 (\r
+ UINTN Dr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr4"\r
+ :\r
+ : "r" (Dr4)\r
+ );\r
+ return Dr4;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 5 (DR5).\r
+\r
+ Writes and returns a new value to DR5. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr5 The value to write to Dr5.\r
+\r
+ @return The value written to Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr5 (\r
+ UINTN Dr5\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr5"\r
+ :\r
+ : "r" (Dr5)\r
+ );\r
+ return Dr5;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 6 (DR6).\r
+\r
+ Writes and returns a new value to DR6. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr6 The value to write to Dr6.\r
+\r
+ @return The value written to Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr6 (\r
+ UINTN Dr6\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr6"\r
+ :\r
+ : "r" (Dr6)\r
+ );\r
+ return Dr6;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 7 (DR7).\r
+\r
+ Writes and returns a new value to DR7. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr7 The value to write to Dr7.\r
+\r
+ @return The value written to Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr7 (\r
+ UINTN Dr7\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr7"\r
+ :\r
+ : "r" (Dr7)\r
+ );\r
+ return Dr7;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Code Segment Register (CS).\r
+\r
+ Reads and returns the current value of CS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of CS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadCs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Data Segment Register (DS).\r
+\r
+ Reads and returns the current value of DS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of DS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadDs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Extra Segment Register (ES).\r
+\r
+ Reads and returns the current value of ES. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of ES.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadEs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%es, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of FS Data Segment Register (FS).\r
+\r
+ Reads and returns the current value of FS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of FS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadFs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%fs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of GS Data Segment Register (GS).\r
+\r
+ Reads and returns the current value of GS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of GS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadGs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%gs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Stack Segment Register (SS).\r
+\r
+ Reads and returns the current value of SS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of SS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadSs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Task Register (TR).\r
+\r
+ Reads and returns the current value of TR. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of TR.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadTr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "str %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Gdtr Pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadGdtr (\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sgdt %0"\r
+ : "=m" (*Gdtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
+\r
+ Writes and the current GDTR descriptor specified by Gdtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Gdtr Pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteGdtr (\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lgdt %0"\r
+ :\r
+ : "m" (*Gdtr)\r
+ );\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Idtr Pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadIdtr (\r
+ OUT IA32_DESCRIPTOR *Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sldt %0"\r
+ : "=m" (*Ldtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Writes the current IDTR descriptor and returns it in Idtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Idtr Pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteIdtr (\r
+ IN CONST IA32_DESCRIPTOR *Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lidt %0"\r
+ :\r
+ : "m" (*Ldtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Local Descriptor Table Register(LDTR) selector.\r
+\r
+ Reads and returns the current 16-bit LDTR descriptor value. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @return The current selector of LDT.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadLdtr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "sldt %0"\r
+ : "=g" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Local Descriptor Table Register (GDTR) selector.\r
+\r
+ Writes and the current LDTR descriptor specified by Ldtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Ldtr 16-bit LDTR selector value.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteLdtr (\r
+ IN UINT16 Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lldtw %0"\r
+ :\r
+ : "g" (Ldtr) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Save the current floating point/SSE/SSE2 context to a buffer.\r
+\r
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
+ available on IA-32 and X64.\r
+\r
+ @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxSave (\r
+ OUT IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxsave %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ ); \r
+}\r
+\r
+\r
+/**\r
+ Restores the current floating point/SSE/SSE2 context from a buffer.\r
+\r
+ Restores the current floating point/SSE/SSE2 state from the buffer specified\r
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxRestore (\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxrstor %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Reads and returns the current value of MM0. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm0 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm0, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Reads and returns the current value of MM1. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm1 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm1, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Reads and returns the current value of MM2. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm2 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm2, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Reads and returns the current value of MM3. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm3 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm3, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Reads and returns the current value of MM4. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm4 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm4, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Reads and returns the current value of MM5. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm5 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm5, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Reads and returns the current value of MM6. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm6 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm6, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Reads and returns the current value of MM7. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm7 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm7, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Writes the current value of MM0. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM0.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm0 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm0" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Writes the current value of MM1. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm1 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm1" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Writes the current value of MM2. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM2.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm2 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm2" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Writes the current value of MM3. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM3.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm3 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm3" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Writes the current value of MM4. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM4.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm4 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm4" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Writes the current value of MM5. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM5.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm5 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm5" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Writes the current value of MM6. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM6.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm6 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm6" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Writes the current value of MM7. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM7.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm7 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm7" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Time Stamp Counter (TSC).\r
+\r
+ Reads and returns the current value of TSC. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of TSC\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadTsc (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HiData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdtsc"\r
+ : "=a" (LowData),\r
+ "=d" (HiData)\r
+ );\r
+ \r
+ return (((UINT64)HiData) << 32) | LowData; \r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of a Performance Counter (PMC).\r
+\r
+ Reads and returns the current value of performance counter specified by\r
+ Index. This function is only available on IA-32 and X64.\r
+\r
+ @param Index The 32-bit Performance Counter index to read.\r
+\r
+ @return The value of the PMC specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmc (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HiData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdpmc"\r
+ : "=a" (LowData),\r
+ "=d" (HiData)\r
+ : "c" (Index)\r
+ );\r
+ \r
+ return (((UINT64)HiData) << 32) | LowData; \r
+}\r
+\r
+\r
+/**\r
+ Sets up a monitor buffer that is used by AsmMwait().\r
+\r
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
+ and Edx. Returns Eax. This function is only available on IA-32 and X64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+ @param Edx The value to load into EDX or RDX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmMonitor (\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "monitor"\r
+ :\r
+ : "a" (Eax),\r
+ "c" (Ecx),\r
+ "d" (Edx)\r
+ );\r
+ \r
+ return Eax;\r
+}\r
+\r
+\r
+/**\r
+ Executes an MWAIT instruction.\r
+\r
+ Executes an MWAIT instruction with the register state specified by Eax and\r
+ Ecx. Returns Eax. This function is only available on IA-32 and X64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmMwait (\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mwait"\r
+ : \r
+ : "a" (Eax),\r
+ "c" (Ecx)\r
+ );\r
+ \r
+ return Eax; \r
+}\r
+\r
+\r
+/**\r
+ Executes a WBINVD instruction.\r
+\r
+ Executes a WBINVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWbinvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("wbinvd":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Executes a INVD instruction.\r
+\r
+ Executes a INVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmInvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("invd":::"memory");\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Flushes a cache line from all the instruction and data caches within the\r
+ coherency domain of the CPU.\r
+\r
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+ This function is only available on IA-32 and X64.\r
+\r
+ @param LinearAddress The address of the cache line to flush. If the CPU is\r
+ in a physical addressing mode, then LinearAddress is a\r
+ physical address. If the CPU is in a virtual\r
+ addressing mode, then LinearAddress is a virtual\r
+ address.\r
+\r
+ @return LinearAddress\r
+**/\r
+VOID *\r
+EFIAPI\r
+AsmFlushCacheLine (\r
+ IN VOID *LinearAddress\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "clflush (%0)"\r
+ :\r
+ : "r" (LinearAddress) \r
+ : "memory"\r
+ );\r
+ \r
+ return LinearAddress;\r
+}\r
+\r
+\r
loaded into memory or is executing at it's linked address.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY));\r
case CODEVIEW_SIGNATURE_RSDS:\r
return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY));\r
- case CODEVIEW_SIGNATURE_MTOC:
- return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));
+ case CODEVIEW_SIGNATURE_MTOC:\r
+ return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));\r
default:\r
break;\r
}\r
-/** @file
- Specific relocation fixups for ARM architecture.
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BasePeCoffLibInternals.h"
-
-
-/**
- Performs an ARM-based specific relocation fixup and is a no-op on other
- instruction sets.
-
- @param Reloc Pointer to the relocation record.
- @param Fixup Pointer to the address to fix up.
- @param FixupData Pointer to a buffer to log the fixups.
- @param Adjust The offset to adjust the fixup.
-
- @return Status code.
-
-**/
-RETURN_STATUS
-PeCoffLoaderRelocateImageEx (
- IN UINT16 *Reloc,
- IN OUT CHAR8 *Fixup,
- IN OUT CHAR8 **FixupData,
- IN UINT64 Adjust
- )
-{
- return RETURN_UNSUPPORTED;
-}
-
-/**
- Returns TRUE if the machine type of PE/COFF image is supported. Supported
- does not mean the image can be executed it means the PE/COFF loader supports
- loading and relocating of the image type. It's up to the caller to support
- the entry point.
-
- The IA32/X64 version PE/COFF loader/relocater both support IA32, X64 and EBC images.
-
- @param Machine Machine type from the PE Header.
-
- @return TRUE if this PE/COFF loader can load the image
-
-**/
-BOOLEAN
-PeCoffLoaderImageFormatSupported (
- IN UINT16 Machine
- )
-{
- if ((Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) || (Machine == IMAGE_FILE_MACHINE_EBC)) {
- return TRUE;
- }
-
- return FALSE;
-}
-
-/**
- Performs an ARM-based specific re-relocation fixup and is a no-op on other
- instruction sets. This is used to re-relocated the image into the EFI virtual
- space for runtime calls.
-
- @param Reloc Pointer to the relocation record.
- @param Fixup Pointer to the address to fix up.
- @param FixupData Pointer to a buffer to log the fixups.
- @param Adjust The offset to adjust the fixup.
-
- @return Status code.
-
-**/
-RETURN_STATUS
-PeHotRelocateImageEx (
- IN UINT16 *Reloc,
- IN OUT CHAR8 *Fixup,
- IN OUT CHAR8 **FixupData,
- IN UINT64 Adjust
- )
-{
- return RETURN_UNSUPPORTED;
-}
-
+/** @file\r
+ Specific relocation fixups for ARM architecture.\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BasePeCoffLibInternals.h"\r
+\r
+\r
+/**\r
+ Performs an ARM-based specific relocation fixup and is a no-op on other\r
+ instruction sets.\r
+\r
+ @param Reloc Pointer to the relocation record.\r
+ @param Fixup Pointer to the address to fix up.\r
+ @param FixupData Pointer to a buffer to log the fixups.\r
+ @param Adjust The offset to adjust the fixup.\r
+\r
+ @return Status code.\r
+\r
+**/\r
+RETURN_STATUS\r
+PeCoffLoaderRelocateImageEx (\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
+ )\r
+{\r
+ return RETURN_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported\r
+ does not mean the image can be executed it means the PE/COFF loader supports\r
+ loading and relocating of the image type. It's up to the caller to support\r
+ the entry point.\r
+ \r
+ The IA32/X64 version PE/COFF loader/relocater both support IA32, X64 and EBC images.\r
+\r
+ @param Machine Machine type from the PE Header.\r
+\r
+ @return TRUE if this PE/COFF loader can load the image\r
+\r
+**/\r
+BOOLEAN\r
+PeCoffLoaderImageFormatSupported (\r
+ IN UINT16 Machine\r
+ )\r
+{\r
+ if ((Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) || (Machine == IMAGE_FILE_MACHINE_EBC)) {\r
+ return TRUE; \r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Performs an ARM-based specific re-relocation fixup and is a no-op on other\r
+ instruction sets. This is used to re-relocated the image into the EFI virtual\r
+ space for runtime calls.\r
+\r
+ @param Reloc Pointer to the relocation record.\r
+ @param Fixup Pointer to the address to fix up.\r
+ @param FixupData Pointer to a buffer to log the fixups.\r
+ @param Adjust The offset to adjust the fixup.\r
+\r
+ @return Status code.\r
+\r
+**/\r
+RETURN_STATUS\r
+PeHotRelocateImageEx (\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
+ )\r
+{\r
+ return RETURN_UNSUPPORTED;\r
+}\r
+\r
only supports relocating IA32, x64, IPF, and EBC images.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);\r
break;\r
\r
- case CODEVIEW_SIGNATURE_MTOC:
+ case CODEVIEW_SIGNATURE_MTOC:\r
ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);\r
- break;
-
+ break;\r
+\r
default:\r
break;\r
}\r
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.\r
#\r
# Copyright (c) 2006 - 2009, Intel Corporation.<BR>\r
-# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+# Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
[Sources.IPF]\r
Ipf/PeCoffLoaderEx.c\r
\r
-[Sources.ARM]
- Arm/PeCoffLoaderEx.c
-
+[Sources.ARM]\r
+ Arm/PeCoffLoaderEx.c\r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
Base Print Library instance implementation.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PrintLibInternal.h"\r
\r
-//
+//\r
// Declare a VA_LIST global variable that is used in calls to BasePrintLibSPrintMarker()\r
// when the BASE_LIST parameter is valid and the VA_LIST parameter is ignored. \r
// A NULL VA_LIST can not be passed into BasePrintLibSPrintMarker() because some \r
-// compilers define VA_LIST to be a structure.
-//
+// compilers define VA_LIST to be a structure.\r
+//\r
VA_LIST gNullVaList;\r
-
+\r
#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)\r
\r
/**\r
{\r
ASSERT_UNICODE_BUFFER (StartOfBuffer);\r
ASSERT_UNICODE_BUFFER (FormatString);\r
- return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, FORMAT_UNICODE | OUTPUT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
+ return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, FORMAT_UNICODE | OUTPUT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);\r
}\r
\r
/**\r
)\r
{\r
ASSERT_UNICODE_BUFFER (StartOfBuffer);\r
- return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, OUTPUT_UNICODE, FormatString, gNullVaList, Marker);
+ return BasePrintLibSPrintMarker ((CHAR8 *)StartOfBuffer, BufferSize >> 1, OUTPUT_UNICODE, FormatString, gNullVaList, Marker);\r
}\r
\r
/**\r
IN BASE_LIST Marker\r
)\r
{\r
- return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);
+ return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);\r
}\r
\r
/**\r
)\r
{\r
ASSERT_UNICODE_BUFFER (FormatString);\r
- return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, FORMAT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);
+ return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, FORMAT_UNICODE, (CHAR8 *)FormatString, gNullVaList, Marker);\r
}\r
\r
/**\r
-/** @file
- Implementation of synchronization functions. Still needs to be ported
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-UINT32
-EFIAPI
-InternalSyncCompareExchange32 (
- IN volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
- )
-{
- return *Value != CompareValue ? *Value :
- ((*Value = ExchangeValue), CompareValue);
-}
-
-/**
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.
-
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
- The compare exchange operation must be performed using MP safe mechanisms.
-
- @param Value A pointer to the 64-bit value for the compare exchange
- operation.
- @param CompareValue 64-bit value used in compare operation.
- @param ExchangeValue 64-bit value used in exchange operation.
-
- @return The original *Value before exchange.
-
-**/
-UINT64
-EFIAPI
-InternalSyncCompareExchange64 (
- IN volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
- )
-{
- return *Value != CompareValue ? *Value :
- ((*Value = ExchangeValue), CompareValue);
-}
-
-/**
- Performs an atomic increment of an 32-bit unsigned integer.
-
- Performs an atomic increment of the 32-bit unsigned integer specified by
- Value and returns the incremented value. The increment operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to increment.
-
- @return The incremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncIncrement (
- IN volatile UINT32 *Value
- )
-{
- return ++*Value;
-}
-
-/**
- Performs an atomic decrement of an 32-bit unsigned integer.
-
- Performs an atomic decrement of the 32-bit unsigned integer specified by
- Value and returns the decrement value. The decrement operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to decrement.
-
- @return The decrement value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncDecrement (
- IN volatile UINT32 *Value
- )
-{
- return --*Value;
-}
+/** @file\r
+ Implementation of synchronization functions. Still needs to be ported\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR> \r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+UINT32\r
+EFIAPI\r
+InternalSyncCompareExchange32 (\r
+ IN volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
+ )\r
+{\r
+ return *Value != CompareValue ? *Value :\r
+ ((*Value = ExchangeValue), CompareValue);\r
+}\r
+\r
+/**\r
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
+\r
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified \r
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and \r
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned. \r
+ The compare exchange operation must be performed using MP safe mechanisms.\r
+\r
+ @param Value A pointer to the 64-bit value for the compare exchange\r
+ operation.\r
+ @param CompareValue 64-bit value used in compare operation.\r
+ @param ExchangeValue 64-bit value used in exchange operation.\r
+\r
+ @return The original *Value before exchange.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalSyncCompareExchange64 (\r
+ IN volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
+ )\r
+{\r
+ return *Value != CompareValue ? *Value :\r
+ ((*Value = ExchangeValue), CompareValue);\r
+}\r
+\r
+/**\r
+ Performs an atomic increment of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic increment of the 32-bit unsigned integer specified by\r
+ Value and returns the incremented value. The increment operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to increment.\r
+\r
+ @return The incremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncIncrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ return ++*Value;\r
+}\r
+\r
+/**\r
+ Performs an atomic decrement of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic decrement of the 32-bit unsigned integer specified by\r
+ Value and returns the decrement value. The decrement operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to decrement.\r
+\r
+ @return The decrement value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncDecrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ return --*Value;\r
+}\r
-/** @file
- GCC inline implementation of BaseSynchronizationLib processor specific functions.
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-
-/**
- Performs an atomic increment of an 32-bit unsigned integer.
-
- Performs an atomic increment of the 32-bit unsigned integer specified by
- Value and returns the incremented value. The increment operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to increment.
-
- @return The incremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncIncrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 Result;
-
- __asm__ __volatile__ (
- "lock \n\t"
- "incl %2 \n\t"
- "movl %2, %%eax "
- : "=a" (Result), // %0
- "=m" (*Value) // %1
- : "m" (*Value) // %2
- : "memory",
- "cc"
- );
-
- return Result;
-
-}
-
-
-/**
- Performs an atomic decrement of an 32-bit unsigned integer.
-
- Performs an atomic decrement of the 32-bit unsigned integer specified by
- Value and returns the decremented value. The decrement operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to decrement.
-
- @return The decremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncDecrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 Result;
-
- __asm__ __volatile__ (
- "lock \n\t"
- "decl %2 \n\t"
- "movl %2, %%eax "
- : "=a" (Result), // %0
- "=m" (*Value) // %1
- : "m" (*Value) // %2
- : "memory",
- "cc"
- );
-
- return Result;
-}
-
-/**
- Performs an atomic compare exchange operation on a 32-bit unsigned integer.
-
- Performs an atomic compare exchange operation on the 32-bit unsigned integer
- specified by Value. If Value is equal to CompareValue, then Value is set to
- ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
- then Value is returned. The compare exchange operation must be performed using
- MP safe mechanisms.
-
-
- @param Value A pointer to the 32-bit value for the compare exchange
- operation.
- @param CompareValue 32-bit value used in compare operation.
- @param ExchangeValue 32-bit value used in exchange operation.
-
- @return The original *Value before exchange.
-
-**/
-UINT32
-EFIAPI
-InternalSyncCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
- )
-{
-
-// GCC 4.1 and forward supports atomic builtins
-#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
-
- return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
-
-#else
-
- __asm__ __volatile__ (
- " \n\t"
- "lock \n\t"
- "cmpxchgl %1, %2 \n\t"
- : "=a" (CompareValue) // %0
- : "q" (ExchangeValue), // %1
- "m" (*Value),m // %2
- "0" (CompareValue) // %4
- : "memory",
- "cc"
- );
-
- return CompareValue;
-
-#endif
-}
-
-/**
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.
-
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
- The compare exchange operation must be performed using MP safe mechanisms.
-
-
- @param Value A pointer to the 64-bit value for the compare exchange
- operation.
- @param CompareValue 64-bit value used in compare operation.
- @param ExchangeValue 64-bit value used in exchange operation.
-
- @return The original *Value before exchange.
-
-**/
-UINT64
-EFIAPI
-InternalSyncCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
- )
-{
-// GCC 4.1 and forward supports atomic builtins
-#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
-
- return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
-
-#else
-
- __asm__ __volatile__ (
- " \n\t"
- "push %%ebx \n\t"
- "movl %2,%%ebx \n\t"
- "lock \n\t"
- "cmpxchg8b (%1) \n\t"
- "pop %%ebx \n\t"
- : "+A" (CompareValue) // %0
- : "S" (Value), // %1
- "r" ((UINT32) ExchangeValue), // %2
- "c" ((UINT32) (ExchangeValue >> 32)) // %3
- : "memory",
- "cc"
- );
-
- return CompareValue;
-
-#endif
-}
-
-
+/** @file\r
+ GCC inline implementation of BaseSynchronizationLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+/**\r
+ Performs an atomic increment of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic increment of the 32-bit unsigned integer specified by\r
+ Value and returns the incremented value. The increment operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to increment.\r
+\r
+ @return The incremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncIncrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ UINT32 Result;\r
+\r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "incl %2 \n\t"\r
+ "movl %2, %%eax "\r
+ : "=a" (Result), // %0\r
+ "=m" (*Value) // %1\r
+ : "m" (*Value) // %2 \r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return Result; \r
+\r
+}\r
+\r
+\r
+/**\r
+ Performs an atomic decrement of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic decrement of the 32-bit unsigned integer specified by\r
+ Value and returns the decremented value. The decrement operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to decrement.\r
+\r
+ @return The decremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncDecrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ UINT32 Result;\r
+ \r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "decl %2 \n\t"\r
+ "movl %2, %%eax "\r
+ : "=a" (Result), // %0\r
+ "=m" (*Value) // %1\r
+ : "m" (*Value) // %2 \r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return Result;\r
+}\r
+\r
+/**\r
+ Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
+\r
+ Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
+ specified by Value. If Value is equal to CompareValue, then Value is set to\r
+ ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
+ then Value is returned. The compare exchange operation must be performed using\r
+ MP safe mechanisms.\r
+\r
+\r
+ @param Value A pointer to the 32-bit value for the compare exchange\r
+ operation.\r
+ @param CompareValue 32-bit value used in compare operation.\r
+ @param ExchangeValue 32-bit value used in exchange operation.\r
+\r
+ @return The original *Value before exchange.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncCompareExchange32 (\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
+ )\r
+{\r
+\r
+// GCC 4.1 and forward supports atomic builtins \r
+#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))\r
+\r
+ return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);\r
+\r
+#else\r
+\r
+ __asm__ __volatile__ (\r
+ " \n\t"\r
+ "lock \n\t"\r
+ "cmpxchgl %1, %2 \n\t"\r
+ : "=a" (CompareValue) // %0\r
+ : "q" (ExchangeValue), // %1\r
+ "m" (*Value),m // %2\r
+ "0" (CompareValue) // %4 \r
+ : "memory",\r
+ "cc"\r
+ );\r
+\r
+ return CompareValue;\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
+\r
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
+ The compare exchange operation must be performed using MP safe mechanisms.\r
+\r
+\r
+ @param Value A pointer to the 64-bit value for the compare exchange\r
+ operation.\r
+ @param CompareValue 64-bit value used in compare operation.\r
+ @param ExchangeValue 64-bit value used in exchange operation.\r
+\r
+ @return The original *Value before exchange.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalSyncCompareExchange64 (\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
+ )\r
+{\r
+// GCC 4.1 and forward supports atomic builtins \r
+#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))\r
+\r
+ return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);\r
+\r
+#else\r
+\r
+ __asm__ __volatile__ (\r
+ " \n\t"\r
+ "push %%ebx \n\t" \r
+ "movl %2,%%ebx \n\t" \r
+ "lock \n\t"\r
+ "cmpxchg8b (%1) \n\t"\r
+ "pop %%ebx \n\t"\r
+ : "+A" (CompareValue) // %0\r
+ : "S" (Value), // %1\r
+ "r" ((UINT32) ExchangeValue), // %2\r
+ "c" ((UINT32) (ExchangeValue >> 32)) // %3\r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return CompareValue;\r
+\r
+#endif\r
+}\r
+\r
+\r
Implementation of synchronization functions.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// GCC inline assembly for Read Write Barrier \r
//\r
-#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
+#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)\r
\r
#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
-/** @file
- GCC inline implementation of BaseSynchronizationLib processor specific functions.
-
- Copyright (c) 2006 - 2009, Intel Corporation<BR>
- Portions copyright (c) 2008-2009 Apple Inc.<BR>
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-
-
-/**
- Performs an atomic increment of an 32-bit unsigned integer.
-
- Performs an atomic increment of the 32-bit unsigned integer specified by
- Value and returns the incremented value. The increment operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to increment.
-
- @return The incremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncIncrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 Result;
-
- __asm__ __volatile__ (
- "lock \n\t"
- "incl %2 \n\t"
- "mov %2, %%eax "
- : "=a" (Result), // %0
- "=m" (*Value) // %1
- : "m" (*Value) // %2
- : "memory",
- "cc"
- );
-
- return Result;
-
-}
-
-
-/**
- Performs an atomic decrement of an 32-bit unsigned integer.
-
- Performs an atomic decrement of the 32-bit unsigned integer specified by
- Value and returns the decremented value. The decrement operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to decrement.
-
- @return The decremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncDecrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 Result;
-
- __asm__ __volatile__ (
- "lock \n\t"
- "decl %2 \n\t"
- "mov %2, %%eax "
- : "=a" (Result), // %0
- "=m" (*Value) // %1
- : "m" (*Value) // %2
- : "memory",
- "cc"
- );
-
- return Result;
-}
-
-
-/**
- Performs an atomic compare exchange operation on a 32-bit unsigned integer.
-
- Performs an atomic compare exchange operation on the 32-bit unsigned integer
- specified by Value. If Value is equal to CompareValue, then Value is set to
- ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
- then Value is returned. The compare exchange operation must be performed using
- MP safe mechanisms.
-
-
- @param Value A pointer to the 32-bit value for the compare exchange
- operation.
- @param CompareValue 32-bit value used in compare operation.
- @param ExchangeValue 32-bit value used in exchange operation.
-
- @return The original *Value before exchange.
-
-**/
-UINT32
-EFIAPI
-InternalSyncCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
- )
-{
-// GCC 4.1 and forward supports atomic builtins
-#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
-
- return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
-
-#else
-
- __asm__ __volatile__ (
- "lock \n\t"
- "cmpxchgl %3, %1 "
- : "=a" (CompareValue), // %0
- "=m" (*Value) // %1
- : "a" (CompareValue), // %2
- "r" (ExchangeValue), // %3
- "m" (*Value)
- : "memory",
- "cc"
- );
-
- return CompareValue;
-
-#endif
-}
-
-
-/**
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.
-
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
- The compare exchange operation must be performed using MP safe mechanisms.
-
-
- @param Value A pointer to the 64-bit value for the compare exchange
- operation.
- @param CompareValue 64-bit value used in compare operation.
- @param ExchangeValue 64-bit value used in exchange operation.
-
- @return The original *Value before exchange.
-
-**/
-UINT64
-EFIAPI
-InternalSyncCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
- )
-{
-// GCC 4.1 and forward supports atomic builtins
-#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))
-
- return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);
-
-#else
-
- __asm__ __volatile__ (
- "lock \n\t"
- "cmpxchgq %3, %1 "
- : "=a" (CompareValue), // %0
- "=m" (*Value) // %1
- : "a" (CompareValue), // %2
- "r" (ExchangeValue), // %3
- "m" (*Value)
- : "memory",
- "cc"
- );
-
- return CompareValue;
-
-#endif
-}
-
-
+/** @file\r
+ GCC inline implementation of BaseSynchronizationLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ Portions copyright (c) 2008-2009 Apple Inc.<BR> \r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+/**\r
+ Performs an atomic increment of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic increment of the 32-bit unsigned integer specified by\r
+ Value and returns the incremented value. The increment operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to increment.\r
+\r
+ @return The incremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncIncrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ UINT32 Result;\r
+\r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "incl %2 \n\t"\r
+ "mov %2, %%eax "\r
+ : "=a" (Result), // %0\r
+ "=m" (*Value) // %1\r
+ : "m" (*Value) // %2 \r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return Result; \r
+\r
+}\r
+\r
+\r
+/**\r
+ Performs an atomic decrement of an 32-bit unsigned integer.\r
+\r
+ Performs an atomic decrement of the 32-bit unsigned integer specified by\r
+ Value and returns the decremented value. The decrement operation must be\r
+ performed using MP safe mechanisms. The state of the return value is not\r
+ guaranteed to be MP safe.\r
+\r
+ @param Value A pointer to the 32-bit value to decrement.\r
+\r
+ @return The decremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncDecrement (\r
+ IN volatile UINT32 *Value\r
+ )\r
+{\r
+ UINT32 Result;\r
+ \r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "decl %2 \n\t"\r
+ "mov %2, %%eax "\r
+ : "=a" (Result), // %0\r
+ "=m" (*Value) // %1\r
+ : "m" (*Value) // %2 \r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
+\r
+ Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
+ specified by Value. If Value is equal to CompareValue, then Value is set to\r
+ ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
+ then Value is returned. The compare exchange operation must be performed using\r
+ MP safe mechanisms.\r
+\r
+\r
+ @param Value A pointer to the 32-bit value for the compare exchange\r
+ operation.\r
+ @param CompareValue 32-bit value used in compare operation.\r
+ @param ExchangeValue 32-bit value used in exchange operation.\r
+\r
+ @return The original *Value before exchange.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncCompareExchange32 (\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
+ )\r
+{\r
+// GCC 4.1 and forward supports atomic builtins \r
+#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))\r
+\r
+ return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);\r
+\r
+#else\r
+\r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "cmpxchgl %3, %1 "\r
+ : "=a" (CompareValue), // %0\r
+ "=m" (*Value) // %1\r
+ : "a" (CompareValue), // %2\r
+ "r" (ExchangeValue), // %3 \r
+ "m" (*Value)\r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return CompareValue;\r
+\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
+\r
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
+ The compare exchange operation must be performed using MP safe mechanisms.\r
+\r
+\r
+ @param Value A pointer to the 64-bit value for the compare exchange\r
+ operation.\r
+ @param CompareValue 64-bit value used in compare operation.\r
+ @param ExchangeValue 64-bit value used in exchange operation.\r
+\r
+ @return The original *Value before exchange.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalSyncCompareExchange64 (\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
+ )\r
+{\r
+// GCC 4.1 and forward supports atomic builtins \r
+#if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)))\r
+\r
+ return __sync_val_compare_and_swap (Value, CompareValue, ExchangeValue);\r
+\r
+#else\r
+\r
+ __asm__ __volatile__ (\r
+ "lock \n\t"\r
+ "cmpxchgq %3, %1 "\r
+ : "=a" (CompareValue), // %0\r
+ "=m" (*Value) // %1\r
+ : "a" (CompareValue), // %2\r
+ "r" (ExchangeValue), // %3 \r
+ "m" (*Value)\r
+ : "memory",\r
+ "cc"\r
+ );\r
+ \r
+ return CompareValue;\r
+\r
+#endif\r
+}\r
+\r
+\r
UEFI Decompress Library implementation refer to UEFI specification.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
- Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+ Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
CharC = (UINT16) GetBits (Sd, nbit);\r
\r
- SetMem16 (&Sd->mPTTable[0] , sizeof (Sd->mPTTable), CharC);
+ SetMem16 (&Sd->mPTTable[0] , sizeof (Sd->mPTTable), CharC);\r
\r
SetMem (Sd->mPTLen, nn, 0);\r
\r
CharC = (UINT16) GetBits (Sd, CBIT);\r
\r
SetMem (Sd->mCLen, NC, 0);\r
- SetMem16 (&Sd->mCTable[0], sizeof (Sd->mCTable), CharC);
+ SetMem16 (&Sd->mCTable[0], sizeof (Sd->mCTable), CharC);\r
\r
return ;\r
}\r
# EFI/PI MdePkg Package\r
#\r
# Copyright (c) 2007 - 2009, Intel Corporation<BR>\r
-# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
+# Portions Copyright (c) 2008-2009 Apple Inc.<BR>\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
PLATFORM_VERSION = 1.01\r
DSC_SPECIFICATION = 0x00010005\r
OUTPUT_DIRECTORY = Build/Mde\r
- SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM
+ SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM\r
BUILD_TARGETS = DEBUG|RELEASE\r
SKUID_IDENTIFIER = DEFAULT\r
\r
projects / mirror_edk2.git / commitdiff