Because the D&I caches were clean before to be disabled, the cache
lines might have got dirty during the cache maintenance operations.
This fix disables D&I caches before to clean them. The performance
drops should be minimised as invalidating the I cache is only a
couple of instruction.
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13503
6f19259b-4bc3-4df7-8a09-
765794883524
//Note: Interrupts will be disabled by the GIC driver when ExitBootServices() will be called.
// Clean, invalidate, disable data cache
- ArmCleanInvalidateDataCache();
ArmDisableDataCache();
+ ArmCleanInvalidateDataCache();
// Invalidate and disable the Instruction cache
- ArmInvalidateInstructionCache ();
ArmDisableInstructionCache ();
+ ArmInvalidateInstructionCache ();
// Turn off MMU
ArmDisableMmu();