\r
**/\r
\r
+//\r
+// This size must be at or below the smallest cache size possible among all\r
+// supported processors\r
+//\r
+#define CACHE_LINE_SIZE 0x20\r
+\r
/**\r
Invalidates the entire instruction cache in cache coherency domain of the\r
calling CPU.\r
IN UINTN Length\r
)\r
{\r
- UINT8 (*Uint8Ptr)[32];\r
+ UINTN Start, End;\r
\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
\r
- Uint8Ptr = Address;\r
- while (Length > sizeof (*Uint8Ptr)) {\r
- AsmFlushCacheLine (Uint8Ptr++);\r
- Length -= sizeof (*Uint8Ptr);\r
- }\r
- if (Length > 0) {\r
- AsmFlushCacheLine (Uint8Ptr);\r
- AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);\r
+ if (Length == 0) {\r
+ return Address;\r
}\r
+\r
+ Start = (UINTN)Address;\r
+ End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
+ Start &= ~(CACHE_LINE_SIZE - 1);\r
+\r
+ do {\r
+ Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
+ } while (Start != End);\r
return Address;\r
}\r
\r