Fixed a bug in WriteBackInvalidDataCache() that always flush cache lines even when...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1504 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
index 3879cdfa2d2b05927f32e71324de2f8bfbd80005..6e812c99c3a75562367fe293f94b023af433bdf3 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
@@ -14,6 +14,12 @@
 \r
 **/\r
 \r
 \r
 **/\r
 \r

+//\r
+// This size must be at or below the smallest cache size possible among all\r
+// supported processors\r
+//\r
+#define CACHE_LINE_SIZE             0x20\r
+\r

 /**\r
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 /**\r
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r


@@ -118,19 +124,21 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
   IN      UINTN                     Length\r
   )\r
 {\r

-  UINT8                             (*Uint8Ptr)[32];\r
+  UINTN                             Start, End;\r

 \r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r
 \r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r

-  Uint8Ptr = Address;\r
-  while (Length > sizeof (*Uint8Ptr)) {\r
-    AsmFlushCacheLine (Uint8Ptr++);\r
-    Length -= sizeof (*Uint8Ptr);\r
-  }\r
-  if (Length > 0) {\r
-    AsmFlushCacheLine (Uint8Ptr);\r
-    AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);\r
+  if (Length == 0) {\r
+    return Address;\r

   }\r
   }\r

+\r
+  Start = (UINTN)Address;\r
+  End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
+  Start &= ~(CACHE_LINE_SIZE - 1);\r
+\r
+  do {\r
+    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
+  } while (Start != End);\r

   return Address;\r
 }\r
 \r
   return Address;\r
 }\r
 \r