SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support

1. Report TPM SIRQ interrupt resource through _CRS
2. Expose _SRS to update interrupt resource & FIFO/TIS interrupt related registers
   defined in TCG PC Client Platform TPM Profile (PTP) Specification spec
https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2-0-v43-150126.pdf
Note: IHV/OEM need to carefully verify this feature with OS TPM driver to make sure there is no impact to system/HW

Cc: Long Qin <qin.long@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Long Qin <qin.long@intel.com>

diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
index cf0642e10457e510642be55e4fa77c7a5b1b29b0..68b5073da6e2f9cd8bab47f967dfd66952b743b3 100644 (file)
--- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
+++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
@@ -43,13 +43,6 @@ DefinitionBlock (
       //\r
       Name (_STR, Unicode ("TPM 2.0 Device"))\r
 \r
-      //\r
-      // Return the resource consumed by TPM device\r
-      //\r
-      Name (_CRS, ResourceTemplate () {\r
-        Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
-      })\r
-\r
       //\r
       // Operational region for Smi port access\r
       //\r
@@ -65,7 +58,19 @@ DefinitionBlock (
       OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
       Field (TPMR, AnyAcc, NoLock, Preserve)\r
       {\r
-        ACC0, 8,\r
+        ACC0, 8,  // TPM_ACCESS_0\r
+        Offset(0x8),\r
+        INTE, 32, // TPM_INT_ENABLE_0\r
+        INTV, 8,  // TPM_INT_VECTOR_0\r
+        Offset(0x10),\r
+        INTS, 32, // TPM_INT_STATUS_0\r
+        INTF, 32, // TPM_INTF_CAPABILITY_0\r
+        STS0, 32, // TPM_STS_0\r
+        Offset(0x24),\r
+        FIFO, 32, // TPM_DATA_FIFO_0\r
+        Offset(0x30),\r
+        TID0, 32, // TPM_INTERFACE_ID_0\r
+                  // ignore the rest\r
       }\r
 \r
       //\r
@@ -89,6 +94,97 @@ DefinitionBlock (
         UCRQ,   32  //   Phyical Presence request operation to Get User Confirmation Status \r
       }\r
 \r
+      Name(RESO, ResourceTemplate () {\r
+        Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)\r
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}\r
+      })\r
+\r
+      //\r
+      // Return the resource consumed by TPM device.\r
+      //\r
+      Method(_CRS,0,Serialized)\r
+      {\r
+        Return(RESO)\r
+      }\r
+\r
+      //\r
+      // Set resources consumed by the TPM device. This is used to\r
+      // assign an interrupt number to the device. The input byte stream\r
+      // has to be the same as returned by _CRS (according to ACPI spec).\r
+      //\r
+      Method(_SRS,1,Serialized)\r
+      {\r
+        //\r
+        // Update resource descriptor\r
+        // Use the field name to identify the offsets in the argument\r
+        // buffer and RESO buffer.\r
+        //\r
+        CreateDWordField(Arg0, ^IRQ._INT, IRQ0)\r
+        CreateDWordField(RESO, ^IRQ._INT, LIRQ)\r
+        Store(IRQ0, LIRQ)\r
+\r
+        CreateBitField(Arg0, ^IRQ._HE, ITRG)\r
+        CreateBitField(RESO, ^IRQ._HE, LTRG)\r
+        Store(ITRG, LTRG)\r
+\r
+        CreateBitField(Arg0, ^IRQ._LL, ILVL)\r
+        CreateBitField(RESO, ^IRQ._LL, LLVL)\r
+        Store(ILVL, LLVL)\r
+\r
+        //\r
+        // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
+        // nibble.\r
+        // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
+        // 1111 - FIFO interface as defined in TIS1.3 is active\r
+        //\r
+        If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
+          //\r
+          // If FIFO interface, interrupt vector register is\r
+          // available. TCG PTP specification allows only\r
+          // values 1..15 in this field. For other interrupts\r
+          // the field should stay 0.\r
+          //\r
+          If (LLess (IRQ0, 16)) {\r
+            Store (And(IRQ0, 0xF), INTV)\r
+          }\r
+          //\r
+          // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
+          // contains settings for interrupt polarity.\r
+          // The other bits of the byte enable individual interrupts.\r
+          // They should be all be zero, but to avoid changing the\r
+          // configuration, the other bits are be preserved.\r
+          // 00 - high level\r
+          // 01 - low level\r
+          // 10 - rising edge\r
+          // 11 - falling edge\r
+          //\r
+          // ACPI spec definitions:\r
+          // _HE: '1' is Edge, '0' is Level\r
+          // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
+          //\r
+          If (LEqual (ITRG, 1)) {\r
+            Or(INTE, 0x00000010, INTE)\r
+          } Else {\r
+            And(INTE, 0xFFFFFFEF, INTE)\r
+          }\r
+          if (LEqual (ILVL, 0)) {\r
+            Or(INTE, 0x00000008, INTE)\r
+          } Else {\r
+            And(INTE, 0xFFFFFFF7, INTE)\r
+          }\r
+        }\r
+      }\r
+\r
+      //\r
+      // Possible resource settings.\r
+      // The format of the data has to follow the same format as\r
+      // _CRS (according to ACPI spec).\r
+      //\r
+      Name (_PRS, ResourceTemplate() {\r
+        Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
+      })\r
+\r
       Method (PTS, 1, Serialized)\r
       {  \r
         //\r