\r
#include <Base.h>\r
#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
#include <Library/PrintLib.h>\r
\r
extern CHAR8 *gCondition[];\r
\r
// Thumb address modes\r
#define LOAD_STORE_FORMAT1 1\r
+#define LOAD_STORE_FORMAT1_H 101\r
+#define LOAD_STORE_FORMAT1_B 111 \r
#define LOAD_STORE_FORMAT2 2\r
#define LOAD_STORE_FORMAT3 3\r
#define LOAD_STORE_FORMAT4 4\r
#define SRS_FORMAT 215\r
#define RFE_FORMAT 216\r
#define LDRD_REG_IMM8_SIGNED 217\r
-\r
-\r
-\r
+#define ADD_IMM12 218\r
+#define ADD_IMM5 219\r
+#define ADR_THUMB2 220\r
+#define CMN_THUMB2 221\r
\r
typedef struct {\r
CHAR8 *Start;\r
{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },\r
{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },\r
- { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },\r
+ { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },\r
{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },\r
- { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },\r
+ { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },\r
{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },\r
{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },\r
- { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },\r
+ { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B },\r
{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
- { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },\r
+ { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H },\r
{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },\r
\r
{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },\r
\r
THUMB_INSTRUCTIONS gOpThumb2[] = {\r
//Instruct OpCode OpCode Mask Addressig Mode\r
+ \r
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW \r
+ { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, <Rm>, {,<shift> #<const>} ;Needs to go before ADD\r
+\r
+ { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
+ { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
+ { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>\r
+ { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>\r
+ { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>\r
+ { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>\r
+ { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>\r
+ { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>\r
+ { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>\r
+ { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>\r
+ { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+ { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>\r
+ { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
+\r
{ "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>\r
{ "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>\r
{ "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>\r
{ "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}\r
};\r
\r
+CHAR8 *gShiftType[] = {\r
+ "LSL",\r
+ "LSR",\r
+ "ASR",\r
+ "ROR"\r
+};\r
+\r
CHAR8 mThumbMregListStr[4*15 + 1];\r
\r
CHAR8 *\r
Str = mThumbMregListStr;\r
*Str = '\0';\r
AsciiStrCat (Str, "{");\r
- // R0 - R7, PC\r
+ \r
for (Index = 0, First = TRUE; Index <= 15; Index++) {\r
if ((RegBitMask & (1 << Index)) != 0) {\r
Start = End = Index;\r
return Data;\r
}\r
\r
+//\r
+// Some instructions specify the PC is always considered aligned \r
+// The PC is after the instruction that is excuting. So you pass\r
+// in the instruction address and you get back the aligned answer\r
+//\r
+PCAlign4 (\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ return (Data + 4) & 0xfffffffc;\r
+}\r
+\r
/**\r
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
point to next instructin. \r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c); \r
return;\r
+ case LOAD_STORE_FORMAT1_H:\r
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3f); \r
+ return;\r
+ case LOAD_STORE_FORMAT1_B:\r
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f); \r
+ return;\r
+\r
case LOAD_STORE_FORMAT2:\r
// A6.5.1 <Rd>, [<Rn>, <Rm>]\r
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm); \r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 2 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target); \r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 2 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target); \r
return;\r
\r
case LOAD_STORE_MULTIPLE_FORMAT1:\r
case ADR_FORMAT:\r
// ADR <Rd>, <Label>\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target); \r
return;\r
}\r
}\r
*OpCodePtrPtr += 1;\r
Rt = (OpCode32 >> 12) & 0xf;\r
Rt2 = (OpCode32 >> 8) & 0xf;\r
+ Rd = (OpCode32 >> 8) & 0xf;\r
Rm = (OpCode32 & 0xf);\r
Rn = (OpCode32 >> 16) & 0xf;\r
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
return;\r
\r
case BL_T2:\r
- // S:I1:I2:imm10:imm11:00\r
- Target = ((OpCode32 << 2) & 0x1ffc) + ((OpCode32 >> 3) & 0x7fe000);\r
+ // BLX S:I1:I2:imm10:imm11:0\r
+ Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);\r
S = (OpCode32 & BIT26) == BIT26;\r
J1 = (OpCode32 & BIT13) == BIT13;\r
J2 = (OpCode32 & BIT11) == BIT11;\r
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1\r
Target |= (S ? BIT25 : 0); // S\r
Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target); \r
return;\r
\r
case POP_T2:\r
case STM_FORMAT:\r
// <Rn>{!}, <registers>\r
W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
return;\r
\r
case LDM_REG_IMM12_SIGNED:\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);\r
return;\r
\r
case LDM_REG_INDIRECT_LSL:\r
return;\r
\r
case LDM_REG_IMM8:\r
+ ASSERT (FALSE);\r
// <rt>, [<rn>, {, #<imm8>}]{!}\r
W = (OpCode32 & BIT8) == BIT8;\r
U = (OpCode32 & BIT9) == BIT9;\r
if ((OpCode32 && 0xff) == 0) {\r
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" ,W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" , W?"!":"");\r
}\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]%a", OpCode32 & 0xff, U?"":"-");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]", OpCode32 & 0xff, U?"":"-");\r
}\r
return;\r
\r
// <Rn>{!}\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
return;\r
+ \r
+ case ADD_IMM12:\r
+ // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, #0x%x", gReg[Rd], gReg[Rn], Target); \r
+ return;\r
+\r
+ case ADD_IMM5:\r
+ // ADC <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, %a", gReg[Rd], gReg[Rn], gReg[Rm]); \r
+ if (Target != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); \r
+ }\r
+ return;\r
+\r
+ case ADR_THUMB2:\r
+ // ADDR <Rd>, <label>\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {\r
+ Target = PCAlign4 (PC) - Target;\r
+ } else {\r
+ Target = PCAlign4 (PC) + Target;\r
+ }\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target); \r
+ return;\r
\r
+ case CMN_THUMB2:\r
+ // CMN <Rn>, <Rm>, {,<shift> #<const>}\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a", gReg[Rn], gReg[Rm]); \r
+ if (Target != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); \r
+ }\r
+ return;\r
}\r
}\r
}\r