UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
authorMichael Kinney <michael.d.kinney@intel.com>
Mon, 28 Nov 2016 22:13:24 +0000 (14:13 -0800)
committerMichael Kinney <michael.d.kinney@intel.com>
Thu, 1 Dec 2016 19:07:13 +0000 (11:07 -0800)
https://bugzilla.tianocore.org/show_bug.cgi?id=277

Remove dependency on layout of PROCESSOR_SMM_DESCRIPTOR
everywhere possible.  The only exception is the standard
SMI entry handler template that is included with the
PiSmmCpuDxeSmm module.  This allows an instance of the
SmmCpuFeaturesLib to provide alternate
PROCESSOR_SMM_DESCRIPTOR structure layouts.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c

index 0c075582c3856cb107ec205fa5c978b43bb70085..378e06520c831d1dc059784380231290b7ed0bfe 100644 (file)
@@ -31,6 +31,9 @@ ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)
 .equ            MSR_EFER, 0xc0000080\r
 .equ            MSR_EFER_XD, 0x800\r
 \r
+#\r
+# Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+#\r
 .equ            DSC_OFFSET, 0xfb00\r
 .equ            DSC_GDTPTR, 0x30\r
 .equ            DSC_GDTSIZ, 0x38\r
index eda1708e3f3a9fc76ee4d4bcac004bbf5ead5ebd..a4f4dcbda6d840904ec78cc06efb1f8bd052ef0e 100644 (file)
@@ -26,6 +26,9 @@ MSR_IA32_MISC_ENABLE  EQU     1A0h
 MSR_EFER      EQU     0c0000080h\r
 MSR_EFER_XD   EQU     0800h\r
 \r
+;\r
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+;\r
 DSC_OFFSET    EQU     0fb00h\r
 DSC_GDTPTR    EQU     30h\r
 DSC_GDTSIZ    EQU     38h\r
index d50a3170aa8f39b8cb3ea48c8238481f8d27a262..4d2383ff972e1d262838c0177248648b3dc80025 100644 (file)
@@ -22,6 +22,9 @@
 %define MSR_EFER      0xc0000080\r
 %define MSR_EFER_XD   0x800\r
 \r
+;\r
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+;\r
 %define DSC_OFFSET 0xfb00\r
 %define DSC_GDTPTR 0x30\r
 %define DSC_GDTSIZ 0x38\r
index 01ddaee4e71bd7e8b9e4e66216d667100e87abc7..c146795acf6970b8721835864bcdcf791c235d8a 100644 (file)
@@ -1371,7 +1371,6 @@ InitializeMpServiceData (
 {\r
   UINT32                    Cr3;\r
   UINTN                     Index;\r
-  PROCESSOR_SMM_DESCRIPTOR  *Psd;\r
   UINT8                     *GdtTssTables;\r
   UINTN                     GdtTableStepSize;\r
 \r
@@ -1406,24 +1405,16 @@ InitializeMpServiceData (
   GdtTssTables = InitGdt (Cr3, &GdtTableStepSize);\r
 \r
   //\r
-  // Initialize PROCESSOR_SMM_DESCRIPTOR for each CPU\r
+  // Install SMI handler for each CPU\r
   //\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
-    Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(mCpuHotPlugData.SmBase[Index] + SMM_PSD_OFFSET);\r
-    CopyMem (Psd, &gcPsd, sizeof (gcPsd));\r
-    Psd->SmmGdtPtr = (UINT64)(UINTN)(GdtTssTables + GdtTableStepSize * Index);\r
-    Psd->SmmGdtSize = gcSmiGdtr.Limit + 1;\r
-\r
-    //\r
-    // Install SMI handler\r
-    //\r
     InstallSmiHandler (\r
       Index,\r
       (UINT32)mCpuHotPlugData.SmBase[Index],\r
       (VOID*)((UINTN)Stacks + (StackSize * Index)),\r
       StackSize,\r
-      (UINTN)Psd->SmmGdtPtr,\r
-      Psd->SmmGdtSize,\r
+      (UINTN)(GdtTssTables + GdtTableStepSize * Index),\r
+      gcSmiGdtr.Limit + 1,\r
       gcSmiIdtr.Base,\r
       gcSmiIdtr.Limit + 1,\r
       Cr3\r
index f957de1f47640bfe5ac0330f878984345ecd7725..4bef60a1ac512426c5e2072df7572343b26476c7 100644 (file)
@@ -711,22 +711,23 @@ PiCpuSmmEntry (
 \r
   //\r
   // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r
-  // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point.  This size\r
-  // is rounded up to nearest power of 2.\r
+  // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r
+  // This size is rounded up to nearest power of 2.\r
   //\r
   TileCodeSize = GetSmiHandlerSize ();\r
   TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
-  TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);\r
+  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
   TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
   TileSize = TileDataSize + TileCodeSize - 1;\r
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
   DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
 \r
   //\r
-  // If the TileSize is larger than space available for the SMI Handler of CPU[i],\r
-  // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],\r
-  // the ASSERT().  If this ASSERT() is triggered, then the SMI Handler size must be\r
-  // reduced.\r
+  // If the TileSize is larger than space available for the SMI Handler of\r
+  // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r
+  // State Map of CPU[i+1], then ASSERT().  If this ASSERT() is triggered, then\r
+  // the SMI Handler size must be reduced or the size of the extra CPU specific\r
+  // context must be reduced.\r
   //\r
   ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r
 \r
index bd6abf28b5f27f138274c6dbe0efd601eae88a5e..611cbc190a1dd0826e16e985817aa19462d43f5a 100644 (file)
@@ -359,31 +359,6 @@ typedef struct {
 \r
 #define SMM_PSD_OFFSET              0xfb00\r
 \r
-typedef struct {\r
-  UINT64                            Signature;              // Offset 0x00\r
-  UINT16                            Reserved1;              // Offset 0x08\r
-  UINT16                            Reserved2;              // Offset 0x0A\r
-  UINT16                            Reserved3;              // Offset 0x0C\r
-  UINT16                            SmmCs;                  // Offset 0x0E\r
-  UINT16                            SmmDs;                  // Offset 0x10\r
-  UINT16                            SmmSs;                  // Offset 0x12\r
-  UINT16                            SmmOtherSegment;        // Offset 0x14\r
-  UINT16                            Reserved4;              // Offset 0x16\r
-  UINT64                            Reserved5;              // Offset 0x18\r
-  UINT64                            Reserved6;              // Offset 0x20\r
-  UINT64                            Reserved7;              // Offset 0x28\r
-  UINT64                            SmmGdtPtr;              // Offset 0x30\r
-  UINT32                            SmmGdtSize;             // Offset 0x38\r
-  UINT32                            Reserved8;              // Offset 0x3C\r
-  UINT64                            Reserved9;              // Offset 0x40\r
-  UINT64                            Reserved10;             // Offset 0x48\r
-  UINT16                            Reserved11;             // Offset 0x50\r
-  UINT16                            Reserved12;             // Offset 0x52\r
-  UINT32                            Reserved13;             // Offset 0x54\r
-  UINT64                            Reserved14;             // Offset 0x58\r
-} PROCESSOR_SMM_DESCRIPTOR;\r
-\r
-\r
 ///\r
 /// All global semaphores' pointer\r
 ///\r
@@ -427,7 +402,6 @@ extern EFI_PHYSICAL_ADDRESS                mGdtBuffer;
 extern UINTN                               mGdtBufferSize;\r
 extern IA32_DESCRIPTOR                     gcSmiIdtr;\r
 extern VOID                                *gcSmiIdtrPtr;\r
-extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;\r
 extern UINT64                              gPhyMask;\r
 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;\r
 extern UINTN                               mSmmStackArrayBase;\r
index d841dd014c4bfb236874d440a800dc2d0604d12d..6becc1b445264f736f2ea8097994cba3426fca5d 100644 (file)
@@ -684,7 +684,7 @@ PatchSmmSaveStateMap (
 \r
   TileCodeSize = GetSmiHandlerSize ();\r
   TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
-  TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);\r
+  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
   TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
   TileSize = TileDataSize + TileCodeSize - 1;\r
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
index 539c0294cd6ee4573c856caf67b0bcbc0b3148ac..c37e9e8302af3c8ce1d9b1dc901dd8b6a602a6d5 100644 (file)
@@ -1,7 +1,7 @@
 /** @file\r
 Provides services to access SMRAM Save State Map\r
 \r
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -23,6 +23,34 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Register/Cpuid.h>\r
 #include <Register/SmramSaveStateMap.h>\r
 \r
+#include "PiSmmCpuDxeSmm.h"\r
+\r
+typedef struct {\r
+  UINT64                            Signature;              // Offset 0x00\r
+  UINT16                            Reserved1;              // Offset 0x08\r
+  UINT16                            Reserved2;              // Offset 0x0A\r
+  UINT16                            Reserved3;              // Offset 0x0C\r
+  UINT16                            SmmCs;                  // Offset 0x0E\r
+  UINT16                            SmmDs;                  // Offset 0x10\r
+  UINT16                            SmmSs;                  // Offset 0x12\r
+  UINT16                            SmmOtherSegment;        // Offset 0x14\r
+  UINT16                            Reserved4;              // Offset 0x16\r
+  UINT64                            Reserved5;              // Offset 0x18\r
+  UINT64                            Reserved6;              // Offset 0x20\r
+  UINT64                            Reserved7;              // Offset 0x28\r
+  UINT64                            SmmGdtPtr;              // Offset 0x30\r
+  UINT32                            SmmGdtSize;             // Offset 0x38\r
+  UINT32                            Reserved8;              // Offset 0x3C\r
+  UINT64                            Reserved9;              // Offset 0x40\r
+  UINT64                            Reserved10;             // Offset 0x48\r
+  UINT16                            Reserved11;             // Offset 0x50\r
+  UINT16                            Reserved12;             // Offset 0x52\r
+  UINT32                            Reserved13;             // Offset 0x54\r
+  UINT64                            Reserved14;             // Offset 0x58\r
+} PROCESSOR_SMM_DESCRIPTOR;\r
+\r
+extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;\r
+\r
 //\r
 // EFER register LMA bit\r
 //\r
@@ -657,6 +685,8 @@ InstallSmiHandler (
   IN UINT32  Cr3\r
   )\r
 {\r
+  PROCESSOR_SMM_DESCRIPTOR  *Psd;\r
+\r
   if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {\r
     //\r
     // Install SMI handler provided by library\r
@@ -675,6 +705,14 @@ InstallSmiHandler (
     return;\r
   }\r
 \r
+  //\r
+  // Initialize PROCESSOR_SMM_DESCRIPTOR\r
+  //\r
+  Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + SMM_PSD_OFFSET);\r
+  CopyMem (Psd, &gcPsd, sizeof (gcPsd));\r
+  Psd->SmmGdtPtr = (UINT64)GdtBase;\r
+  Psd->SmmGdtSize = (UINT32)GdtSize;\r
+\r
   //\r
   // Initialize values in template before copy\r
   //\r