1. Port X64, IPF and EBC arch for BaseLib
authorvanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>
Mon, 2 Jul 2007 09:34:25 +0000 (09:34 +0000)
committervanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>
Mon, 2 Jul 2007 09:34:25 +0000 (09:34 +0000)
2. Port X64 arch codes for BaseMemoryLibRepStr and BaseMemoryLibSee2

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2955 6f19259b-4bc3-4df7-8a09-765794883524

371 files changed:
MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ebc/SwitchStack.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ebc/Synchronization.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ia32/ARShiftU64.S
MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.S
MdePkg/Library/BaseLib/Ia32/CpuFlushTlb.S
MdePkg/Library/BaseLib/Ia32/CpuId.S
MdePkg/Library/BaseLib/Ia32/CpuIdEx.S
MdePkg/Library/BaseLib/Ia32/CpuPause.S
MdePkg/Library/BaseLib/Ia32/CpuSleep.S
MdePkg/Library/BaseLib/Ia32/DisableInterrupts.S
MdePkg/Library/BaseLib/Ia32/DisablePaging32.S
MdePkg/Library/BaseLib/Ia32/DivU64x32.S
MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S
MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S
MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.S
MdePkg/Library/BaseLib/Ia32/EnableInterrupts.S
MdePkg/Library/BaseLib/Ia32/EnablePaging32.S
MdePkg/Library/BaseLib/Ia32/EnablePaging64.S
MdePkg/Library/BaseLib/Ia32/EnablePaging64.asm
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.S
MdePkg/Library/BaseLib/Ia32/FxRestore.S
MdePkg/Library/BaseLib/Ia32/FxSave.S
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange32.S
MdePkg/Library/BaseLib/Ia32/InterlockedCompareExchange64.S
MdePkg/Library/BaseLib/Ia32/InterlockedDecrement.S
MdePkg/Library/BaseLib/Ia32/InterlockedIncrement.S
MdePkg/Library/BaseLib/Ia32/Invd.S
MdePkg/Library/BaseLib/Ia32/LRotU64.S
MdePkg/Library/BaseLib/Ia32/LShiftU64.S
MdePkg/Library/BaseLib/Ia32/LongJump.S
MdePkg/Library/BaseLib/Ia32/ModU64x32.S
MdePkg/Library/BaseLib/Ia32/Monitor.S
MdePkg/Library/BaseLib/Ia32/MultU64x32.S
MdePkg/Library/BaseLib/Ia32/MultU64x64.S
MdePkg/Library/BaseLib/Ia32/Mwait.S
MdePkg/Library/BaseLib/Ia32/RRotU64.S
MdePkg/Library/BaseLib/Ia32/RShiftU64.S
MdePkg/Library/BaseLib/Ia32/ReadCr0.S
MdePkg/Library/BaseLib/Ia32/ReadCr2.S
MdePkg/Library/BaseLib/Ia32/ReadCr3.S
MdePkg/Library/BaseLib/Ia32/ReadCr4.S
MdePkg/Library/BaseLib/Ia32/ReadCs.S
MdePkg/Library/BaseLib/Ia32/ReadDr0.S
MdePkg/Library/BaseLib/Ia32/ReadDr1.S
MdePkg/Library/BaseLib/Ia32/ReadDr2.S
MdePkg/Library/BaseLib/Ia32/ReadDr3.S
MdePkg/Library/BaseLib/Ia32/ReadDr4.S
MdePkg/Library/BaseLib/Ia32/ReadDr5.S
MdePkg/Library/BaseLib/Ia32/ReadDr6.S
MdePkg/Library/BaseLib/Ia32/ReadDr7.S
MdePkg/Library/BaseLib/Ia32/ReadDs.S
MdePkg/Library/BaseLib/Ia32/ReadEflags.S
MdePkg/Library/BaseLib/Ia32/ReadEs.S
MdePkg/Library/BaseLib/Ia32/ReadFs.S
MdePkg/Library/BaseLib/Ia32/ReadGdtr.S
MdePkg/Library/BaseLib/Ia32/ReadGs.S
MdePkg/Library/BaseLib/Ia32/ReadIdtr.S
MdePkg/Library/BaseLib/Ia32/ReadLdtr.S
MdePkg/Library/BaseLib/Ia32/ReadMm0.S
MdePkg/Library/BaseLib/Ia32/ReadMm1.S
MdePkg/Library/BaseLib/Ia32/ReadMm2.S
MdePkg/Library/BaseLib/Ia32/ReadMm3.S
MdePkg/Library/BaseLib/Ia32/ReadMm4.S
MdePkg/Library/BaseLib/Ia32/ReadMm5.S
MdePkg/Library/BaseLib/Ia32/ReadMm6.S
MdePkg/Library/BaseLib/Ia32/ReadMm7.S
MdePkg/Library/BaseLib/Ia32/ReadMsr64.S
MdePkg/Library/BaseLib/Ia32/ReadPmc.S
MdePkg/Library/BaseLib/Ia32/ReadSs.S
MdePkg/Library/BaseLib/Ia32/ReadTr.S
MdePkg/Library/BaseLib/Ia32/ReadTsc.S
MdePkg/Library/BaseLib/Ia32/SetJump.S
MdePkg/Library/BaseLib/Ia32/SwapBytes64.S
MdePkg/Library/BaseLib/Ia32/Thunk16.S
MdePkg/Library/BaseLib/Ia32/Wbinvd.S
MdePkg/Library/BaseLib/Ia32/WriteCr0.S
MdePkg/Library/BaseLib/Ia32/WriteCr2.S
MdePkg/Library/BaseLib/Ia32/WriteCr3.S
MdePkg/Library/BaseLib/Ia32/WriteCr4.S
MdePkg/Library/BaseLib/Ia32/WriteDr0.S
MdePkg/Library/BaseLib/Ia32/WriteDr1.S
MdePkg/Library/BaseLib/Ia32/WriteDr2.S
MdePkg/Library/BaseLib/Ia32/WriteDr3.S
MdePkg/Library/BaseLib/Ia32/WriteDr4.S
MdePkg/Library/BaseLib/Ia32/WriteDr5.S
MdePkg/Library/BaseLib/Ia32/WriteDr6.S
MdePkg/Library/BaseLib/Ia32/WriteDr7.S
MdePkg/Library/BaseLib/Ia32/WriteGdtr.S
MdePkg/Library/BaseLib/Ia32/WriteIdtr.S
MdePkg/Library/BaseLib/Ia32/WriteLdtr.S
MdePkg/Library/BaseLib/Ia32/WriteMm0.S
MdePkg/Library/BaseLib/Ia32/WriteMm1.S
MdePkg/Library/BaseLib/Ia32/WriteMm2.S
MdePkg/Library/BaseLib/Ia32/WriteMm3.S
MdePkg/Library/BaseLib/Ia32/WriteMm4.S
MdePkg/Library/BaseLib/Ia32/WriteMm5.S
MdePkg/Library/BaseLib/Ia32/WriteMm6.S
MdePkg/Library/BaseLib/Ia32/WriteMm7.S
MdePkg/Library/BaseLib/Ia32/WriteMsr64.S
MdePkg/Library/BaseLib/Ipf/AccessDbr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessEicr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessGcr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessGp.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessKr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessPmr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AccessPsr.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/AsmPalCall.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/CpuPause.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/ExecFc.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/GetInterruptState.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/PalCallStatic.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/ReadCpuid.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/SwitchStack.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/Synchronization.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/Unaligned.c [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/asm.h [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/ia_64gen.h [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/longjmp.s [new file with mode: 0644]
MdePkg/Library/BaseLib/Ipf/setjmp.s [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuBreakpoint.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuBreakpoint.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuBreakpoint.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuFlushTlb.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuFlushTlb.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuId.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuId.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuIdEx.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuIdEx.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuPause.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuPause.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuSleep.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/CpuSleep.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/DisableInterrupts.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/DisableInterrupts.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/DisablePaging64.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/DisablePaging64.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnableInterrupts.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnableInterrupts.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnablePaging64.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/EnablePaging64.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FlushCacheLine.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FlushCacheLine.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FxRestore.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FxRestore.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FxSave.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/FxSave.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange32.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange32.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange32.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange64.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange64.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedCompareExchange64.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedDecrement.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedDecrement.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedDecrement.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedIncrement.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedIncrement.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/InterlockedIncrement.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Invd.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Invd.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/LongJump.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/LongJump.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Monitor.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Monitor.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Mwait.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Mwait.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Non-existing.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCr4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadCs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr1.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr1.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr5.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr5.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr6.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr6.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr7.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDr7.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadDs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadEflags.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadEflags.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadEs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadEs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadFs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadFs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadGdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadGdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadGs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadGs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadIdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadIdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadLdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadLdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm1.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm1.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm5.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm5.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm6.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm6.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm7.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMm7.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMsr64.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMsr64.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadMsr64.c [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadPmc.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadPmc.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadSs.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadSs.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadTr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadTr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadTsc.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/ReadTsc.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/SetJump.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/SetJump.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/SwitchStack.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/SwitchStack.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Thunk16.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Thunk16.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Wbinvd.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/Wbinvd.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteCr4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr1.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr1.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr5.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr5.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr6.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr6.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr7.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteDr7.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteGdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteGdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteIdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteIdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteLdtr.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteLdtr.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm0.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm0.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm1.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm1.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm2.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm2.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm3.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm3.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm4.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm4.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm5.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm5.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm6.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm6.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm7.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMm7.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMsr64.S [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMsr64.asm [new file with mode: 0644]
MdePkg/Library/BaseLib/X64/WriteMsr64.c [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/Ia32/CompareMem.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/CompareMem.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/CopyMem.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/CopyMem.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem16.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem16.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem32.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem32.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem64.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem64.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem8.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem8.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem16.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem16.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem32.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem32.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem64.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/SetMem64.asm
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ZeroMem.S
MdePkg/Library/BaseMemoryLibRepStr/Ia32/ZeroMem.asm
MdePkg/Library/BaseMemoryLibRepStr/x64/CompareMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/CopyMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/ScanMem16.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/ScanMem32.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/ScanMem64.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/ScanMem8.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/SetMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/SetMem16.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/SetMem32.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/SetMem64.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibRepStr/x64/ZeroMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/Ia32/CompareMem.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/CompareMem.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/CopyMem.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/CopyMem.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem16.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem16.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem32.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem32.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem64.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem64.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem8.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/ScanMem8.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.asm
MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.S
MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.asm
MdePkg/Library/BaseMemoryLibSse2/x64/CompareMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/CopyMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/ScanMem16.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/ScanMem32.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/ScanMem64.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/ScanMem8.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/SetMem.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/SetMem16.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/SetMem32.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/SetMem64.asm [new file with mode: 0644]
MdePkg/Library/BaseMemoryLibSse2/x64/ZeroMem.asm [new file with mode: 0644]
MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
MdePkg/MdePkg.dsc

diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
new file mode 100644 (file)
index 0000000..352e1c7
--- /dev/null
@@ -0,0 +1,164 @@
+/** @file\r
+  Base Library CPU Functions for EBC\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+extern\r
+UINT64\r
+_break (\r
+  CHAR8 BreakCode\r
+  );\r
+\r
+/**\r
+  Generates a breakpoint on the CPU.\r
+\r
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+  that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+  VOID\r
+  )\r
+{\r
+  _break (3);\r
+}\r
+\r
+/**\r
+  Used to serialize load and store operations.\r
+\r
+  All loads and stores that proceed calls to this function are guaranteed to be\r
+  globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  Disables CPU interrupts.\r
+\r
+  Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts.\r
+\r
+  Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Retrieves the current CPU interrupt state.\r
+\r
+  Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r
+  currently enabled. Otherwise returns FALSE.\r
+\r
+  @retval TRUE  CPU interrupts are enabled.\r
+  @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  EnableInterrupts ();\r
+  DisableInterrupts ();\r
+}\r
+\r
+/**\r
+  Requests CPU to pause for a short period of time.\r
+\r
+  Requests CPU to pause for a short period of time. Typically used in MP\r
+  systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuFlushTlb (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Places the CPU in a sleep state until an interrupt is received.\r
+\r
+  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+  are disabled prior to calling this function, then the CPU will be placed in a\r
+  sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+  VOID\r
+  )\r
+{\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c b/MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c
new file mode 100644 (file)
index 0000000..b485d3e
--- /dev/null
@@ -0,0 +1,78 @@
+/** @file\r
+  Switch Stack functions.\r
+\r
+  Copyright (c) 2006, Intel Corporation\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  SetJumpLongJump.c\r
+\r
+**/\r
+\r
+/**\r
+  Worker function that checks ASSERT condition for JumpBuffer\r
+\r
+  Checks ASSERT condition for JumpBuffer.\r
+\r
+  If JumpBuffer is NULL, then ASSERT().\r
+  For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+\r
+  @param  JumpBuffer    A pointer to CPU context buffer.\r
+\r
+**/\r
+VOID\r
+InternalAssertJumpBuffer (\r
+  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer\r
+  );\r
+\r
+/**\r
+  Saves the current CPU context that can be restored with a call to LongJump() and returns 0.\r
+\r
+  Saves the current CPU context in the buffer specified by JumpBuffer and returns 0.  The initial \r
+  call to SetJump() must always return 0.  Subsequent calls to LongJump() cause a non-zero \r
+  value to be returned by SetJump(). \r
+\r
+  If JumpBuffer is NULL, then ASSERT().\r
+  For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+\r
+  @param  JumpBuffer    A pointer to CPU context buffer.\r
\r
+**/\r
+UINTN\r
+EFIAPI\r
+SetJump (\r
+  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer\r
+  )\r
+{\r
+  InternalAssertJumpBuffer (JumpBuffer);\r
+  return 0;\r
+}\r
+\r
+/**\r
+  Restores the CPU context that was saved with SetJump().\r
+\r
+  Restores the CPU context from the buffer specified by JumpBuffer.\r
+  This function never returns to the caller.\r
+  Instead is resumes execution based on the state of JumpBuffer.\r
+\r
+  @param  JumpBuffer    A pointer to CPU context buffer.\r
+  @param  Value         The value to return when the SetJump() context is restored.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalLongJump (\r
+  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,\r
+  IN      UINTN                     Value\r
+  )\r
+{\r
+  //\r
+  // This function cannot work on EBC\r
+  //\r
+  ASSERT (FALSE);\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ebc/SwitchStack.c b/MdePkg/Library/BaseLib/Ebc/SwitchStack.c
new file mode 100644 (file)
index 0000000..d2861c4
--- /dev/null
@@ -0,0 +1,64 @@
+/** @file\r
+  Switch Stack functions.\r
+\r
+  Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  SwitchStack.c\r
+\r
+**/\r
+\r
+/**\r
+  Transfers control to a function starting with a new stack.\r
+\r
+  Transfers control to the function specified by EntryPoint using the\r
+  new stack specified by NewStack and passing in the parameters specified\r
+  by Context1 and Context2.  Context1 and Context2 are optional and may\r
+  be NULL.  The function EntryPoint must never return.\r
+  Marker will be ignored on IA-32, x64, and EBC.\r
+  IPF CPUs expect one additional parameter of type VOID * that specifies\r
+  the new backing store pointer.\r
+\r
+  If EntryPoint is NULL, then ASSERT().\r
+  If NewStack is NULL, then ASSERT().\r
+\r
+  @param  EntryPoint  A pointer to function to call with the new stack.\r
+  @param  Context1    A pointer to the context to pass into the EntryPoint\r
+                      function.\r
+  @param  Context2    A pointer to the context to pass into the EntryPoint\r
+                      function.\r
+  @param  NewStack    A pointer to the new stack to use for the EntryPoint\r
+                      function.\r
+  @param  Marker      VA_LIST marker for the variable argument list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalSwitchStack (\r
+  IN      SWITCH_STACK_ENTRY_POINT  EntryPoint,\r
+  IN      VOID                      *Context1,   OPTIONAL\r
+  IN      VOID                      *Context2,   OPTIONAL\r
+  IN      VOID                      *NewStack,\r
+  IN      VA_LIST                   Marker\r
+  )\r
+\r
+{\r
+  //\r
+  // This version of this function does not actually change the stack pointer\r
+  // This is to support compilation of CPU types that do not support assemblers\r
+  // such as EBC\r
+  //\r
+\r
+  //\r
+  // Stack should be aligned with CPU_STACK_ALIGNMENT\r
+  //\r
+  ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+\r
+  EntryPoint (Context1, Context2);\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ebc/Synchronization.c b/MdePkg/Library/BaseLib/Ebc/Synchronization.c
new file mode 100644 (file)
index 0000000..5d5bc2f
--- /dev/null
@@ -0,0 +1,99 @@
+/** @file\r
+  Implementation of synchronization functions on EBC.\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  Synchronization.c\r
+\r
+**/\r
+\r
+UINT32\r
+EFIAPI\r
+InternalSyncCompareExchange32 (\r
+  IN      volatile UINT32           *Value,\r
+  IN      UINT32                    CompareValue,\r
+  IN      UINT32                    ExchangeValue\r
+  )\r
+{\r
+  return *Value != CompareValue ? *Value :\r
+           ((*Value = ExchangeValue), CompareValue);\r
+}\r
+\r
+/**\r
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
+\r
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified \r
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and \r
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned. \r
+  The compare exchange operation must be performed using MP safe mechanisms.\r
+\r
+  @param  Value         A pointer to the 64-bit value for the compare exchange\r
+                        operation.\r
+  @param  CompareValue  64-bit value used in compare operation.\r
+  @param  ExchangeValue 64-bit value used in exchange operation.\r
+\r
+  @return The original *Value before exchange.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalSyncCompareExchange64 (\r
+  IN      volatile UINT64           *Value,\r
+  IN      UINT64                    CompareValue,\r
+  IN      UINT64                    ExchangeValue\r
+  )\r
+{\r
+  return *Value != CompareValue ? *Value :\r
+           ((*Value = ExchangeValue), CompareValue);\r
+}\r
+\r
+/**\r
+  Performs an atomic increment of an 32-bit unsigned integer.\r
+\r
+  Performs an atomic increment of the 32-bit unsigned integer specified by\r
+  Value and returns the incremented value. The increment operation must be\r
+  performed using MP safe mechanisms. The state of the return value is not\r
+  guaranteed to be MP safe.\r
+\r
+  @param  Value A pointer to the 32-bit value to increment.\r
+\r
+  @return The incremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncIncrement (\r
+  IN      volatile UINT32           *Value\r
+  )\r
+{\r
+  return ++*Value;\r
+}\r
+\r
+/**\r
+  Performs an atomic decrement of an 32-bit unsigned integer.\r
+\r
+  Performs an atomic decrement of the 32-bit unsigned integer specified by\r
+  Value and returns the decrement value. The decrement operation must be\r
+  performed using MP safe mechanisms. The state of the return value is not\r
+  guaranteed to be MP safe.\r
+\r
+  @param  Value A pointer to the 32-bit value to decrement.\r
+\r
+  @return The decrement value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncDecrement (\r
+  IN      volatile UINT32           *Value\r
+  )\r
+{\r
+  return --*Value;\r
+}\r
index 8476208..5498d2e 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 59a1143..e82434b 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------ ;\r
 # Copyright (c) 2006, Intel Corporation\r
 # All rights reserved. This program and the accompanying materials\r
index 07550ff..f8b1cdc 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------ ;\r
 # Copyright (c) 2006, Intel Corporation\r
 # All rights reserved. This program and the accompanying materials\r
index 2373ad1..6f41e72 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 2d7ec49..48554cc 100644 (file)
@@ -1,72 +1,67 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   CpuIdEx.Asm\r
-#\r
-# Abstract:\r
-#\r
-#   AsmCpuidEx function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-    .686:\r
-    .code:\r
-\r
-#------------------------------------------------------------------------------\r
-#  UINT32\r
-#  EFIAPI\r
-#  AsmCpuidEx (\r
-#    IN   UINT32  RegisterInEax,\r
-#    IN   UINT32  RegisterInEcx,\r
-#    OUT  UINT32  *RegisterOutEax  OPTIONAL,\r
-#    OUT  UINT32  *RegisterOutEbx  OPTIONAL,\r
-#    OUT  UINT32  *RegisterOutEcx  OPTIONAL,\r
-#    OUT  UINT32  *RegisterOutEdx  OPTIONAL\r
-#    )\r
-#------------------------------------------------------------------------------\r
-.globl ASM_PFX(AsmCpuidEx)\r
-ASM_PFX(AsmCpuidEx):\r
-    push    %ebx\r
-    push    %ebp\r
-    movl    %esp, %ebp\r
-    movl    12(%ebp), %eax\r
-    movl    16(%ebp), %ecx\r
-    cpuid\r
-    push    %ecx\r
-    movl    20(%ebp), %ecx\r
-    jecxz   L1\r
-    movl    %eax, (%ecx)\r
-L1:\r
-    movl    24(%ebp), %ecx\r
-    jecxz   L2\r
-    movl    %ebx, (%ecx)\r
-L2:\r
-    movl    28(%ebp), %ecx\r
-    jecxz   L3\r
-    popl    (%ecx)\r
-L3:\r
-    movl    32(%ebp), %edx\r
-    jecxz   L4\r
-    movl    %edx, (%ecx)\r
-L4:\r
-    movl    12(%ebp), %eax\r
-    leave\r
-    pop     %ebx\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   CpuIdEx.Asm
+#
+# Abstract:
+#
+#   AsmCpuidEx function
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+    .686:
+    .code:
+
+#------------------------------------------------------------------------------
+#  UINT32
+#  EFIAPI
+#  AsmCpuidEx (
+#    IN   UINT32  RegisterInEax,
+#    IN   UINT32  RegisterInEcx,
+#    OUT  UINT32  *RegisterOutEax  OPTIONAL,
+#    OUT  UINT32  *RegisterOutEbx  OPTIONAL,
+#    OUT  UINT32  *RegisterOutEcx  OPTIONAL,
+#    OUT  UINT32  *RegisterOutEdx  OPTIONAL
+#    )
+#------------------------------------------------------------------------------
+.globl ASM_PFX(AsmCpuidEx)
+ASM_PFX(AsmCpuidEx):
+    push    %ebx
+    push    %ebp
+    movl    %esp, %ebp
+    movl    12(%ebp), %eax
+    movl    16(%ebp), %ecx
+    cpuid
+    push    %ecx
+    movl    20(%ebp), %ecx
+    jecxz   L1
+    movl    %eax, (%ecx)
+L1:
+    movl    24(%ebp), %ecx
+    jecxz   L2
+    movl    %ebx, (%ecx)
+L2:
+    movl    28(%ebp), %ecx
+    jecxz   L3
+    popl    (%ecx)
+L3:
+    movl    32(%ebp), %edx
+    jecxz   L4
+    movl    %edx, (%ecx)
+L4:
+    movl    12(%ebp), %eax
+    leave
+    pop     %ebx
+    ret
index 3661b1f..5fef9c8 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------ ;\r
 # Copyright (c) 2006, Intel Corporation\r
 # All rights reserved. This program and the accompanying materials\r
index 8bf9d55..ac39e8f 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------ ;\r
 # Copyright (c) 2006, Intel Corporation\r
 # All rights reserved. This program and the accompanying materials\r
index 3a7a81d..ea04225 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f950b05..7898e81 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 1708198..b858278 100644 (file)
@@ -1,46 +1,41 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   DivU64x32.asm\r
-#\r
-# Abstract:\r
-#\r
-#   Calculate the quotient of a 64-bit integer by a 32-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.globl ASM_PFX(InternalMathDivU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathDivU64x32 (\r
-#   IN      UINT64                    Dividend,\r
-#   IN      UINT32                    Divisor\r
-#   );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathDivU64x32):\r
-    movl    8(%esp), %eax\r
-    movl    12(%esp), %ecx\r
-    xorl    %edx, %edx\r
-    divl    %ecx\r
-    push    %eax\r
-    movl    8(%esp), %eax\r
-    divl    %ecx\r
-    pop     %edx\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   DivU64x32.asm
+#
+# Abstract:
+#
+#   Calculate the quotient of a 64-bit integer by a 32-bit integer
+#
+#------------------------------------------------------------------------------
+
+.globl ASM_PFX(InternalMathDivU64x32)
+
+#------------------------------------------------------------------------------
+# UINT64
+# EFIAPI
+# InternalMathDivU64x32 (
+#   IN      UINT64                    Dividend,
+#   IN      UINT32                    Divisor
+#   );
+#------------------------------------------------------------------------------
+ASM_PFX(InternalMathDivU64x32):
+    movl    8(%esp), %eax
+    movl    12(%esp), %ecx
+    xorl    %edx, %edx
+    divl    %ecx
+    push    %eax
+    movl    8(%esp), %eax
+    divl    %ecx
+    pop     %edx
+    ret
index 987e0ea..974373d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 36008bf..cac7169 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 2799832..c5742ae 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 2c83e26..2d60803 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 054a5c9..df5d67c 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 44b7e16..ffa9beb 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 3755c05..435bb39 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-\r
-\r
 ;------------------------------------------------------------------------------\r
 ;\r
 ; Copyright (c) 2006, Intel Corporation\r
index b8c87c2..07a9261 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 4560751..9cfa14b 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 343db36..8857a8e 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 0abb605..a0a6ad9 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ee3278c..98a20a5 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index a92ea6b..dc8f721 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 88c35d5..ecbbc75 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 4e85d29..0a0c1a2 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index fe3ab60..3b866e2 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 9c93242..a4b99eb 100644 (file)
@@ -1,46 +1,41 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   LShiftU64.asm\r
-#\r
-# Abstract:\r
-#\r
-#   64-bit left shift function for IA-32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.globl ASM_PFX(InternalMathLShiftU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathLShiftU64 (\r
-#   IN      UINT64                    Operand,\r
-#   IN      UINTN                     Count\r
-#   );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathLShiftU64):\r
-    movb    12(%esp), %cl\r
-    xorl    %eax, %eax\r
-    movl    4(%esp), %edx\r
-    testb   $32, %cl\r
-    cmovz   %edx, %eax\r
-    cmovz   0x8(%esp), %edx\r
-    shld    %cl, %eax, %edx\r
-    shl     %cl, %eax\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   LShiftU64.asm
+#
+# Abstract:
+#
+#   64-bit left shift function for IA-32
+#
+#------------------------------------------------------------------------------
+
+.globl ASM_PFX(InternalMathLShiftU64)
+
+#------------------------------------------------------------------------------
+# UINT64
+# EFIAPI
+# InternalMathLShiftU64 (
+#   IN      UINT64                    Operand,
+#   IN      UINTN                     Count
+#   );
+#------------------------------------------------------------------------------
+ASM_PFX(InternalMathLShiftU64):
+    movb    12(%esp), %cl
+    xorl    %eax, %eax
+    movl    4(%esp), %edx
+    testb   $32, %cl
+    cmovz   %edx, %eax
+    cmovz   0x8(%esp), %edx
+    shld    %cl, %eax, %edx
+    shl     %cl, %eax
+    ret
index 95dd444..0b76896 100644 (file)
@@ -1,46 +1,41 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   LongJump.Asm\r
-#\r
-# Abstract:\r
-#\r
-#   Implementation of _LongJump() on IA-32.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.globl ASM_PFX(InternalLongJump)\r
-\r
-#------------------------------------------------------------------------------\r
-# VOID\r
-# EFIAPI\r
-# InternalLongJump (\r
-#   IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,\r
-#   IN      UINTN                     Value\r
-#   );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalLongJump):\r
-    pop     %eax\r
-    pop     %edx\r
-    pop     %eax\r
-    movl    (%edx), %ebx\r
-    movl    4(%edx), %esi\r
-    movl    8(%edx), %edi\r
-    movl    12(%edx), %ebp\r
-    movl    16(%edx), %esp\r
-    jmp     *20(%edx)\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   LongJump.Asm
+#
+# Abstract:
+#
+#   Implementation of _LongJump() on IA-32.
+#
+#------------------------------------------------------------------------------
+
+.globl ASM_PFX(InternalLongJump)
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# InternalLongJump (
+#   IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,
+#   IN      UINTN                     Value
+#   );
+#------------------------------------------------------------------------------
+ASM_PFX(InternalLongJump):
+    pop     %eax
+    pop     %edx
+    pop     %eax
+    movl    (%edx), %ebx
+    movl    4(%edx), %esi
+    movl    8(%edx), %edi
+    movl    12(%edx), %ebp
+    movl    16(%edx), %esp
+    jmp     *20(%edx)
index decfeaa..00dc6a0 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 2651124..6e9284d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 5c44957..b9d1eb8 100644 (file)
@@ -1,46 +1,41 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   MultU64x32.asm\r
-#\r
-# Abstract:\r
-#\r
-#   Calculate the product of a 64-bit integer and a 32-bit integer\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-    .386:\r
-    .code:\r
-\r
-.globl ASM_PFX(InternalMathMultU64x32)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathMultU64x32 (\r
-#   IN      UINT64                    Multiplicand,\r
-#   IN      UINT32                    Multiplier\r
-#   );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathMultU64x32):\r
-    movl    12(%esp), %ecx\r
-    movl    %ecx, %eax\r
-    imull   8(%esp), %ecx\r
-    mull    0x4(%esp)\r
-    addl    %ecx, %edx\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   MultU64x32.asm
+#
+# Abstract:
+#
+#   Calculate the product of a 64-bit integer and a 32-bit integer
+#
+#------------------------------------------------------------------------------
+
+    .386:
+    .code:
+
+.globl ASM_PFX(InternalMathMultU64x32)
+
+#------------------------------------------------------------------------------
+# UINT64
+# EFIAPI
+# InternalMathMultU64x32 (
+#   IN      UINT64                    Multiplicand,
+#   IN      UINT32                    Multiplier
+#   );
+#------------------------------------------------------------------------------
+ASM_PFX(InternalMathMultU64x32):
+    movl    12(%esp), %ecx
+    movl    %ecx, %eax
+    imull   8(%esp), %ecx
+    mull    0x4(%esp)
+    addl    %ecx, %edx
+    ret
index 40dda6f..0352386 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 80782b7..12f6a87 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 7e89842..3593563 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 7d58fd6..ca78394 100644 (file)
@@ -1,49 +1,44 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   RShiftU64.asm\r
-#\r
-# Abstract:\r
-#\r
-#   64-bit logical right shift function for IA-32\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-    .686:\r
-    .code:\r
-\r
-.globl ASM_PFX(InternalMathRShiftU64)\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathRShiftU64 (\r
-#   IN      UINT64                    Operand,\r
-#   IN      UINTN                     Count\r
-#   );\r
-#------------------------------------------------------------------------------\r
-ASM_PFX(InternalMathRShiftU64):\r
-    movb    12(%esp), %cl\r
-    xorl    %edx, %edx\r
-    movl    8(%esp), %eax\r
-    testb   $32, %cl\r
-    cmovz   %eax, %edx\r
-    cmovz   0x4(%esp), %eax\r
-    shrdl   %cl, %edx, %eax\r
-    shr     %cl, %edx\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   RShiftU64.asm
+#
+# Abstract:
+#
+#   64-bit logical right shift function for IA-32
+#
+#------------------------------------------------------------------------------
+
+    .686:
+    .code:
+
+.globl ASM_PFX(InternalMathRShiftU64)
+
+#------------------------------------------------------------------------------
+# UINT64
+# EFIAPI
+# InternalMathRShiftU64 (
+#   IN      UINT64                    Operand,
+#   IN      UINTN                     Count
+#   );
+#------------------------------------------------------------------------------
+ASM_PFX(InternalMathRShiftU64):
+    movb    12(%esp), %cl
+    xorl    %edx, %edx
+    movl    8(%esp), %eax
+    testb   $32, %cl
+    cmovz   %eax, %edx
+    cmovz   0x4(%esp), %eax
+    shrdl   %cl, %edx, %eax
+    shr     %cl, %edx
+    ret
index b08c7d7..3433344 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 0b82a25..d308895 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f973dbe..aaec1f0 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ee94991..442d359 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 7406cfb..a3ad69d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 1ba42d9..d4c61f1 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 4fe89da..27c5554 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 916fad7..cca84b9 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 3505589..60b0550 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 44c56aa..84883df 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 3a01225..5abb226 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index e5857b0..9594851 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 8054b96..4ba13ef 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 41e6bd4..c3dc845 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 95b2191..ab5e522 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ed60065..26ed55d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 19d89ef..bd38c6a 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ba6564c..8869164 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 1862596..82b3966 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 7880e7a..0e5d32e 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 301edbd..addb175 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index c6434fc..f191337 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 775a517..790541a 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 7c23a67..231d62c 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ad888b1..1e1f6dd 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index a69e914..5da446b 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index bc047a1..5528fe1 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index a168717..5d9bd11 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index c273279..26866b6 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index e0655b2..505b7e6 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index fd75ef4..055e99c 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 752cb26..4f15248 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 8b095be..af12dd2 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index a4436dd..cab2966 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index a3a70b6..c899308 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 313f416..c15ca44 100644 (file)
@@ -1,43 +1,38 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2006, Intel Corporation\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-# Module Name:\r
-#\r
-#   CpuId.Asm\r
-#\r
-# Abstract:\r
-#\r
-#   AsmCpuid function\r
-#\r
-# Notes:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-\r
-#------------------------------------------------------------------------------\r
-# UINT64\r
-# EFIAPI\r
-# InternalMathSwapBytes64 (\r
-#   IN      UINT64                    Operand\r
-#   );\r
-#------------------------------------------------------------------------------\r
-.globl ASM_PFX(InternalMathSwapBytes64)\r
-ASM_PFX(InternalMathSwapBytes64):\r
-    movl    8(%esp), %eax\r
-    movl    4(%esp), %edx\r
-    bswapl  %eax\r
-    bswapl  %edx\r
-    ret\r
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   CpuId.Asm
+#
+# Abstract:
+#
+#   AsmCpuid function
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# UINT64
+# EFIAPI
+# InternalMathSwapBytes64 (
+#   IN      UINT64                    Operand
+#   );
+#------------------------------------------------------------------------------
+.globl ASM_PFX(InternalMathSwapBytes64)
+ASM_PFX(InternalMathSwapBytes64):
+    movl    8(%esp), %eax
+    movl    4(%esp), %edx
+    bswapl  %eax
+    bswapl  %edx
+    ret
index ca72d0b..c45cdb0 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 9c31adc..b19348d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 5cd75cf..6bce3a4 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 8128e83..64d2c1b 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 06f7208..767182e 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f748c18..dc6828a 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f1fd878..c05af0e 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 291e637..8703176 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 6b6a50a..ca4e301 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 4201c4a..ed23db7 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ef76bdd..d175952 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f10b56e..7e3bb94 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 1cdd816..0827f34 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index ce1e29b..1f3e916 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 07ec92e..3aedf7d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 739edde..c3e6ad3 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 1bb4678..8b2cc3c 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 87a2816..ef70763 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 05182fb..74a3d71 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index c34cecc..a3c548d 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 01250e8..98b11a5 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index cc6ec7d..107c695 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index b090961..be6a6f7 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 6d657c6..51a8973 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index 52c599c..824bbea 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
index f310e88..5c12c98 100644 (file)
@@ -1,8 +1,3 @@
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
-\r
 #------------------------------------------------------------------------------\r
 #\r
 # Copyright (c) 2006, Intel Corporation\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s b/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
new file mode 100644 (file)
index 0000000..49d1fec
--- /dev/null
@@ -0,0 +1,118 @@
+/// @file\r
+///  IPF specific Debug Breakpoint Registers accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessDbr.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadDbr\r
+//\r
+// This routine is used to Reads the current value of Data Breakpoint Register (DBR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit DBR index to read.\r
+//\r
+// Return Value: The current value of DBR by Index.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadDbr, @function\r
+.proc   AsmReadDbr\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmReadDbr::\r
+        mov             r8 = dbr[in0];;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadDbr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteDbr\r
+//\r
+// This routine is used to write the current value to Data Breakpoint Register (DBR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit DBR index to read.\r
+//            The value should be written to DBR\r
+//\r
+// Return Value: The value written to DBR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteDbr, @function\r
+.proc   AsmWriteDbr\r
+.regstk 2, 0, 0, 0\r
+\r
+AsmWriteDbr::\r
+        mov             dbr[in0] = in1\r
+        mov             r8 = in1;;\r
+        srlz.d;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteDbr\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIbr\r
+//\r
+// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit IBR index.\r
+//\r
+// Return Value: The current value of IBR by Index.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIbr, @function\r
+.proc   AsmReadIbr\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmReadIbr::\r
+        mov             r8 = ibr[in0];;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadIbr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteIbr\r
+//\r
+// This routine is used to write the current value to Instruction Breakpoint Register (IBR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit IBR index.\r
+//            The value should be written to IBR\r
+//\r
+// Return Value: The value written to IBR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteIbr, @function\r
+.proc   AsmWriteIbr\r
+.regstk 2, 0, 0, 0\r
+\r
+AsmWriteIbr::\r
+        mov             ibr[in0] = in1\r
+        mov             r8 = in1;;\r
+        srlz.i;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteIbr\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s b/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
new file mode 100644 (file)
index 0000000..03d7e03
--- /dev/null
@@ -0,0 +1,512 @@
+/// @file\r
+///  IPF specific External Interrupt Control Registers accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessEicr.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadLid\r
+//\r
+// This routine is used to read the value of Local Interrupt ID Register (LID).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of LID.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadLid, @function\r
+.proc   AsmReadLid\r
+\r
+AsmReadLid::\r
+         mov            r8 = cr.lid;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadLid\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteLid\r
+//\r
+// This routine is used to write the value to Local Interrupt ID Register (LID).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The value need to be written to LID.\r
+//\r
+// Return Value: The value written to LID.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteLid, @function\r
+.proc   AsmWriteLid\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteLid::\r
+         mov            cr.lid = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteLid\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIvr\r
+//\r
+// This routine is used to read the value of External Interrupt Vector Register (IVR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IVR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIvr, @function\r
+.proc   AsmReadIvr\r
+\r
+AsmReadIvr::\r
+         mov            r8 = cr.ivr;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIvr\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadTpr\r
+//\r
+// This routine is used to read the value of Task Priority Register (TPR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of TPR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadTpr, @function\r
+.proc   AsmReadTpr\r
+\r
+AsmReadTpr::\r
+         mov            r8 = cr.tpr;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadTpr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteTpr\r
+//\r
+// This routine is used to write the value to Task Priority Register (TPR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The value need to be written to TPR.\r
+//\r
+// Return Value: The value written to TPR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteTpr, @function\r
+.proc   AsmWriteTpr\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteTpr::\r
+         mov            cr.tpr = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteTpr\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteEoi\r
+//\r
+// This routine is used to write the value to End of External Interrupt Register (EOI).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The value need to be written to EOI.\r
+//\r
+// Return Value: The value written to EOI.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteEoi, @function\r
+.proc   AsmWriteEoi\r
+\r
+AsmWriteEoi::\r
+         mov            cr.eoi = r0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteEoi\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIrr0\r
+//\r
+// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IRR0.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIrr0, @function\r
+.proc   AsmReadIrr0\r
+\r
+AsmReadIrr0::\r
+         mov            r8 = cr.irr0;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIrr0\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIrr1\r
+//\r
+// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IRR1.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIrr1, @function\r
+.proc   AsmReadIrr1\r
+\r
+AsmReadIrr1::\r
+         mov            r8 = cr.irr1;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIrr1\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIrr2\r
+//\r
+// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IRR2.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIrr2, @function\r
+.proc   AsmReadIrr2\r
+\r
+AsmReadIrr2::\r
+         mov            r8 = cr.irr2;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIrr2\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIrr3\r
+//\r
+// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IRR3.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIrr3, @function\r
+.proc   AsmReadIrr3\r
+\r
+AsmReadIrr3::\r
+         mov            r8 = cr.irr3;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIrr3\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadItv\r
+//\r
+// This routine is used to Read the value of Interval Timer Vector Register (ITV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of ITV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadItv, @function\r
+.proc   AsmReadItv\r
+\r
+AsmReadItv::\r
+         mov            r8 = cr.itv;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadItv\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteItv\r
+//\r
+// This routine is used to write the value to Interval Timer Vector Register (ITV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to ITV\r
+//\r
+// Return Value: The value written to ITV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteItv, @function\r
+.proc   AsmWriteItv\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteItv::\r
+         mov            cr.itv = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteItv\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadPmv\r
+//\r
+// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of PMV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadPmv, @function\r
+.proc   AsmReadPmv\r
+\r
+AsmReadPmv::\r
+         mov            r8 = cr.pmv;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadPmv\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWritePmv\r
+//\r
+// This routine is used to write the value to Performance Monitoring Vector Register (PMV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to PMV\r
+//\r
+// Return Value: The value written to PMV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWritePmv, @function\r
+.proc   AsmWritePmv\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWritePmv::\r
+         mov            cr.pmv = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWritePmv\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadCmcv\r
+//\r
+// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of CMCV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadCmcv, @function\r
+.proc   AsmReadCmcv\r
+\r
+AsmReadCmcv::\r
+         mov            r8 = cr.cmcv;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadCmcv\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteCmcv\r
+//\r
+// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to CMCV\r
+//\r
+// Return Value: The value written to CMCV.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteCmcv, @function\r
+.proc   AsmWriteCmcv\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteCmcv::\r
+         mov            cr.cmcv = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteCmcv\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadLrr0\r
+//\r
+// This routine is used to read the value of Local Redirection Register 0 (LRR0).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of LRR0.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadLrr0, @function\r
+.proc   AsmReadLrr0\r
+\r
+AsmReadLrr0::\r
+         mov            r8 = cr.lrr0;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadLrr0\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteLrr0\r
+//\r
+// This routine is used to write the value to Local Redirection Register 0 (LRR0).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The value need to be written to LRR0.\r
+//\r
+// Return Value: The value written to LRR0.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteLrr0, @function\r
+.proc   AsmWriteLrr0\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteLrr0::\r
+         mov            cr.lrr0 = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteLrr0\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadLrr1\r
+//\r
+// This routine is used to read the value of Local Redirection Register 1 (LRR1).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of LRR1.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadLrr1, @function\r
+.proc   AsmReadLrr1\r
+\r
+AsmReadLrr1::\r
+         mov            r8 = cr.lrr1;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadLrr1\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteLrr1\r
+//\r
+// This routine is used to write the value to Local Redirection Register 1 (LRR1).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The value need to be written to LRR1.\r
+//\r
+// Return Value: The value written to LRR1.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteLrr1, @function\r
+.proc   AsmWriteLrr1\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteLrr1::\r
+         mov            cr.lrr1 = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteLrr1\r
+\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s b/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
new file mode 100644 (file)
index 0000000..54b3a30
--- /dev/null
@@ -0,0 +1,264 @@
+/// @file\r
+///  IPF specific Global Control Registers accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessGcr.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadDcr\r
+//\r
+// This routine is used to Read the value of Default Control Register (DCR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of DCR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadDcr, @function\r
+.proc   AsmReadDcr\r
+\r
+AsmReadDcr::\r
+         mov            r8 = cr.dcr;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadDcr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteDcr\r
+//\r
+// This routine is used to write the value to Default Control Register (DCR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to DCR\r
+//\r
+// Return Value: The value written to DCR.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteDcr, @function\r
+.proc   AsmWriteDcr\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteDcr::\r
+         mov            cr.dcr = in0\r
+         mov            r8 = in0;;\r
+         srlz.i;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteDcr\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadItc\r
+//\r
+// This routine is used to Read the value of Interval Timer Counter Register (ITC).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of ITC.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadItc, @function\r
+.proc   AsmReadItc\r
+\r
+AsmReadItc::\r
+         mov            r8 = ar.itc;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadItc\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteItc\r
+//\r
+// This routine is used to write the value to Interval Timer Counter Register (ITC).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to the ITC\r
+//\r
+// Return Value: The value written to the ITC.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteItc, @function\r
+.proc   AsmWriteItc\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteItc::\r
+         mov            ar.itc = in0\r
+         mov            r8 = in0;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteItc\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadItm\r
+//\r
+// This routine is used to Read the value of Interval Timer Match Register (ITM).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of ITM.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadItm, @function\r
+.proc   AsmReadItm\r
+\r
+AsmReadItm::\r
+         mov            r8 = cr.itm;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadItm\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteItm\r
+//\r
+// This routine is used to write the value to Interval Timer Match Register (ITM).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to ITM\r
+//\r
+// Return Value: The value written to ITM.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteItm, @function\r
+.proc   AsmWriteItm\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteItm::\r
+         mov            cr.itm = in0\r
+         mov            r8 = in0;;\r
+         srlz.d;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteItm\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadIva\r
+//\r
+// This routine is used to read the value of Interruption Vector Address Register (IVA).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of IVA.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadIva, @function\r
+.proc   AsmReadIva\r
+\r
+AsmReadIva::\r
+         mov            r8 = cr.iva;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadIva\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteIva\r
+//\r
+// This routine is used to write the value to Interruption Vector Address Register (IVA).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to IVA\r
+//\r
+// Return Value: The value written to IVA.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteIva, @function\r
+.proc   AsmWriteIva\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteIva::\r
+         mov            cr.iva = in0\r
+         mov            r8 = in0;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWriteIva\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadPta\r
+//\r
+// This routine is used to read the value of Page Table Address Register (PTA).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current value of PTA.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadPta, @function\r
+.proc   AsmReadPta\r
+\r
+AsmReadPta::\r
+         mov            r8 = cr.pta;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmReadPta\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWritePta\r
+//\r
+// This routine is used to write the value to Page Table Address Register (PTA)).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written to PTA\r
+//\r
+// Return Value: The value written to PTA.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWritePta, @function\r
+.proc   AsmWritePta\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWritePta::\r
+         mov            cr.pta = in0\r
+         mov            r8 = in0;;\r
+         srlz.i;;\r
+         srlz.d;;\r
+         br.ret.dpnt    b0;;\r
+.endp    AsmWritePta
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGp.s b/MdePkg/Library/BaseLib/Ipf/AccessGp.s
new file mode 100644 (file)
index 0000000..5c5f20f
--- /dev/null
@@ -0,0 +1,86 @@
+/// @file\r
+///  IPF specific Global Pointer and Stack Pointer accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessGp.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadGp\r
+//\r
+// This routine is used to read the current value of 64-bit Global Pointer (GP).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current GP value.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadGp, @function\r
+.proc   AsmReadGp\r
+\r
+AsmReadGp::\r
+        mov             r8 = gp;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadGp\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteGp\r
+//\r
+// This routine is used to write the current value of 64-bit Global Pointer (GP).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written.\r
+//\r
+// Return Value: The value have been written.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteGp, @function\r
+.proc   AsmWriteGp\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteGp::\r
+        mov             gp = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteGp\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadSp\r
+//\r
+// This routine is used to read the current value of 64-bit Stack Pointer (SP).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current SP value.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadSp, @function\r
+.proc   AsmReadSp\r
+\r
+AsmReadSp::\r
+        mov             r8 = sp;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadSp\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr.s b/MdePkg/Library/BaseLib/Ipf/AccessKr.s
new file mode 100644 (file)
index 0000000..5a38954
--- /dev/null
@@ -0,0 +1,400 @@
+/// @file\r
+///  IPF specific AsmReadKrX() and AsmWriteKrX functions, 'X' is from '0' to '7'\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessKr.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr0\r
+//\r
+// This routine is used to get KR0.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR0.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr0, @function\r
+.proc   AsmReadKr0\r
+\r
+AsmReadKr0::\r
+        mov             r8 = ar.k0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr0\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr0\r
+//\r
+// This routine is used to Write KR0.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR0.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+\r
+.text\r
+.type   AsmWriteKr0, @function\r
+.proc   AsmWriteKr0\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWriteKr0::\r
+        mov             ar.k0 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr0\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr1\r
+//\r
+// This routine is used to get KR1.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR1.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr1, @function\r
+.proc   AsmReadKr1\r
+\r
+AsmReadKr1::\r
+        mov             r8 = ar.k1;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr1\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr1\r
+//\r
+// This routine is used to Write KR1.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR1.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr1, @function\r
+.proc   AsmWriteKr1\r
+\r
+AsmWriteKr1::\r
+        mov             ar.k1 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr1\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr2\r
+//\r
+// This routine is used to get KR2.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR2.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr2, @function\r
+.proc   AsmReadKr2\r
+\r
+AsmReadKr2::\r
+        mov             r8 = ar.k2;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr2\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr2\r
+//\r
+// This routine is used to Write KR2.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR2.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr2, @function\r
+.proc   AsmWriteKr2\r
+\r
+AsmWriteKr2::\r
+        mov             ar.k2 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr2\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr3\r
+//\r
+// This routine is used to get KR3.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR3.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr3, @function\r
+.proc   AsmReadKr3\r
+\r
+AsmReadKr3::\r
+        mov             r8 = ar.k3;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr3\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr3\r
+//\r
+// This routine is used to Write KR3.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR3.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr3, @function\r
+.proc   AsmWriteKr3\r
+\r
+AsmWriteKr3::\r
+        mov             ar.k3 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr3\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr4\r
+//\r
+// This routine is used to get KR4.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR4.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr4, @function\r
+.proc   AsmReadKr4\r
+\r
+AsmReadKr4::\r
+        mov             r8 = ar.k4;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr4\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr4\r
+//\r
+// This routine is used to Write KR4.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR4.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr4, @function\r
+.proc   AsmWriteKr4\r
+\r
+AsmWriteKr4::\r
+        mov             ar.k4 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr4\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr5\r
+//\r
+// This routine is used to get KR5.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR5.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr5, @function\r
+.proc   AsmReadKr5\r
+\r
+AsmReadKr5::\r
+        mov             r8 = ar.k5;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr5\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr5\r
+//\r
+// This routine is used to Write KR5.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR5.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr5, @function\r
+.proc   AsmWriteKr5\r
+\r
+AsmWriteKr5::\r
+        mov             ar.k5 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr5\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr6\r
+//\r
+// This routine is used to get KR6.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR6.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr6, @function\r
+.proc   AsmReadKr6\r
+\r
+AsmReadKr6::\r
+        mov             r8 = ar.k6;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr6\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr6\r
+//\r
+// This routine is used to write KR6.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR6.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr6, @function\r
+.proc   AsmWriteKr6\r
+\r
+AsmWriteKr6::\r
+        mov             ar.k6 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr6\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadKr7\r
+//\r
+// This routine is used to get KR7.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value store in KR7.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadKr7, @function\r
+.proc   AsmReadKr7\r
+\r
+AsmReadKr7::\r
+        mov             r8 = ar.k7;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadKr7\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWriteKr7\r
+//\r
+// This routine is used to write KR7.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  None.\r
+//\r
+// Return Value: The value written to the KR7.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWriteKr7, @function\r
+.proc   AsmWriteKr7\r
+\r
+AsmWriteKr7::\r
+        mov             ar.k7 = in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWriteKr7\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s b/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
new file mode 100644 (file)
index 0000000..cea376c
--- /dev/null
@@ -0,0 +1,124 @@
+/// @file\r
+///  IPF specific Performance Monitor Configuration/Data Registers accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessPmr.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadPmc\r
+//\r
+// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit PMC index.\r
+//\r
+// Return Value: The current value of PMC by Index.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadPmc, @function\r
+.proc   AsmReadPmc\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmReadPmc::\r
+        srlz.i;;\r
+        srlz.d;;\r
+        mov             r8 = pmc[in0];;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadPmc\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWritePmc\r
+//\r
+// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit PMC index.\r
+//            The value should be written to PMC\r
+//\r
+// Return Value: The value written to PMC.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWritePmc, @function\r
+.proc   AsmWritePmc\r
+.regstk 2, 0, 0, 0\r
+\r
+AsmWritePmc::\r
+        mov             pmc[in0] = in1\r
+        mov             r8 = in1;;\r
+        srlz.i;;\r
+        srlz.d;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWritePmc\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadPmd\r
+//\r
+// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit PMD index.\r
+//\r
+// Return Value: The current value of PMD by Index.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadPmd, @function\r
+.proc   AsmReadPmd\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmReadPmd::\r
+        srlz.i;;\r
+        srlz.d;;\r
+        mov             r8 = pmd[in0];;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadPmd\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWritePmd\r
+//\r
+// This routine is used to write the current value to Performance Monitor Data Register (PMD).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit PMD index.\r
+//            The value should be written to PMD\r
+//\r
+// Return Value: The value written to PMD.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWritePmd, @function\r
+.proc   AsmWritePmd\r
+.regstk 2, 0, 0, 0\r
+\r
+AsmWritePmd::\r
+        mov             pmd[in0] = in1\r
+        mov             r8 = in1;;\r
+        srlz.i;;\r
+        srlz.d;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWritePmd\r
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s b/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
new file mode 100644 (file)
index 0000000..9b4fe49
--- /dev/null
@@ -0,0 +1,110 @@
+/// @file\r
+///  IPF specific Processor Status Register accessing functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AccessPsr.s\r
+///\r
+///\r
+\r
+#define CpuModeMask           0x0000001008020000\r
+\r
+#define CpuInVirtualMode             0x1\r
+#define CpuInPhysicalMode            0x0\r
+#define CpuInMixMode                 (0x0 - 0x1)\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadPsr\r
+//\r
+// This routine is used to read the current value of Processor Status Register (PSR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :\r
+//\r
+// Return Value: The current PSR value.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadPsr, @function\r
+.proc   AsmReadPsr\r
+\r
+AsmReadPsr::\r
+        mov             r8 = psr;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmReadPsr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmWritePsr\r
+//\r
+// This routine is used to write the value of Processor Status Register (PSR).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The value need to be written.\r
+//\r
+// Return Value: The value have been written.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmWritePsr, @function\r
+.proc   AsmWritePsr\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmWritePsr::\r
+        mov             psr.l = in0\r
+        mov             r8 = in0;;\r
+        srlz.d;;\r
+        srlz.i;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmWritePsr\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmCpuVirtual\r
+//\r
+// This routine is used to determines if the CPU is currently executing\r
+// in virtual, physical, or mixed mode.\r
+//\r
+// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.\r
+// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
+// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
+// and -1 is returned.\r
+//\r
+// Arguments:\r
+//\r
+// On Entry: None\r
+//\r
+// Return Value: The CPU mode flag\r
+//               return  1  The CPU is in virtual mode.\r
+//               return  0  The CPU is in physical mode.\r
+//               return -1  The CPU is in mixed mode.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmCpuVirtual, @function\r
+.proc   AsmCpuVirtual\r
+\r
+AsmCpuVirtual::\r
+        mov            r29 = psr\r
+        movl           r30 = CpuModeMask;;\r
+        and            r28 = r30, r29;;\r
+        cmp.eq         p6, p7 = r30, r28;;\r
+(p6)    mov            r8 = CpuInVirtualMode;;\r
+(p7)    cmp.eq         p6, p7 = 0x0, r28;;\r
+(p6)    mov            r8 = CpuInPhysicalMode;;\r
+(p7)    mov            r8 = CpuInMixMode;;\r
+        br.ret.dpnt    b0;;\r
+.endp   AsmCpuVirtual
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s b/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
new file mode 100644 (file)
index 0000000..9e70a78
--- /dev/null
@@ -0,0 +1,158 @@
+/// @file\r
+///   Contains an implementation of CallPalProcStacked on Itanium-based\r
+///   architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  AsmPalCall.s\r
+///\r
+///\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//++\r
+//  AsmPalCall\r
+//\r
+//  Makes a PAL procedure call.\r
+//  This is function to make a PAL procedure call.  Based on the Index\r
+//  value this API will make static or stacked PAL call.  The following table\r
+//  describes the usage of PAL Procedure Index Assignment. Architected procedures\r
+//  may be designated as required or optional.  If a PAL procedure is specified\r
+//  as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the\r
+//  Status field of the PAL_CALL_RETURN structure.\r
+//  This indicates that the procedure is not present in this PAL implementation.\r
+//  It is the caller¡¯s responsibility to check for this return code after calling\r
+//  any optional PAL procedure.\r
+//  No parameter checking is performed on the 5 input parameters, but there are\r
+//  some common rules that the caller should follow when making a PAL call.  Any\r
+//  address passed to PAL as buffers for return parameters must be 8-byte aligned.\r
+//  Unaligned addresses may cause undefined results.  For those parameters defined\r
+//  as reserved or some fields defined as reserved must be zero filled or the invalid\r
+//  argument return value may be returned or undefined result may occur during the\r
+//  execution of the procedure.  If the PalEntryPoint  does not point to a valid\r
+//  PAL entry point then the system behavior is undefined.  This function is only\r
+//  available on IPF.\r
+//\r
+//  On Entry :\r
+//           in0:  PAL_PROC entrypoint\r
+//           in1-in4 : PAL_PROC arguments\r
+//\r
+//  Return Value:\r
+//\r
+//  As per stacked calling conventions.\r
+//\r
+//--\r
+//---------------------------------------------------------------------------\r
+\r
+//\r
+// PAL function calls\r
+//\r
+#define PAL_MC_CLEAR_LOG               0x0015\r
+#define PAL_MC_DYNAMIC_STATE           0x0018\r
+#define PAL_MC_ERROR_INFO              0x0019\r
+#define PAL_MC_RESUME                  0x001a\r
+\r
+\r
+.text\r
+.proc AsmPalCall\r
+.type AsmPalCall, @function\r
+\r
+AsmPalCall::\r
+         alloc          loc1 = ar.pfs,5,8,4,0\r
+         mov            loc0 = b0\r
+         mov            loc3 = b5\r
+         mov            loc4 = r2\r
+         mov            loc7 = r1\r
+         mov            r2 = psr;;\r
+         mov            r28 = in1\r
+         mov            loc5 = r2;;\r
+\r
+         movl           loc6 = 0x100;;\r
+         cmp.ge         p6,p7 = r28,loc6;;\r
+\r
+(p6)     movl           loc6 = 0x1FF;;\r
+(p7)     br.dpnt.few PalCallStatic;;                  // 0 ~ 255 make a static Pal Call\r
+(p6)     cmp.le         p6,p7 = r28,loc6;;\r
+(p6)     br.dpnt.few PalCallStacked;;                 // 256 ~ 511 make a stacked Pal Call\r
+(p7)     movl           loc6 = 0x300;;\r
+(p7)     cmp.ge         p6,p7 = r28,loc6;;\r
+(p7)     br.dpnt.few PalCallStatic;;                  // 512 ~ 767 make a static Pal Call\r
+(p6)     movl           loc6 = 0x3FF;;\r
+(p6)     cmp.le         p6,p7 = r28,loc6;;\r
+(p6)     br.dpnt.few PalCallStacked;;                 // 768 ~ 1023 make a stacked Pal Call\r
+\r
+(p7)     mov            r8 = 0xFFFFFFFFFFFFFFFF;;     // > 1024 return invalid\r
+(p7)     br.dpnt.few    ComeBackFromPALCall;;\r
+\r
+PalCallStatic:\r
+         movl           loc6 = PAL_MC_CLEAR_LOG;;\r
+         cmp.eq         p6,p7 = r28,loc6;;\r
+\r
+(p7)     movl           loc6 = PAL_MC_DYNAMIC_STATE;;\r
+(p7)     cmp.eq         p6,p7 = r28,loc6;;\r
+\r
+(p7)     movl           loc6 = PAL_MC_ERROR_INFO;;\r
+(p7)     cmp.eq         p6,p7 = r28,loc6;;\r
+\r
+(p7)     movl           loc6 = PAL_MC_RESUME;;\r
+(p7)     cmp.eq         p6,p7 = r28,loc6 ;;\r
+\r
+         mov            loc6 = 0x1;;\r
+(p7)     dep            r2 = loc6,r2,13,1;;           // psr.ic = 1\r
+\r
+// p6 will be true, if it is one of the MCHK calls. There has been lots of debate\r
+// on psr.ic for these values. For now, do not do any thing to psr.ic\r
+\r
+         dep            r2 = r0,r2,14,1;;             // psr.i = 0\r
+\r
+         mov            psr.l = r2\r
+         srlz.d                                       // Needs data serailization.\r
+         srlz.i                                       // Needs instruction serailization.\r
+\r
+StaticGetPALLocalIP:\r
+         mov            loc2 = ip;;\r
+         add            loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;\r
+         mov            b0 = loc2                     // return address after Pal call\r
+\r
+         mov            r29 = in2\r
+         mov            r30 = in3\r
+         mov            r31 = in4\r
+         mov            b5 = in0;;                    // get the PalProcEntrypt from input\r
+         br.sptk        b5;;                          // Take the plunge.\r
+\r
+PalCallStacked:\r
+         dep            r2 = r0,r2,14,1;;             // psr.i = 0\r
+         mov            psr.l = r2;;\r
+         srlz.d                                       // Needs data serailization.\r
+         srlz.i                                       // Needs instruction serailization.\r
+\r
+StackedGetPALLocalIP:\r
+         mov            out0 = in1\r
+         mov            out1 = in2\r
+         mov            out2 = in3\r
+         mov            out3 = in4\r
+         mov            b5 =  in0 ;;                  // get the PalProcEntrypt from input\r
+         br.call.dpnt   b0 = b5 ;;                    // Take the plunge.\r
+\r
+ComeBackFromPALCall:\r
+         mov            psr.l = loc5 ;;\r
+         srlz.d                                       // Needs data serailization.\r
+         srlz.i                                       // Needs instruction serailization.\r
+\r
+         mov            b5 = loc3\r
+         mov            r2 = loc4\r
+         mov            r1 = loc7\r
+\r
+         mov            b0 = loc0\r
+         mov            ar.pfs = loc1;;\r
+         br.ret.dpnt    b0;;\r
+\r
+.endp AsmPalCall\r
+\r
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
new file mode 100644 (file)
index 0000000..3dcbecf
--- /dev/null
@@ -0,0 +1,123 @@
+/** @file\r
+  Base Library CPU functions for Itanium\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include <BaseLibInternals.h>\r
+\r
+//void __mfa (void);\r
+\r
+#pragma intrinsic (_enable)\r
+#pragma intrinsic (_disable)\r
+#pragma intrinsic (__break)\r
+#pragma intrinsic (__mfa)\r
+\r
+\r
+/**\r
+  Generates a breakpoint on the CPU.\r
+\r
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+  that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+  VOID\r
+  )\r
+{\r
+  __break (0);\r
+}\r
+\r
+/**\r
+  Used to serialize load and store operations.\r
+\r
+  All loads and stores that proceed calls to this function are guaranteed to be\r
+  globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+  VOID\r
+  )\r
+{\r
+  __mfa ();\r
+}\r
+\r
+/**\r
+  Disables CPU interrupts.\r
+\r
+  Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  _disable ();\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts.\r
+\r
+  Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  _enable ();\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  EnableInterrupts ();\r
+  DisableInterrupts ();\r
+}\r
+\r
+/**\r
+  Places the CPU in a sleep state until an interrupt is received.\r
+\r
+  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+  are disabled prior to calling this function, then the CPU will be placed in a\r
+  sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+  VOID\r
+  )\r
+{\r
+  PalCallStatic (NULL, 29, 0, 0, 0);\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s b/MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s
new file mode 100644 (file)
index 0000000..520c51f
--- /dev/null
@@ -0,0 +1,58 @@
+/// @file\r
+///   CpuFlushTlb() function for Itanium-based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  CpuFlushTlb.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.globl PalCallStatic\r
+.type   PalCallStatic, @function\r
+\r
+.proc   CpuFlushTlb\r
+.type   CpuFlushTlb, @function\r
+CpuFlushTlb::\r
+        alloc               loc0 = ar.pfs, 0, 3, 5, 0\r
+        mov                 out0 = 0\r
+        mov                 out1 = 6\r
+        mov                 out2 = 0\r
+        mov                 out3 = 0\r
+        mov                 loc1 = b0\r
+        mov                 out4 = 0\r
+        brl.call.sptk       b0  = PalCallStatic\r
+        mov                 loc2 = psr              // save PSR\r
+        mov                 ar.pfs = loc0\r
+        extr.u              r14 = r10, 32, 32       // r14 <- count1\r
+        rsm                 1 << 14                 // Disable interrupts\r
+        extr.u              r15 = r11, 32, 32       // r15 <- stride1\r
+        extr.u              r10 = r10, 0, 32        // r10 <- count2\r
+        add                 r10 = -1, r10\r
+        extr.u              r11 = r11, 0, 32        // r11 <- stride2\r
+        br.cond.sptk        LoopPredicate\r
+LoopOuter:\r
+        mov                 ar.lc = r10             // LC <- count2\r
+        mov                 ar.ec = r0              // EC <- 0\r
+Loop:\r
+        ptc.e               r9\r
+        add                 r9 = r11, r9            // r9 += stride2\r
+        br.ctop.sptk        Loop\r
+        add                 r9 = r15, r9            // r9 += stride1\r
+LoopPredicate:\r
+        cmp.ne              p6 = r0, r14            // count1 == 0?\r
+        add                 r14 = -1, r14\r
+(p6)    br.cond.sptk        LoopOuter\r
+        mov                 psr.l = loc2\r
+        mov                 b0  = loc1\r
+        br.ret.sptk.many    b0\r
+.endp\r
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuPause.s b/MdePkg/Library/BaseLib/Ipf/CpuPause.s
new file mode 100644 (file)
index 0000000..f52692f
--- /dev/null
@@ -0,0 +1,25 @@
+/// @file\r
+///   CpuPause() function for Itanium-based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  CpuPause.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   CpuPause\r
+.type   CpuPause, @function\r
+CpuPause::\r
+        hint                @pause\r
+        br.ret.sptk.many    b0\r
+.endp\r
diff --git a/MdePkg/Library/BaseLib/Ipf/ExecFc.s b/MdePkg/Library/BaseLib/Ipf/ExecFc.s
new file mode 100644 (file)
index 0000000..a5a9e9b
--- /dev/null
@@ -0,0 +1,66 @@
+/// @file\r
+///  IPF specific AsmFc() and AsmFci () functions\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: ExecFc.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmFc\r
+//\r
+// This routine is used to execute a FC instruction on the specific address.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The specific address need to execute FC instruction.\r
+//\r
+// Return Value: The specific address have been execute FC instruction.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmFc, @function\r
+.proc   AsmFc\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmFc::\r
+        fc              in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmFc\r
+\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmFci\r
+//\r
+// This routine is used to execute a FC.i instruction on the specific address.\r
+//\r
+// Arguments :\r
+//\r
+// On Entry :  The specific address need to execute FC.i instruction.\r
+//\r
+// Return Value: The specific address have been execute FC.i instruction.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmFci, @function\r
+.proc   AsmFci\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmFci::\r
+        fc.i            in0\r
+        mov             r8 = in0;;\r
+        br.ret.dpnt     b0;;\r
+.endp   AsmFci
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s
new file mode 100644 (file)
index 0000000..6e467f0
--- /dev/null
@@ -0,0 +1,96 @@
+//++\r
+// Copyright (c) 2006, Intel Corporation                                                         \r
+// All rights reserved. This program and the accompanying materials                          \r
+// are licensed and made available under the terms and conditions of the BSD License         \r
+// which accompanies this distribution.  The full text of the license may be found at        \r
+// http://opensource.org/licenses/bsd-license.php                                            \r
+//                                                                                           \r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+// \r
+//  Module Name:\r
+//    FlushCacheRange.s \r
+//\r
+//  Abstract:\r
+//    Assemble routine to flush cache lines \r
+//\r
+// Revision History:\r
+//\r
+//--\r
+.file  "IpfCpuCache.s"\r
+\r
+#include  "IpfMacro.i"\r
+//#include  "IpfDefines.h"\r
+\r
+//\r
+//  Invalidates a range of instruction cache lines in the cache coherency domain\r
+//  of the calling CPU.\r
+//\r
+//  Invalidates the instruction cache lines specified by Address and Length. If\r
+//  Address is not aligned on a cache line boundary, then entire instruction\r
+//  cache line containing Address is invalidated. If Address + Length is not\r
+//  aligned on a cache line boundary, then the entire instruction cache line\r
+//  containing Address + Length -1 is invalidated. This function may choose to\r
+//  invalidate the entire instruction cache if that is more efficient than\r
+//  invalidating the specified range. If Length is 0, the no instruction cache\r
+//  lines are invalidated. Address is returned.\r
+//\r
+//  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+//\r
+//  @param  Address The base address of the instruction cache lines to\r
+//                  invalidate. If the CPU is in a physical addressing mode, then\r
+//                  Address is a physical address. If the CPU is in a virtual\r
+//                  addressing mode, then Address is a virtual address.\r
+//\r
+//  @param  Length  The number of bytes to invalidate from the instruction cache.\r
+//\r
+//  @return Address\r
+//  \r
+//  VOID *\r
+//  EFIAPI\r
+//  IpfFlushCacheRange (\r
+//    IN      VOID                      *Address,\r
+//    IN      UINTN                     Length\r
+//    );\r
+//\r
+PROCEDURE_ENTRY (IpfFlushCacheRange)\r
+\r
+      NESTED_SETUP (5,8,0,0)\r
+            \r
+      mov         loc2 = ar.lc\r
+      \r
+      mov         loc3 = in0                  // Start address.\r
+      mov         loc4 = in1;;                // Length in bytes.\r
+      \r
+      cmp.eq  p6,p7 = loc4, r0;;               // If Length is zero then don't flush any cache\r
+      (p6)  br.spnt.many DoneFlushingC;;         \r
+      \r
+      add         loc4 = loc4,loc3 \r
+      mov         loc5 = 1;;\r
+      sub         loc4 = loc4, loc5 ;; // the End address to flush\r
+                                         \r
+      dep         loc3 = r0,loc3,0,5          \r
+      dep         loc4 = r0,loc4,0,5;;         \r
+      shr         loc3 = loc3,5             \r
+      shr         loc4 = loc4,5;;    // 32 byte cache line\r
+      \r
+      sub         loc4 = loc4,loc3;; // total flush count, It should be add 1 but \r
+                                     // the br.cloop will first execute one time \r
+      mov         loc3 = in0                  \r
+      mov         loc5 = 32      \r
+      mov         ar.lc = loc4;;\r
+\r
+StillFlushingC:\r
+      fc          loc3;; \r
+      sync.i;;\r
+      srlz.i;;\r
+      add         loc3 = loc5,loc3;;\r
+      br.cloop.sptk.few StillFlushingC;;\r
+\r
+DoneFlushingC:      \r
+      mov         ar.lc = loc2     \r
+      mov          r8   = in0       // return *Address\r
+      NESTED_RETURN\r
+\r
+PROCEDURE_EXIT (IpfFlushCacheRange)\r
+\r
diff --git a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s b/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
new file mode 100644 (file)
index 0000000..d5b5fc8
--- /dev/null
@@ -0,0 +1,27 @@
+/// @file\r
+///   Retrieve of the interrupt state of the running processor for the Itanium\r
+///   architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  GetInterruptState.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   GetInterruptState\r
+.type   GetInterruptState, @function\r
+GetInterruptState::\r
+        mov                 r8  = psr\r
+        extr.u              r8  = r8, 14, 1\r
+        br.ret.sptk.many    b0\r
+.endp   GetInterruptState\r
diff --git a/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s
new file mode 100644 (file)
index 0000000..3a278d7
--- /dev/null
@@ -0,0 +1,29 @@
+/// @file\r
+///   Contains an implementation of InterlockedCompareExchange32 on Itanium-\r
+///   based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  InterlockedCompareExchange32.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   InternalSyncCompareExchange32\r
+.type   InternalSyncCompareExchange32, @function\r
+InternalSyncCompareExchange32::\r
+        zxt4                r33 = r33\r
+        mov                 ar.ccv = r33\r
+        cmpxchg4.rel        r8  = [r32], r34\r
+        mf\r
+        br.ret.sptk.many    b0\r
+.endp   InternalSyncCompareExchange32
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s
new file mode 100644 (file)
index 0000000..88b9d2b
--- /dev/null
@@ -0,0 +1,28 @@
+/// @file\r
+///   Contains an implementation of InterlockedCompareExchange64 on Itanium-\r
+///   based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  InterlockedCompareExchange64.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   InternalSyncCompareExchange64\r
+.type   InternalSyncCompareExchange64, @function\r
+InternalSyncCompareExchange64::\r
+        mov                 ar.ccv = r33\r
+        cmpxchg8.rel        r8  = [r32], r34\r
+        mf\r
+        br.ret.sptk.many    b0\r
+.endp   InternalSyncCompareExchange64
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c b/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
new file mode 100644 (file)
index 0000000..60d0a37
--- /dev/null
@@ -0,0 +1,68 @@
+/** @file\r
+  SwitchStack() function for IPF.\r
+\r
+  Copyright (c) 2007, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  InternalSwitchStack.c\r
+\r
+**/\r
+\r
+#include <BaseLibInternals.h>\r
+\r
+/**
+  Transfers control to a function starting with a new stack.
+
+  Transfers control to the function specified by EntryPoint using the
+  new stack specified by NewStack and passing in the parameters specified
+  by Context1 and Context2.  Context1 and Context2 are optional and may
+  be NULL.  The function EntryPoint must never return.
+  Marker will be ignored on IA-32, x64, and EBC.
+  IPF CPUs expect one additional parameter of type VOID * that specifies
+  the new backing store pointer.\r
+
+  If EntryPoint is NULL, then ASSERT().\r
+  If NewStack is NULL, then ASSERT().\r
+
+  @param  EntryPoint  A pointer to function to call with the new stack.
+  @param  Context1    A pointer to the context to pass into the EntryPoint
+                      function.
+  @param  Context2    A pointer to the context to pass into the EntryPoint
+                      function.
+  @param  NewStack    A pointer to the new stack to use for the EntryPoint
+                      function.\r
+  @param  Marker      VA_LIST marker for the variable argument list.
+
+**/\r
+VOID
+EFIAPI
+InternalSwitchStack (
+  IN      SWITCH_STACK_ENTRY_POINT  EntryPoint,
+  IN      VOID                      *Context1,   OPTIONAL
+  IN      VOID                      *Context2,   OPTIONAL
+  IN      VOID                      *NewStack,
+  IN      VA_LIST                   Marker
+  )\r
+\r
+{\r
+  VOID                      *NewBsp;\r
+\r
+  //\r
+  // Get new backing store pointer from variable list\r
+  //\r
+  NewBsp   = VA_ARG (Marker, VOID *);\r
+\r
+  //\r
+  // Stack should be aligned with CPU_STACK_ALIGNMENT\r
+  //\r
+  ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+  ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+\r
+  AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ipf/PalCallStatic.s b/MdePkg/Library/BaseLib/Ipf/PalCallStatic.s
new file mode 100644 (file)
index 0000000..c21d742
--- /dev/null
@@ -0,0 +1,48 @@
+/// @file\r
+///   Contains an implementation of CallPalProcStatic on Itanium-based\r
+///   architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  PalCallStatic.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   PalCallStatic\r
+.type   PalCallStatic, @function\r
+.regstk 5, 0, 0, 0\r
+PalCallStatic::\r
+        cmp.eq              p15 = in0, r0\r
+        mov                 r31 = in4\r
+        mov                 r8  = ip\r
+\r
+(p15)   mov                 in0 = ar.k5\r
+        add                 r8  = (_PalProcReturn - PalCallStatic), r8\r
+        mov                 r30 = in3\r
+\r
+        mov                 in4 = psr\r
+        mov                 in3 = b0\r
+        mov                 b7  = in0\r
+\r
+        rsm                 1 << 14                 // Disable interrupts\r
+        mov                 r29 = in2\r
+        mov                 r28 = in1\r
+\r
+        mov                 b0  = r8\r
+        br.cond.sptk.many   b7\r
+\r
+_PalProcReturn:\r
+        mov                 psr.l = in4\r
+        mov                 b0  = in3\r
+        br.ret.sptk.many    b0\r
+.endp   PalCallStatic\r
diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s b/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
new file mode 100644 (file)
index 0000000..2176dad
--- /dev/null
@@ -0,0 +1,40 @@
+/// @file\r
+///  IPF specific AsmReadCpuid()function\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: ReadCpuid.s\r
+///\r
+///\r
+\r
+//---------------------------------------------------------------------------------\r
+//++\r
+// AsmReadCpuid\r
+//\r
+// This routine is used to Reads the current value of Processor Identifier Register (CPUID).\r
+//\r
+// Arguments :\r
+//\r
+// On Entry : The 8-bit Processor Identifier Register index to read.\r
+//\r
+// Return Value: The current value of Processor Identifier Register specified by Index.\r
+//\r
+//--\r
+//----------------------------------------------------------------------------------\r
+.text\r
+.type   AsmReadCpuid, @function\r
+.proc   AsmReadCpuid\r
+.regstk 1, 0, 0, 0\r
+\r
+AsmReadCpuid::\r
+        mov             r8 = cpuid[in0];;\r
+        br.ret.dpnt     b0;;\r
+.endp    AsmReadCpuid\r
+\r
diff --git a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s b/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
new file mode 100644 (file)
index 0000000..a3c524f
--- /dev/null
@@ -0,0 +1,50 @@
+/// @file\r
+///  IPF specific SwitchStack() function\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: SwitchStack.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   AsmSwitchStackAndBackingStore\r
+.type   AsmSwitchStackAndBackingStore, @function\r
+.regstk 5, 0, 0, 0\r
+AsmSwitchStackAndBackingStore::\r
+        mov                 r14 = ar.rsc\r
+        movl                r2  = ~((((1 << 14) - 1) << 16) | 3)\r
+\r
+        mov                 r17 = in1\r
+        mov                 r18 = in2\r
+        and                 r2  = r14, r2\r
+\r
+        mov                 ar.rsc = r2\r
+        mov                 sp  = in3\r
+        mov                 r19 = in4\r
+\r
+        ld8.nt1             r16 = [in0], 8\r
+        ld8.nta             gp  = [in0]\r
+        mov                 r3  = -1\r
+\r
+        loadrs\r
+        mov                 ar.bspstore = r19\r
+        mov                 b7  = r16\r
+\r
+        alloc               r2  = ar.pfs, 0, 0, 2, 0\r
+        mov                 out0 = r17\r
+        mov                 out1 = r18\r
+\r
+        mov                 ar.rnat = r3\r
+        mov                 ar.rsc = r14\r
+        br.call.sptk.many   b0  = b7\r
+.endp   AsmSwitchStackAndBackingStore\r
diff --git a/MdePkg/Library/BaseLib/Ipf/Synchronization.c b/MdePkg/Library/BaseLib/Ipf/Synchronization.c
new file mode 100644 (file)
index 0000000..c29a876
--- /dev/null
@@ -0,0 +1,79 @@
+/** @file\r
+  Implementation of synchronization functions on Itanium.\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  Synchronization.c\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+  Performs an atomic increment of an 32-bit unsigned integer.\r
+\r
+  Performs an atomic increment of the 32-bit unsigned integer specified by\r
+  Value and returns the incremented value. The increment operation must be\r
+  performed using MP safe mechanisms. The state of the return value is not\r
+  guaranteed to be MP safe.\r
+\r
+  @param  Value A pointer to the 32-bit value to increment.\r
+\r
+  @return The incremented value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncIncrement (\r
+  IN      volatile UINT32           *Value\r
+  )\r
+{\r
+  UINT32                            OriginalValue;\r
+\r
+  do {\r
+    OriginalValue = *Value;\r
+  } while (OriginalValue != InternalSyncCompareExchange32 (\r
+                              Value,\r
+                              OriginalValue,\r
+                              OriginalValue + 1\r
+                              ));\r
+  return OriginalValue + 1;\r
+}\r
+\r
+/**\r
+  Performs an atomic decrement of an 32-bit unsigned integer.\r
+\r
+  Performs an atomic decrement of the 32-bit unsigned integer specified by\r
+  Value and returns the decrement value. The decrement operation must be\r
+  performed using MP safe mechanisms. The state of the return value is not\r
+  guaranteed to be MP safe.\r
+\r
+  @param  Value A pointer to the 32-bit value to decrement.\r
+\r
+  @return The decrement value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalSyncDecrement (\r
+  IN      volatile UINT32           *Value\r
+  )\r
+{\r
+  UINT32                            OriginalValue;\r
+\r
+  do {\r
+    OriginalValue = *Value;\r
+  } while (OriginalValue != InternalSyncCompareExchange32 (\r
+                              Value,\r
+                              OriginalValue,\r
+                              OriginalValue - 1\r
+                              ));\r
+  return OriginalValue - 1;\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ipf/Unaligned.c b/MdePkg/Library/BaseLib/Ipf/Unaligned.c
new file mode 100644 (file)
index 0000000..1c4a937
--- /dev/null
@@ -0,0 +1,248 @@
+/** @file\r
+  Unaligned access functions of BaseLib for IPF.\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  Unaligned.c\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include <BaseLibInternals.h>\r
+\r
+/**\r
+  Reads a 16-bit value from memory that may be unaligned.\r
+\r
+  This function returns the 16-bit value pointed to by Buffer. The function\r
+  guarantees that the read operation does not produce an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 16-bit value that may be unaligned.\r
+\r
+  @return *Uint16\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+ReadUnaligned16 (\r
+  IN      CONST UINT16              *Buffer\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));\r
+}\r
+\r
+/**\r
+  Writes a 16-bit value to memory that may be unaligned.\r
+\r
+  This function writes the 16-bit value specified by Value to Buffer. Value is\r
+  returned. The function guarantees that the write operation does not produce\r
+  an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 16-bit value that may be unaligned.\r
+  @param  Value   16-bit value to write to Buffer.\r
+\r
+  @return Value\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+WriteUnaligned16 (\r
+  OUT     UINT16                    *Buffer,\r
+  IN      UINT16                    Value\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  ((UINT8*)Buffer)[0] = (UINT8)Value;\r
+  ((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);\r
+\r
+  return Value;\r
+}\r
+\r
+/**\r
+  Reads a 24-bit value from memory that may be unaligned.\r
+\r
+  This function returns the 24-bit value pointed to by Buffer. The function\r
+  guarantees that the read operation does not produce an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 24-bit value that may be unaligned.\r
+\r
+  @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned24 (\r
+  IN      CONST UINT32              *Buffer\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  return (UINT32)(\r
+            ReadUnaligned16 ((UINT16*)Buffer) |\r
+            (((UINT8*)Buffer)[2] << 16)\r
+            );\r
+}\r
+\r
+/**\r
+  Writes a 24-bit value to memory that may be unaligned.\r
+\r
+  This function writes the 24-bit value specified by Value to Buffer. Value is\r
+  returned. The function guarantees that the write operation does not produce\r
+  an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 24-bit value that may be unaligned.\r
+  @param  Value   24-bit value to write to Buffer.\r
+\r
+  @return The value written.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned24 (\r
+  OUT     UINT32                    *Buffer,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
+  *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);\r
+  return Value;\r
+}\r
+\r
+/**\r
+  Reads a 32-bit value from memory that may be unaligned.\r
+\r
+  This function returns the 32-bit value pointed to by Buffer. The function\r
+  guarantees that the read operation does not produce an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 32-bit value that may be unaligned.\r
+\r
+  @return *Uint32\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned32 (\r
+  IN      CONST UINT32              *Buffer\r
+  )\r
+{\r
+  UINT16  LowerBytes;\r
+  UINT16  HigherBytes;\r
+\r
+  ASSERT (Buffer != NULL);\r
+\r
+  LowerBytes  = ReadUnaligned16 ((UINT16*) Buffer);\r
+  HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);\r
+\r
+  return (UINT32) (LowerBytes | (HigherBytes << 16));\r
+}\r
+\r
+/**\r
+  Writes a 32-bit value to memory that may be unaligned.\r
+\r
+  This function writes the 32-bit value specified by Value to Buffer. Value is\r
+  returned. The function guarantees that the write operation does not produce\r
+  an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 32-bit value that may be unaligned.\r
+  @param  Value   32-bit value to write to Buffer.\r
+\r
+  @return Value\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned32 (\r
+  OUT     UINT32                    *Buffer,\r
+  IN      UINT32                    Value\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
+  WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));\r
+  return Value;\r
+}\r
+\r
+/**\r
+  Reads a 64-bit value from memory that may be unaligned.\r
+\r
+  This function returns the 64-bit value pointed to by Buffer. The function\r
+  guarantees that the read operation does not produce an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 64-bit value that may be unaligned.\r
+\r
+  @return *Uint64\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+ReadUnaligned64 (\r
+  IN      CONST UINT64              *Buffer\r
+  )\r
+{\r
+  UINT32  LowerBytes;\r
+  UINT32  HigherBytes;\r
+\r
+  ASSERT (Buffer != NULL);\r
+\r
+  LowerBytes  = ReadUnaligned32 ((UINT32*) Buffer);\r
+  HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);\r
+\r
+  return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));\r
+}\r
+\r
+/**\r
+  Writes a 64-bit value to memory that may be unaligned.\r
+\r
+  This function writes the 64-bit value specified by Value to Buffer. Value is\r
+  returned. The function guarantees that the write operation does not produce\r
+  an alignment fault.\r
+\r
+  If the Buffer is NULL, then ASSERT().\r
+\r
+  @param  Buffer  Pointer to a 64-bit value that may be unaligned.\r
+  @param  Value   64-bit value to write to Buffer.\r
+\r
+  @return Value\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+WriteUnaligned64 (\r
+  OUT     UINT64                    *Buffer,\r
+  IN      UINT64                    Value\r
+  )\r
+{\r
+  ASSERT (Buffer != NULL);\r
+\r
+  WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);\r
+  WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));\r
+  return Value;\r
+}\r
diff --git a/MdePkg/Library/BaseLib/Ipf/asm.h b/MdePkg/Library/BaseLib/Ipf/asm.h
new file mode 100644 (file)
index 0000000..8ef0b30
--- /dev/null
@@ -0,0 +1,27 @@
+/// @file\r
+///   This module contains generic macros for an assembly writer.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation<BR>\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: asm.h\r
+///\r
+#ifndef _ASM_H\r
+#define _ASM_H\r
+\r
+#define TRUE  1\r
+#define FALSE 0\r
+#define PROCEDURE_ENTRY(name)   .##text;            \\r
+  .##type name, @function; \\r
+  .##proc name; \\r
+  name::\r
+\r
+#define PROCEDURE_EXIT(name)  .##endp name\r
+\r
+#endif // _ASM_H\r
diff --git a/MdePkg/Library/BaseLib/Ipf/ia_64gen.h b/MdePkg/Library/BaseLib/Ipf/ia_64gen.h
new file mode 100644 (file)
index 0000000..081cc4a
--- /dev/null
@@ -0,0 +1,205 @@
+/// @file\r
+/// \r
+/// \r
+/// Copyright (c) 2006, Intel Corporation<BR>\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+/// \r
+/// Module Name: ia_64gen.h\r
+///\r
+#ifndef _IA64GEN_H\r
+#define _IA64GEN_H\r
+\r
+#define TT_UNAT           0\r
+#define C_PSR             0\r
+#define J_UNAT            0\r
+#define T_TYPE            0\r
+#define T_IPSR            0x8\r
+#define T_ISR             0x10\r
+#define T_IIP             0x18\r
+#define T_IFA             0x20\r
+#define T_IIPA            0x28\r
+#define T_IFS             0x30\r
+#define T_IIM             0x38\r
+#define T_RSC             0x40\r
+#define T_BSP             0x48\r
+#define T_BSPSTORE        0x50\r
+#define T_RNAT            0x58\r
+#define T_PFS             0x60\r
+#define T_KBSPSTORE       0x68\r
+#define T_UNAT            0x70\r
+#define T_CCV             0x78\r
+#define T_DCR             0x80\r
+#define T_PREDS           0x88\r
+#define T_NATS            0x90\r
+#define T_R1              0x98\r
+#define T_GP              0x98\r
+#define T_R2              0xa0\r
+#define T_R3              0xa8\r
+#define T_R4              0xb0\r
+#define T_R5              0xb8\r
+#define T_R6              0xc0\r
+#define T_R7              0xc8\r
+#define T_R8              0xd0\r
+#define T_R9              0xd8\r
+#define T_R10             0xe0\r
+#define T_R11             0xe8\r
+#define T_R12             0xf0\r
+#define T_SP              0xf0\r
+#define T_R13             0xf8\r
+#define T_R14             0x100\r
+#define T_R15             0x108\r
+#define T_R16             0x110\r
+#define T_R17             0x118\r
+#define T_R18             0x120\r
+#define T_R19             0x128\r
+#define T_R20             0x130\r
+#define T_R21             0x138\r
+#define T_R22             0x140\r
+#define T_R23             0x148\r
+#define T_R24             0x150\r
+#define T_R25             0x158\r
+#define T_R26             0x160\r
+#define T_R27             0x168\r
+#define T_R28             0x170\r
+#define T_R29             0x178\r
+#define T_R30             0x180\r
+#define T_R31             0x188\r
+#define T_F2              0x1f0\r
+#define T_F3              0x200\r
+#define T_F4              0x210\r
+#define T_F5              0x220\r
+#define T_F6              0x230\r
+#define T_F7              0x240\r
+#define T_F8              0x250\r
+#define T_F9              0x260\r
+#define T_F10             0x270\r
+#define T_F11             0x280\r
+#define T_F12             0x290\r
+#define T_F13             0x2a0\r
+#define T_F14             0x2b0\r
+#define T_F15             0x2c0\r
+#define T_F16             0x2d0\r
+#define T_F17             0x2e0\r
+#define T_F18             0x2f0\r
+#define T_F19             0x300\r
+#define T_F20             0x310\r
+#define T_F21             0x320\r
+#define T_F22             0x330\r
+#define T_F23             0x340\r
+#define T_F24             0x350\r
+#define T_F25             0x360\r
+#define T_F26             0x370\r
+#define T_F27             0x380\r
+#define T_F28             0x390\r
+#define T_F29             0x3a0\r
+#define T_F30             0x3b0\r
+#define T_F31             0x3c0\r
+#define T_FPSR            0x1e0\r
+#define T_B0              0x190\r
+#define T_B1              0x198\r
+#define T_B2              0x1a0\r
+#define T_B3              0x1a8\r
+#define T_B4              0x1b0\r
+#define T_B5              0x1b8\r
+#define T_B6              0x1c0\r
+#define T_B7              0x1c8\r
+#define T_EC              0x1d0\r
+#define T_LC              0x1d8\r
+#define J_NATS            0x8\r
+#define J_PFS             0x10\r
+#define J_BSP             0x18\r
+#define J_RNAT            0x20\r
+#define J_PREDS           0x28\r
+#define J_LC              0x30\r
+#define J_R4              0x38\r
+#define J_R5              0x40\r
+#define J_R6              0x48\r
+#define J_R7              0x50\r
+#define J_SP              0x58\r
+#define J_F2              0x60\r
+#define J_F3              0x70\r
+#define J_F4              0x80\r
+#define J_F5              0x90\r
+#define J_F16             0xa0\r
+#define J_F17             0xb0\r
+#define J_F18             0xc0\r
+#define J_F19             0xd0\r
+#define J_F20             0xe0\r
+#define J_F21             0xf0\r
+#define J_F22             0x100\r
+#define J_F23             0x110\r
+#define J_F24             0x120\r
+#define J_F25             0x130\r
+#define J_F26             0x140\r
+#define J_F27             0x150\r
+#define J_F28             0x160\r
+#define J_F29             0x170\r
+#define J_F30             0x180\r
+#define J_F31             0x190\r
+#define J_FPSR            0x1a0\r
+#define J_B0              0x1a8\r
+#define J_B1              0x1b0\r
+#define J_B2              0x1b8\r
+#define J_B3              0x1c0\r
+#define J_B4              0x1c8\r
+#define J_B5              0x1d0\r
+#define TRAP_FRAME_LENGTH 0x3d0\r
+#define C_UNAT            0x28\r
+#define C_NATS            0x30\r
+#define C_PFS             0x8\r
+#define C_BSPSTORE        0x10\r
+#define C_RNAT            0x18\r
+#define C_RSC             0x20\r
+#define C_PREDS           0x38\r
+#define C_LC              0x40\r
+#define C_DCR             0x48\r
+#define C_R1              0x50\r
+#define C_GP              0x50\r
+#define C_R4              0x58\r
+#define C_R5              0x60\r
+#define C_R6              0x68\r
+#define C_R7              0x70\r
+#define C_SP              0x78\r
+#define C_R13             0x80\r
+#define C_F2              0x90\r
+#define C_F3              0xa0\r
+#define C_F4              0xb0\r
+#define C_F5              0xc0\r
+#define C_F16             0xd0\r
+#define C_F17             0xe0\r
+#define C_F18             0xf0\r
+#define C_F19             0x100\r
+#define C_F20             0x110\r
+#define C_F21             0x120\r
+#define C_F22             0x130\r
+#define C_F23             0x140\r
+#define C_F24             0x150\r
+#define C_F25             0x160\r
+#define C_F26             0x170\r
+#define C_F27             0x180\r
+#define C_F28             0x190\r
+#define C_F29             0x1a0\r
+#define C_F30             0x1b0\r
+#define C_F31             0x1c0\r
+#define C_FPSR            0x1d0\r
+#define C_B0              0x1d8\r
+#define C_B1              0x1e0\r
+#define C_B2              0x1e8\r
+#define C_B3              0x1f0\r
+#define C_B4              0x1f8\r
+#define C_B5              0x200\r
+#define TT_R2             0x8\r
+#define TT_R3             0x10\r
+#define TT_R8             0x18\r
+#define TT_R9             0x20\r
+#define TT_R10            0x28\r
+#define TT_R11            0x30\r
+#define TT_R14            0x38\r
+\r
+#endif _IA64GEN_H\r
diff --git a/MdePkg/Library/BaseLib/Ipf/longjmp.s b/MdePkg/Library/BaseLib/Ipf/longjmp.s
new file mode 100644 (file)
index 0000000..20a0df1
--- /dev/null
@@ -0,0 +1,121 @@
+/// @file\r
+///  Contains an implementation of longjmp for the Itanium-based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: longjmp.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   InternalLongJump\r
+.type   InternalLongJump, @function\r
+.regstk 2, 0, 0, 0\r
+InternalLongJump::\r
+        add                 r10 = 0x10*20 + 8*14, in0\r
+        movl                r2  = ~((((1 << 14) - 1) << 16) | 3)\r
+\r
+        ld8.nt1             r14 = [r10], -8*2       // BSP, skip PFS\r
+        mov                 r15 = ar.bspstore       // BSPSTORE\r
+\r
+        ld8.nt1             r17 = [r10], -8         // UNAT after spill\r
+        mov                 r16 = ar.rsc            // RSC\r
+        cmp.leu             p6  = r14, r15\r
+\r
+        ld8.nt1             r18 = [r10], -8         // UNAT\r
+        ld8.nt1             r25 = [r10], -8         // b5\r
+        and                 r2  = r16, r2\r
+\r
+        ldf.fill.nt1        f2  = [in0], 0x10\r
+        ld8.nt1             r24 = [r10], -8         // b4\r
+        mov                 b5  = r25\r
+\r
+        mov                 ar.rsc = r2\r
+        ld8.nt1             r23 = [r10], -8         // b3\r
+        mov                 b4  = r24\r
+\r
+        ldf.fill.nt1        f3  = [in0], 0x10\r
+        mov                 ar.unat = r17\r
+(p6)    br.spnt.many        _skip_flushrs\r
+\r
+        flushrs\r
+        mov                 r15 = ar.bsp            // New BSPSTORE\r
+\r
+_skip_flushrs:\r
+        mov                 r31 = ar.rnat           // RNAT\r
+        loadrs\r
+\r
+        ldf.fill.nt1        f4  = [in0], 0x10\r
+        ld8.nt1             r22 = [r10], -8\r
+        dep                 r2  = -1, r14, 3, 6\r
+\r
+        ldf.fill.nt1        f5  = [in0], 0x10\r
+        ld8.nt1             r21 = [r10], -8\r
+        cmp.ltu             p6  = r2, r15\r
+\r
+        ld8.nt1             r20 = [r10], -0x10      // skip sp\r
+(p6)    ld8.nta             r31 = [r2]\r
+        mov                 b3  = r23\r
+\r
+        ldf.fill.nt1        f16 = [in0], 0x10\r
+        ld8.fill.nt1        r7  = [r10], -8\r
+        mov                 b2  = r22\r
+\r
+        ldf.fill.nt1        f17 = [in0], 0x10\r
+        ld8.fill.nt1        r6  = [r10], -8\r
+        mov                 b1  = r21\r
+\r
+        ldf.fill.nt1        f18 = [in0], 0x10\r
+        ld8.fill.nt1        r5  = [r10], -8\r
+        mov                 b0  = r20\r
+\r
+        ldf.fill.nt1        f19 = [in0], 0x10\r
+        ld8.fill.nt1        r4  = [r10], 8*13\r
+\r
+        ldf.fill.nt1        f20 = [in0], 0x10\r
+        ld8.nt1             r19 = [r10], 0x10       // PFS\r
+\r
+        ldf.fill.nt1        f21 = [in0], 0x10\r
+        ld8.nt1             r26 = [r10], 8          // Predicate\r
+        mov                 ar.pfs = r19\r
+\r
+        ldf.fill.nt1        f22 = [in0], 0x10\r
+        ld8.nt1             r27 = [r10], 8          // LC\r
+        mov                 pr  = r26, -1\r
+\r
+        ldf.fill.nt1        f23 = [in0], 0x10\r
+        ld8.nt1             r28 = [r10], -17*8 - 0x10\r
+        mov                 ar.lc = r27\r
+\r
+        ldf.fill.nt1        f24 = [in0], 0x10\r
+        ldf.fill.nt1        f25 = [in0], 0x10\r
+        mov                 r8  = in1\r
+\r
+        ldf.fill.nt1        f26 = [in0], 0x10\r
+        ldf.fill.nt1        f31 = [r10], -0x10\r
+\r
+        ldf.fill.nt1        f27 = [in0], 0x10\r
+        ldf.fill.nt1        f30 = [r10], -0x10\r
+\r
+        ldf.fill.nt1        f28 = [in0]\r
+        ldf.fill.nt1        f29 = [r10], 0x10*3 + 8*4\r
+\r
+        ld8.fill.nt1        sp  = [r10]\r
+        mov                 ar.unat = r18\r
+\r
+        mov                 ar.bspstore = r14\r
+        mov                 ar.rnat = r31\r
+\r
+        invala\r
+        mov                 ar.rsc = r16\r
+        br.ret.sptk         b0\r
+.endp\r
diff --git a/MdePkg/Library/BaseLib/Ipf/setjmp.s b/MdePkg/Library/BaseLib/Ipf/setjmp.s
new file mode 100644 (file)
index 0000000..e2b346e
--- /dev/null
@@ -0,0 +1,108 @@
+/// @file\r
+///  Contains an implementation of longjmp for the Itanium-based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: longjmp.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.globl InternalAssertJumpBuffer\r
+.type   InternalAssertJumpBuffer, @function\r
+\r
+.proc   SetJump\r
+.type   SetJump, @function\r
+SetJump::\r
+        alloc               loc0 = ar.pfs, 1, 2, 1, 0\r
+        mov                 loc1 = b0\r
+        mov                 out0 = in0\r
+\r
+        brl.call.sptk.many  b0  = InternalAssertJumpBuffer\r
+\r
+        mov                 r14 = ar.unat\r
+        mov                 r15 = ar.bsp\r
+        add                 r10 = 0x10*20, in0\r
+\r
+        stf.spill.nta       [in0] = f2, 0x10\r
+        st8.spill.nta       [r10] = r4, 8\r
+        mov                 r21 = b1\r
+\r
+        stf.spill.nta       [in0] = f3, 0x10\r
+        st8.spill.nta       [r10] = r5, 8\r
+        mov                 r22 = b2\r
+\r
+        stf.spill.nta       [in0] = f4, 0x10\r
+        st8.spill.nta       [r10] = r6, 8\r
+        mov                 r23 = b3\r
+\r
+        stf.spill.nta       [in0] = f5, 0x10\r
+        st8.spill.nta       [r10] = r7, 8\r
+        mov                 r24 = b4\r
+\r
+        stf.spill.nta       [in0] = f16, 0x10\r
+        st8.spill.nta       [r10] = sp, 8\r
+        mov                 r25 = b5\r
+\r
+        stf.spill.nta       [in0] = f17, 0x10\r
+        st8.nta             [r10] = loc1, 8\r
+        mov                 r16 = pr\r
+\r
+        stf.spill.nta       [in0] = f18, 0x10\r
+        st8.nta             [r10] = r21, 8\r
+        mov                 r17 = ar.lc\r
+\r
+        stf.spill.nta       [in0] = f19, 0x10\r
+        st8.nta             [r10] = r22, 8\r
+\r
+        stf.spill.nta       [in0] = f20, 0x10\r
+        st8.nta             [r10] = r23, 8\r
+\r
+        stf.spill.nta       [in0] = f21, 0x10\r
+        st8.nta             [r10] = r24, 8\r
+\r
+        stf.spill.nta       [in0] = f22, 0x10\r
+        st8.nta             [r10] = r25, 8\r
+\r
+        stf.spill.nta       [in0] = f23, 0x10\r
+        mov                 r18 = ar.unat\r
+\r