--- /dev/null
+/** @file\r
+ MSR Definitions for Pentium(R) 4 Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.\r
+\r
+**/\r
+\r
+#ifndef __PENTIUM_4_MSR_H__\r
+#define __PENTIUM_4_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range\r
+ Determination.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
+ Enables and disables processor features; (R) indicates current processor\r
+ configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state\r
+ /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.\r
+ /// The value in this bit is written on the deassertion of RESET#; the bit\r
+ /// is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 OutputTriStateEnabled:1;\r
+ ///\r
+ /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
+ /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
+ /// value in this bit is written on the deassertion of RESET#; the bit is\r
+ /// set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
+ /// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
+ /// strapping of A7#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 InOrderQueueDepth:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
+ /// observation is enabled (0) or disabled (1) as determined by the\r
+ /// strapping of A9#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 MCERR_ObservationDisabled:1;\r
+ ///\r
+ /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
+ /// observation is enabled (0) or disabled (1) as determined by the\r
+ /// strapping of A10#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ ///\r
+ /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
+ /// value as set by the strapping of A12# and A11#. The logical cluster ID\r
+ /// value is written into the field on the deassertion of RESET#; the\r
+ /// field is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
+ /// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
+ /// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
+ /// the address bus signal is asserted.\r
+ ///\r
+ UINT32 BusParkDisable:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
+ /// by the strapping of BR[3:0]. The logical ID value is written into the\r
+ /// field on the deassertion of RESET#; the field is set to 1 when the\r
+ /// address bus signal is asserted.\r
+ ///\r
+ UINT32 AgentID:2;\r
+ UINT32 Reserved2:18;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
+ Enables and disables processor features.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the\r
+ /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
+ /// to disabled (0, default).\r
+ ///\r
+ UINT32 RCNT_SCNT:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
+ /// bus parity checking; clear to enable parity checking.\r
+ ///\r
+ UINT32 DataErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
+ /// (default); clear to enable.\r
+ ///\r
+ UINT32 ResponseErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
+ /// (default); clear to enable.\r
+ ///\r
+ UINT32 AddressRequestErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
+ /// for initiator bus requests (default); clear to enable.\r
+ ///\r
+ UINT32 InitiatorMCERR_Disable:1;\r
+ ///\r
+ /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
+ /// for initiator internal errors (default); clear to enable.\r
+ ///\r
+ UINT32 InternalMCERR_Disable:1;\r
+ ///\r
+ /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
+ /// (default); clear to enable driver.\r
+ ///\r
+ UINT32 BINIT_DriverDisable:1;\r
+ UINT32 Reserved1:25;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
+ this MSR varies according to the MODEL value in the CPUID version\r
+ information. The following bit field layout applies to Pentium 4 and Xeon\r
+ Processors with MODEL encoding equal or greater than 2. (R) The field\r
+ Indicates the current processor frequency configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
+ /// bus speed: *EncodingScalable Bus Speed*\r
+ ///\r
+ /// 000B 100 MHz (Model 2).\r
+ /// 000B 266 MHz (Model 3 or 4)\r
+ /// 001B 133 MHz\r
+ /// 010B 200 MHz\r
+ /// 011B 166 MHz\r
+ /// 100B 333 MHz (Model 6)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 011B.\r
+ /// 266.67 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33\r
+ /// MHz should be utilized if performing calculation with System Bus\r
+ /// Speed when encoding is 100B and model encoding = 6. All other values\r
+ /// are reserved.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved2:5;\r
+ ///\r
+ /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
+ /// The processor core clock frequency to system bus frequency ratio\r
+ /// observed at the de-assertion of the reset pin.\r
+ ///\r
+ UINT32 ClockRatio:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
+ this MSR varies according to the MODEL value of the CPUID version\r
+ information. This bit field layout applies to Pentium 4 and Xeon Processors\r
+ with MODEL encoding less than 2. Indicates current processor frequency\r
+ configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:21;\r
+ ///\r
+ /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
+ /// bus speed: *Encoding* *Scalable Bus Speed*\r
+ ///\r
+ /// 000B 100 MHz All others values reserved.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
+ "IA32_MCG Extended Machine Check State MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] DS When set, the bit indicates that a page assist or page\r
+ /// fault occurred during DS normal operation. The processors response is\r
+ /// to shut down. The bit is used as an aid for debugging DS handling\r
+ /// code. It is the responsibility of the user (BIOS or operating system)\r
+ /// to clear this bit for normal operation.\r
+ ///\r
+ UINT32 DS:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
+ "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the\r
+ associated state-save MSRs) exist only in Intel 64 processors. These\r
+ registers contain valid information only when the processor is operating in\r
+ 64-bit mode at the time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
+\r
+\r
+/**\r
+ Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
+ When read, specifies the value of the target TM2 transition last written.\r
+ When set, it sets the next target value for TM2 transition. 4, 6. Shared.\r
+ For Family F, Model 4 and Model 6 processors: When read, specifies the value\r
+ of the target TM2 transition last written. Writes may cause #GP exceptions.\r
+\r
+ @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable. See Table 35-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
+ ///\r
+ UINT32 FPU:1;\r
+ ///\r
+ /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
+ /// Monitor," and see Table 35-2.\r
+ ///\r
+ UINT32 TM1:1;\r
+ ///\r
+ /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
+ /// to be issued instead of a split-lock cycle. Operating systems that set\r
+ /// this bit must align system structures to avoid split-lock scenarios.\r
+ /// When the bit is clear (default), normal split-locks are issued to the\r
+ /// bus.\r
+ /// This debug feature is specific to the Pentium 4 processor.\r
+ ///\r
+ UINT32 SplitLockDisable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
+ /// cache is disabled; when clear (default) the third-level cache is\r
+ /// enabled. This flag is reserved for processors that do not have a\r
+ /// third-level cache. Note that the bit controls only the third-level\r
+ /// cache; and only if overall caching is enabled through the CD flag of\r
+ /// control register CR0, the page-level cache controls, and/or the MTRRs.\r
+ /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
+ ///\r
+ UINT32 ThirdLevelCacheDisable:1;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ ///\r
+ /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
+ /// suppressed during a Split Lock access. When clear (default), LOCK is\r
+ /// not suppressed.\r
+ ///\r
+ UINT32 SuppressLockEnable:1;\r
+ ///\r
+ /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
+ /// When clear (default), enables the prefetch queue.\r
+ ///\r
+ UINT32 PrefetchQueueDisable:1;\r
+ ///\r
+ /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
+ /// reporting through the FERR# pin is enabled; when clear, this interrupt\r
+ /// reporting function is disabled.\r
+ /// When this flag is set and the processor is in the stop-clock state\r
+ /// (STPCLK# is asserted), asserting the FERR# pin signals to the\r
+ /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,\r
+ /// SMI#, or RESET#) is pending and that the processor should return to\r
+ /// normal operation to handle the interrupt. This flag does not affect\r
+ /// the normal operation of the FERR# pin (to indicate an unmasked\r
+ /// floatingpoint error) when the STPCLK# pin is not asserted.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
+ /// Table 35-2. When set, the processor does not support branch trace\r
+ /// storage (BTS); when clear, BTS is supported.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)\r
+ /// See Table 35-2. When set, the processor does not support precise\r
+ /// event-based sampling (PEBS); when clear, PEBS is supported.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ ///\r
+ /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
+ /// sensor indicates that the die temperature is at the predetermined\r
+ /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce\r
+ /// the bus to core ratio and voltage according to the value last written\r
+ /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the\r
+ /// processor does not change the VID signals or the bus to core ratio\r
+ /// when the processor enters a thermal managed state. If the TM2 feature\r
+ /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then\r
+ /// this feature is not supported and BIOS must not alter the contents of\r
+ /// this bit location. The processor is operating out of spec if both this\r
+ /// bit and the TM1 bit are set to disabled states.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ ///\r
+ /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
+ /// the processor fetches the cache line of the 128-byte sector containing\r
+ /// currently required data. When set to 0, the processor fetches both\r
+ /// cache lines in the sector.\r
+ /// Single processor platforms should not set this bit. Server platforms\r
+ /// should set or clear this bit based on platform performance observed\r
+ /// in validation and testing. BIOS may contain a setup option that\r
+ /// controls the setting of this bit.\r
+ ///\r
+ UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting\r
+ /// this can cause unexpected behavior to software that depends on the\r
+ /// availability of CPUID leaves greater than 3.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ ///\r
+ /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
+ /// is placed in shared mode; when clear (default), the cache is placed in\r
+ /// adaptive mode. This bit is only enabled for IA-32 processors that\r
+ /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data\r
+ /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are\r
+ /// identical, data in L1 is shared across logical processors. Otherwise,\r
+ /// L1 is not shared and cache use is competitive. If the Context ID\r
+ /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,\r
+ /// the ability to switch modes is not supported. BIOS must not alter the\r
+ /// contents of IA32_MISC_ENABLE[24].\r
+ ///\r
+ UINT32 L1DataCacheContextMode:1;\r
+ UINT32 Reserved5:7;\r
+ UINT32 Reserved6:2;\r
+ ///\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved7:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ 3, 4, 6. Shared. Platform Feature Requirements (R).\r
+\r
+ @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:18;\r
+ ///\r
+ /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
+ /// has specific platform requirements. The details of the platform\r
+ /// requirements are listed in the respective data sheets of the processor.\r
+ ///\r
+ UINT32 PLATFORM:1;\r
+ UINT32 Reserved2:13;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
+ a pointer to the last branch instruction that the processor executed prior\r
+ to the last exception that was generated or the last interrupt that was\r
+ handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear\r
+ IP Linear address of the last branch instruction (If IA32e mode is active).\r
+ From Linear IP Linear address of the last branch instruction. Reserved.\r
+\r
+ @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
+ contains a pointer to the target of the last branch instruction that the\r
+ processor executed prior to the last exception that was generated or the\r
+ last interrupt that was handled. See Section 17.10.3, "Last Exception\r
+ Records.". Unique. From Linear IP Linear address of the target of the last\r
+ branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
+ of the target of the last branch instruction. Reserved.\r
+\r
+ @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
+ features are used. Bit definitions are discussed in the referenced section.\r
+ See Section 17.10.1, "MSR_DEBUGCTLA MSR.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
+ index (0-3 or 0-15) that points to the top of the last branch record stack\r
+ (that is, that points the index of the MSR containing the most recent branch\r
+ record). See Section 17.10.2, "LBR Stack for Processors Based on Intel\r
+ NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
+\r
+\r
+/**\r
+ 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
+ registers on the last branch record stack. It contains pointers to the\r
+ source and destination instruction for one of the last four branches,\r
+ exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
+ MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
+ 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
+ Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ for Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
+#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
+#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
+#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
+#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
+#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
+#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
+#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
+#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
+#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
+#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
+#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
+#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
+#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
+#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
+#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
+#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
+#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
+#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
+#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
+#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
+#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
+#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
+#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
+#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
+#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
+#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
+#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
+#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
+#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
+#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
+#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
+\r
+\r
+/**\r
+ 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
+ on later processors. It is only available on processor family 0FH, models\r
+ 01H-02H.\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
+\r
+\r
+/**\r
+ 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
+ on later processors. It is only available on processor family 0FH, models\r
+ 01H-02H.\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ALF_ESCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
+#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
+#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
+#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
+#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
+#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)\r
+ Controls the enabling of precise event sampling and replay tagging.\r
+\r
+ @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 12:0] See Table 19-26.\r
+ ///\r
+ UINT32 EventNum:13;\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 24] UOP Tag Enables replay tagging when set.\r
+ ///\r
+ UINT32 UOP:1;\r
+ ///\r
+ /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
+ /// processor when set; disables PEBS when clear (default). See Section\r
+ /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
+ /// that do not support Intel HyperThreading Technology.\r
+ ///\r
+ UINT32 ENABLE_PEBS_MY_THR:1;\r
+ ///\r
+ /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
+ /// processor when set; disables PEBS when clear (default). See Section\r
+ /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// logical processor. This bit is reserved for IA-32 processors that do\r
+ /// not support Intel Hyper-Threading Technology.\r
+ ///\r
+ UINT32 ENABLE_PEBS_OTH_THR:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-26.\r
+\r
+ @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
+\r
+\r
+/**\r
+ 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
+ record registers on the last branch record stack (680H-68FH). This part of\r
+ the stack contains pointers to the source instruction for one of the last 16\r
+ branches, exceptions, or interrupts taken by the processor. The MSRs at\r
+ 680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
+ 0FH, model 03H. These MSRs replace MSRs previously located at\r
+ 1DBH-1DEH.which performed the same function for early releases. See Section\r
+ 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
+ Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
+/// @}\r
+\r
+\r
+/**\r
+ 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
+ record registers on the last branch record stack (6C0H-6CFH). This part of\r
+ the stack contains pointers to the destination instruction for one of the\r
+ last 16 branches, exceptions, or interrupts that the processor took. See\r
+ Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ for Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
+/// @}\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See\r
+ Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ with Up to 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See\r
+ Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ with Up to 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
+\r
+\r
+/**\r
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See\r
+ Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
+ with Up to 8-MByte L3 Cache" for details.\r
+\r
+ @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
+\r
+\r
+/**\r
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache" for details.\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
+\r
+\r
+/**\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
+\r
+\r
+/**\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
+\r
+\r
+/**\r
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
+ 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
+\r
+\r
+/**\r
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache" for details.\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
+\r
+#endif\r
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