gArmPlatformTokenSpaceGuid.PcdStandalone
[FixedPcd]
- gArmTokenSpaceGuid.PcdNormalFdBaseAddress
- gArmTokenSpaceGuid.PcdNormalFdSize
#include <Library/MemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
+\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
entry\r
\r
**/\r
-VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {\r
- UINT32 CacheAttributes;\r
- BOOLEAN bTrustzoneSupport = FALSE;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT(VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
- } else {\r
- CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
- }\r
-\r
- // ReMap (Either NOR Flash or DRAM)\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_DRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_DRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMC CS7\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS0-CS1 - NOR Flash 1 & 2\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // SMB CS2 - SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
-\r
- // SMB CS3-CS6 - Motherboard Peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
-\r
- // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
- if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) {\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ;\r
- VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
+VOID\r
+ArmPlatformGetVirtualMemoryMap (\r
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
+ )\r
+{\r
+ UINT32 CacheAttributes;\r
+ BOOLEAN bTrustzoneSupport = FALSE;\r
+ UINTN Index = 0;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
+\r
+ ASSERT(VirtualMemoryMap != NULL);\r
+\r
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+ if (VirtualMemoryTable == NULL) {\r
+ return;\r
+ }\r
+\r
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);\r
+ } else {\r
+ CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);\r
+ }\r
+\r
+ // ReMap (Either NOR Flash or DRAM)\r
+ VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // DDR\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_DRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_DRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMC CS7\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS0-CS1 - NOR Flash 1 & 2\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // SMB CS2 - SRAM\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+ // SMB CS3-CS6 - Motherboard Peripherals\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
+ if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) {\r
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE;\r
+ VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE;\r
+ VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ;\r
+ VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);\r
+\r
+ ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
+ } else {\r
+ ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
+ }\r
+\r
+ // End of Table\r
+ VirtualMemoryTable[++Index].PhysicalBase = 0;\r
+ VirtualMemoryTable[Index].VirtualBase = 0;\r
+ VirtualMemoryTable[Index].Length = 0;\r
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+\r
+ *VirtualMemoryMap = VirtualMemoryTable;\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
ArmPlatformGetAdditionalSystemMemory (\r
- OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
-) {\r
+ OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap\r
+ )\r
+{\r
return EFI_UNSUPPORTED;\r
}\r
gArmPlatformTokenSpaceGuid.PcdStandalone\r
\r
[FixedPcd]\r
- gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
- gArmTokenSpaceGuid.PcdNormalFdSize\r
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
- gArmTokenSpaceGuid.PcdNormalFdBaseAddress
- gArmTokenSpaceGuid.PcdNormalFdSize
-
gArmTokenSpaceGuid.PcdL2x0ControllerBase
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
\r
[FixedPcd]\r
- gArmTokenSpaceGuid.PcdNormalFdBaseAddress\r
- gArmTokenSpaceGuid.PcdNormalFdSize\r
-\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
VOID
);
-/**
- Return the information about the memory region in permanent memory used by PEI
-
- One of the PEI Module must install the permament memory used by PEI. This function returns the
- information about this region for your platform to this PEIM module.
-
- @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules
- @param[out] PeiMemorySize Size of the memory region used by PEI core and modules
-
-**/
-VOID ArmPlatformGetPeiMemory (
- OUT UINTN* PeiMemoryBase,
- OUT UINTN* PeiMemorySize
- );
-
/**
Return the Virtual Memory Map of your platform
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
+\r
//\r
// The protocols, PPI and GUID defintions for this module\r
//\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/ArmPlatformLib.h>\r
\r
-//\r
-// Module globals\r
-//\r
-\r
VOID\r
InitMmu (\r
VOID\r
)\r
{\r
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;\r
- VOID *TranslationTableBase;\r
- UINTN TranslationTableSize;\r
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;\r
+ VOID *TranslationTableBase;\r
+ UINTN TranslationTableSize;\r
\r
- // Get Virtual Memory Map from the Platform Library\r
- ArmPlatformGetVirtualMemoryMap(&MemoryTable);\r
+ // Get Virtual Memory Map from the Platform Library\r
+ ArmPlatformGetVirtualMemoryMap(&MemoryTable);\r
\r
- //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in\r
- // DRAM (even at the top of DRAM as it is the first permanent memory allocation)\r
- ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in\r
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)\r
+ ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
}\r
\r
-// May want to put this into a library so you only need the PCD setings if you are using the feature?\r
+// May want to put this into a library so you only need the PCD settings if you are using the feature?\r
VOID\r
BuildMemoryTypeInformationHob (\r
VOID\r
Info[9].Type = EfiMaxMemoryType;\r
Info[9].NumberOfPages = 0;\r
\r
-\r
BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info));\r
}\r
-\r
/*++\r
\r
Routine Description:\r
InitMmu ();\r
\r
if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {\r
- // Optional feature that helps prevent EFI memory map fragmentation. \r
+ // Optional feature that helps prevent EFI memory map fragmentation.\r
BuildMemoryTypeInformationHob ();\r
}\r
\r
#/** @file\r
# \r
-# Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
*\r
**/\r
\r
-#include <PiPei.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
#include <Drivers/PL390Gic.h>\r
\r
+#include "PrePeiCore.h"\r
+\r
extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
\r
/*\r
*/\r
VOID\r
EFIAPI\r
-secondary_main(IN UINTN CoreId)\r
+SecondaryMain (\r
+ IN UINTN CoreId\r
+ )\r
{\r
- //Function pointer to Secondary Core entry point\r
- VOID (*secondary_start)(VOID);\r
- UINTN secondary_entry_addr=0;\r
+ // Function pointer to Secondary Core entry point\r
+ VOID (*secondary_start)(VOID);\r
+ UINTN secondary_entry_addr=0;\r
\r
- //Clear Secondary cores MailBox\r
- ArmClearMPCoreMailbox();\r
+ // Clear Secondary cores MailBox\r
+ ArmClearMPCoreMailbox();\r
\r
- while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
- ArmCallWFI();\r
- //Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
- }\r
+ while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
+ ArmCallWFI();\r
+ // Acknowledge the interrupt and send End of Interrupt signal.\r
+ PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ }\r
\r
- secondary_start = (VOID (*)())secondary_entry_addr;\r
+ secondary_start = (VOID (*)())secondary_entry_addr;\r
\r
- //Jump to secondary core entry point.\r
- secondary_start();\r
+ // Jump to secondary core entry point.\r
+ secondary_start();\r
\r
- //the secondaries shouldn't reach here\r
- ASSERT(FALSE);\r
+ // The secondaries shouldn't reach here\r
+ ASSERT(FALSE);\r
}\r
\r
-VOID primary_main (\r
+VOID\r
+EFIAPI\r
+PrimaryMain (\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ //Enable the GIC Distributor\r
+ PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
- // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
- if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
- // Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
- }\r
+ // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
+ if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+ // Sending SGI to all the Secondary CPU interfaces\r
+ PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ }\r
\r
- //\r
- // Bind this information into the SEC hand-off state\r
- // Note: this must be in sync with the stuff in the asm file\r
- // Note also: HOBs (pei temp ram) MUST be above stack\r
- //\r
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
- SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
- SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
- SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+ //\r
+ // Bind this information into the SEC hand-off state\r
+ // Note: this must be in sync with the stuff in the asm file\r
+ // Note also: HOBs (pei temp ram) MUST be above stack\r
+ //\r
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+ SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
+ SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
\r
- // jump to pei core entry point\r
- (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+ // Jump to PEI core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
}\r
*\r
**/\r
\r
-#include <PiPei.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Chipset/ArmV7.h>\r
\r
+#include "PrePeiCore.h"\r
+\r
extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
\r
VOID\r
EFIAPI\r
-secondary_main(IN UINTN CoreId)\r
+SecondaryMain (\r
+ IN UINTN CoreId\r
+ )\r
{\r
- ASSERT(FALSE);\r
+ ASSERT(FALSE);\r
}\r
\r
-VOID primary_main (\r
+VOID\r
+EFIAPI\r
+PrimaryMain (\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
-\r
-\r
- //\r
- // Bind this information into the SEC hand-off state\r
- // Note: this must be in sync with the stuff in the asm file\r
- // Note also: HOBs (pei temp ram) MUST be above stack\r
- //\r
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
- SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
- SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
- SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
-\r
- // jump to pei core entry point\r
- (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+\r
+\r
+ //\r
+ // Bind this information into the SEC hand-off state\r
+ // Note: this must be in sync with the stuff in the asm file\r
+ // Note also: HOBs (pei temp ram) MUST be above stack\r
+ //\r
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+ SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
+ SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+\r
+ // jump to pei core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
}\r
*\r
**/\r
\r
-#include <PiPei.h>\r
-#include <Ppi/TemporaryRamSupport.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
+#include <Library/PrintLib.h>\r
#include <Library/ArmLib.h>\r
+#include <Library/SerialPortLib.h>\r
#include <Chipset/ArmV7.h>\r
\r
-EFI_STATUS\r
-EFIAPI\r
-SecTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
- );\r
-\r
-VOID\r
-SecSwitchStack (\r
- INTN StackDelta\r
- );\r
+#include "PrePeiCore.h"\r
\r
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};\r
\r
}\r
};\r
\r
-// Vector Table for Pei Phase\r
-VOID PeiVectorTable (VOID);\r
-\r
-\r
VOID\r
CEntryPoint (\r
IN UINTN CoreId,\r
ArmInvalidateInstructionCache();\r
\r
// Enable Instruction & Data caches\r
- ArmEnableDataCache();\r
- ArmEnableInstructionCache();\r
+ ArmEnableDataCache ();\r
+ ArmEnableInstructionCache ();\r
\r
//\r
// Note: Doesn't have to Enable CPU interface in non-secure world,\r
//If not primary Jump to Secondary Main\r
if(0 == CoreId) {\r
//Goto primary Main.\r
- primary_main(PeiCoreEntryPoint);\r
+ PrimaryMain (PeiCoreEntryPoint);\r
} else {\r
- secondary_main(CoreId);\r
+ SecondaryMain (CoreId);\r
}\r
\r
// PEI Core should always load and never return\r
{\r
//\r
// Migrate the whole temporary memory to permenent memory.\r
- // \r
+ //\r
CopyMem (\r
(VOID*)(UINTN)PermanentMemoryBase, \r
(VOID*)(UINTN)TemporaryMemoryBase, \r
--- /dev/null
+/** @file\r
+* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+#ifndef __PREPEICORE_H_\r
+#define __PREPEICORE_H_\r
+\r
+#include <PiPei.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ );\r
+\r
+VOID\r
+SecSwitchStack (\r
+ INTN StackDelta\r
+ );\r
+\r
+// Vector Table for Pei Phase\r
+VOID PeiVectorTable (VOID);\r
+\r
+VOID\r
+EFIAPI\r
+PrimaryMain (\r
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
+ );\r
+\r
+/*\r
+ * This is the main function for secondary cores. They loop around until a non Null value is written to\r
+ * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r
+ * Note:The secondary cores, while executing secondary_main, assumes that:\r
+ * : SGI 0 is configured as Non-secure interrupt\r
+ * : Priority Mask is configured to allow SGI 0\r
+ * : Interrupt Distributor and CPU interfaces are enabled\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+SecondaryMain (\r
+ IN UINTN CoreId\r
+ );\r
+\r
+#endif\r