DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
[LibraryClasses.ARM]
#
\r
BOOLEAN mInterruptState = FALSE;\r
\r
+\r
+/**\r
+ This function flushes the range of addresses from Start to Start+Length \r
+ from the processor's data cache. If Start is not aligned to a cache line \r
+ boundary, then the bytes before Start to the preceding cache line boundary \r
+ are also flushed. If Start+Length is not aligned to a cache line boundary, \r
+ then the bytes past Start+Length to the end of the next cache line boundary \r
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
+ supported. If the data cache is fully coherent with all DMA operations, then \r
+ this function can just return EFI_SUCCESS. If the processor does not support \r
+ flushing a range of the data cache, then the entire data cache can be flushed.\r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+ @param Start The beginning physical address to flush from the processor's data\r
+ cache.\r
+ @param Length The number of bytes to flush from the processor's data cache. This\r
+ function may flush more bytes than Length specifies depending upon\r
+ the granularity of the flush operation that the processor supports.\r
+ @param FlushType Specifies the type of flush operation to perform.\r
+\r
+ @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
+ the processor's data cache.\r
+ @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
+ by FlushType.\r
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
+ from the processor's data cache.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
IN EFI_CPU_FLUSH_TYPE FlushType\r
)\r
{\r
+ DEBUG ((EFI_D_ERROR, "CpuFlushCpuDataCache (%lx, %lx, %x)\n", Start, Length, FlushType));\r
+\r
switch (FlushType) {\r
case EfiCpuFlushTypeWriteBack:\r
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
return EFI_SUCCESS;\r
}\r
\r
+\r
+/**\r
+ This function enables interrupt processing by the processor. \r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+\r
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.\r
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
}\r
\r
\r
+/**\r
+ This function disables interrupt processing by the processor.\r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+\r
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.\r
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
return EFI_SUCCESS;\r
}\r
\r
+\r
+/**\r
+ This function retrieves the processor's current interrupt state a returns it in \r
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
+ are currently disabled, then FALSE is returned.\r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+ @param State A pointer to the processor's current interrupt state. Set to TRUE if\r
+ interrupts are enabled and FALSE if interrupts are disabled.\r
+\r
+ @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r
+ @retval EFI_INVALID_PARAMETER State is NULL.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
return EFI_SUCCESS;\r
}\r
\r
+\r
+/**\r
+ This function generates an INIT on the processor. If this function succeeds, then the\r
+ processor will be reset, and control will not be returned to the caller. If InitType is \r
+ not supported by this processor, or the processor cannot programmatically generate an \r
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
+ occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
+\r
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
+ @param InitType The type of processor INIT to perform.\r
+\r
+ @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r
+ @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r
+ by this processor.\r
+ @retval EFI_DEVICE_ERROR The processor INIT failed.\r
+\r
+**/\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
return EFI_UNSUPPORTED;\r
}\r
\r
-EFI_STATUS\r
-EFIAPI\r
-CpuSetMemoryAttributes (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
\r
//\r
// Globals used to initialize the protocol\r
IN EFI_HANDLE ImageHandle,\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
-{ \r
+{\r
+ EFI_STATUS Status;\r
+\r
InitializeExceptions (&mCpu); \r
- return gBS->InstallMultipleProtocolInterfaces (&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);\r
+ \r
+ \r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &mCpuHandle, \r
+ &gEfiCpuArchProtocolGuid, &mCpu, \r
+ &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r
+ NULL\r
+ );\r
+ \r
+ //\r
+ // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
+ // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
+ // after the protocol is installed\r
+ //\r
+ SyncCacheConfig (&mCpu);\r
+ \r
+ return Status;\r
}\r
\r
\r
#include <Library/ArmLib.h>\r
#include <Library/BaseMemoryLib.h>\r
-#include <Library/CacheMaintenanceLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/CpuLib.h>\r
\r
+#include <Guid/DebugImageInfoTable.h>\r
#include <Protocol/Cpu.h>\r
#include <Protocol/DebugSupport.h>\r
#include <Protocol/DebugSupportPeriodicCallback.h>\r
+#include <Protocol/VirtualUncachedPages.h>\r
+#include <Protocol/LoadedImage.h>\r
+\r
+\r
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \\r
+ EFI_MEMORY_WC | \\r
+ EFI_MEMORY_WT | \\r
+ EFI_MEMORY_WB | \\r
+ EFI_MEMORY_UCE \\r
+ )\r
\r
\r
/**\r
);\r
\r
\r
+EFI_STATUS\r
+EFIAPI\r
+CpuSetMemoryAttributes (\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
+ );\r
+\r
EFI_STATUS\r
InitializeExceptions (\r
IN EFI_CPU_ARCH_PROTOCOL *Cpu\r
);\r
\r
+EFI_STATUS\r
+SyncCacheConfig (\r
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+ );\r
+\r
+EFI_STATUS \r
+ConvertSectionToPages (\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress\r
+ );\r
+\r
+\r
+extern VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages;\r
+\r
#endif // __CPU_DXE_ARM_EXCEPTION_H__\r
#\r
ExceptionSupport.ARMv6.asm | RVCT\r
# ExceptionSupport.ARMv6.S | GCC\r
+ Mmu.c\r
\r
[Packages]\r
ArmPkg/ArmPkg.dec\r
CacheMaintenanceLib\r
UefiDriverEntryPoint\r
ArmLib\r
+ DxeServicesTableLib\r
+ PeCoffGetEntryPointLib\r
+ UefiLib\r
+ CpuLib\r
\r
[Protocols]\r
gEfiCpuArchProtocolGuid\r
gEfiDebugSupportPeriodicCallbackProtocolGuid\r
+ gVirtualUncachedPagesProtocolGuid\r
+\r
+[Guids]\r
+ gEfiDebugImageInfoTableGuid\r
\r
[Pcd.common]\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
**/\r
\r
#include "CpuDxe.h" \r
-#include <Library/CacheMaintenanceLib.h>\r
+\r
+EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *gDebugImageTableHeader = NULL;
\r
VOID\r
ExceptionHandlersStart (\r
return EFI_SUCCESS;\r
}\r
\r
+\r
+UINT32
+EFIAPI
+PeCoffGetSizeOfHeaders (
+ IN VOID *Pe32Data
+ )
+{
+ EFI_IMAGE_DOS_HEADER *DosHdr;
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
+ UINTN SizeOfHeaders;
+
+ DosHdr = (EFI_IMAGE_DOS_HEADER *)Pe32Data;
+ if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+ //
+ // DOS image header is present, so read the PE header after the DOS image header.
+ //
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
+ } else {
+ //
+ // DOS image header is not present, so PE header is at the image base.
+ //
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
+ }
+
+ if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {
+ SizeOfHeaders = sizeof (EFI_TE_IMAGE_HEADER) + (UINTN)Hdr.Te->BaseOfCode - (UINTN)Hdr.Te->StrippedSize;
+ } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
+ SizeOfHeaders = Hdr.Pe32->OptionalHeader.SizeOfHeaders;
+ }
+
+ return SizeOfHeaders;
+}\r
+\r
+\r
+CHAR8 *\r
+GetImageName (\r
+ IN UINT32 FaultAddress,\r
+ OUT UINT32 *ImageBase,\r
+ OUT UINT32 *PeCoffSizeOfHeaders\r
+ )\r
+{\r
+ EFI_DEBUG_IMAGE_INFO *DebugTable;
+ UINTN Entry;
+ CHAR8 *Address;
+
+ \r
+ DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;\r
+ if (DebugTable == NULL) {\r
+ return NULL;\r
+ }\r
+\r
+ Address = (CHAR8 *)(UINTN)FaultAddress;\r
+ for (Entry = 0; Entry < gDebugImageTableHeader->TableSize; Entry++, DebugTable++) {
+ if (DebugTable->NormalImage != NULL) {
+ if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
+ if ((Address >= DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
+ *ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+ *PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
+ return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
+ }
+ }
+ }
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+\r
CHAR8 *gExceptionTypeString[] = {\r
"Reset",\r
"Undefined Instruction",\r
}\r
\r
//\r
- // Code after here is the default exception handler...\r
+ // Code after here is the default exception handler... Dump the context\r
//\r
- DEBUG ((EFI_D_ERROR, "%a Exception from %08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC));\r
- ASSERT (FALSE);\r
+ DEBUG ((EFI_D_ERROR, "\n%a Exception from instruction at 0x%08x CPSR 0x%08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR));\r
+ DEBUG_CODE_BEGIN ();\r
+ CHAR8 *Pdb;
+ UINT32 ImageBase;
+ UINT32 PeCoffSizeOfHeader;
+ UINT32 Offset;
+ \r
+ Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);\r
+ Offset = SystemContext.SystemContextArm->PC - ImageBase;\r
+ if (Pdb != NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a\n", Pdb));\r
\r
+ //\r
+ // A PE/COFF image loads its headers into memory so the headers are \r
+ // included in the linked addressess. ELF and Mach-O images do not\r
+ // include the headers so the first byte of the image is usually\r
+ // text (code). If you look at link maps from ELF or Mach-O images\r
+ // you need to subtact out the size of the PE/COFF header to get\r
+ // get the offset that matches the link map. \r
+ //\r
+ DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%08x (ELF or Mach-O offset) 0x%08x\n", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+ }\r
+ DEBUG_CODE_END ();\r
+ DEBUG ((EFI_D_ERROR, " R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));\r
+ DEBUG ((EFI_D_ERROR, " R4 0x%08x R5 0x%08x R6 0x%08x R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));\r
+ DEBUG ((EFI_D_ERROR, " R8 0x%08x R9 0x%08x R10 0x%08x R11 0x%08x\n", SystemContext.SystemContextArm->R8, SystemContext.SystemContextArm->R9, SystemContext.SystemContextArm->R10, SystemContext.SystemContextArm->R11));\r
+ DEBUG ((EFI_D_ERROR, "R12 0x%08x SP 0x%08x LR 0x%08x PC 0x%08x\n", SystemContext.SystemContextArm->R12, SystemContext.SystemContextArm->SP, SystemContext.SystemContextArm->LR, SystemContext.SystemContextArm->PC));\r
+ DEBUG ((EFI_D_ERROR, "DFSR 0x%08x DFAR 0x%08x IFSR 0x%08x IFAR 0x%08x\n\n", SystemContext.SystemContextArm->DFSR, SystemContext.SystemContextArm->DFAR, SystemContext.SystemContextArm->IFSR, SystemContext.SystemContextArm->IFAR));\r
+\r
+ ASSERT (FALSE);\r
+// while (TRUE) {\r
+// CpuSleep ();\r
+// }\r
}\r
\r
\r
BOOLEAN Enabled;\r
EFI_PHYSICAL_ADDRESS Base;\r
\r
+ Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&gDebugImageTableHeader);
+ if (EFI_ERROR (Status)) {
+ gDebugImageTableHeader = NULL;
+ }
+\r
//\r
// Disable interrupts\r
//\r
\r
#include "CpuDxe.h"\r
\r
+//\r
+// For debug switch me back to to EFI_D_PAGE when done\r
+//\r
+#define L_EFI_D_PAGE EFI_D_ERROR\r
+\r
//\r
// Translation/page table definitions\r
//\r
break;\r
default:\r
return EFI_UNSUPPORTED;\r
- break;\r
}\r
\r
// determine protection attributes\r
switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r
case ARM_SECTION_NO_ACCESS: // no read, no write\r
- *GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
+ //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
break;\r
\r
case ARM_SECTION_PRIV_ACCESS_ONLY:\r
\r
default:\r
return EFI_UNSUPPORTED;\r
- break;\r
}\r
\r
// now process eXectue Never attribute\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Searches memory descriptors covered by given memory range.\r
+\r
+ This function searches into the Gcd Memory Space for descriptors\r
+ (from StartIndex to EndIndex) that contains the memory range\r
+ specified by BaseAddress and Length.\r
+\r
+ @param MemorySpaceMap Gcd Memory Space Map as array.\r
+ @param NumberOfDescriptors Number of descriptors in map.\r
+ @param BaseAddress BaseAddress for the requested range.\r
+ @param Length Length for the requested range.\r
+ @param StartIndex Start index into the Gcd Memory Space Map.\r
+ @param EndIndex End index into the Gcd Memory Space Map.\r
+\r
+ @retval EFI_SUCCESS Search successfully.\r
+ @retval EFI_NOT_FOUND The requested descriptors does not exist.\r
+\r
+**/\r
+EFI_STATUS\r
+SearchGcdMemorySpaces (\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ OUT UINTN *StartIndex,\r
+ OUT UINTN *EndIndex\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ *StartIndex = 0;\r
+ *EndIndex = 0;\r
+ for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
+ if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
+ BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ *StartIndex = Index;\r
+ }\r
+ if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
+ BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ *EndIndex = Index;\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+\r
+/**\r
+ Sets the attributes for a specified range in Gcd Memory Space Map.\r
+\r
+ This function sets the attributes for a specified range in\r
+ Gcd Memory Space Map.\r
+\r
+ @param MemorySpaceMap Gcd Memory Space Map as array\r
+ @param NumberOfDescriptors Number of descriptors in map\r
+ @param BaseAddress BaseAddress for the range\r
+ @param Length Length for the range\r
+ @param Attributes Attributes to set\r
+\r
+ @retval EFI_SUCCESS Memory attributes set successfully\r
+ @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r
+\r
+**/\r
+EFI_STATUS\r
+SetGcdMemorySpaceAttributes (\r
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
+ IN UINTN NumberOfDescriptors,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN StartIndex;\r
+ UINTN EndIndex;\r
+ EFI_PHYSICAL_ADDRESS RegionStart;\r
+ UINT64 RegionLength;\r
+\r
+ //\r
+ // Get all memory descriptors covered by the memory range\r
+ //\r
+ Status = SearchGcdMemorySpaces (\r
+ MemorySpaceMap,\r
+ NumberOfDescriptors,\r
+ BaseAddress,\r
+ Length,\r
+ &StartIndex,\r
+ &EndIndex\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Go through all related descriptors and set attributes accordingly\r
+ //\r
+ for (Index = StartIndex; Index <= EndIndex; Index++) {\r
+ if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
+ continue;\r
+ }\r
+ //\r
+ // Calculate the start and end address of the overlapping range\r
+ //\r
+ if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
+ RegionStart = BaseAddress;\r
+ } else {\r
+ RegionStart = MemorySpaceMap[Index].BaseAddress;\r
+ }\r
+ if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+ RegionLength = BaseAddress + Length - RegionStart;\r
+ } else {\r
+ RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
+ }\r
+ //\r
+ // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
+ //\r
+ gDS->SetMemorySpaceAttributes (\r
+ RegionStart,\r
+ RegionLength,\r
+ (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
+ );\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
\r
\r
EFI_STATUS\r
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 i;\r
- UINT32 Descriptor;\r
- UINT32 SectionAttributes;\r
- EFI_PHYSICAL_ADDRESS NextRegionBase;\r
- UINT64 NextRegionLength;\r
- UINT64 GcdAttributes;\r
- UINT32 NextRegionAttributes = 0;\r
+ EFI_STATUS Status;\r
+ UINT32 i;\r
+ UINT32 Descriptor;\r
+ UINT32 SectionAttributes;\r
+ EFI_PHYSICAL_ADDRESS NextRegionBase;\r
+ UINT64 NextRegionLength;\r
+ UINT64 GcdAttributes;\r
+ UINT32 NextRegionAttributes = 0;\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
\r
\r
+ DEBUG ((L_EFI_D_PAGE, "SyncCacheConfig()\n"));\r
+\r
// This code assumes MMU is enabled and filed with section translations\r
ASSERT (ArmMmuEnabled ());\r
\r
+ //\r
+ // Get the memory space map from GCD\r
+ //\r
+ MemorySpaceMap = NULL;\r
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
\r
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r
NextRegionBase = NextRegionLength = 0;\r
for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r
\r
- // obtain existing descriptor\r
- Descriptor = FirstLevelTable[i];\r
+ // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section\r
+ Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));\r
\r
// extract attributes (cacheability and permissions)\r
SectionAttributes = Descriptor & 0xDEC;\r
\r
// convert section entry attributes to GCD bitmask\r
Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r
- ASSERT_EFI_ERROR(Status);\r
+ ASSERT_EFI_ERROR (Status);\r
\r
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
- Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);\r
- ASSERT_EFI_ERROR(Status);\r
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
+\r
\r
// start on a new region\r
NextRegionLength = 0;\r
// Cause a page fault if these ranges are accessed.\r
EntryMask = 0x3;\r
EntryValue = 0;\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
break;\r
\r
default:\r
return EFI_UNSUPPORTED;\r
- break;\r
}\r
\r
// obtain page table base\r
Descriptor = FirstLevelTable[FirstLevelIdx];\r
\r
// does this descriptor need to be converted from section entry to 4K pages?\r
- if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {\r
+ if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r
if (EFI_ERROR(Status)) {\r
// exit for loop\r
\r
// calculate index into the page table\r
PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r
- ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
+ ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
\r
// get the entry\r
PageTableEntry = PageTable[PageTableIndex];\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
\r
+ // Make sure we handle a section range that is unmapped \r
+ EntryMask = ARM_DESC_TYPE_MASK;\r
+ EntryValue = ARM_DESC_TYPE_SECTION;\r
+\r
// Although the PI spec is unclear on this the GCD guarantees that only\r
// one Attribute bit is set at a time, so we can safely use a switch statement\r
switch(Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
// map to strongly ordered\r
- EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+ EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
// map to normal non-cachable\r
- EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+ EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
// write through with no-allocate\r
- EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
+ EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
// write back (with allocate)\r
- EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
+ EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
case EFI_MEMORY_WP:\r
case EFI_MEMORY_UCE:\r
// cannot be implemented UEFI definition unclear for ARM\r
// Cause a page fault if these ranges are accessed.\r
- EntryMask = 0x3;\r
- EntryValue = 0;\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+ EntryValue = ARM_DESC_TYPE_FAULT;\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
break;\r
\r
\r
default:\r
return EFI_UNSUPPORTED;\r
- break;\r
}\r
\r
// obtain page table base\r
Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
// has this descriptor already been coverted to pages?\r
- if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {\r
+ if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
// forward this 1MB range to page table function instead\r
Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
} else {\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
\r
- DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
+ DEBUG ((L_EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
\r
// obtain page table base\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
\r
// calculate index into first level translation table for start of modification\r
FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
- ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+ ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
\r
// get section attributes and convert to page attributes\r
SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
// TODO: change to use only PageTable base and length\r
// ArmInvalidateDataCache ();\r
- InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);\r
+DEBUG ((EFI_D_ERROR, "InvalidateDataCacheRange (%x, %x)\n", (UINTN)PageTableAddr, EFI_PAGE_SIZE));\r
+\r
+ InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);\r
\r
// formulate page table entry, Domain=0, NS=0\r
PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
\r
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
// is the base and length a multiple of 1 MB?\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
} else {\r
// base and/or length is not a multiple of 1 MB\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
}\r
\r
IN UINT64 Attributes\r
)\r
{\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
// minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
+ DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));\r
return EFI_UNSUPPORTED;\r
}\r
\r
*Attributes = GcdDescriptor.Attributes;\r
}\r
}\r
- \r
+ASSERT (FALSE); \r
//\r
// Make this address range page fault if accessed. If it is a DMA buffer than this would \r
// be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r
// to that address. \r
//\r
- Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);\r
+ Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r
if (!EFI_ERROR (Status)) {\r
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
-CpuFreeConvertedPages (\r
+CpuReconvertPagesPages (\r
IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
IN EFI_PHYSICAL_ADDRESS Address,\r
IN UINTN Length,\r
//\r
// Unmap the alaised Address\r
//\r
- Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);\r
+ Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r
if (!EFI_ERROR (Status)) {\r
//\r
// Restore atttributes\r
\r
VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r
CpuConvertPagesToUncachedVirtualAddress,\r
- CpuFreeConvertedPages\r
+ CpuReconvertPagesPages\r
};\r
\r
\r
VOID *
EFIAPI
ArmGetTranslationTableBaseAddress (
+ VOID
);
VOID
\r
struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {\r
CONVERT_PAGES_TO_UNCACHED_VIRTUAL_ADDRESS ConvertPages;\r
- FREE_CONVERTED_PAGES FreeConvertedPages;\r
+ FREE_CONVERTED_PAGES RevertPages;\r
};\r
\r
extern EFI_GUID gVirtualUncachedPagesProtocolGuid;\r
\r
-#endif
\ No newline at end of file
+#endif \r
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
- if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
- {
- CacheOperation();
- }
- else
- {
+ if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
+ CacheOperation ();
+ } else {
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
- while (AlignedAddress < EndAddress)
- {
+ while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
mcr p15,0,r0,c2,c0,0
bx lr
-ArmSetTranslationTableBaseAddress
+ArmGetTranslationTableBaseAddress
mrc p15,0,r0,c2,c0,0
bx lr
\r
\r
\r
-EFI_CPU_ARCH_PROTOCOL *gCpu;\r
+EFI_CPU_ARCH_PROTOCOL *gDebugUncachedCpu;\r
VIRTUAL_UNCACHED_PAGES_PROTOCOL *gVirtualUncachedPages;\r
\r
//\r
{\r
EFI_STATUS Status;\r
\r
- Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);\r
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gDebugUncachedCpu);\r
ASSERT_EFI_ERROR(Status);\r
\r
Status = gBS->LocateProtocol (&gVirtualUncachedPagesProtocolGuid, NULL, (VOID **)&gVirtualUncachedPages);\r
MdePkg/MdePkg.dec\r
ArmPkg/ArmPkg.dec\r
\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
\r
[LibraryClasses]\r
BaseLib\r
- UefiMemoryAllocationLib\r
+ MemoryAllocationLib\r
ArmLib\r
\r
+[Protocols]\r
+ gEfiCpuArchProtocolGuid\r
+ gVirtualUncachedPagesProtocolGuid\r
\r
[FixedPcd]\r
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask\r
\r
\r
[Depex]\r
- gEfiCpuArchProtocolGuid\r
- gVirtualUncachedPagesProtocolGuid
\ No newline at end of file
+ gEfiCpuArchProtocolGuid AND gVirtualUncachedPagesProtocolGuid
\ No newline at end of file
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
# DEBUG_ASSERT_ENABLED 0x01
-
# DEBUG_PRINT_ENABLED 0x02
-
# DEBUG_CODE_ENABLED 0x04
-
# CLEAR_MEMORY_ENABLED 0x08
-
# ASSERT_BREAKPOINT_ENABLED 0x10
-
# ASSERT_DEADLOOP_ENABLED 0x20
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
# DEBUG_INIT 0x00000001 // Initialization
-
# DEBUG_WARN 0x00000002 // Warnings
-
# DEBUG_LOAD 0x00000004 // Load events
-
# DEBUG_FS 0x00000008 // EFI File system
-
# DEBUG_POOL 0x00000010 // Alloc & Free's
-
# DEBUG_PAGE 0x00000020 // Alloc & Free's
-
# DEBUG_INFO 0x00000040 // Verbose
-
# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
-
# DEBUG_VARIABLE 0x00000100 // Variable
-
# DEBUG_BM 0x00000400 // Boot Manager
-
# DEBUG_BLKIO 0x00001000 // BlkIo Driver
-
# DEBUG_NET 0x00004000 // SNI Driver
-
# DEBUG_UNDI 0x00010000 // UNDI Driver
-
# DEBUG_LOADFILE 0x00020000 // UNDI Driver
-
# DEBUG_EVENT 0x00080000 // Event messages
-
# DEBUG_ERROR 0x80000000 // Error
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
MemoryTable[0].Length = MemoryLength;\r
MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
\r
- // Uncached DDR Mirror\r
- MemoryTable[1].PhysicalBase = MemoryBase;\r
- MemoryTable[1].VirtualBase = MemoryBase | UncachedMemoryMask;\r
- MemoryTable[1].Length = MemoryLength;\r
- MemoryTable[1].Attributes = DDR_ATTRIBUTES_UNCACHED;\r
-\r
// SOC Registers. L3 interconnects\r
- MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
- MemoryTable[2].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
- MemoryTable[2].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
- MemoryTable[2].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r
+ MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+ MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+ MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+ MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r
\r
// SOC Registers. L4 interconnects\r
- MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
- MemoryTable[3].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
- MemoryTable[3].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
- MemoryTable[3].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r
+ MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+ MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+ MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+ MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r
\r
// End of Table\r
- MemoryTable[4].PhysicalBase = 0;\r
- MemoryTable[4].VirtualBase = 0;\r
- MemoryTable[4].Length = 0;\r
- MemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+ MemoryTable[3].PhysicalBase = 0;\r
+ MemoryTable[3].VirtualBase = 0;\r
+ MemoryTable[3].Length = 0;\r
+ MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
\r
ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
\r