Added support for L2 (4K) page tables and made the CPU driver change cachability...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 7cd60182fd1cb57d3a82b7d36bb6e70c09f75c33..7001f28f17cc6d7cfad755d39e92d7ecca725236 100644 (file)
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -49,6 +49,7 @@
   DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
 
   ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
   DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
 
   ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf

+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf

 
 [LibraryClasses.ARM]
   #
 
 [LibraryClasses.ARM]
   #

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
index d3f0ff505dc98442b8fae8baf2c602f79c345d2c..a4ac97c65da21efec40b15d698e08875639b35f8 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -16,6 +16,34 @@
 \r
 BOOLEAN mInterruptState   = FALSE;\r
 \r
 \r
 BOOLEAN mInterruptState   = FALSE;\r
 \r

+\r
+/**\r
+  This function flushes the range of addresses from Start to Start+Length \r
+  from the processor's data cache. If Start is not aligned to a cache line \r
+  boundary, then the bytes before Start to the preceding cache line boundary \r
+  are also flushed. If Start+Length is not aligned to a cache line boundary, \r
+  then the bytes past Start+Length to the end of the next cache line boundary \r
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
+  supported. If the data cache is fully coherent with all DMA operations, then \r
+  this function can just return EFI_SUCCESS. If the processor does not support \r
+  flushing a range of the data cache, then the entire data cache can be flushed.\r
+\r
+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
+  @param  Start            The beginning physical address to flush from the processor's data\r
+                           cache.\r
+  @param  Length           The number of bytes to flush from the processor's data cache. This\r
+                           function may flush more bytes than Length specifies depending upon\r
+                           the granularity of the flush operation that the processor supports.\r
+  @param  FlushType        Specifies the type of flush operation to perform.\r
+\r
+  @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
+                                the processor's data cache.\r
+  @retval EFI_UNSUPPORTEDT      The processor does not support the cache flush type specified\r
+                                by FlushType.\r
+  @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
+                                from the processor's data cache.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 CpuFlushCpuDataCache (\r
 EFI_STATUS\r
 EFIAPI\r
 CpuFlushCpuDataCache (\r


@@ -25,6 +53,8 @@ CpuFlushCpuDataCache (
   IN EFI_CPU_FLUSH_TYPE              FlushType\r
   )\r
 {\r
   IN EFI_CPU_FLUSH_TYPE              FlushType\r
   )\r
 {\r

+  DEBUG ((EFI_D_ERROR, "CpuFlushCpuDataCache (%lx, %lx, %x)\n", Start, Length, FlushType));\r
+\r

   switch (FlushType) {\r
     case EfiCpuFlushTypeWriteBack:\r
       WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
   switch (FlushType) {\r
     case EfiCpuFlushTypeWriteBack:\r
       WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r


@@ -42,6 +72,16 @@ CpuFlushCpuDataCache (
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

+\r
+/**\r
+  This function enables interrupt processing by the processor. \r
+\r
+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
+\r
+  @retval EFI_SUCCESS           Interrupts are enabled on the processor.\r
+  @retval EFI_DEVICE_ERROR      Interrupts could not be enabled on the processor.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 CpuEnableInterrupt (\r
 EFI_STATUS\r
 EFIAPI\r
 CpuEnableInterrupt (\r


@@ -55,6 +95,15 @@ CpuEnableInterrupt (
 }\r
 \r
 \r
 }\r
 \r
 \r

+/**\r
+  This function disables interrupt processing by the processor.\r
+\r
+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
+\r
+  @retval EFI_SUCCESS           Interrupts are disabled on the processor.\r
+  @retval EFI_DEVICE_ERROR      Interrupts could not be disabled on the processor.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 CpuDisableInterrupt (\r
 EFI_STATUS\r
 EFIAPI\r
 CpuDisableInterrupt (\r


@@ -67,6 +116,20 @@ CpuDisableInterrupt (
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

+\r
+/**\r
+  This function retrieves the processor's current interrupt state a returns it in \r
+  State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
+  are currently disabled, then FALSE is returned.\r
+\r
+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
+  @param  State            A pointer to the processor's current interrupt state. Set to TRUE if\r
+                           interrupts are enabled and FALSE if interrupts are disabled.\r
+\r
+  @retval EFI_SUCCESS           The processor's current interrupt state was returned in State.\r
+  @retval EFI_INVALID_PARAMETER State is NULL.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 CpuGetInterruptState (\r
 EFI_STATUS\r
 EFIAPI\r
 CpuGetInterruptState (\r


@@ -82,6 +145,23 @@ CpuGetInterruptState (
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

+\r
+/**\r
+  This function generates an INIT on the processor. If this function succeeds, then the\r
+  processor will be reset, and control will not be returned to the caller. If InitType is \r
+  not supported by this processor, or the processor cannot programmatically generate an \r
+  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
+  occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
+\r
+  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
+  @param  InitType         The type of processor INIT to perform.\r
+\r
+  @retval EFI_SUCCESS           The processor INIT was performed. This return code should never be seen.\r
+  @retval EFI_UNSUPPORTED       The processor INIT operation specified by InitType is not supported\r
+                                by this processor.\r
+  @retval EFI_DEVICE_ERROR      The processor INIT failed.\r
+\r
+**/\r

 EFI_STATUS\r
 EFIAPI\r
 CpuInit (\r
 EFI_STATUS\r
 EFIAPI\r
 CpuInit (\r


@@ -115,17 +195,6 @@ CpuGetTimerValue (
   return EFI_UNSUPPORTED;\r
 }\r
 \r
   return EFI_UNSUPPORTED;\r
 }\r
 \r

-EFI_STATUS\r
-EFIAPI\r
-CpuSetMemoryAttributes (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
-  IN UINT64                    Length,\r
-  IN UINT64                    Attributes\r
-  )\r
-{\r
-  return EFI_UNSUPPORTED;\r
-}\r

 \r
 //\r
 // Globals used to initialize the protocol\r
 \r
 //\r
 // Globals used to initialize the protocol\r


@@ -149,8 +218,26 @@ CpuDxeInitialize (
   IN EFI_HANDLE         ImageHandle,\r
   IN EFI_SYSTEM_TABLE   *SystemTable\r
   )\r
   IN EFI_HANDLE         ImageHandle,\r
   IN EFI_SYSTEM_TABLE   *SystemTable\r
   )\r

-{ \r
+{\r
+  EFI_STATUS  Status;\r
+\r

   InitializeExceptions (&mCpu);  \r
   InitializeExceptions (&mCpu);  \r

-  return gBS->InstallMultipleProtocolInterfaces (&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);\r
+  \r
+  \r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                &mCpuHandle, \r
+                &gEfiCpuArchProtocolGuid,           &mCpu, \r
+                &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r
+                NULL\r
+                );\r
+  \r
+  //\r
+  // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
+  // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
+  // after the protocol is installed\r
+  //\r
+  SyncCacheConfig (&mCpu);\r
+  \r
+  return Status;\r

 }\r
 \r
 }\r
 \r

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
index 36133e11c31475d69f546a346fd5b0c06c1c6b6c..8a71075c65bdf28f9ed684f1a5ab3bbd9898e8b7 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
@@ -19,14 +19,29 @@
 \r
 #include <Library/ArmLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 \r
 #include <Library/ArmLib.h>\r
 #include <Library/BaseMemoryLib.h>\r

-#include <Library/CacheMaintenanceLib.h>\r

 #include <Library/DebugLib.h>\r
 #include <Library/PcdLib.h>\r
 #include <Library/UefiBootServicesTableLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/PcdLib.h>\r
 #include <Library/UefiBootServicesTableLib.h>\r

+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/CpuLib.h>\r

 \r
 \r

+#include <Guid/DebugImageInfoTable.h>\r

 #include <Protocol/Cpu.h>\r
 #include <Protocol/DebugSupport.h>\r
 #include <Protocol/DebugSupportPeriodicCallback.h>\r
 #include <Protocol/Cpu.h>\r
 #include <Protocol/DebugSupport.h>\r
 #include <Protocol/DebugSupportPeriodicCallback.h>\r

+#include <Protocol/VirtualUncachedPages.h>\r
+#include <Protocol/LoadedImage.h>\r
+\r
+\r
+#define EFI_MEMORY_CACHETYPE_MASK     (EFI_MEMORY_UC  | \\r
+                                       EFI_MEMORY_WC  | \\r
+                                       EFI_MEMORY_WT  | \\r
+                                       EFI_MEMORY_WB  | \\r
+                                       EFI_MEMORY_UCE   \\r
+                                       )\r

 \r
 \r
 /**\r
 \r
 \r
 /**\r


@@ -83,9 +98,31 @@ RegisterDebuggerInterruptHandler (
   );\r
 \r
 \r
   );\r
 \r
 \r

+EFI_STATUS\r
+EFIAPI\r
+CpuSetMemoryAttributes (\r
+  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
+  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN UINT64                    Length,\r
+  IN UINT64                    Attributes\r
+  );\r
+\r

 EFI_STATUS\r
 InitializeExceptions (\r
        IN EFI_CPU_ARCH_PROTOCOL    *Cpu\r
        );\r
 \r
 EFI_STATUS\r
 InitializeExceptions (\r
        IN EFI_CPU_ARCH_PROTOCOL    *Cpu\r
        );\r
 \r

+EFI_STATUS\r
+SyncCacheConfig (\r
+  IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
+  );\r
+\r
+EFI_STATUS \r
+ConvertSectionToPages (\r
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress\r
+  );\r
+\r
+\r
+extern VIRTUAL_UNCACHED_PAGES_PROTOCOL  gVirtualUncachedPages;\r
+\r

 #endif // __CPU_DXE_ARM_EXCEPTION_H__\r
 #endif // __CPU_DXE_ARM_EXCEPTION_H__\r

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
index f22b255c8d3d9274c69dbe0051b902ce3ecf463d..d4b494536bdf1e31cb5e53d18b2a2619fad74996 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
@@ -39,6 +39,7 @@
 #\r
   ExceptionSupport.ARMv6.asm | RVCT\r
 #  ExceptionSupport.ARMv6.S   | GCC\r
 #\r
   ExceptionSupport.ARMv6.asm | RVCT\r
 #  ExceptionSupport.ARMv6.S   | GCC\r

+  Mmu.c\r

 \r
 [Packages]\r
   ArmPkg/ArmPkg.dec\r
 \r
 [Packages]\r
   ArmPkg/ArmPkg.dec\r


@@ -50,10 +51,18 @@
   CacheMaintenanceLib\r
   UefiDriverEntryPoint\r
   ArmLib\r
   CacheMaintenanceLib\r
   UefiDriverEntryPoint\r
   ArmLib\r

+  DxeServicesTableLib\r
+  PeCoffGetEntryPointLib\r
+  UefiLib\r
+  CpuLib\r

 \r
 [Protocols]\r
   gEfiCpuArchProtocolGuid\r
   gEfiDebugSupportPeriodicCallbackProtocolGuid\r
 \r
 [Protocols]\r
   gEfiCpuArchProtocolGuid\r
   gEfiDebugSupportPeriodicCallbackProtocolGuid\r

+  gVirtualUncachedPagesProtocolGuid\r
+\r
+[Guids]\r
+  gEfiDebugImageInfoTableGuid\r

 \r
 [Pcd.common]\r
   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
 \r
 [Pcd.common]\r
   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r

diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c
index 9910bd2b881a5d730784f243cb63ed9446d70e9d..1f84e314b4a80d7017b440265f7a6ec98f9bf868 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/Exception.c
@@ -13,7 +13,8 @@
 **/\r
 \r
 #include "CpuDxe.h" \r
 **/\r
 \r
 #include "CpuDxe.h" \r

-#include <Library/CacheMaintenanceLib.h>\r
+\r
+EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *gDebugImageTableHeader = NULL;

 \r
 VOID\r
 ExceptionHandlersStart (\r
 \r
 VOID\r
 ExceptionHandlersStart (\r


@@ -120,6 +121,76 @@ RegisterDebuggerInterruptHandler (
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

+\r
+UINT32
+EFIAPI
+PeCoffGetSizeOfHeaders (
+  IN VOID     *Pe32Data
+  )
+{
+  EFI_IMAGE_DOS_HEADER                  *DosHdr;
+  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION   Hdr;
+  UINTN                                 SizeOfHeaders;
+
+  DosHdr = (EFI_IMAGE_DOS_HEADER *)Pe32Data;
+  if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+    //
+    // DOS image header is present, so read the PE header after the DOS image header.
+    //
+    Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
+  } else {
+    //
+    // DOS image header is not present, so PE header is at the image base.
+    //
+    Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
+  }
+
+  if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {
+   SizeOfHeaders = sizeof (EFI_TE_IMAGE_HEADER) + (UINTN)Hdr.Te->BaseOfCode - (UINTN)Hdr.Te->StrippedSize;
+  } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
+    SizeOfHeaders = Hdr.Pe32->OptionalHeader.SizeOfHeaders;
+  }
+
+  return SizeOfHeaders;
+}\r
+\r
+\r
+CHAR8 *\r
+GetImageName (\r
+  IN  UINT32  FaultAddress,\r
+  OUT UINT32  *ImageBase,\r
+  OUT UINT32  *PeCoffSizeOfHeaders\r
+  )\r
+{\r
+  EFI_DEBUG_IMAGE_INFO  *DebugTable;
+  UINTN                 Entry;
+  CHAR8                 *Address;
+
+  \r
+  DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;\r
+  if (DebugTable == NULL) {\r
+    return NULL;\r
+  }\r
+\r
+  Address = (CHAR8 *)(UINTN)FaultAddress;\r
+  for (Entry = 0; Entry < gDebugImageTableHeader->TableSize; Entry++, DebugTable++) {
+    if (DebugTable->NormalImage != NULL) {
+      if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) && 
+          (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
+        if ((Address >= DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
+            (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
+          *ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+          *PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
+          return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
+        }           
+      }
+    }  
+  }\r
+\r
+  return NULL;\r
+}\r
+\r
+\r

 CHAR8 *gExceptionTypeString[] = {\r
   "Reset",\r
   "Undefined Instruction",\r
 CHAR8 *gExceptionTypeString[] = {\r
   "Reset",\r
   "Undefined Instruction",\r


@@ -174,11 +245,41 @@ CommonCExceptionHandler (
   }\r
 \r
   //\r
   }\r
 \r
   //\r

-  // Code after here is the default exception handler...\r
+  // Code after here is the default exception handler... Dump the context\r

   //\r
   //\r

-  DEBUG ((EFI_D_ERROR, "%a Exception from %08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC));\r
-  ASSERT (FALSE);\r
+  DEBUG ((EFI_D_ERROR, "\n%a Exception from instruction at 0x%08x  CPSR 0x%08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR));\r
+  DEBUG_CODE_BEGIN ();\r
+    CHAR8   *Pdb;
+    UINT32  ImageBase;
+    UINT32  PeCoffSizeOfHeader;
+    UINT32  Offset;
+  \r
+    Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);\r
+    Offset = SystemContext.SystemContextArm->PC - ImageBase;\r
+    if (Pdb != NULL) {\r
+      DEBUG ((EFI_D_ERROR, "%a\n", Pdb));\r

 \r
 \r

+      //\r
+      // A PE/COFF image loads its headers into memory so the headers are \r
+      // included in the linked addressess. ELF and Mach-O images do not\r
+      // include the headers so the first byte of the image is usually\r
+      // text (code). If you look at link maps from ELF or Mach-O images\r
+      // you need to subtact out the size of the PE/COFF header to get\r
+      // get the offset that matches the link map. \r
+      //\r
+      DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%08x (ELF or Mach-O offset) 0x%08x\n", ImageBase, Offset, Offset - PeCoffSizeOfHeader));\r
+    }\r
+  DEBUG_CODE_END ();\r
+  DEBUG ((EFI_D_ERROR, " R0 0x%08x  R1 0x%08x  R2 0x%08x  R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));\r
+  DEBUG ((EFI_D_ERROR, " R4 0x%08x  R5 0x%08x  R6 0x%08x  R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));\r
+  DEBUG ((EFI_D_ERROR, " R8 0x%08x  R9 0x%08x R10 0x%08x R11 0x%08x\n", SystemContext.SystemContextArm->R8, SystemContext.SystemContextArm->R9, SystemContext.SystemContextArm->R10, SystemContext.SystemContextArm->R11));\r
+  DEBUG ((EFI_D_ERROR, "R12 0x%08x  SP 0x%08x  LR 0x%08x  PC 0x%08x\n", SystemContext.SystemContextArm->R12, SystemContext.SystemContextArm->SP, SystemContext.SystemContextArm->LR, SystemContext.SystemContextArm->PC));\r
+  DEBUG ((EFI_D_ERROR, "DFSR 0x%08x  DFAR 0x%08x IFSR 0x%08x  IFAR 0x%08x\n\n", SystemContext.SystemContextArm->DFSR, SystemContext.SystemContextArm->DFAR, SystemContext.SystemContextArm->IFSR, SystemContext.SystemContextArm->IFAR));\r
+\r
+  ASSERT (FALSE);\r
+//  while (TRUE) {\r
+//    CpuSleep ();\r
+//  }\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -195,6 +296,11 @@ InitializeExceptions (
   BOOLEAN              Enabled;\r
   EFI_PHYSICAL_ADDRESS Base;\r
 \r
   BOOLEAN              Enabled;\r
   EFI_PHYSICAL_ADDRESS Base;\r
 \r

+  Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&gDebugImageTableHeader);
+  if (EFI_ERROR (Status)) {
+    gDebugImageTableHeader = NULL;
+  }
+\r

   //\r
   // Disable interrupts\r
   //\r
   //\r
   // Disable interrupts\r
   //\r

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index c6b5c08ce17fb40816c809d813799967d6422bf5..a0977dd1107379edc05915b68f51a879a2fe6cbe 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -16,6 +16,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "CpuDxe.h"\r
 \r
 \r
 #include "CpuDxe.h"\r
 \r

+//\r
+// For debug switch me back to to EFI_D_PAGE when done\r
+//\r
+#define L_EFI_D_PAGE EFI_D_ERROR\r
+\r

 //\r
 // Translation/page table definitions\r
 //\r
 //\r
 // Translation/page table definitions\r
 //\r


@@ -170,13 +175,12 @@ SectionToGcdAttributes (
       break;\r
     default:\r
       return EFI_UNSUPPORTED;\r
       break;\r
     default:\r
       return EFI_UNSUPPORTED;\r

-      break;\r

   }\r
     \r
   // determine protection attributes\r
   switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r
     case ARM_SECTION_NO_ACCESS: // no read, no write\r
   }\r
     \r
   // determine protection attributes\r
   switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r
     case ARM_SECTION_NO_ACCESS: // no read, no write\r

-      *GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r
+      //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r

       break;\r
 \r
     case ARM_SECTION_PRIV_ACCESS_ONLY:\r
       break;\r
 \r
     case ARM_SECTION_PRIV_ACCESS_ONLY:\r


@@ -193,7 +197,6 @@ SectionToGcdAttributes (
 \r
     default:\r
       return EFI_UNSUPPORTED;\r
 \r
     default:\r
       return EFI_UNSUPPORTED;\r

-      break;\r

   }\r
 \r
   // now process eXectue Never attribute\r
   }\r
 \r
   // now process eXectue Never attribute\r


@@ -204,6 +207,132 @@ SectionToGcdAttributes (
   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

+/**\r
+  Searches memory descriptors covered by given memory range.\r
+\r
+  This function searches into the Gcd Memory Space for descriptors\r
+  (from StartIndex to EndIndex) that contains the memory range\r
+  specified by BaseAddress and Length.\r
+\r
+  @param  MemorySpaceMap       Gcd Memory Space Map as array.\r
+  @param  NumberOfDescriptors  Number of descriptors in map.\r
+  @param  BaseAddress          BaseAddress for the requested range.\r
+  @param  Length               Length for the requested range.\r
+  @param  StartIndex           Start index into the Gcd Memory Space Map.\r
+  @param  EndIndex             End index into the Gcd Memory Space Map.\r
+\r
+  @retval EFI_SUCCESS          Search successfully.\r
+  @retval EFI_NOT_FOUND        The requested descriptors does not exist.\r
+\r
+**/\r
+EFI_STATUS\r
+SearchGcdMemorySpaces (\r
+  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,\r
+  IN UINTN                               NumberOfDescriptors,\r
+  IN EFI_PHYSICAL_ADDRESS                BaseAddress,\r
+  IN UINT64                              Length,\r
+  OUT UINTN                              *StartIndex,\r
+  OUT UINTN                              *EndIndex\r
+  )\r
+{\r
+  UINTN           Index;\r
+\r
+  *StartIndex = 0;\r
+  *EndIndex   = 0;\r
+  for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
+    if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
+        BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+      *StartIndex = Index;\r
+    }\r
+    if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
+        BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+      *EndIndex = Index;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+\r
+/**\r
+  Sets the attributes for a specified range in Gcd Memory Space Map.\r
+\r
+  This function sets the attributes for a specified range in\r
+  Gcd Memory Space Map.\r
+\r
+  @param  MemorySpaceMap       Gcd Memory Space Map as array\r
+  @param  NumberOfDescriptors  Number of descriptors in map\r
+  @param  BaseAddress          BaseAddress for the range\r
+  @param  Length               Length for the range\r
+  @param  Attributes           Attributes to set\r
+\r
+  @retval EFI_SUCCESS          Memory attributes set successfully\r
+  @retval EFI_NOT_FOUND        The specified range does not exist in Gcd Memory Space\r
+\r
+**/\r
+EFI_STATUS\r
+SetGcdMemorySpaceAttributes (\r
+  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,\r
+  IN UINTN                               NumberOfDescriptors,\r
+  IN EFI_PHYSICAL_ADDRESS                BaseAddress,\r
+  IN UINT64                              Length,\r
+  IN UINT64                              Attributes\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  UINTN                 Index;\r
+  UINTN                 StartIndex;\r
+  UINTN                 EndIndex;\r
+  EFI_PHYSICAL_ADDRESS  RegionStart;\r
+  UINT64                RegionLength;\r
+\r
+  //\r
+  // Get all memory descriptors covered by the memory range\r
+  //\r
+  Status = SearchGcdMemorySpaces (\r
+             MemorySpaceMap,\r
+             NumberOfDescriptors,\r
+             BaseAddress,\r
+             Length,\r
+             &StartIndex,\r
+             &EndIndex\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Go through all related descriptors and set attributes accordingly\r
+  //\r
+  for (Index = StartIndex; Index <= EndIndex; Index++) {\r
+    if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
+      continue;\r
+    }\r
+    //\r
+    // Calculate the start and end address of the overlapping range\r
+    //\r
+    if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
+      RegionStart = BaseAddress;\r
+    } else {\r
+      RegionStart = MemorySpaceMap[Index].BaseAddress;\r
+    }\r
+    if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+      RegionLength = BaseAddress + Length - RegionStart;\r
+    } else {\r
+      RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
+    }\r
+    //\r
+    // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
+    //\r
+    gDS->SetMemorySpaceAttributes (\r
+           RegionStart,\r
+           RegionLength,\r
+           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
+           );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

 \r
 \r
 EFI_STATUS\r
 \r
 \r
 EFI_STATUS\r


@@ -211,20 +340,31 @@ SyncCacheConfig (
   IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
   )\r
 {\r
   IN  EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r
   )\r
 {\r

-  EFI_STATUS            Status;\r
-  UINT32                i;\r
-  UINT32                Descriptor;\r
-  UINT32                SectionAttributes;\r
-  EFI_PHYSICAL_ADDRESS  NextRegionBase;\r
-  UINT64                NextRegionLength;\r
-  UINT64                GcdAttributes;\r
-  UINT32                NextRegionAttributes = 0;\r
+  EFI_STATUS                          Status;\r
+  UINT32                              i;\r
+  UINT32                              Descriptor;\r
+  UINT32                              SectionAttributes;\r
+  EFI_PHYSICAL_ADDRESS                NextRegionBase;\r
+  UINT64                              NextRegionLength;\r
+  UINT64                              GcdAttributes;\r
+  UINT32                              NextRegionAttributes = 0;\r

   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r

+  UINTN                               NumberOfDescriptors;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;\r

 \r
 \r
 \r
 \r

+  DEBUG ((L_EFI_D_PAGE, "SyncCacheConfig()\n"));\r
+\r

   // This code assumes MMU is enabled and filed with section translations\r
   ASSERT (ArmMmuEnabled ());\r
 \r
   // This code assumes MMU is enabled and filed with section translations\r
   ASSERT (ArmMmuEnabled ());\r
 \r

+  //\r
+  // Get the memory space map from GCD\r
+  //\r
+  MemorySpaceMap = NULL;\r
+  Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r

 \r
   // The GCD implementation maintains its own copy of the state of memory space attributes.  GCD needs\r
   // to know what the initial memory space attributes are.  The CPU Arch. Protocol does not provide a\r
 \r
   // The GCD implementation maintains its own copy of the state of memory space attributes.  GCD needs\r
   // to know what the initial memory space attributes are.  The CPU Arch. Protocol does not provide a\r


@@ -240,8 +380,8 @@ SyncCacheConfig (
   NextRegionBase = NextRegionLength = 0;\r
   for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r
 \r
   NextRegionBase = NextRegionLength = 0;\r
   for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r
 \r

-    // obtain existing descriptor\r
-    Descriptor = FirstLevelTable[i];\r
+    // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section\r
+    Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));\r

 \r
     // extract attributes (cacheability and permissions)\r
     SectionAttributes = Descriptor & 0xDEC;\r
 \r
     // extract attributes (cacheability and permissions)\r
     SectionAttributes = Descriptor & 0xDEC;\r


@@ -254,11 +394,11 @@ SyncCacheConfig (
         \r
         // convert section entry attributes to GCD bitmask\r
         Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r
         \r
         // convert section entry attributes to GCD bitmask\r
         Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r

-        ASSERT_EFI_ERROR(Status);\r
+        ASSERT_EFI_ERROR (Status);\r

 \r
         // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r
 \r
         // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r

-        Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);\r
-        ASSERT_EFI_ERROR(Status);\r
+        SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r
+\r

 \r
         // start on a new region\r
         NextRegionLength = 0;\r
 \r
         // start on a new region\r
         NextRegionLength = 0;\r


@@ -343,12 +483,11 @@ UpdatePageEntries (
       // Cause a page fault if these ranges are accessed.\r
       EntryMask   = 0x3;\r
       EntryValue = 0;\r
       // Cause a page fault if these ranges are accessed.\r
       EntryMask   = 0x3;\r
       EntryValue = 0;\r

-      DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+      DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r

       break;\r
 \r
     default:\r
       return EFI_UNSUPPORTED;\r
       break;\r
 \r
     default:\r
       return EFI_UNSUPPORTED;\r

-      break;\r

   }\r
 \r
   // obtain page table base\r
   }\r
 \r
   // obtain page table base\r


@@ -369,7 +508,7 @@ UpdatePageEntries (
     Descriptor = FirstLevelTable[FirstLevelIdx];\r
 \r
     // does this descriptor need to be converted from section entry to 4K pages?\r
     Descriptor = FirstLevelTable[FirstLevelIdx];\r
 \r
     // does this descriptor need to be converted from section entry to 4K pages?\r

-    if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {\r
+    if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r

       Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r
       if (EFI_ERROR(Status)) {\r
         // exit for loop\r
       Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r
       if (EFI_ERROR(Status)) {\r
         // exit for loop\r


@@ -385,7 +524,7 @@ UpdatePageEntries (
 \r
     // calculate index into the page table\r
     PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r
 \r
     // calculate index into the page table\r
     PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r

-    ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
+    ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r

 \r
     // get the entry\r
     PageTableEntry = PageTable[PageTableIndex];\r
 \r
     // get the entry\r
     PageTableEntry = PageTable[PageTableIndex];\r


@@ -436,35 +575,39 @@ UpdateSectionEntries (
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
   // EntryValue: values at bit positions specified by EntryMask\r
 \r
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
   // EntryValue: values at bit positions specified by EntryMask\r
 \r

+  // Make sure we handle a section range that is unmapped \r
+  EntryMask = ARM_DESC_TYPE_MASK;\r
+  EntryValue = ARM_DESC_TYPE_SECTION;\r
+\r

   // Although the PI spec is unclear on this the GCD guarantees that only\r
   // one Attribute bit is set at a time, so we can safely use a switch statement\r
   switch(Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r
   // Although the PI spec is unclear on this the GCD guarantees that only\r
   // one Attribute bit is set at a time, so we can safely use a switch statement\r
   switch(Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r

-      EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r

       // map to strongly ordered\r
       // map to strongly ordered\r

-      EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+      EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r

       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r
       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r

-      EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r

       // map to normal non-cachable\r
       // map to normal non-cachable\r

-      EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+      EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r

       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r
       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r

-      EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r

       // write through with no-allocate\r
       // write through with no-allocate\r

-      EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
+      EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r

       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r
       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r

-      EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+      EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r

       // write back (with allocate)\r
       // write back (with allocate)\r

-      EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
+      EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r

       break;\r
 \r
     case EFI_MEMORY_WP:\r
       break;\r
 \r
     case EFI_MEMORY_WP:\r


@@ -473,15 +616,13 @@ UpdateSectionEntries (
     case EFI_MEMORY_UCE:\r
       // cannot be implemented UEFI definition unclear for ARM\r
       // Cause a page fault if these ranges are accessed.\r
     case EFI_MEMORY_UCE:\r
       // cannot be implemented UEFI definition unclear for ARM\r
       // Cause a page fault if these ranges are accessed.\r

-      EntryMask   = 0x3;\r
-      EntryValue = 0;\r
-      DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
+      EntryValue = ARM_DESC_TYPE_FAULT;\r
+      DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r

       break;\r
 \r
 \r
     default:\r
       return EFI_UNSUPPORTED;\r
       break;\r
 \r
 \r
     default:\r
       return EFI_UNSUPPORTED;\r

-      break;\r

   }\r
 \r
   // obtain page table base\r
   }\r
 \r
   // obtain page table base\r


@@ -499,7 +640,7 @@ UpdateSectionEntries (
     Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
 \r
     // has this descriptor already been coverted to pages?\r
     Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
 \r
     // has this descriptor already been coverted to pages?\r

-    if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {\r
+    if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r

       // forward this 1MB range to page table function instead\r
       Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
     } else {\r
       // forward this 1MB range to page table function instead\r
       Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
     } else {\r


@@ -539,14 +680,14 @@ ConvertSectionToPages (
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r
 \r
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;\r
   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;\r
 \r

-  DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r
+  DEBUG ((L_EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r

 \r
   // obtain page table base\r
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
 \r
   // calculate index into first level translation table for start of modification\r
   FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r
 \r
   // obtain page table base\r
   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
 \r
   // calculate index into first level translation table for start of modification\r
   FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r

-  ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r
+  ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r

 \r
   // get section attributes and convert to page attributes\r
   SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r
 \r
   // get section attributes and convert to page attributes\r
   SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r


@@ -588,7 +729,9 @@ ConvertSectionToPages (
   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
   // TODO: change to use only PageTable base and length\r
   // ArmInvalidateDataCache ();\r
   // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
   // TODO: change to use only PageTable base and length\r
   // ArmInvalidateDataCache ();\r

-  InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);\r
+DEBUG ((EFI_D_ERROR, "InvalidateDataCacheRange (%x, %x)\n", (UINTN)PageTableAddr, EFI_PAGE_SIZE));\r
+\r
+  InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);\r

 \r
   // formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
 \r
   // formulate page table entry, Domain=0, NS=0\r
   PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r


@@ -613,11 +756,11 @@ SetMemoryAttributes (
   \r
   if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
     // is the base and length a multiple of 1 MB?\r
   \r
   if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r
     // is the base and length a multiple of 1 MB?\r

-    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+    DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r

     Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   } else {\r
     // base and/or length is not a multiple of 1 MB\r
     Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   } else {\r
     // base and/or length is not a multiple of 1 MB\r

-    DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r
+    DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r

     Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   }\r
 \r
     Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r
   }\r
 \r


@@ -664,8 +807,10 @@ CpuSetMemoryAttributes (
   IN UINT64                    Attributes\r
   )\r
 {\r
   IN UINT64                    Attributes\r
   )\r
 {\r

+  DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r

   if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
     // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
   if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
     // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r

+    DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));\r

     return EFI_UNSUPPORTED;\r
   }\r
   \r
     return EFI_UNSUPPORTED;\r
   }\r
   \r


@@ -698,13 +843,13 @@ CpuConvertPagesToUncachedVirtualAddress (
       *Attributes = GcdDescriptor.Attributes;\r
     }\r
   }\r
       *Attributes = GcdDescriptor.Attributes;\r
     }\r
   }\r

-  \r
+ASSERT (FALSE);  \r

   //\r
   // Make this address range page fault if accessed. If it is a DMA buffer than this would \r
   // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r
   // to that address. \r
   //\r
   //\r
   // Make this address range page fault if accessed. If it is a DMA buffer than this would \r
   // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r
   // to that address. \r
   //\r

-  Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);\r
+  Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r

   if (!EFI_ERROR (Status)) {\r
     Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
   }\r
   if (!EFI_ERROR (Status)) {\r
     Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
   }\r


@@ -715,7 +860,7 @@ CpuConvertPagesToUncachedVirtualAddress (
 \r
 EFI_STATUS\r
 EFIAPI\r
 \r
 EFI_STATUS\r
 EFIAPI\r

-CpuFreeConvertedPages (\r
+CpuReconvertPagesPages (\r

   IN  VIRTUAL_UNCACHED_PAGES_PROTOCOL   *This,\r
   IN  EFI_PHYSICAL_ADDRESS              Address,\r
   IN  UINTN                             Length,\r
   IN  VIRTUAL_UNCACHED_PAGES_PROTOCOL   *This,\r
   IN  EFI_PHYSICAL_ADDRESS              Address,\r
   IN  UINTN                             Length,\r


@@ -728,7 +873,7 @@ CpuFreeConvertedPages (
   //\r
   // Unmap the alaised Address\r
   //\r
   //\r
   // Unmap the alaised Address\r
   //\r

-  Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);\r
+  Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r

   if (!EFI_ERROR (Status)) {\r
     //\r
     // Restore atttributes\r
   if (!EFI_ERROR (Status)) {\r
     //\r
     // Restore atttributes\r


@@ -742,7 +887,7 @@ CpuFreeConvertedPages (
 \r
 VIRTUAL_UNCACHED_PAGES_PROTOCOL  gVirtualUncachedPages = {\r
   CpuConvertPagesToUncachedVirtualAddress,\r
 \r
 VIRTUAL_UNCACHED_PAGES_PROTOCOL  gVirtualUncachedPages = {\r
   CpuConvertPagesToUncachedVirtualAddress,\r

-  CpuFreeConvertedPages\r
+  CpuReconvertPagesPages\r

 };\r
 \r
 \r
 };\r
 \r
 \r

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5cadb3c42ad506dbd1cb43ed50601c3779dc4c76..371075b132f2d2f4b685bffc7fea6159a60d2d27 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -263,6 +263,7 @@ ArmSetTranslationTableBaseAddress (
 VOID *
 EFIAPI
 ArmGetTranslationTableBaseAddress (
 VOID *
 EFIAPI
 ArmGetTranslationTableBaseAddress (

+  VOID

   );
 
 VOID
   );
 
 VOID

diff --git a/ArmPkg/Include/Protocol/VirtualUncachedPages.h b/ArmPkg/Include/Protocol/VirtualUncachedPages.h
index 32deec2514b483ccebba763f591b467d731469ac..cd397962afdb38c720c51bbcfba23d4ffa6e50fa 100644 (file)
--- a/ArmPkg/Include/Protocol/VirtualUncachedPages.h
+++ b/ArmPkg/Include/Protocol/VirtualUncachedPages.h
@@ -52,9 +52,9 @@ EFI_STATUS
 \r
 struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {\r
   CONVERT_PAGES_TO_UNCACHED_VIRTUAL_ADDRESS  ConvertPages;\r
 \r
 struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {\r
   CONVERT_PAGES_TO_UNCACHED_VIRTUAL_ADDRESS  ConvertPages;\r

-  FREE_CONVERTED_PAGES                       FreeConvertedPages;\r
+  FREE_CONVERTED_PAGES                       RevertPages;\r

 };\r
 \r
 extern EFI_GUID gVirtualUncachedPagesProtocolGuid;\r
 \r
 };\r
 \r
 extern EFI_GUID gVirtualUncachedPagesProtocolGuid;\r
 \r

-#endif 
\ No newline at end of file
+#endif \r

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 7da6b42a928b8b9ab91ecd769bbfa35d14fa9dee..b5754e6dcae2f1fb971123f67be0ae07ac21646f 100644 (file)
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -27,19 +27,15 @@ CacheRangeOperation (
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
   UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
   
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
   UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
   

-  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
-  {
-    CacheOperation();
-  }
-  else
-  {
+  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
+    CacheOperation ();
+  } else {

     // Align address (rounding down)
     UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
     UINTN EndAddress     = (UINTN)Start + Length;
 
     // Perform the line operation on an address in each cache line
     // Align address (rounding down)
     UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
     UINTN EndAddress     = (UINTN)Start + Length;
 
     // Perform the line operation on an address in each cache line

-    while (AlignedAddress < EndAddress)
-    {
+    while (AlignedAddress < EndAddress) {

       LineOperation(AlignedAddress);
       AlignedAddress += ArmCacheLineLength;
     }
       LineOperation(AlignedAddress);
       AlignedAddress += ArmCacheLineLength;
     }

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index ecae8a31a2f08137351a52331123f3bc3e3679d7..630c72fdeeb7de56782963d05301b07532951111 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -66,7 +66,7 @@ ArmSetTranslationTableBaseAddress
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 

-ArmSetTranslationTableBaseAddress
+ArmGetTranslationTableBaseAddress

   mrc     p15,0,r0,c2,c0,0
   bx      lr
 
   mrc     p15,0,r0,c2,c0,0
   bx      lr
 

diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
index b4c1c5f2e5f13c94e8a3913c9c6f5cf18bd06937..80e7c8c4729c4a611766aba4395eca350769c2f0 100644 (file)
--- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
+++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
@@ -49,7 +49,7 @@ UncachedInternalAllocateAlignedPages (
   \r
   \r
 \r
   \r
   \r
 \r

-EFI_CPU_ARCH_PROTOCOL           *gCpu;\r
+EFI_CPU_ARCH_PROTOCOL           *gDebugUncachedCpu;\r

 VIRTUAL_UNCACHED_PAGES_PROTOCOL *gVirtualUncachedPages;\r
 \r
 //\r
 VIRTUAL_UNCACHED_PAGES_PROTOCOL *gVirtualUncachedPages;\r
 \r
 //\r


@@ -641,7 +641,7 @@ DebugUncachedMemoryAllocationLibConstructor (
 {\r
   EFI_STATUS    Status;\r
   \r
 {\r
   EFI_STATUS    Status;\r
   \r

-  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);\r
+  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gDebugUncachedCpu);\r

   ASSERT_EFI_ERROR(Status);\r
 \r
   Status = gBS->LocateProtocol (&gVirtualUncachedPagesProtocolGuid, NULL, (VOID **)&gVirtualUncachedPages);\r
   ASSERT_EFI_ERROR(Status);\r
 \r
   Status = gBS->LocateProtocol (&gVirtualUncachedPagesProtocolGuid, NULL, (VOID **)&gVirtualUncachedPages);\r

diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
index 102ef7801035ebd23043e390468837cac4ad42d6..9cf29015d5920c0c9b26e8561e35777701536e1d 100644 (file)
--- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
@@ -29,19 +29,19 @@
   MdePkg/MdePkg.dec\r
   ArmPkg/ArmPkg.dec\r
 \r
   MdePkg/MdePkg.dec\r
   ArmPkg/ArmPkg.dec\r
 \r

-[Protocols]\r
-  gEfiCpuArchProtocolGuid\r

 \r
 [LibraryClasses]\r
   BaseLib\r
 \r
 [LibraryClasses]\r
   BaseLib\r

-  UefiMemoryAllocationLib\r
+  MemoryAllocationLib\r

   ArmLib\r
 \r
   ArmLib\r
 \r

+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+  gVirtualUncachedPagesProtocolGuid\r

 \r
 [FixedPcd]\r
   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask\r
   \r
   \r
 [Depex]\r
 \r
 [FixedPcd]\r
   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask\r
   \r
   \r
 [Depex]\r

-  gEfiCpuArchProtocolGuid\r
-  gVirtualUncachedPagesProtocolGuid
\ No newline at end of file
+  gEfiCpuArchProtocolGuid AND gVirtualUncachedPagesProtocolGuid
\ No newline at end of file

diff --git a/BeagleBoardPkg/BeagleBoardPkg.dsc b/BeagleBoardPkg/BeagleBoardPkg.dsc
index 6765fa8f0c823d9d97c6f82e82901f383fec60cf..928224b1011e972147eeeb5b5a28cd29e8262540 100644 (file)
--- a/BeagleBoardPkg/BeagleBoardPkg.dsc
+++ b/BeagleBoardPkg/BeagleBoardPkg.dsc
@@ -40,6 +40,7 @@
 
 
   ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
 
 
   ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf

+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf

   
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf


@@ -90,7 +91,10 @@
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
   
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
   

-  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf

 
   TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf  
   OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
 
   TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf  
   OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf


@@ -206,49 +210,29 @@
   gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
 
 # DEBUG_ASSERT_ENABLED       0x01
   gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
 
 # DEBUG_ASSERT_ENABLED       0x01

-

 # DEBUG_PRINT_ENABLED        0x02
 # DEBUG_PRINT_ENABLED        0x02

-

 # DEBUG_CODE_ENABLED         0x04
 # DEBUG_CODE_ENABLED         0x04

-

 # CLEAR_MEMORY_ENABLED       0x08
 # CLEAR_MEMORY_ENABLED       0x08

-

 # ASSERT_BREAKPOINT_ENABLED  0x10
 # ASSERT_BREAKPOINT_ENABLED  0x10

-

 # ASSERT_DEADLOOP_ENABLED    0x20
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
 
 #  DEBUG_INIT      0x00000001  // Initialization
 # ASSERT_DEADLOOP_ENABLED    0x20
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
 
 #  DEBUG_INIT      0x00000001  // Initialization

-

 #  DEBUG_WARN      0x00000002  // Warnings
 #  DEBUG_WARN      0x00000002  // Warnings

-

 #  DEBUG_LOAD      0x00000004  // Load events
 #  DEBUG_LOAD      0x00000004  // Load events

-

 #  DEBUG_FS        0x00000008  // EFI File system
 #  DEBUG_FS        0x00000008  // EFI File system

-

 #  DEBUG_POOL      0x00000010  // Alloc & Free's
 #  DEBUG_POOL      0x00000010  // Alloc & Free's

-

 #  DEBUG_PAGE      0x00000020  // Alloc & Free's
 #  DEBUG_PAGE      0x00000020  // Alloc & Free's

-

 #  DEBUG_INFO      0x00000040  // Verbose
 #  DEBUG_INFO      0x00000040  // Verbose

-

 #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
 #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers

-

 #  DEBUG_VARIABLE  0x00000100  // Variable
 #  DEBUG_VARIABLE  0x00000100  // Variable

-

 #  DEBUG_BM        0x00000400  // Boot Manager
 #  DEBUG_BM        0x00000400  // Boot Manager

-

 #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
 #  DEBUG_BLKIO     0x00001000  // BlkIo Driver

-

 #  DEBUG_NET       0x00004000  // SNI Driver
 #  DEBUG_NET       0x00004000  // SNI Driver

-

 #  DEBUG_UNDI      0x00010000  // UNDI Driver
 #  DEBUG_UNDI      0x00010000  // UNDI Driver

-

 #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
 #  DEBUG_LOADFILE  0x00020000  // UNDI Driver

-

 #  DEBUG_EVENT     0x00080000  // Event messages
 #  DEBUG_EVENT     0x00080000  // Event messages

-

 #  DEBUG_ERROR     0x80000000  // Error
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
 #  DEBUG_ERROR     0x80000000  // Error
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004

diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c
index facc5deae40d6c07e7385305abd9e6ddbecea551..d7c906244c5ab21345bd8e22efdb21c1d896c141 100755 (executable)
--- a/BeagleBoardPkg/Sec/Cache.c
+++ b/BeagleBoardPkg/Sec/Cache.c
@@ -58,29 +58,23 @@ InitCache (
   MemoryTable[0].Length       = MemoryLength;\r
   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
 \r
   MemoryTable[0].Length       = MemoryLength;\r
   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
 \r

-  // Uncached DDR Mirror\r
-  MemoryTable[1].PhysicalBase = MemoryBase;\r
-  MemoryTable[1].VirtualBase  = MemoryBase | UncachedMemoryMask;\r
-  MemoryTable[1].Length       = MemoryLength;\r
-  MemoryTable[1].Attributes   = DDR_ATTRIBUTES_UNCACHED;\r
-\r

   // SOC Registers. L3 interconnects\r
   // SOC Registers. L3 interconnects\r

-  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
-  MemoryTable[2].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
-  MemoryTable[2].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r

   \r
   // SOC Registers. L4 interconnects\r
   \r
   // SOC Registers. L4 interconnects\r

-  MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
-  MemoryTable[3].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
-  MemoryTable[3].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r

 \r
   // End of Table\r
 \r
   // End of Table\r

-  MemoryTable[4].PhysicalBase = 0;\r
-  MemoryTable[4].VirtualBase  = 0;\r
-  MemoryTable[4].Length       = 0;\r
-  MemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+  MemoryTable[3].PhysicalBase = 0;\r
+  MemoryTable[3].VirtualBase  = 0;\r
+  MemoryTable[3].Length       = 0;\r
+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r

   \r
   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
   \r
   \r
   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
   \r