MdeModulePkg/NvmExpressDxe: Handling return of write to sq and cq db

In case of an async command if updating the submission queue tail
doorbell fails then the command will not be picked up by device and
no completion response will be created. This scenario has to be handled.
Also if we create an AsyncRequest element and insert in the async queue,
it will never receive a completion so in the timer routine this element
won't be freed, resulting in memory leak. Also in case of blocking calls
we should capture the status of updating completion queue head doorbell
register and return it to caller of PassThru.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Suman Prakash <suman.p@samsung.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
index ef3d772cc28b1ebe640b066ee24da505fc5f4144..fb80f39ce8977e97858c07fe4a77fe9b9681774b 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
@@ -603,7 +603,7 @@ NvmExpressPassThru (
     Private->SqTdbl[QueueId].Sqt ^= 1;\r
   }\r
   Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);\r
-  PciIo->Mem.Write (\r
+  Status = PciIo->Mem.Write (\r
                PciIo,\r
                EfiPciIoWidthUint32,\r
                NVME_BAR,\r
@@ -612,6 +612,10 @@ NvmExpressPassThru (
                &Data\r
                );\r
 \r
+  if (EFI_ERROR (Status)) {\r
+    goto EXIT;\r
+  }\r
+\r
   //\r
   // For non-blocking requests, return directly if the command is placed\r
   // in the submission queue.\r
@@ -695,7 +699,7 @@ NvmExpressPassThru (
   }\r
 \r
   Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);\r
-  PciIo->Mem.Write (\r
+  Status = PciIo->Mem.Write (\r
                PciIo,\r
                EfiPciIoWidthUint32,\r
                NVME_BAR,\r