ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native mode

The GICv3 driver must use native mode to drive a GICv3 due to
the fact that v2 compatibility is optional in the v3 spec.
However, if v2 compatibility is implemented, it is the default
and needs to be disabled first by setting the Affinity Routing
Enable (ARE) bit.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
[added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode]
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Tested-by: Ard Biesheuvel <ard@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 75960ed8df8dd5958856a0289c5c7cf437e70ed1..ced392980102e6b2bfe6ebbc2490be1709612e89 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -69,6 +69,9 @@
   # Linux (instead of PSCI)\r
   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
 \r
+  # Define if the GICv3 controller should use the GICv2 legacy\r
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
+\r
 [PcdsFixedAtBuild.common]\r
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
 \r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
index 92f3b1d31282ad80cde0ed484da5ead3de9513bd..e554301c4b28022c805f69242cf6ee979d19abc2 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -1,7 +1,7 @@
 #/** @file\r
 #\r
 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>\r
+#  Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>\r
 #\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
@@ -54,6 +54,7 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase\r
   gArmTokenSpaceGuid.PcdGicRedistributorsBase\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\r
 \r
 [Depex]\r
   gEfiCpuArchProtocolGuid\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 7c53e39793df7f9c1c2368c587bb6e16cc1e55a6..48708e3812b4736fcd2399e05a92cab02f532555 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -186,7 +186,7 @@ ArmGicEnableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     // Write set-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -219,7 +219,7 @@ ArmGicDisableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     // Write clear-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -252,7 +252,7 @@ ArmGicIsInterruptEnabled (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
   } else {\r
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index 9f466792e99617a8991d1900b61529da191802ae..2ae3fd31e8927b8995238f2a0b60cabe26f6b95a 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -47,3 +47,6 @@
 \r
 [Pcd]\r
   gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+\r
+[FeaturePcd]\r
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index 9097b37f2b8146c4f721867c7d6bd5594621991e..7d4e49e4b96fc094c647823b75097f1bbd9dac59 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -48,3 +48,6 @@
 \r
 [Pcd]\r
   gArmPlatformTokenSpaceGuid.PcdCoreCount\r
+\r
+[FeaturePcd]\r
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index e94e015e1ff098d34e625c2bad575e05cbc010a6..f3bf1910c5070d30df3c0e7aaacfcd54261a8440 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -249,6 +249,14 @@ GicV3DxeInitialize (
   mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);\r
   mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
 \r
+  //\r
+  // We will be driving this GIC in native v3 mode, i.e., with Affinity\r
+  // Routing enabled. So ensure that the ARE bit is set.\r
+  //\r
+  if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
+    MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);\r
+  }\r
+\r
   for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r
 \r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 2ab99772d1e1a88ca18c8f732aa6b75d13b1e585..e2a4818c4c0c62fd74aff9bba8df91222a21cde4 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -53,6 +53,9 @@ typedef enum {
 // GICv3 specific registers\r
 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
 \r
+// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
+#define ARM_GIC_ICDDCR_ARE      (1 << 4)\r
+\r
 //\r
 // GIC Redistributor\r
 //\r