UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
authorRay Ni <ray.ni@intel.com>
Mon, 8 Apr 2019 07:32:00 +0000 (15:32 +0800)
committerRay Ni <ray.ni@intel.com>
Tue, 9 Apr 2019 01:12:22 +0000 (09:12 +0800)
Reserved6 is changed to Reserved7 because the bit width is changed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UefiCpuPkg/Include/Register/Cpuid.h

index e0f4f96..a67f2a1 100644 (file)
@@ -1506,8 +1506,11 @@ typedef union {
     /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
     ///\r
     UINT32  AVX512_VPOPCNTDQ:1;\r
-    UINT32  Reserved6:2;\r
-\r
+    UINT32  Reserved7:1;\r
+    ///\r
+    /// [Bits 16] Supports 5-level paging if 1.\r
+    ///\r
+    UINT32  FiveLevelPage:1;\r
     ///\r
     /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
     /// in 64-bit mode.\r