UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging

Reserved6 is changed to Reserved7 because the bit width is changed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index e0f4f968f4b6f59dd444cdde0652c4a2c0b37d48..a67f2a1dff169d99c0df24a62800a21f9eec4d6d 100644 (file)
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -1506,8 +1506,11 @@ typedef union {
     /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
     ///\r
     UINT32  AVX512_VPOPCNTDQ:1;\r
     /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
     ///\r
     UINT32  AVX512_VPOPCNTDQ:1;\r

-    UINT32  Reserved6:2;\r
-\r
+    UINT32  Reserved7:1;\r
+    ///\r
+    /// [Bits 16] Supports 5-level paging if 1.\r
+    ///\r
+    UINT32  FiveLevelPage:1;\r

     ///\r
     /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
     /// in 64-bit mode.\r
     ///\r
     /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
     /// in 64-bit mode.\r