ArmPkg: correct TTBR1_EL1 settings in TCR_EL1

As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure
it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since
reset.

Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU
may make page table walks via TTBR1_EL1 at any time, potentially using
UNKNOWN values. This can result in a number of potential problems (e.g.
the CPU may load from MMIO registers as part of a page table walk).

Additionally, in the presence of Cortex-A57 erratum #822227, we must
program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value
of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a
hypervisor which makes use of PAR_EL1.

This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above
to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any
CPU capable of running EDK2 must support this granule, and given
TCR_EL1.EPD1, programming the field is not detrimental in the absence of
the erratum.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 3c3df6d9835cd9610c989232855faf68f29a38a4..f660e65aac332659802d77889a91392abd0599aa 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -108,6 +108,7 @@
 #define TCR_PS_256TB                            (5 << 16)\r
 \r
 #define TCR_TG0_4KB                             (0 << 14)\r
+#define TCR_TG1_4KB                             (2 << 30)\r
 \r
 #define TCR_IPS_4GB                             (0ULL << 32)\r
 #define TCR_IPS_64GB                            (1ULL << 32)\r
@@ -116,6 +117,7 @@
 #define TCR_IPS_16TB                            (4ULL << 32)\r
 #define TCR_IPS_256TB                           (5ULL << 32)\r
 \r
+#define TCR_EPD1                                (1 << 23)\r
 \r
 #define TTBR_ASID_FIELD                      (48)\r
 #define TTBR_ASID_MASK                       (0xFF << TTBR_ASID_FIELD)\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 377a7858d43616453dd66d5a2e6744839807f5a7..f967a6478840c99aaa4401b7ec99ac67eb1bb801 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -628,7 +628,8 @@ ArmConfigureMmu (
       return RETURN_UNSUPPORTED;\r
     }\r
   } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
-    TCR = T0SZ | TCR_TG0_4KB;\r
+    // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r
+    TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;\r
 \r
     // Set the Physical Address Size using MaxAddress\r
     if (MaxAddress < SIZE_4GB) {\r