Add code to protect the whole BIOS region on SPI flash, except UEFI Variable region.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17618 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
index 760b8b00b47e53eebf9d7f66c2a24a88ea39c5e7..dba84fb6596785265c5c3494685689989f7fcc10 100644 (file)
--- a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
+++ b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
@@ -353,12 +353,23 @@ SpiBiosProtectionFunction(
 {\r
 \r
   UINTN                             mPciD31F0RegBase;\r
-  UINTN                             BiosFlaLower = 0;\r
-  UINTN                             BiosFlaLimit = 0x7fffff;\r
-\r
-  BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r
+  UINTN                             BiosFlaLower0;\r
+  UINTN                             BiosFlaLimit0;\r
+  UINTN                             BiosFlaLower1;\r
+  UINTN                             BiosFlaLimit1;  \r
+  \r
 \r
+  BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r
+  BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;  \r
+  #ifdef MINNOW2_FSP_BUILD\r
+  BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);\r
+  BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;\r
+  #else\r
+  BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);\r
+  BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;\r
+  #endif\r
 \r
+  \r
   mPciD31F0RegBase = MmPciAddress (0,\r
                          DEFAULT_PCI_BUS_NUMBER_PCH,\r
                          PCI_DEVICE_NUMBER_PCH_LPC,\r
@@ -391,7 +402,7 @@ SpiBiosProtectionFunction(
   //\r
   MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),\r
     B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\\r
-    (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));\r
+    (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));\r
 \r
   //\r
   //Lock down PR0\r
@@ -405,6 +416,25 @@ SpiBiosProtectionFunction(
     DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));\r
   }\r
 \r
+  //\r
+  //Set PR1\r
+  //\r
+\r
+  MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),\r
+    B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\\r
+    (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));\r
+\r
+  //\r
+  //Lock down PR1\r
+  //\r
+  MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));\r
+\r
+  //\r
+  // Verify if it's really locked.\r
+  //\r
+  if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {\r
+    DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));\r
+  }\r
   return;\r
 \r
 }\r
@@ -690,7 +720,7 @@ InitializePlatform (
              &mReadyToBootEvent\r
              );\r
   //\r
-  // Create a ReadyToBoot Event to run enable PR0 and lock down\r
+  // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region\r
   //\r
   if(mSystemConfiguration.SpiRwProtect==1) {\r
     Status = EfiCreateEventReadyToBootEx (\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
index daf6d70184aeea53a628647d9d962fba65b25f2a..27216b7879081a92f422ceb76d8565158115db42 100644 (file)
--- a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
@@ -62,6 +62,7 @@
   Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
   SecurityPkg/SecurityPkg.dec\r
   CryptoPkg/CryptoPkg.dec\r
+  IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
 \r
 [LibraryClasses]\r
   BaseLib\r
@@ -133,7 +134,13 @@
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
   gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress\r
   gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
+  \r
 \r
 [Depex]\r
   gEfiPciRootBridgeIoProtocolGuid     AND\r