ArmPkg/ArmLib: retrieve cache line length from CTR not CCSIDR

The stride used by the cache maintenance by MVA instructions should
be retrieved from CTR_EL0.DminLine and CTR_EL0.IminLine, whose values
reflect the actual geometry of the caches. Using CCSIDR for this purpose
violates the architecture.

Also, move the line length accessors to common code, since there is no
need to keep them separate between ARMv7 and AArch64.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18754 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
index 4bea20356fa3a5e9c7471b7f9d1debd6f2bef275..dec125f248cd2af79eb127256633c7c32282d97a 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -21,31 +21,6 @@
 #include "AArch64Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
-UINTN\r
-EFIAPI\r
-ArmDataCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-}\r
-\r
-\r
 VOID\r
 AArch64DataCacheOperation (\r
   IN  AARCH64_CACHE_OPERATION  DataCacheOperation\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
index 44edff869eaeb9ad253d4f35c41ac824ffdaef3f..b53f455bfad295825266c444fa52682ef3254361 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
@@ -20,33 +20,6 @@
 #include "ArmV7Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
-UINTN\r
-EFIAPI\r
-ArmDataCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
-  VOID\r
-  )\r
-{\r
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;\r
-\r
-  // * 4 converts to bytes\r
-  return (1 << (CCSIDR + 2)) * 4;\r
-\r
-//  return 64;\r
-}\r
-\r
-\r
 VOID\r
 ArmV7DataCacheOperation (\r
   IN  ARM_V7_CACHE_OPERATION  DataCacheOperation\r

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c
index 4febc45220a3baafff42d7e46ae0b38cd13e3dc6..ad0a265e9f597d2623ac4b9c4a8de8666a0c9705 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLib.c
+++ b/ArmPkg/Library/ArmLib/Common/ArmLib.c
@@ -70,3 +70,21 @@ ArmUnsetCpuActlrBit (
   Value &= ~Bits;\r
   ArmWriteCpuActlr (Value);\r
 }\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  return 4 << ((ArmCacheInfo () >> 16) & 0xf); // CTR_EL0.DminLine\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  return 4 << (ArmCacheInfo () & 0xf); // CTR_EL0.IminLine\r
+}\r