/** @file\r
PCI command register operations supporting functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
\r
/**\r
- Check the cpability supporting by given device.\r
+ Check the capability supporting by given device.\r
\r
@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
\r
- @retval TRUE Cpability supportted.\r
- @retval FALSE Cpability not supportted.\r
+ @retval TRUE Capability supported.\r
+ @retval FALSE Capability not supported.\r
\r
**/\r
BOOLEAN\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
UINT8 CapabilityID;\r
\r
//\r
- // To check the cpability of this device supports\r
+ // To check the capability of this device supports\r
//\r
if (!PciCapabilitySupport (PciIoDevice)) {\r
return EFI_UNSUPPORTED;\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
/** @file\r
PCI command register operations supporting functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
);\r
\r
/**\r
- Check the cpability supporting by given device.\r
+ Check the capability supporting by given device.\r
\r
@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r
\r
- @retval TRUE Cpability supportted.\r
- @retval FALSE Cpability not supportted.\r
+ @retval TRUE Capability supported.\r
+ @retval FALSE Capability not supported.\r
\r
**/\r
BOOLEAN\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
@param Offset A pointer to the offset returned.\r
@param NextRegBlock A pointer to the next block returned.\r
\r
- @retval EFI_SUCCESS Successfuly located capability register block.\r
+ @retval EFI_SUCCESS Successfully located capability register block.\r
@retval EFI_UNSUPPORTED Pci device does not support capability.\r
@retval EFI_NOT_FOUND Pci device support but can not find register block.\r
\r
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**\r
- Macro that disalbes command register.\r
+ Macro that disables command register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The disabled value written into command register.\r
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**\r
- Macro that disalbes PCI bridge control register.\r
+ Macro that disables PCI bridge control register.\r
\r
@param a[in] Pointer to instance of PCI_IO_DEVICE.\r
@param b[in] The disabled value written into command register.\r
/** @file\r
- Supporting functions implementaion for PCI devices management.\r
+ Supporting functions implementation for PCI devices management.\r
\r
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>\r
}\r
\r
/**\r
- Destroy root bridge and remove it from deivce tree.\r
+ Destroy root bridge and remove it from device tree.\r
\r
@param RootBridge The bridge want to be removed.\r
\r
\r
All direct or indirect allocated resource for this node will be freed.\r
\r
- @param PciIoDevice A pointer to the PCI_IO_DEVICE to be destoried.\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE to be destroyed.\r
\r
**/\r
VOID\r
\r
@param Controller Root bridge handle.\r
\r
- @retval EFI_SUCCESS Destory all devcie nodes successfully.\r
+ @retval EFI_SUCCESS Destroy all device nodes successfully.\r
@retval EFI_NOT_FOUND Cannot find any PCI device under specified\r
root bridge.\r
\r
/**\r
Create root bridge device.\r
\r
- @param RootBridgeHandle Specified root bridge hanle.\r
+ @param RootBridgeHandle Specified root bridge handle.\r
\r
@return The crated root bridge device instance, NULL means no\r
root bridge device instance created.\r
}\r
\r
/**\r
- Judege whether Pci device existed.\r
+ Judge whether Pci device existed.\r
\r
- @param Bridge Parent bridege instance.\r
+ @param Bridge Parent bridge instance.\r
@param PciIoDevice Device instance.\r
\r
@retval TRUE Pci device existed.\r
/** @file\r
Supporting functions declaration for PCI devices management.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
);\r
\r
/**\r
- Destroy root bridge and remove it from deivce tree.\r
+ Destroy root bridge and remove it from device tree.\r
\r
@param RootBridge The bridge want to be removed.\r
\r
\r
@param Controller Root bridge handle.\r
\r
- @retval EFI_SUCCESS Destory all devcie nodes successfully.\r
+ @retval EFI_SUCCESS Destroy all device nodes successfully.\r
@retval EFI_NOT_FOUND Cannot find any PCI device under specified\r
root bridge.\r
\r
/**\r
Create root bridge device.\r
\r
- @param RootBridgeHandle Specified root bridge hanle.\r
+ @param RootBridgeHandle Specified root bridge handle.\r
\r
@return The crated root bridge device instance, NULL means no\r
root bridge device instance created.\r
\r
\r
/**\r
- Judege whether Pci device existed.\r
+ Judge whether Pci device existed.\r
\r
- @param Bridge Parent bridege instance.\r
+ @param Bridge Parent bridge instance.\r
@param PciIoDevice Device instance.\r
\r
@retval TRUE Pci device existed.\r
\r
All direct or indirect allocated resource for this node will be freed.\r
\r
- @param PciIoDevice A pointer to the PCI_IO_DEVICE to be destoried.\r
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE to be destroyed.\r
\r
**/\r
VOID\r
/** @file\r
- Functions implementation for Bus Specific Driver Override protoocl.\r
+ Functions implementation for Bus Specific Driver Override protocol.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/** @file\r
- Functions declaration for Bus Specific Driver Override protoocl.\r
+ Functions declaration for Bus Specific Driver Override protocol.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
@retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
- not enumerate this device, including its child devices if it is a PCI-to-PCI\r
- bridge.\r
+ not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+ bridge.\r
\r
**/\r
EFI_STATUS\r
/** @file\r
PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
root bridge will then be created.\r
\r
@param Bridge Parent bridge instance.\r
- @param StartBusNumber Bus number of begining.\r
+ @param StartBusNumber Bus number of beginning.\r
\r
@retval EFI_SUCCESS PCI device is found.\r
@retval other Some error occurred when reading PCI bridge information.\r
}\r
\r
/**\r
- Seach required device and create PCI device instance.\r
+ Search required device and create PCI device instance.\r
\r
@param Bridge Parent bridge instance.\r
@param Pci Input PCI device information block.\r
\r
if (Descriptor->AddrSpaceGranularity == 32) {\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {\r
Type = PciBarTypePMem32;\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Descriptor->SpecificFlag == 0) {\r
Type = PciBarTypeMem32;\r
\r
if (Descriptor->AddrSpaceGranularity == 64) {\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {\r
Type = PciBarTypePMem64;\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Descriptor->SpecificFlag == 0) {\r
Type = PciBarTypeMem64;\r
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
- // Initalize the bridge control register\r
+ // Initialize the bridge control register\r
//\r
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
\r
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
- // Initalize the bridge control register\r
+ // Initialize the bridge control register\r
//\r
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
}\r
}\r
\r
/**\r
- Create device path for pci deivce.\r
+ Create device path for pci device.\r
\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
@param PciIoDevice Pci device instance.\r
@param Command Input command register value, and\r
returned supported register value.\r
- @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ @param BridgeControl Input bridge control value for PPB or P2C, and\r
returned supported bridge control value.\r
@param OldCommand Returned and stored old command register offset.\r
@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
EFI_STATUS Status;\r
\r
//\r
- // For Root Bridge, just copy it by RootBridgeIo proctocol\r
+ // For Root Bridge, just copy it by RootBridgeIo protocol\r
// so as to keep consistent with the actual attribute\r
//\r
if (PciIoDevice->Parent == NULL) {\r
return Status;\r
}\r
//\r
- // Detect Fast Bact to Bact support for the device under the bridge\r
+ // Detect Fast Back to Back support for the device under the bridge\r
//\r
Status = GetFastBackToBackSupport (Temp, PCI_PRIMARY_STATUS_OFFSET);\r
if (FastB2BSupport && EFI_ERROR (Status)) {\r
}\r
\r
//\r
- // Fix the length to support some spefic 64 bit BAR\r
+ // Fix the length to support some special 64 bit BAR\r
//\r
Value |= ((UINT32) -1 << HighBitSet32 (Value));\r
\r
\r
}\r
//\r
- // Workaround. Some platforms inplement IO bar with 0 length\r
+ // Workaround. Some platforms implement IO bar with 0 length\r
// Need to treat it as no-bar\r
//\r
if (PciIoDevice->PciBar[BarIndex].Length == 0) {\r
}\r
\r
//\r
- // Fix the length to support some spefic 64 bit BAR\r
+ // Fix the length to support some special 64 bit BAR\r
//\r
if (Value == 0) {\r
DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));\r
//\r
// Put all the resource apertures\r
// Resource base is set to all ones so as to indicate its resource\r
- // has not been alloacted\r
+ // has not been allocated\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
\r
/**\r
- Create and initiliaze general PCI I/O device instance for\r
+ Create and initialize general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
\r
- @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Bridge Parent bridge instance.\r
@param Pci Input Pci information block.\r
@param Bus Device Bus NO.\r
@param Device Device device NO.\r
}\r
\r
//\r
- // Record the root bridgeio protocol\r
+ // Record the root bridge-io protocol\r
//\r
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
\r
} else {\r
\r
//\r
- // If unsuccessly, destroy the entire node\r
+ // If unsuccessfully, destroy the entire node\r
//\r
DestroyRootBridge (RootBridgeDev);\r
}\r
/** @file\r
- PCI emumeration support functions declaration for PCI Bus module.\r
+ PCI enumeration support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
root bridge will then be created.\r
\r
@param Bridge Parent bridge instance.\r
- @param StartBusNumber Bus number of begining.\r
+ @param StartBusNumber Bus number of beginning.\r
\r
@retval EFI_SUCCESS PCI device is found.\r
@retval other Some error occurred when reading PCI bridge information.\r
);\r
\r
/**\r
- Seach required device and create PCI device instance.\r
+ Search required device and create PCI device instance.\r
\r
@param Bridge Parent bridge instance.\r
@param Pci Input PCI device information block.\r
);\r
\r
/**\r
- Create device path for pci deivce.\r
+ Create device path for pci device.\r
\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
\r
- @return device path protocol instance for specific pci device.\r
+ @return Device path protocol instance for specific pci device.\r
\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
@param PciIoDevice Pci device instance.\r
@param Command Input command register value, and\r
returned supported register value.\r
- @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ @param BridgeControl Input bridge control value for PPB or P2C, and\r
returned supported bridge control value.\r
@param OldCommand Returned and stored old command register offset.\r
@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
);\r
\r
/**\r
- Create and initiliaze general PCI I/O device instance for\r
+ Create and initialize general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
\r
@param Bridge Parent bridge instance.\r
/** @file\r
PCI Hot Plug support functions implementation for PCI Bus module..\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
\r
/**\r
- Compare two device pathes to check if they are exactly same.\r
+ Compare two device paths to check if they are exactly same.\r
\r
@param DevicePath1 A pointer to the first device path data structure.\r
@param DevicePath2 A pointer to the second device path data structure.\r
private data structure.\r
\r
@retval EFI_SUCCESS They are same.\r
- @retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.\r
+ @retval EFI_UNSUPPORTED No PCI Hot Plug controller on the platform.\r
@retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private\r
data structure.\r
\r
\r
@param HpbDevicePath A pointer to device path data structure to be tested.\r
@param HpIndex If HpIndex is not NULL, return the index of root hot\r
- plug in global array when TRUE is retuned.\r
+ plug in global array when TRUE is returned.\r
\r
@retval TRUE The device path is for root pci hot plug bus.\r
@retval FALSE The device path is not for root pci hot plug bus.\r
\r
@param HpcDevicePath A pointer to device path data structure to be tested.\r
@param HpIndex If HpIndex is not NULL, return the index of root hot\r
- plug in global array when TRUE is retuned.\r
+ plug in global array when TRUE is returned.\r
\r
@retval TRUE The device path is for root pci hot plug controller.\r
@retval FALSE The device path is not for root pci hot plug controller.\r
Creating event object for PCI Hot Plug controller.\r
\r
@param HpIndex Index of hot plug device in global array.\r
- @param Event The retuned event that invoke this function.\r
+ @param Event The returned event that invoke this function.\r
\r
- @return Status of create event invoken.\r
+ @return Status of create event.\r
\r
**/\r
EFI_STATUS\r
\r
@param[in] PciIoDevice The device being checked.\r
\r
- @retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.\r
+ @retval TRUE PciIoDevice is a PCIe port that accepts a hot-plugged device.\r
@retval FALSE Otherwise.\r
\r
**/\r
/** @file\r
PCI Hot Plug support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
} ROOT_HPC_DATA;\r
\r
//\r
-// Reference of some global variabes\r
+// Reference of some global variables\r
//\r
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;\r
extern EFI_HPC_LOCATION *gPciRootHpcPool;\r
);\r
\r
/**\r
- Compare two device pathes to check if they are exactly same.\r
+ Compare two device paths to check if they are exactly same.\r
\r
@param DevicePath1 A pointer to the first device path data structure.\r
@param DevicePath2 A pointer to the second device path data structure.\r
private data structure.\r
\r
@retval EFI_SUCCESS They are same.\r
- @retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.\r
+ @retval EFI_UNSUPPORTED No PCI Hot Plug controller on the platform.\r
@retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private\r
data structure.\r
\r
\r
@param HpbDevicePath A pointer to device path data structure to be tested.\r
@param HpIndex If HpIndex is not NULL, return the index of root hot\r
- plug in global array when TRUE is retuned.\r
+ plug in global array when TRUE is returned.\r
\r
@retval TRUE The device path is for root pci hot plug bus.\r
@retval FALSE The device path is not for root pci hot plug bus.\r
\r
@param HpcDevicePath A pointer to device path data structure to be tested.\r
@param HpIndex If HpIndex is not NULL, return the index of root hot\r
- plug in global array when TRUE is retuned.\r
+ plug in global array when TRUE is returned.\r
\r
@retval TRUE The device path is for root pci hot plug controller.\r
@retval FALSE The device path is not for root pci hot plug controller.\r
Creating event object for PCI Hot Plug controller.\r
\r
@param HpIndex Index of hot plug device in global array.\r
- @param Event The retuned event that invoke this function.\r
+ @param Event The returned event that invoke this function.\r
\r
- @return Status of create event invoken.\r
+ @return Status of create event.\r
\r
**/\r
EFI_STATUS\r
\r
@param[in] PciIoDevice The device being checked.\r
\r
- @retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.\r
+ @retval TRUE PciIoDevice is a PCIe port that accepts a hot-plugged device.\r
@retval FALSE Otherwise.\r
\r
**/\r
/** @file\r
EFI PCI IO protocol functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param Operation Set or Disable.\r
\r
@retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
- @retval EFI_SUCCESS Successfully set new attributs.\r
+ @retval EFI_SUCCESS Successfully set new attributes.\r
\r
**/\r
EFI_STATUS\r
\r
if (Temp == NULL) {\r
//\r
- // If there is no VGA device on the segement, set\r
+ // If there is no VGA device on the segment, set\r
// this graphics card to decode the palette range\r
//\r
return EFI_SUCCESS;\r
//\r
// Just a trick for ENABLE attribute\r
// EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r
- // So, this logic doesn't confrom to UEFI spec, which should be removed.\r
+ // So, this logic doesn't conform to UEFI spec, which should be removed.\r
// But this trick logic is still kept for some binary drivers that depend on it.\r
//\r
if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r
Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
}\r
//\r
- // The upstream bridge should be also set to revelant attribute\r
+ // The upstream bridge should be also set to relevant attribute\r
// expect for IO, Mem and BusMaster\r
//\r
UpStreamAttributes = Attributes &\r
\r
case PciBarTypePMem32:\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
\r
case PciBarTypePMem64:\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
return EFI_UNSUPPORTED;\r
}\r
//\r
- // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and\r
+ // Attributes must be supported. Make sure the BAR range described by BarIndex, Offset, and\r
// Length are valid for this PCI device.\r
//\r
NonRelativeOffset = *Offset;\r
/** @file\r
EFI PCI IO protocol functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param Operation Set or Disable.\r
\r
@retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
- @retval EFI_SUCCESS Successfully set new attributs.\r
+ @retval EFI_SUCCESS Successfully set new attributes.\r
\r
**/\r
EFI_STATUS\r
/** @file\r
PCI Rom supporting funtions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// Programe all upstream bridge\r
//\r
- ProgrameUpstreamBridgeForRom(PciDevice, RomBar, TRUE);\r
+ ProgramUpstreamBridgeForRom (PciDevice, RomBar, TRUE);\r
\r
//\r
// Setting the memory space bit in the function's command register\r
//\r
// Destroy the programmed bar in all the upstream bridge.\r
//\r
- ProgrameUpstreamBridgeForRom(PciDevice, RomBar, FALSE);\r
+ ProgramUpstreamBridgeForRom (PciDevice, RomBar, FALSE);\r
\r
//\r
// disable rom decode\r
/** @file\r
- PCI Rom supporting funtions declaration for PCI Bus module.\r
+ PCI Rom supporting functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/** @file\r
- Power management support fucntions implementation for PCI Bus module.\r
+ Power management support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/** @file\r
- Power management support fucntions delaration for PCI Bus module.\r
+ Power management support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/** @file\r
- PCI resouces support functions implemntation for PCI Bus module.\r
+ PCI resources support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
/**\r
This routine is used to merge two different resource trees in need of\r
- resoure degradation.\r
+ resource degradation.\r
\r
For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
- to merge prefectchable memory resource list into normal memory list.\r
+ to merge prefetchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
This function is used to calculate the resource aperture\r
for a given bridge device.\r
\r
- @param Bridge PCI resouce node for given bridge device.\r
+ @param Bridge PCI resource node for given bridge device.\r
\r
**/\r
VOID\r
}\r
\r
/**\r
- Get IO/Memory resource infor for given PCI device.\r
+ Get IO/Memory resource info for given PCI device.\r
\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO .\r
);\r
\r
//\r
- // Recursively create resouce map on this bridge\r
+ // Recursively create resource map on this bridge\r
//\r
CreateResourceMap (\r
Temp,\r
This function is used to program the resource allocated\r
for each resource node under specified bridge.\r
\r
- @param Base Base address of resource to be progammed.\r
+ @param Base Base address of resource to be programmed.\r
@param Bridge PCI resource node for the bridge device.\r
\r
- @retval EFI_SUCCESS Successfully to program all resouces\r
+ @retval EFI_SUCCESS Successfully to program all resources\r
on given PCI bridge device.\r
@retval EFI_OUT_OF_RESOURCES Base is all one.\r
\r
/**\r
Program Bar register for PCI device.\r
\r
- @param Base Base address for PCI device resource to be progammed.\r
- @param Node Point to resoure node structure.\r
+ @param Base Base address for PCI device resource to be programmed.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
VOID\r
/**\r
Program IOV VF Bar register for PCI device.\r
\r
- @param Base Base address for PCI device resource to be progammed.\r
- @param Node Point to resoure node structure.\r
+ @param Base Base address for PCI device resource to be programmed.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
EFI_STATUS\r
}\r
\r
/**\r
- Program PCI-PCI bridge apperture.\r
+ Program PCI-PCI bridge aperture.\r
\r
@param Base Base address for resource.\r
- @param Node Point to resoure node structure.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
VOID\r
Address = 0;\r
//\r
// If no device resource of this PPB, return anyway\r
- // Apperture is set default in the initialization code\r
+ // Aperture is set default in the initialization code\r
//\r
if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
//\r
/**\r
Program parent bridge for Option Rom.\r
\r
- @param PciDevice Pci deivce instance.\r
- @param OptionRomBase Base address for Optiona Rom.\r
+ @param PciDevice Pci device instance.\r
+ @param OptionRomBase Base address for Option Rom.\r
@param Enable Enable or disable PCI memory.\r
\r
**/\r
VOID\r
-ProgrameUpstreamBridgeForRom (\r
+ProgramUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
IN BOOLEAN Enable\r
Node.Offset = 0;\r
\r
//\r
- // Program PPB to only open a single <= 16MB apperture\r
+ // Program PPB to only open a single <= 16MB aperture\r
//\r
if (Enable) {\r
//\r
}\r
\r
/**\r
- Destory given resource tree.\r
+ Destroy given resource tree.\r
\r
@param Bridge PCI resource root node of resource tree.\r
\r
\r
//\r
// Memory Base/Limit Register 0\r
- // Bar 1 denodes memory range 0\r
+ // Bar 1 decodes memory range 0\r
//\r
Node = CreateResourceNode (\r
PciDev,\r
\r
//\r
// Memory Base/Limit Register 1\r
- // Bar 2 denodes memory range1\r
+ // Bar 2 decodes memory range1\r
//\r
Node = CreateResourceNode (\r
PciDev,\r
\r
//\r
// Io Base/Limit\r
- // Bar 3 denodes io range 0\r
+ // Bar 3 decodes io range 0\r
//\r
Node = CreateResourceNode (\r
PciDev,\r
\r
//\r
// Io Base/Limit\r
- // Bar 4 denodes io range 0\r
+ // Bar 4 decodes io range 0\r
//\r
Node = CreateResourceNode (\r
PciDev,\r
\r
} else {\r
//\r
- // Set pre-fetchable bit\r
+ // Set prefetchable bit\r
//\r
PciIo->Pci.Read (\r
PciIo,\r
} else {\r
\r
//\r
- // Set pre-fetchable bit\r
+ // Set prefetchable bit\r
//\r
PciIo->Pci.Read (\r
PciIo,\r
if (Ptr->AddrSpaceGranularity == 32) {\r
\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
if (Ptr->AddrLen != 0) {\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
if (Ptr->AddrLen != 0) {\r
if (Ptr->AddrSpaceGranularity == 64) {\r
\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
if (Ptr->AddrLen != 0) {\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
if (Ptr->AddrLen != 0) {\r
/** @file\r
- PCI resouces support functions declaration for PCI Bus module.\r
+ PCI resources support functions declaration for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
/**\r
This routine is used to merge two different resource trees in need of\r
- resoure degradation.\r
+ resource degradation.\r
\r
For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
- to merge prefectchable memory resource list into normal memory list.\r
+ to merge prefetchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
This function is used to calculate the resource aperture\r
for a given bridge device.\r
\r
- @param Bridge PCI resouce node for given bridge device.\r
+ @param Bridge PCI resource node for given bridge device.\r
\r
**/\r
VOID\r
);\r
\r
/**\r
- Get IO/Memory resource infor for given PCI device.\r
+ Get IO/Memory resource info for given PCI device.\r
\r
@param PciDev Pci device instance.\r
@param IoNode Resource info node for IO .\r
);\r
\r
/**\r
- This function is used to extract resource request from\r
- IOV VF device node list.\r
+ This function is used to create a IOV VF resource node.\r
\r
@param PciDev Pci device instance.\r
@param Length Length of Io/Memory resource.\r
@param ResType Type of resource: IO/Memory.\r
@param ResUsage Resource usage.\r
\r
- @return PCI resource node created for given PCI device.\r
+ @return PCI resource node created for given VF PCI device.\r
NULL means PCI resource node is not created.\r
\r
**/\r
This function is used to program the resource allocated\r
for each resource node under specified bridge.\r
\r
- @param Base Base address of resource to be progammed.\r
+ @param Base Base address of resource to be programmed.\r
@param Bridge PCI resource node for the bridge device.\r
\r
- @retval EFI_SUCCESS Successfully to program all resouces\r
+ @retval EFI_SUCCESS Successfully to program all resources\r
on given PCI bridge device.\r
@retval EFI_OUT_OF_RESOURCES Base is all one.\r
\r
/**\r
Program Bar register for PCI device.\r
\r
- @param Base Base address for PCI device resource to be progammed.\r
- @param Node Point to resoure node structure.\r
+ @param Base Base address for PCI device resource to be programmed.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
VOID\r
/**\r
Program IOV VF Bar register for PCI device.\r
\r
- @param Base Base address for PCI device resource to be progammed.\r
- @param Node Point to resoure node structure.\r
+ @param Base Base address for PCI device resource to be programmed.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
EFI_STATUS\r
);\r
\r
/**\r
- Program PCI-PCI bridge apperture.\r
+ Program PCI-PCI bridge aperture.\r
\r
@param Base Base address for resource.\r
- @param Node Point to resoure node structure.\r
+ @param Node Point to resource node structure.\r
\r
**/\r
VOID\r
/**\r
Program parent bridge for Option Rom.\r
\r
- @param PciDevice Pci deivce instance.\r
- @param OptionRomBase Base address for Optiona Rom.\r
+ @param PciDevice Pci device instance.\r
+ @param OptionRomBase Base address for Option Rom.\r
@param Enable Enable or disable PCI memory.\r
\r
**/\r
VOID\r
-ProgrameUpstreamBridgeForRom (\r
+ProgramUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
IN BOOLEAN Enable\r
);\r
\r
/**\r
- Destory given resource tree.\r
+ Destroy given resource tree.\r
\r
@param Bridge PCI resource root node of resource tree.\r
\r
/** @file\r
Set up ROM Table for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param Bus Bus NO of PCI space.\r
@param Dev Dev NO of PCI space.\r
@param Func Func NO of PCI space.\r
- @param RomImage Option ROM buffer.\r
- @param RomSize Size of Option ROM buffer.\r
-\r
+ @param RomImage Option Rom buffer.\r
+ @param RomSize Size of Option Rom buffer.\r
**/\r
VOID\r
PciRomAddImageMapping (\r
projects / mirror_edk2.git / commitdiff