From: Star Zeng <star.zeng@intel.com>
Date: Thu, 24 Aug 2017 09:42:49 +0000 (+0800)
Subject: MdeModulePkg XhciDxe: Fix Map and Unmap inconsistency
X-Git-Tag: edk2-stable201903~3577
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=0b9c0c65400262ee41eb8f4f4d9079fab4777437

MdeModulePkg XhciDxe: Fix Map and Unmap inconsistency

We found there are loops of *2* Maps and only *1* Unmap and
the DMA buffer address is decreasing.

It is caused by the below code flow.
XhcAsyncInterruptTransfer ->
  XhcCreateUrb ->
    XhcCreateTransferTrb ->
      Map Urb->DataMap           (1)

Timer: loops of *2* Maps and only *1* Unmap
XhcMonitorAsyncRequests ->
  XhcFlushAsyncIntMap ->
    Unmap and Map Urb->DataMap   (2)
  XhcUpdateAsyncRequest ->
    XhcCreateTransferTrb ->
      Map Urb->DataMap           (3)

This patch is to eliminate (3).

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
---

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 6013d7620f..21fdcf130a 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -259,8 +259,11 @@ XhcCreateTransferTrb (
   } else {
     EPType  = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
   }
-  
-  if (Urb->Data != NULL) {
+
+  //
+  // No need to remap.
+  //
+  if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
     if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
       MapOp = EfiPciIoOperationBusMasterWrite;
     } else {