From: Ruiyu Ni <ruiyu.ni@intel.com>
Date: Tue, 6 Feb 2018 07:26:41 +0000 (+0800)
Subject: UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling
X-Git-Tag: edk2-stable201903~2430
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=0c8b88022372846a377c424f46e671d8868d4ece

UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling

Today's implementation only assumes SandyBridge CPU supports
Extended On-Demand Clock Modulation Duty Cycle.
Actually it is supported when CPUID.06h.EAX[5] == 1.

When platform requests 50% throttling, it causes value 1000b
set to the low-4 bits of IA32_CLOCK_MODULATION.
But the wrong code sets 1000b to bits[1-3] which causes assertion.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
---

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
index 56e53561e9..84d59de78f 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
@@ -1,7 +1,7 @@
 /** @file
   Clock Modulation feature.
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -67,40 +67,34 @@ ClockModulationInitialize (
   IN BOOLEAN                           State
   )
 {
-  if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
-    CPU_REGISTER_TABLE_WRITE_FIELD (
-      ProcessorNumber,
-      Msr,
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION,
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER,
-      Bits.OnDemandClockModulationDutyCycle,
-      PcdGet8 (PcdCpuClockModulationDutyCycle)
-      );
-    CPU_REGISTER_TABLE_WRITE_FIELD (
-      ProcessorNumber,
-      Msr,
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION,
-      MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER,
-      Bits.OnDemandClockModulationEnable,
-      (State) ? 1 : 0
-      );
-  } else {
-    CPU_REGISTER_TABLE_WRITE_FIELD (
-      ProcessorNumber,
-      Msr,
-      MSR_IA32_CLOCK_MODULATION,
-      MSR_IA32_CLOCK_MODULATION_REGISTER,
-      Bits.OnDemandClockModulationDutyCycle,
-      PcdGet8 (PcdCpuClockModulationDutyCycle)
-      );
+  CPUID_THERMAL_POWER_MANAGEMENT_EAX   ThermalPowerManagementEax;
+  AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &ThermalPowerManagementEax.Uint32, NULL, NULL, NULL);
+
+  CPU_REGISTER_TABLE_WRITE_FIELD (
+    ProcessorNumber,
+    Msr,
+    MSR_IA32_CLOCK_MODULATION,
+    MSR_IA32_CLOCK_MODULATION_REGISTER,
+    Bits.OnDemandClockModulationDutyCycle,
+    PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1
+    );
+  if (ThermalPowerManagementEax.Bits.ECMD == 1) {
     CPU_REGISTER_TABLE_WRITE_FIELD (
       ProcessorNumber,
       Msr,
       MSR_IA32_CLOCK_MODULATION,
       MSR_IA32_CLOCK_MODULATION_REGISTER,
-      Bits.OnDemandClockModulationEnable,
-      (State) ? 1 : 0
+      Bits.ExtendedOnDemandClockModulationDutyCycle,
+      PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0
       );
   }
+  CPU_REGISTER_TABLE_WRITE_FIELD (
+    ProcessorNumber,
+    Msr,
+    MSR_IA32_CLOCK_MODULATION,
+    MSR_IA32_CLOCK_MODULATION_REGISTER,
+    Bits.OnDemandClockModulationEnable,
+    (State) ? 1 : 0
+    );
   return RETURN_SUCCESS;
 }