From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Thu, 2 Mar 2017 10:36:14 +0000 (+0000)
Subject: ArmPkg/CpuDxe ARM: avoid unnecessary cache/TLB maintenance
X-Git-Tag: edk2-stable201903~4460
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=22c7a5b70e220f681f10a0bb70fc0d76775f1b8e;hp=22c7a5b70e220f681f10a0bb70fc0d76775f1b8e

ArmPkg/CpuDxe ARM: avoid unnecessary cache/TLB maintenance

Page and section entries in the page tables are updated using the
helper ArmUpdateTranslationTableEntry(), which cleans the page
table entry to the PoC, and invalidates the TLB entry covering
the page described by the entry being updated.

Since we may be updating section entries, we might be leaving stale
TLB entries at this point (for all pages in the section except the
first one), which will be invalidated wholesale at the end of
SetMemoryAttributes(). At that point, all caches are cleaned *and*
invalidated as well.

This cache maintenance is costly and unnecessary. The TLB maintenance
is only necessary if we updated any section entries, since any page
by page entries that have been updated will have been invalidated
individually by ArmUpdateTranslationTableEntry().

So drop the clean/invalidate of the caches, and only perform the
full TLB flush if UpdateSectionEntries() was called, or if sections
were split by UpdatePageEntries(). Finally, make the cache maintenance
on the remapped regions themselves conditional on whether any memory
type attributes were modified.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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