From: andrewfish Date: Wed, 21 Apr 2010 17:40:27 +0000 (+0000) Subject: Enable NEON (SIMD instructions) via coprocessor register so CopyMem/SetMem can use... X-Git-Tag: edk2-stable201903~15956 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=2ed3c9ccf8c056aa4df35fcd29f670ee1238fbd0 Enable NEON (SIMD instructions) via coprocessor register so CopyMem/SetMem can use VLDM and friends if you want. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10386 6f19259b-4bc3-4df7-8a09-765794883524 --- diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S index 950ba43c69..07e054732f 100644 --- a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S +++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S @@ -35,6 +35,14 @@ ASM_PFX(_ModuleEntryPoint): orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ mcr p15, 0, r0, c1, c0, 0 + + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + // Set CPU vectors to start of DRAM LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm index 033f03c684..d46ae2b0da 100644 --- a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm +++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm @@ -39,6 +39,13 @@ _ModuleEntryPoint orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ mcr p15, 0, r0, c1, c0, 0 + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + msr FPEXC,r0 + // Set CPU vectors to start of DRAM LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base mcr p15, 0, r0, c12, c0, 0