From: Ma, Maurice <maurice.ma@intel.com>
Date: Wed, 29 Apr 2015 03:50:20 +0000 (+0000)
Subject: Add dual FSP binaries support.
X-Git-Tag: edk2-stable201903~9978
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=5c7c41f81d4b89a90dadc01b3c3f4481251852a2

Add dual FSP binaries support.

There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524
---

diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf b/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
index 97e88138bd..cde101b907 100644
--- a/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
+++ b/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
@@ -81,6 +81,7 @@
 [Pcd]
   gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize       ## CONSUMES
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase                 ## CONSUMES
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase           ## CONSUMES
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize                 ## CONSUMES
   gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize               ## CONSUMES
   gFspWrapperTokenSpaceGuid.PcdFspApiVersion                  ## CONSUMES
diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
index f11015e993..35a994e960 100644
--- a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
+++ b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
@@ -261,7 +261,11 @@ PeiMemoryDiscoveredNotify (
   VOID                      *FspHobList;
   EFI_HOB_GUID_TYPE         *GuidHob;
 
-  FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
+  if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
+    FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
+  } else {
+    FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
+  }
   if (FspHeader == NULL) {
     return EFI_DEVICE_ERROR;
   }
diff --git a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
index 859b26728d..f8e8e826f1 100644
--- a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
+++ b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
@@ -120,7 +120,11 @@ FspDxeEntryPoint (
   VOID       *Registration;
   EFI_EVENT  ProtocolNotifyEvent;
 
-  mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
+  if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
+    mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
+  } else {
+    mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
+  }
   DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", mFspHeader));
   if (mFspHeader == NULL) {
     return EFI_DEVICE_ERROR;
diff --git a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
index 3b819d9bb9..8175dbd324 100644
--- a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
+++ b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
@@ -49,6 +49,7 @@
 
 [Pcd]
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase       ## CONSUMES
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize       ## CONSUMES
 
 [Depex]
diff --git a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
index bfed1cc97a..1fc8e2c484 100644
--- a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
+++ b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
@@ -59,10 +59,22 @@
   ## Provides the size of the BIOS Flash Device.
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
 
-  ## Indicates the base address of the FSP binary.
+  ## Indicates the base address of the factory FSP binary.
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003
-  ## Provides the size of the FSP binary.
+  ## Indicates the base address of the updatable FSP binary to support Dual FSP.
+  #  There could be two FSP images at different locations in a flash - 
+  #  one factory version (default) and updatable version (updatable).
+  #  TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.
+  #  FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,
+  #  FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,
+  #  PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase
+  #  is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means
+  #  there is no updatable FSP.
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008
+  ## Provides the size of the factory FSP binary.
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004
+  ## Provides the size of the updatable FSP binary to support Dual FSP.
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009
 
   ## Indicates the base address of the first Microcode Patch in the Microcode Region
   gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005