From: Jeff Fan <jeff.fan@intel.com>
Date: Tue, 6 Sep 2016 10:50:14 +0000 (+0800)
Subject: UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment
X-Git-Tag: edk2-stable201903~5826
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=634429c0aafd2f3032c730bd4fc813e96024e6d2

UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
---

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index a8916b4a44..62c5b7eba7 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
   @endcode
+  @note MSR_PENTIUM_TSC is defined as TSC in SDM.
 **/
 #define MSR_PENTIUM_TSC                          0x00000010
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
   @endcode
+  @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 **/
 #define MSR_PENTIUM_CESR                         0x00000011
 
@@ -112,6 +116,8 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
   @endcode
+  @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
+        MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
   @{
 **/
 #define MSR_PENTIUM_CTR0                         0x00000012