From: lgao4 Date: Tue, 9 Dec 2008 14:04:41 +0000 (+0000) Subject: Add the detailed descriptions for the structure data member in these protocol. X-Git-Tag: edk2-stable201903~19311 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=992f22b99a90d1b217b1e6f702b238f1ff319753 Add the detailed descriptions for the structure data member in these protocol. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6935 6f19259b-4bc3-4df7-8a09-765794883524 --- diff --git a/MdePkg/Include/Guid/DebugImageInfoTable.h b/MdePkg/Include/Guid/DebugImageInfoTable.h index 4404ace03b..19003f958a 100644 --- a/MdePkg/Include/Guid/DebugImageInfoTable.h +++ b/MdePkg/Include/Guid/DebugImageInfoTable.h @@ -34,9 +34,9 @@ #define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01 typedef struct { - UINT64 Signature; /// A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE - EFI_PHYSICAL_ADDRESS EfiSystemTableBase; /// The physical address of the EFI system table. - UINT32 Crc32; /// A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid. + UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE + EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table. + UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid. } EFI_SYSTEM_TABLE_POINTER; typedef struct { diff --git a/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h b/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h index b9c2d4d4a5..20f798328d 100644 --- a/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h +++ b/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h @@ -17,25 +17,20 @@ #ifndef __FILE_SYSTEM_VOLUME_LABEL_INFO_H__ #define __FILE_SYSTEM_VOLUME_LABEL_INFO_H__ -#define EFI_FILE_SYSTEM_VOLUME_LABEL_INFO_ID_GUID \ +#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \ { \ 0xDB47D7D3, 0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \ } -#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \ - EFI_FILE_SYSTEM_VOLUME_LABEL_INFO_ID_GUID - typedef struct { /// /// The Null-terminated string that is the volume's label. /// CHAR16 VolumeLabel[1]; -} EFI_FILE_SYSTEM_VOLUME_LABEL_INFO; - -typedef EFI_FILE_SYSTEM_VOLUME_LABEL_INFO EFI_FILE_SYSTEM_VOLUME_LABEL; +} EFI_FILE_SYSTEM_VOLUME_LABEL; -#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL_INFO \ - EFI_FIELD_OFFSET (EFI_FILE_SYSTEM_VOLUME_LABEL_INFO, VolumeLabel) +#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \ + EFI_FIELD_OFFSET (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel) extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid; diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/IndustryStandard/Pal.h index b726201f9c..e377587759 100644 --- a/MdePkg/Include/IndustryStandard/Pal.h +++ b/MdePkg/Include/IndustryStandard/Pal.h @@ -287,25 +287,25 @@ typedef struct { #define PAL_CACHE_PROT_INFO 38 typedef struct { - UINT64 ThreadId : 16; /// The thread identifier of the logical - /// processor for which information is being - /// returned. This value will be unique on a per core basis. + UINT64 ThreadId : 16; ///< The thread identifier of the logical + ///< processor for which information is being + ///< returned. This value will be unique on a per core basis. UINT64 Reserved1: 16; - UINT64 CoreId: 16; /// The core identifier of the logical processor - /// for which information is being returned. - /// This value will be unique on a per physical - /// processor package basis. + UINT64 CoreId: 16; ///< The core identifier of the logical processor + ///< for which information is being returned. + ///< This value will be unique on a per physical + ///< processor package basis. UINT64 Reserved2: 16; } PAL_PCOC_N_CACHE_INFO1; typedef struct { - UINT64 LogicalAddress : 16; /// Logical address: geographical address - /// of the logical processor for which - /// information is being returned. This is - /// the same value that is returned by the - /// PAL_FIXED_ADDR procedure when it is - /// called on the logical processor. + UINT64 LogicalAddress : 16; ///< Logical address: geographical address + ///< of the logical processor for which + ///< information is being returned. This is + ///< the same value that is returned by the + ///< PAL_FIXED_ADDR procedure when it is + ///< called on the logical processor. UINT64 Reserved1: 16; UINT64 Reserved2: 32; } PAL_PCOC_N_CACHE_INFO2; @@ -481,26 +481,26 @@ typedef struct { #define PAL_PTCE_INFO 6 typedef struct { - UINT64 NumberSets:8; /// Unsigned 8-bit integer denoting the number - /// of hash sets for the specified level - /// (1=fully associative) - UINT64 NumberWays:8; /// Unsigned 8-bit integer denoting the - /// associativity of the specified level - /// (1=direct). - UINT64 NumberEntries:16; /// Unsigned 16-bit integer denoting the - /// number of entries in the specified TC. - UINT64 PageSizeIsOptimized:1; /// Flag denoting whether the - /// specified level is optimized for - /// the region's preferred page size - /// (1=optimized) tc_pages indicates - /// which page sizes are usable by - /// this translation cache. - UINT64 TcIsUnified:1; /// Flag denoting whether the specified TC is - /// unified (1=unified). - UINT64 EntriesReduction:1; /// Flag denoting whether installed - /// translation registers will reduce - /// the number of entries within the - /// specified TC. + UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number + ///< of hash sets for the specified level + ///< (1=fully associative) + UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the + ///< associativity of the specified level + ///< (1=direct). + UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the + ///< number of entries in the specified TC. + UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the + ///< specified level is optimized for + ///< the region's preferred page size + ///< (1=optimized) tc_pages indicates + ///< which page sizes are usable by + ///< this translation cache. + UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is + ///< unified (1=unified). + UINT64 EntriesReduction:1; ///< Flag denoting whether installed + ///< translation registers will reduce + ///< the number of entries within the + ///< specified TC. } PAL_TC_INFO; /** @@ -564,48 +564,48 @@ typedef struct { #define PAL_VM_PAGE_SIZE 34 typedef struct { - UINT64 WalkerPresent:1; /// 1-bit flag indicating whether a hardware - /// TLB walker is implemented (1 = walker - /// present). - UINT64 WidthOfPhysicalAddress: 7; /// Unsigned 7-bit integer - /// denoting the number of bits of - /// physical address implemented. - UINT64 WidthOfKey:8; /// Unsigned 8-bit integer denoting the number - /// of bits mplemented in the PKR.key field. - UINT64 MaxPkrIndex:8; /// Unsigned 8-bit integer denoting the - /// maximum PKR index (number of PKRs-1). - UINT64 HashTagId:8; /// Unsigned 8-bit integer which uniquely - /// identifies the processor hash and tag - /// algorithm. - UINT64 MaxDtrIndex:8; /// Unsigned 8 bit integer denoting the - /// maximum data translation register index - /// (number of dtr entries - 1). - UINT64 MaxItrIndex:8; /// Unsigned 8 bit integer denoting the - /// maximum instruction translation register - /// index (number of itr entries - 1). - UINT64 NumberOfUniqueTc:8; /// Unsigned 8-bit integer denoting the - /// number of unique TCs implemented. - /// This is a maximum of - /// 2*num_tc_levels. - UINT64 NumberOfTcLevels:8; /// Unsigned 8-bit integer denoting the - /// number of TC levels. + UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware + ///< TLB walker is implemented (1 = walker + ///< present). + UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer + ///< denoting the number of bits of + ///< physical address implemented. + UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number + ///< of bits mplemented in the PKR.key field. + UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the + ///< maximum PKR index (number of PKRs-1). + UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely + ///< identifies the processor hash and tag + ///< algorithm. + UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the + ///< maximum data translation register index + ///< (number of dtr entries - 1). + UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the + ///< maximum instruction translation register + ///< index (number of itr entries - 1). + UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the + ///< number of unique TCs implemented. + ///< This is a maximum of + ///< 2*num_tc_levels. + UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the + ///< number of TC levels. } PAL_VM_INFO1; typedef struct { - UINT64 WidthOfVirtualAddress:8; /// Unsigned 8-bit integer denoting - /// is the total number of virtual - /// address bits - 1. - UINT64 WidthOfRid:8; /// Unsigned 8-bit integer denoting the number - /// of bits implemented in the RR.rid field. - UINT64 MaxPurgedTlbs:16; /// Unsigned 16 bit integer denoting the - /// maximum number of concurrent outstanding - /// TLB purges allowed by the processor. A - /// value of 0 indicates one outstanding - /// purge allowed. A value of 216-1 - /// indicates no limit on outstanding - /// purges. All other values indicate the - /// actual number of concurrent outstanding - /// purges allowed. + UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting + ///< is the total number of virtual + ///< address bits - 1. + UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number + ///< of bits implemented in the RR.rid field. + UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the + ///< maximum number of concurrent outstanding + ///< TLB purges allowed by the processor. A + ///< value of 0 indicates one outstanding + ///< purge allowed. A value of 216-1 + ///< indicates no limit on outstanding + ///< purges. All other values indicate the + ///< actual number of concurrent outstanding + ///< purges allowed. UINT64 Reserved:32; } PAL_VM_INFO2; @@ -985,46 +985,46 @@ typedef struct { #define PAL_FREQ_RATIOS 14 typedef struct { - UINT64 NumberOfLogicalProcessors:16; /// Total number of logical - /// processors on this physical - /// processor package that are - /// enabled. - UINT64 ThreadsPerCore:8; /// Number of threads per core. + UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical + ///< processors on this physical + ///< processor package that are + ///< enabled. + UINT64 ThreadsPerCore:8; ///< Number of threads per core. UINT64 Reserved1:8; - UINT64 CoresPerProcessor; /// Total number of cores on this - /// physical processor package. + UINT64 CoresPerProcessor; ///< Total number of cores on this + ///< physical processor package. UINT64 Reserved2:8; - UINT64 PhysicalProcessorPackageId:8; /// Physical processor package - /// identifier which was - /// assigned at reset by the - /// platform or bus - /// controller. This value may - /// or may not be unique - /// across the entire platform - /// since it depends on the - /// platform vendor's policy. + UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package + ///< identifier which was + ///< assigned at reset by the + ///< platform or bus + ///< controller. This value may + ///< or may not be unique + ///< across the entire platform + ///< since it depends on the + ///< platform vendor's policy. UINT64 Reserved3:8; } PAL_LOGICAL_PROCESSPR_OVERVIEW; typedef struct { - UINT64 ThreadId:16; /// The thread identifier of the logical - /// processor for which information is being - /// returned. This value will be unique on a per - /// core basis. + UINT64 ThreadId:16; ///< The thread identifier of the logical + ///< processor for which information is being + ///< returned. This value will be unique on a per + ///< core basis. UINT64 Reserved1:16; - UINT64 CoreId:16; /// The core identifier of the logical processor - /// for which information is being returned. - /// This value will be unique on a per physical - /// processor package basis. + UINT64 CoreId:16; ///< The core identifier of the logical processor + ///< for which information is being returned. + ///< This value will be unique on a per physical + ///< processor package basis. UINT64 Reserved2:16; } PAL_LOGICAL_PROCESSORN_INFO1; typedef struct { - UINT64 LogicalAddress:16; /// Geographical address of the logical - /// processor for which information is being - /// returned. This is the same value that is - /// returned by the PAL_FIXED_ADDR procedure - /// when it is called on the logical processor. + UINT64 LogicalAddress:16; ///< Geographical address of the logical + ///< processor for which information is being + ///< returned. This is the same value that is + ///< returned by the PAL_FIXED_ADDR procedure + ///< when it is called on the logical processor. UINT64 Reserved:48; } PAL_LOGICAL_PROCESSORN_INFO2; @@ -1063,17 +1063,17 @@ typedef struct { #define PAL_LOGICAL_TO_PHYSICAL 42 typedef struct { - UINT64 NumberOfPmcPairs:8; /// Unsigned 8-bit number defining the - /// number of generic PMC/PMD pairs. - UINT64 WidthOfCounter:8; /// Unsigned 8-bit number in the range - /// 0:60 defining the number of - /// implemented counter bits. - UINT64 TypeOfCycleCounting:8; /// Unsigned 8-bit number defining the - /// event type for counting processor cycles. - UINT64 TypeOfRetiredInstructionBundle:8; /// Retired Unsigned 8-bit - /// number defining the - /// event type for retired - /// instruction bundles. + UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the + ///< number of generic PMC/PMD pairs. + UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range + ///< 0:60 defining the number of + ///< implemented counter bits. + UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the + ///< event type for counting processor cycles. + UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit + ///< number defining the + ///< event type for retired + ///< instruction bundles. UINT64 Reserved:32; } PAL_PERFORMANCE_INFO; @@ -1134,314 +1134,314 @@ typedef struct { typedef struct { UINT64 Reserved1:36; - UINT64 FaultInUndefinedIns:1; /// Bit36, No Unimplemented - /// instruction address reported as - /// fault. Denotes how the processor - /// reports the detection of - /// unimplemented instruction - /// addresses. When 1, the processor - /// reports an Unimplemented - /// Instruction Address fault on the - /// unimplemented address; when 0, it - /// reports an Unimplemented - /// Instruction Address trap on the - /// previous instruction in program - /// order. This feature may only be - /// interrogated by - /// PAL_PROC_GET_FEATURES. It may not - /// be enabled or disabled by - /// PAL_PROC_SET_FEATURES. The - /// corresponding argument is ignored. + UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented + ///< instruction address reported as + ///< fault. Denotes how the processor + ///< reports the detection of + ///< unimplemented instruction + ///< addresses. When 1, the processor + ///< reports an Unimplemented + ///< Instruction Address fault on the + ///< unimplemented address; when 0, it + ///< reports an Unimplemented + ///< Instruction Address trap on the + ///< previous instruction in program + ///< order. This feature may only be + ///< interrogated by + ///< PAL_PROC_GET_FEATURES. It may not + ///< be enabled or disabled by + ///< PAL_PROC_SET_FEATURES. The + ///< corresponding argument is ignored. - UINT64 NoPresentPmi:1; /// Bit37, No INIT, PMI, and LINT pins - /// present. Denotes the absence of INIT, - /// PMI, LINT0 and LINT1 pins on the - /// processor. When 1, the pins are absent. - /// When 0, the pins are present. This - /// feature may only be interrogated by - /// PAL_PROC_GET_FEATURES. It may not be - /// enabled or disabled by - /// PAL_PROC_SET_FEATURES. The corresponding - /// argument is ignored. + UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins + ///< present. Denotes the absence of INIT, + ///< PMI, LINT0 and LINT1 pins on the + ///< processor. When 1, the pins are absent. + ///< When 0, the pins are present. This + ///< feature may only be interrogated by + ///< PAL_PROC_GET_FEATURES. It may not be + ///< enabled or disabled by + ///< PAL_PROC_SET_FEATURES. The corresponding + ///< argument is ignored. - UINT64 NoSimpleImpInUndefinedIns:1; /// Bit38, No Simple - /// implementation of - /// unimplemented instruction - /// addresses. Denotes how an - /// unimplemented instruction - /// address is recorded in IIP - /// on an Unimplemented - /// Instruction Address trap or - /// fault. When 1, the full - /// unimplemented address is - /// recorded in IIP; when 0, the - /// address is sign extended - /// (virtual addresses) or zero - /// extended (physical - /// addresses). This feature may - /// only be interrogated by - /// PAL_PROC_GET_FEATURES. It - /// may not be enabled or - /// disabled by - /// PAL_PROC_SET_FEATURES. The - /// corresponding argument is - /// ignored. - - UINT64 NoVariablePState:1; /// Bit39, No Variable P-state - /// performance: A value of 1, indicates - /// that a processor implements - /// techniques to optimize performance - /// for the given P-state power budget - /// by dynamically varying the - /// frequency, such that maximum - /// performance is achieved for the - /// power budget. A value of 0, - /// indicates that P-states have no - /// frequency variation or very small - /// frequency variations for their given - /// power budget. This feature may only - /// be interrogated by - /// PAL_PROC_GET_FEATURES. it may not be - /// enabled or disabled by - /// PAL_PROC_SET_FEATURES. The - /// corresponding argument is ignored. - - UINT64 NoVM:1; /// Bit40, No Virtual Machine features implemented. - /// Denotes whether PSR.vm is implemented. This - /// feature may only be interrogated by - /// PAL_PROC_GET_FEATURES. It may not be enabled or - /// disabled by PAL_PROC_SET_FEATURES. The - /// corresponding argument is ignored. - - UINT64 NoXipXpsrXfs:1; /// Bit41, No XIP, XPSR, and XFS - /// implemented. Denotes whether XIP, XPSR, - /// and XFS are implemented for machine - /// check recovery. This feature may only be - /// interrogated by PAL_PROC_GET_FEATURES. - /// It may not be enabled or disabled by - /// PAL_PROC_SET_FEATURES. The corresponding - /// argument is ignored. - - UINT64 NoXr1ThroughXr3:1; /// Bit42, No XR1 through XR3 implemented. - /// Denotes whether XR1 XR3 are - /// implemented for machine check - /// recovery. This feature may only be - /// interrogated by PAL_PROC_GET_FEATURES. - /// It may not be enabled or disabled by - /// PAL_PROC_SET_FEATURES. The - /// corresponding argument is ignored. - - UINT64 DisableDynamicPrediction:1; /// Bit43, Disable Dynamic - /// Predicate Prediction. When - /// 0, the processor may predict - /// predicate results and - /// execute speculatively, but - /// may not commit results until - /// the actual predicates are - /// known. When 1, the processor - /// shall not execute predicated - /// instructions until the - /// actual predicates are known. - - UINT64 DisableSpontaneousDeferral:1; /// Bit44, Disable Spontaneous - /// Deferral. When 1, the - /// processor may optionally - /// defer speculative loads - /// that do not encounter any - /// exception conditions, but - /// that trigger other - /// implementation-dependent - /// conditions (e.g., cache - /// miss). When 0, spontaneous - /// deferral is disabled. - - UINT64 DisableDynamicDataCachePrefetch:1; /// Bit45, Disable Dynamic - /// Data Cache Prefetch. - /// When 0, the processor - /// may prefetch into the - /// caches any data which - /// has not been accessed - /// by instruction - /// execution, but which - /// is likely to be - /// accessed. When 1, no - /// data may be fetched - /// until it is needed for - /// instruction execution - /// or is fetched by an - /// lfetch instruction. - - UINT64 DisableDynamicInsCachePrefetch:1; /// Bit46, Disable - /// DynamicInstruction Cache - /// Prefetch. When 0, the - /// processor may prefetch - /// into the caches any - /// instruction which has - /// not been executed, but - /// whose execution is - /// likely. When 1, - /// instructions may not be - /// fetched until needed or - /// hinted for execution. - /// (Prefetch for a hinted - /// branch is allowed even - /// when dynamic instruction - /// cache prefetch is - /// disabled.) - - UINT64 DisableBranchPrediction:1; /// Bit47, Disable Dynamic branch - /// prediction. When 0, the - /// processor may predict branch - /// targets and speculatively - /// execute, but may not commit - /// results. When 1, the processor - /// must wait until branch targets - /// are known to execute. + UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple + ///< implementation of + ///< unimplemented instruction + ///< addresses. Denotes how an + ///< unimplemented instruction + ///< address is recorded in IIP + ///< on an Unimplemented + ///< Instruction Address trap or + ///< fault. When 1, the full + ///< unimplemented address is + ///< recorded in IIP; when 0, the + ///< address is sign extended + ///< (virtual addresses) or zero + ///< extended (physical + ///< addresses). This feature may + ///< only be interrogated by + ///< PAL_PROC_GET_FEATURES. It + ///< may not be enabled or + ///< disabled by + ///< PAL_PROC_SET_FEATURES. The + ///< corresponding argument is + ///< ignored. + + UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state + ///< performance: A value of 1, indicates + ///< that a processor implements + ///< techniques to optimize performance + ///< for the given P-state power budget + ///< by dynamically varying the + ///< frequency, such that maximum + ///< performance is achieved for the + ///< power budget. A value of 0, + ///< indicates that P-states have no + ///< frequency variation or very small + ///< frequency variations for their given + ///< power budget. This feature may only + ///< be interrogated by + ///< PAL_PROC_GET_FEATURES. it may not be + ///< enabled or disabled by + ///< PAL_PROC_SET_FEATURES. The + ///< corresponding argument is ignored. + + UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented. + ///< Denotes whether PSR.vm is implemented. This + ///< feature may only be interrogated by + ///< PAL_PROC_GET_FEATURES. It may not be enabled or + ///< disabled by PAL_PROC_SET_FEATURES. The + ///< corresponding argument is ignored. + + UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS + ///< implemented. Denotes whether XIP, XPSR, + ///< and XFS are implemented for machine + ///< check recovery. This feature may only be + ///< interrogated by PAL_PROC_GET_FEATURES. + ///< It may not be enabled or disabled by + ///< PAL_PROC_SET_FEATURES. The corresponding + ///< argument is ignored. + + UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented. + ///< Denotes whether XR1 XR3 are + ///< implemented for machine check + ///< recovery. This feature may only be + ///< interrogated by PAL_PROC_GET_FEATURES. + ///< It may not be enabled or disabled by + ///< PAL_PROC_SET_FEATURES. The + ///< corresponding argument is ignored. + + UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic + ///< Predicate Prediction. When + ///< 0, the processor may predict + ///< predicate results and + ///< execute speculatively, but + ///< may not commit results until + ///< the actual predicates are + ///< known. When 1, the processor + ///< shall not execute predicated + ///< instructions until the + ///< actual predicates are known. + + UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous + ///< Deferral. When 1, the + ///< processor may optionally + ///< defer speculative loads + ///< that do not encounter any + ///< exception conditions, but + ///< that trigger other + ///< implementation-dependent + ///< conditions (e.g., cache + ///< miss). When 0, spontaneous + ///< deferral is disabled. + + UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic + ///< Data Cache Prefetch. + ///< When 0, the processor + ///< may prefetch into the + ///< caches any data which + ///< has not been accessed + ///< by instruction + ///< execution, but which + ///< is likely to be + ///< accessed. When 1, no + ///< data may be fetched + ///< until it is needed for + ///< instruction execution + ///< or is fetched by an + ///< lfetch instruction. + + UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable + ///< DynamicInstruction Cache + ///< Prefetch. When 0, the + ///< processor may prefetch + ///< into the caches any + ///< instruction which has + ///< not been executed, but + ///< whose execution is + ///< likely. When 1, + ///< instructions may not be + ///< fetched until needed or + ///< hinted for execution. + ///< (Prefetch for a hinted + ///< branch is allowed even + ///< when dynamic instruction + ///< cache prefetch is + ///< disabled.) + + UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch + ///< prediction. When 0, the + ///< processor may predict branch + ///< targets and speculatively + ///< execute, but may not commit + ///< results. When 1, the processor + ///< must wait until branch targets + ///< are known to execute. UINT64 Reserved2:4; - UINT64 DisablePState:1; /// Bit52, Disable P-states. When 1, the PAL - /// P-state procedures (PAL_PSTATE_INFO, - /// PAL_SET_PSTATE, PAL_GET_PSTATE) will - /// return with a status of -1 - /// (Unimplemented procedure). - - UINT64 EnableMcaOnDataPoisoning:1; /// Bit53, Enable MCA signaling - /// on data-poisoning event - /// detection. When 0, a CMCI - /// will be signaled on error - /// detection. When 1, an MCA - /// will be signaled on error - /// detection. If this feature - /// is not supported, then the - /// corresponding argument is - /// ignored when calling - /// PAL_PROC_SET_FEATURES. Note - /// that the functionality of - /// this bit is independent of - /// the setting in bit 60 - /// (Enable CMCI promotion), and - /// that the bit 60 setting does - /// not affect CMCI signaling - /// for data-poisoning related - /// events. Volume 2: Processor - /// Abstraction Layer 2:431 - /// PAL_PROC_GET_FEATURES - - UINT64 EnableVmsw:1; /// Bit54, Enable the use of the vmsw - /// instruction. When 0, the vmsw instruction - /// causes a Virtualization fault when - /// executed at the most privileged level. - /// When 1, this bit will enable normal - /// operation of the vmsw instruction. - - UINT64 EnableEnvNotification:1; /// Bit55, Enable external - /// notification when the processor - /// detects hardware errors caused - /// by environmental factors that - /// could cause loss of - /// deterministic behavior of the - /// processor. When 1, this bit will - /// enable external notification, - /// when 0 external notification is - /// not provided. The type of - /// external notification of these - /// errors is processor-dependent. A - /// loss of processor deterministic - /// behavior is considered to have - /// occurred if these - /// environmentally induced errors - /// cause the processor to deviate - /// from its normal execution and - /// eventually causes different - /// behavior which can be observed - /// at the processor bus pins. - /// Processor errors that do not - /// have this effects (i.e., - /// software induced machine checks) - /// may or may not be promoted - /// depending on the processor - /// implementation. - - UINT64 DisableBinitWithTimeout:1; /// Bit56, Disable a BINIT on - /// internal processor time-out. - /// When 0, the processor may - /// generate a BINIT on an - /// internal processor time-out. - /// When 1, the processor will not - /// generate a BINIT on an - /// internal processor time-out. - /// The event is silently ignored. - - UINT64 DisableDPM:1; /// Bit57, Disable Dynamic Power Management - /// (DPM). When 0, the hardware may reduce - /// power consumption by removing the clock - /// input from idle functional units. When 1, - /// all functional units will receive clock - /// input, even when idle. - - UINT64 DisableCoherency:1; /// Bit58, Disable Coherency. When 0, - /// the processor uses normal coherency - /// requests and responses. When 1, the - /// processor answers all requests as if - /// the line were not present. - - UINT64 DisableCache:1; /// Bit59, Disable Cache. When 0, the - /// processor performs cast outs on - /// cacheable pages and issues and responds - /// to coherency requests normally. When 1, - /// the processor performs a memory access - /// for each reference regardless of cache - /// contents and issues no coherence - /// requests and responds as if the line - /// were not present. Cache contents cannot - /// be relied upon when the cache is - /// disabled. WARNING: Semaphore - /// instructions may not be atomic or may - /// cause Unsupported Data Reference faults - /// if caches are disabled. - - UINT64 EnableCmciPromotion:1; /// Bit60, Enable CMCI promotion When - /// 1, Corrected Machine Check - /// Interrupts (CMCI) are promoted to - /// MCAs. They are also further - /// promoted to BERR if bit 39, Enable - /// MCA promotion, is also set and - /// they are promoted to BINIT if bit - /// 38, Enable MCA to BINIT promotion, - /// is also set. This bit has no - /// effect if MCA signalling is - /// disabled (see - /// PAL_BUS_GET/SET_FEATURES) - - UINT64 EnableMcaToBinitPromotion:1; /// Bit61, Enable MCA to BINIT - /// promotion. When 1, machine - /// check aborts (MCAs) are - /// promoted to the Bus - /// Initialization signal, and - /// the BINIT pin is assert on - /// each occurrence of an MCA. - /// Setting this bit has no - /// effect if BINIT signalling - /// is disabled. (See - /// PAL_BUS_GET/SET_FEATURES) - - UINT64 EnableMcaPromotion:1; /// Bit62, Enable MCA promotion. When - /// 1, machine check aborts (MCAs) are - /// promoted to the Bus Error signal, - /// and the BERR pin is assert on each - /// occurrence of an MCA. Setting this - /// bit has no effect if BERR - /// signalling is disabled. (See - /// PAL_BUS_GET/SET_FEATURES) + UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL + ///< P-state procedures (PAL_PSTATE_INFO, + ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will + ///< return with a status of -1 + ///< (Unimplemented procedure). + + UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling + ///< on data-poisoning event + ///< detection. When 0, a CMCI + ///< will be signaled on error + ///< detection. When 1, an MCA + ///< will be signaled on error + ///< detection. If this feature + ///< is not supported, then the + ///< corresponding argument is + ///< ignored when calling + ///< PAL_PROC_SET_FEATURES. Note + ///< that the functionality of + ///< this bit is independent of + ///< the setting in bit 60 + ///< (Enable CMCI promotion), and + ///< that the bit 60 setting does + ///< not affect CMCI signaling + ///< for data-poisoning related + ///< events. Volume 2: Processor + ///< Abstraction Layer 2:431 + ///< PAL_PROC_GET_FEATURES + + UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw + ///< instruction. When 0, the vmsw instruction + ///< causes a Virtualization fault when + ///< executed at the most privileged level. + ///< When 1, this bit will enable normal + ///< operation of the vmsw instruction. + + UINT64 EnableEnvNotification:1; ///< Bit55, Enable external + ///< notification when the processor + ///< detects hardware errors caused + ///< by environmental factors that + ///< could cause loss of + ///< deterministic behavior of the + ///< processor. When 1, this bit will + ///< enable external notification, + ///< when 0 external notification is + ///< not provided. The type of + ///< external notification of these + ///< errors is processor-dependent. A + ///< loss of processor deterministic + ///< behavior is considered to have + ///< occurred if these + ///< environmentally induced errors + ///< cause the processor to deviate + ///< from its normal execution and + ///< eventually causes different + ///< behavior which can be observed + ///< at the processor bus pins. + ///< Processor errors that do not + ///< have this effects (i.e., + ///< software induced machine checks) + ///< may or may not be promoted + ///< depending on the processor + ///< implementation. + + UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on + ///< internal processor time-out. + ///< When 0, the processor may + ///< generate a BINIT on an + ///< internal processor time-out. + ///< When 1, the processor will not + ///< generate a BINIT on an + ///< internal processor time-out. + ///< The event is silently ignored. + + UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management + ///< (DPM). When 0, the hardware may reduce + ///< power consumption by removing the clock + ///< input from idle functional units. When 1, + ///< all functional units will receive clock + ///< input, even when idle. + + UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0, + ///< the processor uses normal coherency + ///< requests and responses. When 1, the + ///< processor answers all requests as if + ///< the line were not present. + + UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the + ///< processor performs cast outs on + ///< cacheable pages and issues and responds + ///< to coherency requests normally. When 1, + ///< the processor performs a memory access + ///< for each reference regardless of cache + ///< contents and issues no coherence + ///< requests and responds as if the line + ///< were not present. Cache contents cannot + ///< be relied upon when the cache is + ///< disabled. WARNING: Semaphore + ///< instructions may not be atomic or may + ///< cause Unsupported Data Reference faults + ///< if caches are disabled. + + UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When + ///< 1, Corrected Machine Check + ///< Interrupts (CMCI) are promoted to + ///< MCAs. They are also further + ///< promoted to BERR if bit 39, Enable + ///< MCA promotion, is also set and + ///< they are promoted to BINIT if bit + ///< 38, Enable MCA to BINIT promotion, + ///< is also set. This bit has no + ///< effect if MCA signalling is + ///< disabled (see + ///< PAL_BUS_GET/SET_FEATURES) + + UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT + ///< promotion. When 1, machine + ///< check aborts (MCAs) are + ///< promoted to the Bus + ///< Initialization signal, and + ///< the BINIT pin is assert on + ///< each occurrence of an MCA. + ///< Setting this bit has no + ///< effect if BINIT signalling + ///< is disabled. (See + ///< PAL_BUS_GET/SET_FEATURES) + + UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When + ///< 1, machine check aborts (MCAs) are + ///< promoted to the Bus Error signal, + ///< and the BERR pin is assert on each + ///< occurrence of an MCA. Setting this + ///< bit has no effect if BERR + ///< signalling is disabled. (See + ///< PAL_BUS_GET/SET_FEATURES) - UINT64 EnableBerrPromotion:1; /// Bit63. Enable BERR promotion. When - /// 1, the Bus Error (BERR) signal is - /// promoted to the Bus Initialization - /// (BINIT) signal, and the BINIT pin - /// is asserted on the occurrence of - /// each Bus Error. Setting this bit - /// has no effect if BINIT signalling - /// is disabled. (See - /// PAL_BUS_GET/SET_FEATURES) + UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When + ///< 1, the Bus Error (BERR) signal is + ///< promoted to the Bus Initialization + ///< (BINIT) signal, and the BINIT pin + ///< is asserted on the occurrence of + ///< each Bus Error. Setting this bit + ///< has no effect if BINIT signalling + ///< is disabled. (See + ///< PAL_BUS_GET/SET_FEATURES) } PAL_PROCESSOR_FEATURES; /** @@ -1567,20 +1567,20 @@ typedef struct { #define PAL_RSE_INFO 19 typedef struct { - UINT64 VersionOfPalB:16; /// Is a 16-bit binary coded decimal (BCD) - /// number that provides identification - /// information about the PAL_B firmware. + UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD) + ///< number that provides identification + ///< information about the PAL_B firmware. UINT64 Reserved1:8; - UINT64 PalVendor:8; /// Is an unsigned 8-bit integer indicating the - /// vendor of the PAL code. - UINT64 VersionOfPalA:16; /// Is a 16-bit binary coded decimal (BCD) - /// number that provides identification - /// information about the PAL_A firmware. In - /// the split PAL_A model, this return value - /// is the version number of the - /// processor-specific PAL_A. The generic - /// PAL_A version is not returned by this - /// procedure in the split PAL_A model. + UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the + ///< vendor of the PAL code. + UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD) + ///< number that provides identification + ///< information about the PAL_A firmware. In + ///< the split PAL_A model, this return value + ///< is the version number of the + ///< processor-specific PAL_A. The generic + ///< PAL_A version is not returned by this + ///< procedure in the split PAL_A model. UINT64 Reserved2:16; } PAL_VERSION_INFO; @@ -1693,38 +1693,38 @@ typedef struct { #define PAL_STRUCTURE_SPECIFIC_ERROR 2 typedef struct { - UINT64 CoreId:4; /// Bit3:0, Processor core ID (default is 0 for - /// processors with a single core) - - UINT64 ThreadId:4; /// Bit7:4, Logical thread ID (default is 0 for - /// processors that execute a single thread) - - UINT64 InfoOfInsCache:4; /// Bit11:8, Error information is - /// available for 1st, 2nd, 3rd, and 4th - /// level instruction caches. - - UINT64 InfoOfDataCache:4; /// Bit15:12, Error information is - /// available for 1st, 2nd, 3rd, and 4th - /// level data/unified caches. - - UINT64 InfoOfInsTlb:4; /// Bit19:16 Error information is available - /// for 1st, 2nd, 3rd, and 4th level - /// instruction TLB. - - UINT64 InfoOfDataTlb:4; /// Bit23:20, Error information is available - /// for 1st, 2nd, 3rd, and 4th level - /// data/unified TLB - - UINT64 InfoOfProcessorBus:4; /// Bit27:24 Error information is - /// available for the 1st, 2nd, 3rd, - /// and 4th level processor bus - /// hierarchy. - UINT64 InfoOfRegisterFile:4; /// Bit31:28 Error information is - /// available on register file - /// structures. - UINT64 InfoOfMicroArch:4; /// Bit47:32, Error information is - /// available on micro-architectural - /// structures. + UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for + ///< processors with a single core) + + UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for + ///< processors that execute a single thread) + + UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is + ///< available for 1st, 2nd, 3rd, and 4th + ///< level instruction caches. + + UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is + ///< available for 1st, 2nd, 3rd, and 4th + ///< level data/unified caches. + + UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available + ///< for 1st, 2nd, 3rd, and 4th level + ///< instruction TLB. + + UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available + ///< for 1st, 2nd, 3rd, and 4th level + ///< data/unified TLB + + UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is + ///< available for the 1st, 2nd, 3rd, + ///< and 4th level processor bus + ///< hierarchy. + UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is + ///< available on register file + ///< structures. + UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is + ///< available on micro-architectural + ///< structures. UINT64 Reserved:16; } PAL_MC_ERROR_INFO_LEVEL_INDEX; @@ -1738,178 +1738,178 @@ typedef struct { #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4 typedef struct { - UINT64 Operation:4; /// Bit3:0, Type of cache operation that caused - /// the machine check: 0 - unknown or internal - /// error 1 - load 2 - store 3 - instruction - /// fetch or instruction prefetch 4 - data - /// prefetch (both hardware and software) 5 - - /// snoop (coherency check) 6 - cast out - /// (explicit or implicit write-back of a cache - /// line) 7 - move in (cache line fill) - - UINT64 FailedCacheLevel:2; /// Bit5:4 Level of cache where the - /// error occurred. A value of 0 - /// indicates the first level of cache. + UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused + ///< the machine check: 0 - unknown or internal + ///< error 1 - load 2 - store 3 - instruction + ///< fetch or instruction prefetch 4 - data + ///< prefetch (both hardware and software) 5 - + ///< snoop (coherency check) 6 - cast out + ///< (explicit or implicit write-back of a cache + ///< line) 7 - move in (cache line fill) + + UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the + ///< error occurred. A value of 0 + ///< indicates the first level of cache. UINT64 Reserved1:2; - UINT64 FailedInDataPart:1; /// Bit8, Failure located in the data part of the cache line. - UINT64 FailedInTagPart:1; /// Bit9, Failure located in the tag part of the cache line. - UINT64 FailedInDataCache:1; /// Bit10, Failure located in the data cache + UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line. + UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line. + UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache - UINT64 FailedInInsCache:1; /// Bit11, Failure located in the - /// instruction cache. + UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the + ///< instruction cache. - UINT64 Mesi:3; /// Bit14:12, 0 - cache line is invalid. 1 - cache - /// line is held shared. 2 - cache line is held - /// exclusive. 3 - cache line is modified. All other - /// values are reserved. + UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache + ///< line is held shared. 2 - cache line is held + ///< exclusive. 3 - cache line is modified. All other + ///< values are reserved. - UINT64 MesiIsValid:1; /// Bit15, The mesi field in the cache_check - /// parameter is valid. + UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check + ///< parameter is valid. - UINT64 FailedWay:5; /// Bit20:16, Failure located in the way of - /// the cache indicated by this value. + UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of + ///< the cache indicated by this value. - UINT64 WayIndexIsValid:1; /// Bit21, The way and index field in the - /// cache_check parameter is valid. + UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the + ///< cache_check parameter is valid. UINT64 Reserved2:1; - UINT64 MultipleBitsError:1; /// Bit23, A multiple-bit error was - /// detected, and data was poisoned for - /// the corresponding cache line during - /// castout. + UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was + ///< detected, and data was poisoned for + ///< the corresponding cache line during + ///< castout. UINT64 Reserved3:8; - UINT64 IndexOfCacheLineError:20; /// Bit51:32, Index of the cache - /// line where the error occurred. + UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache + ///< line where the error occurred. UINT64 Reserved4:2; - UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value - /// is set to zero, the instruction that - /// generated the machine check was an - /// Intel Itanium instruction. If this bit - /// is set to one, the instruction that - /// generated the machine check was IA-32 - /// instruction. - - UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the - /// cache_check parameter is valid. - - UINT64 PrivilegeLevel:2; /// Bit57:56, Privilege level. The - /// privilege level of the instruction - /// bundle responsible for generating the - /// machine check. - - UINT64 PrivilegeLevelIsValide:1; /// Bit58, The pl field of the - /// cache_check parameter is - /// valid. - - UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit - /// is set to one to indicate that the machine - /// check has been corrected. - - UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid: - /// This bit is set to one to - /// indicate that a valid target - /// address has been logged. - - UINT64 RequesterIdentifier:1; /// Bit61, Requester identifier: This - /// bit is set to one to indicate that - /// a valid requester identifier has - /// been logged. - - UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This - /// bit is set to one to indicate that - /// a valid responder identifier has - /// been logged. - - UINT64 PreciseInsPointer:1; /// Bit63, Precise instruction pointer. - /// This bit is set to one to indicate - /// that a valid precise instruction - /// pointer has been logged. + UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value + ///< is set to zero, the instruction that + ///< generated the machine check was an + ///< Intel Itanium instruction. If this bit + ///< is set to one, the instruction that + ///< generated the machine check was IA-32 + ///< instruction. + + UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the + ///< cache_check parameter is valid. + + UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The + ///< privilege level of the instruction + ///< bundle responsible for generating the + ///< machine check. + + UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the + ///< cache_check parameter is + ///< valid. + + UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit + ///< is set to one to indicate that the machine + ///< check has been corrected. + + UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid: + ///< This bit is set to one to + ///< indicate that a valid target + ///< address has been logged. + + UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This + ///< bit is set to one to indicate that + ///< a valid requester identifier has + ///< been logged. + + UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This + ///< bit is set to one to indicate that + ///< a valid responder identifier has + ///< been logged. + + UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer. + ///< This bit is set to one to indicate + ///< that a valid precise instruction + ///< pointer has been logged. } PAL_CACHE_CHECK_INFO; typedef struct { - UINT64 FailedSlot:8; /// Bit7:0, Slot number of the translation - /// register where the failure occurred. - UINT64 FailedSlotIsValid:1; /// Bit8, The tr_slot field in the - /// TLB_check parameter is valid. + UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation + ///< register where the failure occurred. + UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the + ///< TLB_check parameter is valid. UINT64 Reserved1 :1; - UINT64 TlbLevel:2; /// Bit11:10, The level of the TLB where the - /// error occurred. A value of 0 indicates the - /// first level of TLB + UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the + ///< error occurred. A value of 0 indicates the + ///< first level of TLB UINT64 Reserved2 :4; - UINT64 FailedInDataTr:1; /// Bit16, Error occurred in the data - /// translation registers. - - UINT64 FailedInInsTr:1; /// Bit17, Error occurred in the instruction - /// translation registers - - UINT64 FailedInDataTc:1; /// Bit18, Error occurred in data - /// translation cache. - - UINT64 FailedInInsTc:1; /// Bit19, Error occurred in the instruction - /// translation cache. - - UINT64 FailedOperation:4; /// Bit23:20, Type of cache operation that - /// caused the machine check: 0 - unknown - /// 1 - TLB access due to load instruction - /// 2 - TLB access due to store - /// instruction 3 - TLB access due to - /// instruction fetch or instruction - /// prefetch 4 - TLB access due to data - /// prefetch (both hardware and software) - /// 5 - TLB shoot down access 6 - TLB - /// probe instruction (probe, tpa) 7 - - /// move in (VHPT fill) 8 - purge (insert - /// operation that purges entries or a TLB - /// purge instruction) All other values - /// are reserved. + UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data + ///< translation registers. + + UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction + ///< translation registers + + UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data + ///< translation cache. + + UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction + ///< translation cache. + + UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that + ///< caused the machine check: 0 - unknown + ///< 1 - TLB access due to load instruction + ///< 2 - TLB access due to store + ///< instruction 3 - TLB access due to + ///< instruction fetch or instruction + ///< prefetch 4 - TLB access due to data + ///< prefetch (both hardware and software) + ///< 5 - TLB shoot down access 6 - TLB + ///< probe instruction (probe, tpa) 7 - + ///< move in (VHPT fill) 8 - purge (insert + ///< operation that purges entries or a TLB + ///< purge instruction) All other values + ///< are reserved. UINT64 Reserved3:30; - UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value - /// is set to zero, the instruction that - /// generated the machine check was an - /// Intel Itanium instruction. If this bit - /// is set to one, the instruction that - /// generated the machine check was IA-32 - /// instruction. - - UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the - /// TLB_check parameter is valid. - - UINT64 PrivelegeLevel:2; /// Bit57:56, Privilege level. The - /// privilege level of the instruction - /// bundle responsible for generating the - /// machine check. - - UINT64 PrivelegeLevelIsValid:1; /// Bit58, The pl field of the - /// TLB_check parameter is valid. - - UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit - /// is set to one to indicate that the machine - /// check has been corrected. - - UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid: - /// This bit is set to one to - /// indicate that a valid target - /// address has been logged. - - UINT64 RequesterIdentifier:1; /// Bit61 Requester identifier: This - /// bit is set to one to indicate that - /// a valid requester identifier has - /// been logged. - - UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This - /// bit is set to one to indicate that - /// a valid responder identifier has - /// been logged. - - UINT64 PreciseInsPointer:1; /// Bit63 Precise instruction pointer. - /// This bit is set to one to indicate - /// that a valid precise instruction - /// pointer has been logged. + UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value + ///< is set to zero, the instruction that + ///< generated the machine check was an + ///< Intel Itanium instruction. If this bit + ///< is set to one, the instruction that + ///< generated the machine check was IA-32 + ///< instruction. + + UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the + ///< TLB_check parameter is valid. + + UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The + ///< privilege level of the instruction + ///< bundle responsible for generating the + ///< machine check. + + UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the + ///< TLB_check parameter is valid. + + UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit + ///< is set to one to indicate that the machine + ///< check has been corrected. + + UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid: + ///< This bit is set to one to + ///< indicate that a valid target + ///< address has been logged. + + UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This + ///< bit is set to one to indicate that + ///< a valid requester identifier has + ///< been logged. + + UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This + ///< bit is set to one to indicate that + ///< a valid responder identifier has + ///< been logged. + + UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer. + ///< This bit is set to one to indicate + ///< that a valid precise instruction + ///< pointer has been logged. } PAL_TLB_CHECK_INFO; /** @@ -2217,131 +2217,131 @@ typedef struct { #define PAL_TEST_INFO 37 typedef struct { - UINT64 BufferSize:56; /// Indicates the size in bytes of the memory - /// buffer that is passed to this procedure. - /// BufferSize must be greater than or equal in - /// size to the bytes_needed return value from - /// PAL_TEST_INFO, otherwise this procedure will - /// return with an invalid argument return - /// value. - - UINT64 TestPhase:8; /// Defines which phase of the processor - /// self-tests are requested to be run. A value - /// of zero indicates to run phase two of the - /// processor self-tests. Phase two of the - /// processor self-tests are ones that require - /// external memory to execute correctly. A - /// value of one indicates to run phase one of - /// the processor self-tests. Phase one of the - /// processor self-tests are tests run during - /// PALE_RESET and do not depend on external - /// memory to run correctly. When the caller - /// requests to have phase one of the processor - /// self-test run via this procedure call, a - /// memory buffer may be needed to save and - /// restore state as required by the PAL calling - /// conventions. The procedure PAL_TEST_INFO - /// informs the caller about the requirements of - /// the memory buffer. + UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory + ///< buffer that is passed to this procedure. + ///< BufferSize must be greater than or equal in + ///< size to the bytes_needed return value from + ///< PAL_TEST_INFO, otherwise this procedure will + ///< return with an invalid argument return + ///< value. + + UINT64 TestPhase:8; ///< Defines which phase of the processor + ///< self-tests are requested to be run. A value + ///< of zero indicates to run phase two of the + ///< processor self-tests. Phase two of the + ///< processor self-tests are ones that require + ///< external memory to execute correctly. A + ///< value of one indicates to run phase one of + ///< the processor self-tests. Phase one of the + ///< processor self-tests are tests run during + ///< PALE_RESET and do not depend on external + ///< memory to run correctly. When the caller + ///< requests to have phase one of the processor + ///< self-test run via this procedure call, a + ///< memory buffer may be needed to save and + ///< restore state as required by the PAL calling + ///< conventions. The procedure PAL_TEST_INFO + ///< informs the caller about the requirements of + ///< the memory buffer. } PAL_TEST_INFO_INFO; typedef struct { - UINT64 TestControl:47; /// This is an ordered implementation-specific - /// control word that allows the user control - /// over the length and runtime of the - /// processor self-tests. This control word is - /// ordered from the longest running tests up - /// to the shortest running tests with bit 0 - /// controlling the longest running test. PAL - /// may not implement all 47-bits of the - /// test_control word. PAL communicates if a - /// bit provides control by placing a zero in - /// that bit. If a bit provides no control, - /// PAL will place a one in it. PAL will have - /// two sets of test_control bits for the two - /// phases of the processor self-test. PAL - /// provides information about implemented - /// test_control bits at the hand-off from PAL - /// to SAL for the firmware recovery check. - /// These test_control bits provide control - /// for phase one of processor self-test. It - /// also provides this information via the PAL - /// procedure call PAL_TEST_INFO for both the - /// phase one and phase two processor tests - /// depending on which information the caller - /// is requesting. PAL interprets these bits - /// as input parameters on two occasions. The - /// first time is when SAL passes control back - /// to PAL after the firmware recovery check. - /// The second time is when a call to - /// PAL_TEST_PROC is made. When PAL interprets - /// these bits it will only interpret - /// implemented test_control bits and will - /// ignore the values located in the - /// unimplemented test_control bits. PAL - /// interprets the implemented bits such that - /// if a bit contains a zero, this indicates - /// to run the test. If a bit contains a one, - /// this indicates to PAL to skip the test. If - /// the cs bit indicates that control is not - /// available, the test_control bits will be - /// ignored or generate an illegal argument in - /// procedure calls if the caller sets these - /// bits. + UINT64 TestControl:47; ///< This is an ordered implementation-specific + ///< control word that allows the user control + ///< over the length and runtime of the + ///< processor self-tests. This control word is + ///< ordered from the longest running tests up + ///< to the shortest running tests with bit 0 + ///< controlling the longest running test. PAL + ///< may not implement all 47-bits of the + ///< test_control word. PAL communicates if a + ///< bit provides control by placing a zero in + ///< that bit. If a bit provides no control, + ///< PAL will place a one in it. PAL will have + ///< two sets of test_control bits for the two + ///< phases of the processor self-test. PAL + ///< provides information about implemented + ///< test_control bits at the hand-off from PAL + ///< to SAL for the firmware recovery check. + ///< These test_control bits provide control + ///< for phase one of processor self-test. It + ///< also provides this information via the PAL + ///< procedure call PAL_TEST_INFO for both the + ///< phase one and phase two processor tests + ///< depending on which information the caller + ///< is requesting. PAL interprets these bits + ///< as input parameters on two occasions. The + ///< first time is when SAL passes control back + ///< to PAL after the firmware recovery check. + ///< The second time is when a call to + ///< PAL_TEST_PROC is made. When PAL interprets + ///< these bits it will only interpret + ///< implemented test_control bits and will + ///< ignore the values located in the + ///< unimplemented test_control bits. PAL + ///< interprets the implemented bits such that + ///< if a bit contains a zero, this indicates + ///< to run the test. If a bit contains a one, + ///< this indicates to PAL to skip the test. If + ///< the cs bit indicates that control is not + ///< available, the test_control bits will be + ///< ignored or generate an illegal argument in + ///< procedure calls if the caller sets these + ///< bits. - UINT64 ControlSupport:1; /// This bit defines if an implementation - /// supports control of the PAL self-tests - /// via the self-test control word. If - /// this bit is 0, the implementation does - /// not support control of the processor - /// self-tests via the self-test control - /// word. If this bit is 1, the - /// implementation does support control of - /// the processor self-tests via the - /// self-test control word. If control is - /// not supported, GR37 will be ignored at - /// the hand-off between SAL and PAL after - /// the firmware recovery check and the - /// PAL procedures related to the - /// processor self-tests may return - /// illegal arguments if a user tries to - /// use the self-test control features. + UINT64 ControlSupport:1; ///< This bit defines if an implementation + ///< supports control of the PAL self-tests + ///< via the self-test control word. If + ///< this bit is 0, the implementation does + ///< not support control of the processor + ///< self-tests via the self-test control + ///< word. If this bit is 1, the + ///< implementation does support control of + ///< the processor self-tests via the + ///< self-test control word. If control is + ///< not supported, GR37 will be ignored at + ///< the hand-off between SAL and PAL after + ///< the firmware recovery check and the + ///< PAL procedures related to the + ///< processor self-tests may return + ///< illegal arguments if a user tries to + ///< use the self-test control features. UINT64 Reserved:16; } PAL_SELF_TEST_CONTROL; typedef struct { - UINT64 Attributes:8; /// Specifies the memory attributes that are - /// allowed to be used with the memory buffer - /// passed to this procedure. The attributes - /// parameter is a vector where each bit - /// represents one of the virtual memory - /// attributes defined by the architecture.See - /// MEMORY_AATRIBUTES. The caller is required - /// to support the cacheable attribute for the - /// memory buffer, otherwise an invalid - /// argument will be returned. + UINT64 Attributes:8; ///< Specifies the memory attributes that are + ///< allowed to be used with the memory buffer + ///< passed to this procedure. The attributes + ///< parameter is a vector where each bit + ///< represents one of the virtual memory + ///< attributes defined by the architecture.See + ///< MEMORY_AATRIBUTES. The caller is required + ///< to support the cacheable attribute for the + ///< memory buffer, otherwise an invalid + ///< argument will be returned. UINT64 Reserved:8; - UINT64 TestControl:48; /// Is the self-test control word - /// corresponding to the test_phase passed. - /// This test_control directs the coverage and - /// runtime of the processor self-tests - /// specified by the test_phase input - /// argument. Information on if this - /// feature is implemented and the number of - /// bits supported can be obtained by the - /// PAL_TEST_INFO procedure call. If this - /// feature is implemented by the processor, - /// the caller can selectively skip parts of - /// the processor self-test by setting - /// test_control bits to a one. If a bit has a - /// zero, this test will be run. The values in - /// the unimplemented bits are ignored. If - /// PAL_TEST_INFO indicated that the self-test - /// control word is not implemented, this - /// procedure will return with an invalid - /// argument status if the caller sets any of - /// the test_control bits. See - /// PAL_SELF_TEST_CONTROL. + UINT64 TestControl:48; ///< Is the self-test control word + ///< corresponding to the test_phase passed. + ///< This test_control directs the coverage and + ///< runtime of the processor self-tests + ///< specified by the test_phase input + ///< argument. Information on if this + ///< feature is implemented and the number of + ///< bits supported can be obtained by the + ///< PAL_TEST_INFO procedure call. If this + ///< feature is implemented by the processor, + ///< the caller can selectively skip parts of + ///< the processor self-test by setting + ///< test_control bits to a one. If a bit has a + ///< zero, this test will be run. The values in + ///< the unimplemented bits are ignored. If + ///< PAL_TEST_INFO indicated that the self-test + ///< control word is not implemented, this + ///< procedure will return with an invalid + ///< argument status if the caller sets any of + ///< the test_control bits. See + ///< PAL_SELF_TEST_CONTROL. } PAL_TEST_CONTROL; /** @@ -2379,12 +2379,12 @@ typedef struct { #define PAL_TEST_PROC 258 typedef struct { - UINT32 NumberOfInterruptControllers; /// Number of interrupt - /// controllers currently - /// enabled on the system. + UINT32 NumberOfInterruptControllers; ///< Number of interrupt + ///< controllers currently + ///< enabled on the system. - UINT32 NumberOfProcessors; /// Number of processors currently - /// enabled on the system. + UINT32 NumberOfProcessors; ///< Number of processors currently + ///< enabled on the system. } PAL_PLATFORM_INFO; /** @@ -2659,150 +2659,150 @@ typedef struct { #define PAL_SET_HW_POLICY 49 typedef struct { - UINT64 Mode:3; /// Bit2:0, Indicates the mode of operation for this - /// procedure: 0 - Query mode 1 - Error inject mode - /// (err_inj should also be specified) 2 - Cancel - /// outstanding trigger. All other fields in - /// PAL_MC_ERROR_TYPE_INFO, - /// PAL_MC_ERROR_STRUCTURE_INFO and - /// PAL_MC_ERROR_DATA_BUFFER are ignored. All other - /// values are reserved. - - UINT64 ErrorInjection:3; /// Bit5:3, indicates the mode of error - /// injection: 0 - Error inject only (no - /// error consumption) 1 - Error inject - /// and consume All other values are - /// reserved. - - UINT64 ErrorSeverity:2; /// Bit7:6, indicates the severity desired - /// for error injection/query. Definitions - /// of the different error severity types - /// 0 - Corrected error 1 - Recoverable - /// error 2 - Fatal error 3 - Reserved - - UINT64 ErrorStructure:5; /// Bit12:8, Indicates the structure - /// identification for error - /// injection/query: 0 - Any structure - /// (cannot be used during query mode). - /// When selected, the structure type used - /// for error injection is determined by - /// PAL. 1 - Cache 2 - TLB 3 - Register - /// file 4 - Bus/System interconnect 5-15 - /// - Reserved 16-31 - Processor - /// specific error injection - /// capabilities.ErrorDataBuffer is used - /// to specify error types. Please refer - /// to the processor specific - /// documentation for additional details. - - UINT64 StructureHierarchy:3; /// Bit15:13, Indicates the structure - /// hierarchy for error - /// injection/query: 0 - Any level of - /// hierarchy (cannot be used during - /// query mode). When selected, the - /// structure hierarchy used for error - /// injection is determined by PAL. 1 - /// - Error structure hierarchy - /// level-1 2 - Error structure - /// hierarchy level-2 3 - Error - /// structure hierarchy level-3 4 - - /// Error structure hierarchy level-4 - /// All other values are reserved. - /// Reserved 63:16 Reserved + UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this + ///< procedure: 0 - Query mode 1 - Error inject mode + ///< (err_inj should also be specified) 2 - Cancel + ///< outstanding trigger. All other fields in + ///< PAL_MC_ERROR_TYPE_INFO, + ///< PAL_MC_ERROR_STRUCTURE_INFO and + ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other + ///< values are reserved. + + UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error + ///< injection: 0 - Error inject only (no + ///< error consumption) 1 - Error inject + ///< and consume All other values are + ///< reserved. + + UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired + ///< for error injection/query. Definitions + ///< of the different error severity types + ///< 0 - Corrected error 1 - Recoverable + ///< error 2 - Fatal error 3 - Reserved + + UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure + ///< identification for error + ///< injection/query: 0 - Any structure + ///< (cannot be used during query mode). + ///< When selected, the structure type used + ///< for error injection is determined by + ///< PAL. 1 - Cache 2 - TLB 3 - Register + ///< file 4 - Bus/System interconnect 5-15 + ///< - Reserved 16-31 - Processor + ///< specific error injection + ///< capabilities.ErrorDataBuffer is used + ///< to specify error types. Please refer + ///< to the processor specific + ///< documentation for additional details. + + UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure + ///< hierarchy for error + ///< injection/query: 0 - Any level of + ///< hierarchy (cannot be used during + ///< query mode). When selected, the + ///< structure hierarchy used for error + ///< injection is determined by PAL. 1 + ///< - Error structure hierarchy + ///< level-1 2 - Error structure + ///< hierarchy level-2 3 - Error + ///< structure hierarchy level-3 4 - + ///< Error structure hierarchy level-4 + ///< All other values are reserved. + ///< Reserved 63:16 Reserved UINT64 Reserved:48; } PAL_MC_ERROR_TYPE_INFO; typedef struct { - UINT64 StructInfoIsValid:1; /// Bit0 When 1, indicates that the - /// structure information fields - /// (c_t,cl_p,cl_id) are valid and - /// should be used for error injection. - /// When 0, the structure information - /// fields are ignored, and the values - /// of these fields used for error - /// injection are - /// implementation-specific. - - UINT64 CacheType:2; /// Bit2:1 Indicates which cache should be used - /// for error injection: 0 - Reserved 1 - - /// Instruction cache 2 - Data or unified cache - /// 3 - Reserved - - UINT64 PortionOfCacheLine:3; /// Bit5:3 Indicates the portion of the - /// cache line where the error should - /// be injected: 0 - Reserved 1 - Tag - /// 2 - Data 3 - mesi All other - /// values are reserved. - - UINT64 Mechanism:3; /// Bit8:6 Indicates which mechanism is used to - /// identify the cache line to be used for error - /// injection: 0 - Reserved 1 - Virtual address - /// provided in the inj_addr field of the buffer - /// pointed to by err_data_buffer should be used - /// to identify the cache line for error - /// injection. 2 - Physical address provided in - /// the inj_addr field of the buffer pointed to - /// by err_data_buffershould be used to identify - /// the cache line for error injection. 3 - way - /// and index fields provided in err_data_buffer - /// should be used to identify the cache line - /// for error injection. All other values are - /// reserved. - - UINT64 DataPoisonOfCacheLine:1; /// Bit9 When 1, indicates that a - /// multiple bit, non-correctable - /// error should be injected in the - /// cache line specified by cl_id. - /// If this injected error is not - /// consumed, it may eventually - /// cause a data-poisoning event - /// resulting in a corrected error - /// signal, when the associated - /// cache line is cast out (implicit - /// or explicit write-back of the - /// cache line). The error severity - /// specified by err_sev in - /// err_type_info must be set to 0 - /// (corrected error) when this bit - /// is set. + UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the + ///< structure information fields + ///< (c_t,cl_p,cl_id) are valid and + ///< should be used for error injection. + ///< When 0, the structure information + ///< fields are ignored, and the values + ///< of these fields used for error + ///< injection are + ///< implementation-specific. + + UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used + ///< for error injection: 0 - Reserved 1 - + ///< Instruction cache 2 - Data or unified cache + ///< 3 - Reserved + + UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the + ///< cache line where the error should + ///< be injected: 0 - Reserved 1 - Tag + ///< 2 - Data 3 - mesi All other + ///< values are reserved. + + UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to + ///< identify the cache line to be used for error + ///< injection: 0 - Reserved 1 - Virtual address + ///< provided in the inj_addr field of the buffer + ///< pointed to by err_data_buffer should be used + ///< to identify the cache line for error + ///< injection. 2 - Physical address provided in + ///< the inj_addr field of the buffer pointed to + ///< by err_data_buffershould be used to identify + ///< the cache line for error injection. 3 - way + ///< and index fields provided in err_data_buffer + ///< should be used to identify the cache line + ///< for error injection. All other values are + ///< reserved. + + UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a + ///< multiple bit, non-correctable + ///< error should be injected in the + ///< cache line specified by cl_id. + ///< If this injected error is not + ///< consumed, it may eventually + ///< cause a data-poisoning event + ///< resulting in a corrected error + ///< signal, when the associated + ///< cache line is cast out (implicit + ///< or explicit write-back of the + ///< cache line). The error severity + ///< specified by err_sev in + ///< err_type_info must be set to 0 + ///< (corrected error) when this bit + ///< is set. UINT64 Reserved1:22; - UINT64 TrigerInfoIsValid:1; /// Bit32 When 1, indicates that the - /// trigger information fields (trigger, - /// trigger_pl) are valid and should be - /// used for error injection. When 0, - /// the trigger information fields are - /// ignored and error injection is - /// performed immediately. - - UINT64 Triger:4; /// Bit36:33 Indicates the operation type to be - /// used as the error trigger condition. The - /// address corresponding to the trigger is - /// specified in the trigger_addr field of the - /// buffer pointed to by err_data_buffer: 0 - - /// Instruction memory access. The trigger match - /// conditions for this operation type are similar - /// to the IBR address breakpoint match conditions - /// 1 - Data memory access. The trigger match - /// conditions for this operation type are similar - /// to the DBR address breakpoint match conditions - /// All other values are reserved. - - UINT64 PrivilegeOfTriger:3; /// Bit39:37 Indicates the privilege - /// level of the context during which - /// the error should be injected: 0 - - /// privilege level 0 1 - privilege - /// level 1 2 - privilege level 2 3 - - /// privilege level 3 All other values - /// are reserved. If the implementation - /// does not support privilege level - /// qualifier for triggers (i.e. if - /// trigger_pl is 0 in the capabilities - /// vector), this field is ignored and - /// triggers can be taken at any - /// privilege level. + UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the + ///< trigger information fields (trigger, + ///< trigger_pl) are valid and should be + ///< used for error injection. When 0, + ///< the trigger information fields are + ///< ignored and error injection is + ///< performed immediately. + + UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be + ///< used as the error trigger condition. The + ///< address corresponding to the trigger is + ///< specified in the trigger_addr field of the + ///< buffer pointed to by err_data_buffer: 0 - + ///< Instruction memory access. The trigger match + ///< conditions for this operation type are similar + ///< to the IBR address breakpoint match conditions + ///< 1 - Data memory access. The trigger match + ///< conditions for this operation type are similar + ///< to the DBR address breakpoint match conditions + ///< All other values are reserved. + + UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege + ///< level of the context during which + ///< the error should be injected: 0 - + ///< privilege level 0 1 - privilege + ///< level 1 2 - privilege level 2 3 - + ///< privilege level 3 All other values + ///< are reserved. If the implementation + ///< does not support privilege level + ///< qualifier for triggers (i.e. if + ///< trigger_pl is 0 in the capabilities + ///< vector), this field is ignored and + ///< triggers can be taken at any + ///< privilege level. UINT64 Reserved2:24; } PAL_MC_ERROR_STRUCT_INFO; diff --git a/MdePkg/Include/IndustryStandard/SmBus.h b/MdePkg/Include/IndustryStandard/SmBus.h index 89142c1f85..fd2c253464 100644 --- a/MdePkg/Include/IndustryStandard/SmBus.h +++ b/MdePkg/Include/IndustryStandard/SmBus.h @@ -1,5 +1,6 @@ /** @file - This file declares the SMBus definitions defined in SmBus Specifciation V2.0. + This file declares the SMBus definitions defined in SmBus Specifciation V2.0 + and defined in PI1.0 specification volume 5. Copyright (c) 2007 - 2008, Intel Corporation All rights reserved. This program and the accompanying materials @@ -34,14 +35,16 @@ typedef struct { /// Smbus Device Address /// typedef struct { + /// + /// The SMBUS hardware address to which the SMBUS device is preassigned or allocated. + /// UINTN SmbusDeviceAddress : 7; } EFI_SMBUS_DEVICE_ADDRESS; /// /// Smbus Operations /// -typedef enum _EFI_SMBUS_OPERATION -{ +typedef enum _EFI_SMBUS_OPERATION { EfiSmbusQuickRead, EfiSmbusQuickWrite, EfiSmbusReceiveByte, @@ -56,5 +59,10 @@ typedef enum _EFI_SMBUS_OPERATION EfiSmbusBWBRProcessCall } EFI_SMBUS_OPERATION; +/// +/// EFI_SMBUS_DEVICE_COMMAND +/// +typedef UINTN EFI_SMBUS_DEVICE_COMMAND; + #endif diff --git a/MdePkg/Include/Ppi/Smbus2.h b/MdePkg/Include/Ppi/Smbus2.h index 21778ae491..175b2b70a7 100644 --- a/MdePkg/Include/Ppi/Smbus2.h +++ b/MdePkg/Include/Ppi/Smbus2.h @@ -28,12 +28,6 @@ typedef struct _EFI_PEI_SMBUS2_PPI EFI_PEI_SMBUS2_PPI; -// -// EFI_SMBUS_DEVICE_COMMAND -// -typedef UINTN EFI_SMBUS_DEVICE_COMMAND; - - /** Executes an SMBus operation to an SMBus controller. Returns when either the command has been executed or an error is encountered in doing the operation. diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h index b59ca4d52e..3203f79dd0 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -444,12 +444,12 @@ typedef struct { #define EXCEPT_EBC_DEBUG 2 #define EXCEPT_EBC_BREAKPOINT 3 #define EXCEPT_EBC_OVERFLOW 4 -#define EXCEPT_EBC_INVALID_OPCODE 5 /// opcode out of range +#define EXCEPT_EBC_INVALID_OPCODE 5 ///< opcode out of range #define EXCEPT_EBC_STACK_FAULT 6 #define EXCEPT_EBC_ALIGNMENT_CHECK 7 -#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 /// malformed instruction -#define EXCEPT_EBC_BAD_BREAK 9 /// BREAK 0 or undefined BREAK -#define EXCEPT_EBC_STEP 10 /// to support debug stepping +#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< malformed instruction +#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK +#define EXCEPT_EBC_STEP 10 ///< to support debug stepping /// /// For coding convenience, define the maximum valid EBC exception. /// diff --git a/MdePkg/Include/Protocol/DevicePath.h b/MdePkg/Include/Protocol/DevicePath.h index b5ce7378cf..16e8eb4289 100644 --- a/MdePkg/Include/Protocol/DevicePath.h +++ b/MdePkg/Include/Protocol/DevicePath.h @@ -839,7 +839,7 @@ typedef struct { // // Use VENDOR_DEVICE_PATH struct // -#define MEDIA_VENDOR_DP 0x03 /// Media vendor device path subtype +#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype /// /// File Path Media Device Path SubType diff --git a/MdePkg/Include/Protocol/FirmwareVolume2.h b/MdePkg/Include/Protocol/FirmwareVolume2.h index fc743305ba..07767f3c70 100644 --- a/MdePkg/Include/Protocol/FirmwareVolume2.h +++ b/MdePkg/Include/Protocol/FirmwareVolume2.h @@ -418,9 +418,9 @@ EFI_STATUS OUT UINT32 *AuthenticationStatus ); -// -// EFI_FV_WRITE_POLICY -// +/// +/// EFI_FV_WRITE_POLICY, two policies (unreliable write and reliable write) are defined. +/// typedef UINT32 EFI_FV_WRITE_POLICY; #define EFI_FV_UNRELIABLE_WRITE 0x00000000 #define EFI_FV_RELIABLE_WRITE 0x00000001 diff --git a/MdePkg/Include/Protocol/HiiFont.h b/MdePkg/Include/Protocol/HiiFont.h index dd19f29012..9145089734 100644 --- a/MdePkg/Include/Protocol/HiiFont.h +++ b/MdePkg/Include/Protocol/HiiFont.h @@ -62,8 +62,9 @@ typedef struct _EFI_HII_ROW_INFO { } EFI_HII_ROW_INFO; /// -/// EFI_FONT_INFO_MASK -/// +/// Font info flag. All flags (FONT, SIZE, STYLE, and COLOR) are defined. +/// They are defined as EFI_FONT_INFO_*** +/// typedef UINT32 EFI_FONT_INFO_MASK; #define EFI_FONT_INFO_SYS_FONT 0x00000001 @@ -87,6 +88,8 @@ typedef struct { } EFI_FONT_INFO; /** + Describes font output-related information. + This structure is used for describing the way in which a string should be rendered in a particular font. FontInfo specifies the basic font information and ForegroundColor and BackgroundColor @@ -94,34 +97,7 @@ typedef struct { in FontInfoMask describe where the system default should be supplied instead of the specified information. The flags also describe what options can be used to make a match between the - font requested and the font available. If EFI_FONT_INFO_SYS_FONT - is specified, then the font name in FontInfo is ignored and the - system font name is used. This flag cannot be used with - EFI_FONT_INFO_ANY_FONT. If EFI_FONT_INFO_SYS_SIZE is specified, - then the font height specified in FontInfo is ignored and the - system font height is used instead. This flag cannot be used - with EFI_FONT_INFO_ANY_SIZE. If EFI_FONT_INFO_SYS_STYLE is - specified, then the font style in FontInfo is ignored and the - system font style is used. This flag cannot be used with - EFI_FONT_INFO_ANY_STYLE. If EFI_FONT_INFO_SYS_FORE_COLOR is - specified, then ForegroundColor is ignored and the system - foreground color is used. If EFI_FONT_INFO_SYS_BACK_COLOR is - specified, then BackgroundColor is ignored and the system - background color is used. If EFI_FONT_INFO_RESIZE is specified, - then the system may attempt to stretch or shrink a font to meet - the size requested. This flag cannot be used with - EFI_FONT_INFO_ANY_SIZE. If EFI_FONT_INFO_RESTYLE is specified, - then the system may attempt to remove some of the specified - styles in order to meet the style requested. This flag cannot be - used with EFI_FONT_INFO_ANY_STYLE. If EFI_FONT_INFO_ANY_FONT is - specified, then the system may attempt to match with any font. - This flag cannot be used with EFI_FONT_INFO_SYS_FONT. If - EFI_FONT_INFO_ANY_SIZE is specified, then the system may attempt - to match with any font size. This flag cannot be used with - EFI_FONT_INFO_SYS_SIZE or EFI_FONT_INFO_RESIZE. If - EFI_FONT_INFO_ANY_STYLE is specified, then the system may - attempt to match with any font style. This flag cannot be used - with EFI_FONT_INFO_SYS_STYLE or EFI_FONT_INFO_RESTYLE. + font requested and the font available. **/ typedef struct _EFI_FONT_DISPLAY_INFO { EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor; diff --git a/MdePkg/Include/Protocol/HiiImage.h b/MdePkg/Include/Protocol/HiiImage.h index 624b354134..412dcccfa4 100644 --- a/MdePkg/Include/Protocol/HiiImage.h +++ b/MdePkg/Include/Protocol/HiiImage.h @@ -160,9 +160,10 @@ EFI_STATUS ); -// -// EFI_HII_DRAW_FLAGS -// +/// +/// EFI_HII_DRAW_FLAGS describes how the image is to be drawn. +/// These flags are defined as EFI_HII_DRAW_FLAG_*** +/// typedef UINT32 EFI_HII_DRAW_FLAGS; #define EFI_HII_DRAW_FLAG_CLIP 0x00000001 @@ -172,7 +173,6 @@ typedef UINT32 EFI_HII_DRAW_FLAGS; #define EFI_HII_DRAW_FLAG_FORCE_OPAQUE 0x00000020 #define EFI_HII_DIRECT_TO_SCREEN 0x00000080 - /** Definition of EFI_IMAGE_OUTPUT. diff --git a/MdePkg/Include/Protocol/Ip4.h b/MdePkg/Include/Protocol/Ip4.h index d19cc7b34d..ab598484af 100644 --- a/MdePkg/Include/Protocol/Ip4.h +++ b/MdePkg/Include/Protocol/Ip4.h @@ -52,19 +52,74 @@ typedef struct { } EFI_IP4_VARIABLE_DATA; typedef struct { + /// + /// The default IPv4 protocol packets to send and receive. Ignored + /// when AcceptPromiscuous is TRUE. + /// UINT8 DefaultProtocol; + /// + /// Set to TRUE to receive all IPv4 packets that get through the receive filters. + /// Set to FALSE to receive only the DefaultProtocol IPv4 + /// packets that get through the receive filters. + /// BOOLEAN AcceptAnyProtocol; + /// + /// Set to TRUE to receive ICMP error report packets. Ignored when + /// AcceptPromiscuous or AcceptAnyProtocol is TRUE. + /// BOOLEAN AcceptIcmpErrors; + /// + /// Set to TRUE to receive broadcast IPv4 packets. Ignored when + /// AcceptPromiscuous is TRUE. + /// Set to FALSE to stop receiving broadcast IPv4 packets. + /// BOOLEAN AcceptBroadcast; + /// + /// Set to TRUE to receive all IPv4 packets that are sent to any + /// hardware address or any protocol address. + /// Set to FALSE to stop receiving all promiscuous IPv4 packets + /// BOOLEAN AcceptPromiscuous; + /// + /// Set to TRUE to use the default IPv4 address and default routing table. + /// BOOLEAN UseDefaultAddress; + /// + /// The station IPv4 address that will be assigned to this EFI IPv4Protocol instance. + /// EFI_IPv4_ADDRESS StationAddress; + /// + /// The subnet address mask that is associated with the station address. + /// EFI_IPv4_ADDRESS SubnetMask; + /// + /// TypeOfService field in transmitted IPv4 packets. + /// UINT8 TypeOfService; + /// + /// TimeToLive field in transmitted IPv4 packets. + /// UINT8 TimeToLive; + /// + /// State of the DoNotFragment bit in transmitted IPv4 packets. + /// BOOLEAN DoNotFragment; + /// + /// Set to TRUE to send and receive unformatted packets. The other + /// IPv4 receive filters are still applied. Fragmentation is disabled for RawData mode. + /// BOOLEAN RawData; + /// + /// The timer timeout value (number of microseconds) for the + /// receive timeout event to be associated with each assembled + /// packet. Zero means do not drop assembled packets. + /// UINT32 ReceiveTimeout; + /// + /// The timer timeout value (number of microseconds) for the + /// transmit timeout event to be associated with each outgoing + /// packet. Zero means do not drop outgoing packets. + /// UINT32 TransmitTimeout; } EFI_IP4_CONFIG_DATA; @@ -81,14 +136,41 @@ typedef struct { } EFI_IP4_ICMP_TYPE; typedef struct { + /// + /// Set to TRUE after this EFI IPv4 Protocol instance has been successfully configured. + /// BOOLEAN IsStarted; + /// + /// Current configuration settings. + /// EFI_IP4_CONFIG_DATA ConfigData; + /// + /// Set to TRUE when the EFI IPv4 Protocol instance has a station address and subnet mask. + /// BOOLEAN IsConfigured; + /// + /// Number of joined multicast groups. + /// UINT32 GroupCount; + /// + /// List of joined multicast group addresses. + /// EFI_IPv4_ADDRESS *GroupTable; + /// + /// Number of entries in the routing table. + /// UINT32 RouteCount; + /// + /// Routing table entries. + /// EFI_IP4_ROUTE_TABLE *RouteTable; + /// + /// Number of entries in the supported ICMP types list. + /// UINT32 IcmpTypeCount; + /// + /// Array of ICMP types and codes that are supported by this EFI IPv4 Protocol driver + /// EFI_IP4_ICMP_TYPE *IcmpTypeList; } EFI_IP4_MODE_DATA; @@ -149,10 +231,26 @@ typedef struct { } EFI_IP4_TRANSMIT_DATA; typedef struct { + /// + /// This Event will be signaled after the Status field is updated + /// by the EFI IPv4 Protocol driver. The type of Event must be + /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// EFI_EVENT Event; + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// EFI_STATUS Status; union { + /// + /// When this token is used for receiving, RxData is a pointer to the EFI_IP4_RECEIVE_DATA. + /// EFI_IP4_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to the EFI_IP4_TRANSMIT_DATA. + /// EFI_IP4_TRANSMIT_DATA *TxData; } Packet; } EFI_IP4_COMPLETION_TOKEN; diff --git a/MdePkg/Include/Protocol/Ip4Config.h b/MdePkg/Include/Protocol/Ip4Config.h index 1871489d30..d195ba7e66 100644 --- a/MdePkg/Include/Protocol/Ip4Config.h +++ b/MdePkg/Include/Protocol/Ip4Config.h @@ -30,10 +30,22 @@ typedef struct _EFI_IP4_CONFIG_PROTOCOL EFI_IP4_CONFIG_PROTOCOL; EFI_VARIABLE_RUNTIME_ACCESS) typedef struct { + /// + /// Default station IP address, stored in network byte order. + /// EFI_IPv4_ADDRESS StationAddress; + /// + /// Default subnet mask, stored in network byte order. + /// EFI_IPv4_ADDRESS SubnetMask; + /// + /// Number of entries in the following RouteTable. May be zero. + /// UINT32 RouteTableSize; - EFI_IP4_ROUTE_TABLE *RouteTable; //OPTIONAL + /// + /// Default routing table data (stored in network byte order). + /// + EFI_IP4_ROUTE_TABLE *RouteTable; } EFI_IP4_IPCONFIG_DATA; diff --git a/MdePkg/Include/Protocol/ManagedNetwork.h b/MdePkg/Include/Protocol/ManagedNetwork.h index 8aedc7f90d..3f2d05ea7c 100644 --- a/MdePkg/Include/Protocol/ManagedNetwork.h +++ b/MdePkg/Include/Protocol/ManagedNetwork.h @@ -31,15 +31,58 @@ typedef struct _EFI_MANAGED_NETWORK_PROTOCOL EFI_MANAGED_NETWORK_PROTOCOL; typedef struct { + /// + /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed + /// from the MNP receive queue will be dropped if its receive timeout expires. + /// UINT32 ReceivedQueueTimeoutValue; + /// + /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed + /// from the MNP transmit queue will be dropped if its receive timeout expires. + /// UINT32 TransmitQueueTimeoutValue; + /// + /// Ethernet type II 16-bit protocol type in host byte order. Valid + /// values are zero and 1,500 to 65,535. + /// UINT16 ProtocolTypeFilter; + /// + /// Set to TRUE to receive packets that are sent to the network + /// device MAC address. The startup default value is FALSE. + /// BOOLEAN EnableUnicastReceive; + /// + /// Set to TRUE to receive packets that are sent to any of the + /// active multicast groups. The startup default value is FALSE. + /// BOOLEAN EnableMulticastReceive; + /// + /// Set to TRUE to receive packets that are sent to the network + /// device broadcast address. The startup default value is FALSE. + /// BOOLEAN EnableBroadcastReceive; + /// + /// Set to TRUE to receive packets that are sent to any MAC address. + /// The startup default value is FALSE. + /// BOOLEAN EnablePromiscuousReceive; + /// + /// Set to TRUE to drop queued packets when the configuration + /// is changed. The startup default value is FALSE. + /// BOOLEAN FlushQueuesOnReset; + /// + /// Set to TRUE to timestamp all packets when they are received + /// by the MNP. Note that timestamps may be unsupported in some + /// MNP implementations. The startup default value is FALSE. + /// BOOLEAN EnableReceiveTimestamps; + /// + /// Set to TRUE to disable background polling in this MNP + /// instance. Note that background polling may not be supported in + /// all MNP implementations. The startup default value is FALSE, + /// unless background polling is not supported. + /// BOOLEAN DisableBackgroundPolling; } EFI_MANAGED_NETWORK_CONFIG_DATA; @@ -77,10 +120,26 @@ typedef struct { typedef struct { + /// + /// This Event will be signaled after the Status field is updated + /// by the MNP. The type of Event must be + /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// EFI_EVENT Event; + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// EFI_STATUS Status; union { + /// + /// When this token is used for receiving, RxData is a pointer to the EFI_MANAGED_NETWORK_RECEIVE_DATA. + /// EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to the EFI_MANAGED_NETWORK_TRANSMIT_DATA. + /// EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData; } Packet; } EFI_MANAGED_NETWORK_COMPLETION_TOKEN; diff --git a/MdePkg/Include/Protocol/Mtftp4.h b/MdePkg/Include/Protocol/Mtftp4.h index f2c3084b88..15cfd98831 100644 --- a/MdePkg/Include/Protocol/Mtftp4.h +++ b/MdePkg/Include/Protocol/Mtftp4.h @@ -98,14 +98,41 @@ typedef struct { } EFI_MTFTP4_ERROR_HEADER; typedef union { + /// + /// Type of packets as defined by the MTFTPv4 packet opcodes. + /// UINT16 OpCode; + /// + /// Read request packet header. + /// EFI_MTFTP4_REQ_HEADER Rrq; + /// + /// Write request packet header. + /// EFI_MTFTP4_REQ_HEADER Wrq; + /// + /// Option acknowledge packet header. + /// EFI_MTFTP4_OACK_HEADER Oack; + /// + /// Data packet header. + /// EFI_MTFTP4_DATA_HEADER Data; + /// + /// Acknowledgement packet header. + /// EFI_MTFTP4_ACK_HEADER Ack; + /// + /// Data packet header with big block number. + /// EFI_MTFTP4_DATA8_HEADER Data8; + /// + /// Acknowledgement header with big block num. + /// EFI_MTFTP4_ACK8_HEADER Ack8; + /// + /// Error packet header. + /// EFI_MTFTP4_ERROR_HEADER Error; } EFI_MTFTP4_PACKET; @@ -477,17 +504,60 @@ struct _EFI_MTFTP4_PROTOCOL { }; struct _EFI_MTFTP4_TOKEN { + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// EFI_STATUS Status; + /// + /// The event that will be signaled when the operation completes. If + /// set to NULL, the corresponding function will wait until the read or + /// write operation finishes. The type of Event must be + /// EVT_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// EFI_EVENT Event; + /// + /// If not NULL, the data that will be used to override the existing configure data. + /// EFI_MTFTP4_OVERRIDE_DATA *OverrideData; + /// + /// Pointer to the ASCIIZ file name string. + /// UINT8 *Filename; + /// + /// Pointer to the ASCIIZ mode string. If NULL, ¡°octet¡± is used. + /// UINT8 *ModeStr; + /// + /// Number of option/value string pairs. + /// UINT32 OptionCount; + /// + /// Pointer to an array of option/value string pairs. Ignored if OptionCount is zero. + /// EFI_MTFTP4_OPTION *OptionList; + /// + /// Size of the data buffer. + /// OUT UINT64 BufferSize; + /// + /// Pointer to the data buffer. Data that is downloaded from the + /// MTFTPv4 server is stored here. Data that is uploaded to the + /// MTFTPv4 server is read from here. Ignored if BufferSize is zero. + /// OUT VOID *Buffer; + /// + /// Pointer to the callback function to check the contents of the received packet. + /// EFI_MTFTP4_CHECK_PACKET CheckPacket; + /// + /// Pointer to the function to be called when a timeout occurs. + /// EFI_MTFTP4_TIMEOUT_CALLBACK TimeoutCallback; + /// + /// Pointer to the function to provide the needed packet contents. + /// EFI_MTFTP4_PACKET_NEEDED PacketNeeded; }; diff --git a/MdePkg/Include/Protocol/PciIo.h b/MdePkg/Include/Protocol/PciIo.h index 0aaa718428..2a49ea8e5a 100644 --- a/MdePkg/Include/Protocol/PciIo.h +++ b/MdePkg/Include/Protocol/PciIo.h @@ -81,8 +81,18 @@ typedef enum { /// ******************************************************* /// typedef enum { + /// + /// A read operation from system memory by a bus master. + /// EfiPciIoOperationBusMasterRead, + /// + /// A write operation from system memory by a bus master. + /// EfiPciIoOperationBusMasterWrite, + /// + /// Provides both read and write access to system memory by both the processor and a + /// bus master. The buffer is coherent from both the processor¡¯s and the bus master's point of view. + /// EfiPciIoOperationBusMasterCommonBuffer, EfiPciIoOperationMaximum } EFI_PCI_IO_PROTOCOL_OPERATION; @@ -93,10 +103,25 @@ typedef enum { /// ******************************************************* /// typedef enum { + /// + /// Retrieve the PCI controller¡¯s current attributes, and return them in Result. + /// EfiPciIoAttributeOperationGet, + /// + /// Set the PCI controller¡¯s current attributes to Attributes. + /// EfiPciIoAttributeOperationSet, + /// + /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller. + /// EfiPciIoAttributeOperationEnable, + /// + /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller. + /// EfiPciIoAttributeOperationDisable, + /// + /// Retrieve the PCI controller's supported attributes, and return them in Result. + /// EfiPciIoAttributeOperationSupported, EfiPciIoAttributeOperationMaximum } EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION; @@ -168,7 +193,13 @@ EFI_STATUS ); typedef struct { + /// + /// Read PCI controller registers in the PCI memory or I/O space. + /// EFI_PCI_IO_PROTOCOL_IO_MEM Read; + /// + /// Write PCI controller registers in the PCI memory or I/O space. + /// EFI_PCI_IO_PROTOCOL_IO_MEM Write; } EFI_PCI_IO_PROTOCOL_ACCESS; @@ -201,7 +232,13 @@ EFI_STATUS ); typedef struct { + /// + /// Read PCI controller registers in PCI configuration space. + /// EFI_PCI_IO_PROTOCOL_CONFIG Read; + /// + /// Write PCI controller registers in PCI configuration space. + /// EFI_PCI_IO_PROTOCOL_CONFIG Write; } EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h index a563f94aef..970aee0642 100644 --- a/MdePkg/Include/Protocol/PciRootBridgeIo.h +++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h @@ -169,7 +169,13 @@ EFI_STATUS ); typedef struct { + /// + /// Read PCI controller registers in the PCI root bridge memory space. + /// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read; + /// + /// Write PCI controller registers in the PCI root bridge memory space. + /// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write; } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS; diff --git a/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h b/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h index f8267d8610..26b1503582 100644 --- a/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h +++ b/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h @@ -25,24 +25,24 @@ 0x245dca21, 0xfb7b, 0x11d3, {0x8f, 0x01, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ } -// -// UEFI Revision Number Definition -// +/// +/// UEFI Revision Number Definition +/// #define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION 0x00010000 -// -// EFI 1.1 Revision Number defintion -// +/// +/// EFI 1.1 Revision Number defintion +/// #define EFI_PXE_BASE_CODE_CALLBACK_INTERFACE_REVISION \ EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION /// -/// Protocol definition +/// UEFI Protocol name /// typedef struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL; /// -/// Protocol defined in EFI1.1. +/// EFI1.1 Protocol name /// typedef EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK; diff --git a/MdePkg/Include/Protocol/ScsiIo.h b/MdePkg/Include/Protocol/ScsiIo.h index cf37eba5e9..e0204cce22 100644 --- a/MdePkg/Include/Protocol/ScsiIo.h +++ b/MdePkg/Include/Protocol/ScsiIo.h @@ -39,16 +39,16 @@ typedef struct _EFI_SCSI_IO_PROTOCOL EFI_SCSI_IO_PROTOCOL; // SCSI Host Adapter Status definition // #define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OK 0x00 -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09 // timeout when processing the command -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT 0x0b // timeout when waiting for the command processing -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d // a message reject was received when processing command -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_RESET 0x0e // a bus reset was detected +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09 ///< timeout when processing the command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT 0x0b ///< timeout when waiting for the command processing +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d ///< a message reject was received when processing command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_RESET 0x0e ///< a bus reset was detected #define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10 // the adapter failed in issuing request sense command -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11 // selection timeout -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12 // data overrun or data underrun -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_FREE 0x13 // Unexepected bus free -#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 // Target bus phase sequence failure +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10 ///< the adapter failed in issuing request sense command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11 ///< selection timeout +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12 ///< data overrun or data underrun +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_FREE 0x13 ///< Unexepected bus free +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 ///< Target bus phase sequence failure #define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OTHER 0x7f @@ -56,27 +56,80 @@ typedef struct _EFI_SCSI_IO_PROTOCOL EFI_SCSI_IO_PROTOCOL; // SCSI Target Status definition // #define EFI_SCSI_IO_STATUS_TARGET_GOOD 0x00 -#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02 // check condition -#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04 // condition met -#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08 // busy -#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10 // intermediate -#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 // intermediate-condition met -#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18 // reservation conflict -#define EFI_SCSI_IO_STATUS_TARGET_COMMOND_TERMINATED 0x22 // command terminated -#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28 // queue full +#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02 ///< check condition +#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04 ///< condition met +#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08 ///< busy +#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10 ///< intermediate +#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 ///< intermediate-condition met +#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18 ///< reservation conflict +#define EFI_SCSI_IO_STATUS_TARGET_COMMOND_TERMINATED 0x22 ///< command terminated +#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28 ///< queue full typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI Request + /// Packet is greater than Timeout. + /// UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for SCSI READ command + /// VOID *InDataBuffer; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for SCSI WRITE command. + /// VOID *OutDataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device. + /// VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// UINT32 InTransferLength; + /// + /// On Input, the size, in bytes of OutDataBuffer. On Output, the + /// Number of bytes transferred between SCSI Controller and the SCSI device. + /// UINT32 OutTransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are + /// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// UINT8 DataDirection; + /// + /// The status of the SCSI Host Controller that produces the SCSI + /// bus where the SCSI device attached when the SCSI Request + /// Packet was executed on the SCSI Controller. + /// UINT8 HostAdapterStatus; + /// + /// The status returned by the SCSI device when the SCSI Request + /// Packet was executed. + /// UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// UINT8 SenseDataLength; } EFI_SCSI_IO_SCSI_REQUEST_PACKET; diff --git a/MdePkg/Include/Protocol/ScsiPassThru.h b/MdePkg/Include/Protocol/ScsiPassThru.h index ee498e0ec3..1790c1af43 100644 --- a/MdePkg/Include/Protocol/ScsiPassThru.h +++ b/MdePkg/Include/Protocol/ScsiPassThru.h @@ -66,23 +66,85 @@ typedef struct _EFI_SCSI_PASS_THRU_PROTOCOL EFI_SCSI_PASS_THRU_PROTOCOL; #define EFI_SCSI_STATUS_TARGET_QUEUE_FULL 0x28 // queue full typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI Request + /// Packet is greater than Timeout. + /// UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device. Must be aligned to the boundary + /// specified in the IoAlign field of the + /// EFI_SCSI_PASS_THRU_MODE structure. + /// VOID *DataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device. + /// VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// UINT32 TransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are + /// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// UINT8 DataDirection; + /// + /// The status of the SCSI Host Controller that produces the SCSI + /// bus where the SCSI device attached when the SCSI Request + /// Packet was executed on the SCSI Controller. + /// UINT8 HostAdapterStatus; + /// + /// The status returned by the SCSI device when the SCSI Request + /// Packet was executed. + /// UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// UINT8 SenseDataLength; } EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET; typedef struct { + /// + /// A Null-terminated Unicode string that represents the printable name of the SCSI controller. + /// CHAR16 *ControllerName; + /// + /// A Null-terminated Unicode string that represents the printable name of the SCSI channel. + /// CHAR16 *ChannelName; + /// + /// The Target ID of the host adapter on the SCSI channel. + /// UINT32 AdapterId; + /// + /// Additional information on the attributes of the SCSI channel. + /// UINT32 Attributes; + /// + /// Supplies the alignment requirement for any buffer used in a data transfer. + /// UINT32 IoAlign; } EFI_SCSI_PASS_THRU_MODE; diff --git a/MdePkg/Include/Protocol/ScsiPassThruExt.h b/MdePkg/Include/Protocol/ScsiPassThruExt.h index d63f056c5a..7ec0dd9737 100644 --- a/MdePkg/Include/Protocol/ScsiPassThruExt.h +++ b/MdePkg/Include/Protocol/ScsiPassThruExt.h @@ -66,23 +66,84 @@ typedef struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL EFI_EXT_SCSI_PASS_THRU_PROTOCOL; #define EFI_EXT_SCSI_STATUS_TARGET_TASK_ABORTED 0x40 typedef struct { + /// + /// The Target ID of the host adapter on the SCSI channel. + /// UINT32 AdapterId; + /// + /// Additional information on the attributes of the SCSI channel. + /// UINT32 Attributes; + /// + /// Supplies the alignment requirement for any buffer used in a data transfer. + /// UINT32 IoAlign; } EFI_EXT_SCSI_PASS_THRU_MODE; typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI + /// Request Packet is greater than Timeout. + /// UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for read and bidirectional commands. + /// VOID *InDataBuffer; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for write or bidirectional commands. + /// VOID *OutDataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device specified by Target and Lun. + /// VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// UINT32 InTransferLength; + /// + /// On Input, the size, in bytes of OutDataBuffer. On Output, the + /// Number of bytes transferred between SCSI Controller and the SCSI device. + /// UINT32 OutTransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are 6, + /// 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// UINT8 DataDirection; + /// + /// The status of the host adapter specified by This when the SCSI + /// Request Packet was executed on the target device. + /// UINT8 HostAdapterStatus; + /// + /// The status returned by the device specified by Target and Lun + /// when the SCSI Request Packet was executed. + /// UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// UINT8 SenseDataLength; } EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET; diff --git a/MdePkg/Include/Protocol/SimpleFileSystem.h b/MdePkg/Include/Protocol/SimpleFileSystem.h index eb850be94f..ddfbebb80c 100644 --- a/MdePkg/Include/Protocol/SimpleFileSystem.h +++ b/MdePkg/Include/Protocol/SimpleFileSystem.h @@ -31,14 +31,13 @@ typedef struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL typedef struct _EFI_FILE_PROTOCOL EFI_FILE_PROTOCOL; typedef struct _EFI_FILE_PROTOCOL *EFI_FILE_HANDLE; - /// -/// Protocol GUID defined in EFI1.1. +/// Protocol GUID name defined in EFI1.1. /// #define SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID /// -/// Protocol defined in EFI1.1. +/// Protocol name defined in EFI1.1. /// typedef EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_FILE_IO_INTERFACE; typedef struct _EFI_FILE_PROTOCOL EFI_FILE; @@ -66,12 +65,18 @@ EFI_STATUS ); #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000 + /// /// Revision defined in EFI1.1 /// #define EFI_FILE_IO_INTERFACE_REVISION EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL { + /// + /// The version of the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. The version + /// specified by this specification is 0x00010000. All future revisions + /// must be backwards compatible. + /// UINT64 Revision; EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME OpenVolume; }; diff --git a/MdePkg/Include/Protocol/SimpleNetwork.h b/MdePkg/Include/Protocol/SimpleNetwork.h index 252c5bd492..1d9cc67bdf 100644 --- a/MdePkg/Include/Protocol/SimpleNetwork.h +++ b/MdePkg/Include/Protocol/SimpleNetwork.h @@ -144,24 +144,84 @@ typedef enum { #define MAX_MCAST_FILTER_CNT 16 typedef struct { + /// + /// Reports the current state of the network interface. + /// UINT32 State; + /// + /// The size, in bytes, of the network interface's HW address. + /// UINT32 HwAddressSize; + /// + /// The size, in bytes, of the network interface's media header. + /// UINT32 MediaHeaderSize; + /// + /// The maximum size, in bytes, of the packets supported by the network interface. + /// UINT32 MaxPacketSize; + /// + /// The size, in bytes, of the NVRAM device attached to the network interface. + /// UINT32 NvRamSize; + /// + /// The size that must be used for all NVRAM reads and writes. The + /// start address for NVRAM read and write operations and the total + /// length of those operations, must be a multiple of this value. The + /// legal values for this field are 0, 1, 2, 4, and 8. + /// UINT32 NvRamAccessSize; + /// + /// The multicast receive filter settings supported by the network interface. + /// UINT32 ReceiveFilterMask; + /// + /// The current multicast receive filter settings. + /// UINT32 ReceiveFilterSetting; + /// + /// The maximum number of multicast address receive filters supported by the driver. + /// UINT32 MaxMCastFilterCount; + /// + /// The current number of multicast address receive filters. + /// UINT32 MCastFilterCount; + /// + /// Array containing the addresses of the current multicast address receive filters. + /// EFI_MAC_ADDRESS MCastFilter[MAX_MCAST_FILTER_CNT]; + /// + /// The current HW MAC address for the network interface. + /// EFI_MAC_ADDRESS CurrentAddress; + /// + /// The current HW MAC address for broadcast packets. + /// EFI_MAC_ADDRESS BroadcastAddress; + /// + /// The permanent HW MAC address for the network interface. + /// EFI_MAC_ADDRESS PermanentAddress; + /// + /// The interface type of the network interface. + /// UINT8 IfType; + /// + /// TRUE if the HW MAC address can be changed. + /// BOOLEAN MacAddressChangeable; + /// + /// TRUE if the network interface can transmit more than one packet at a time. + /// BOOLEAN MultipleTxSupported; + /// + /// TRUE if the presence of media can be determined; otherwise FALSE. + /// BOOLEAN MediaPresentSupported; + /// + /// TRUE if media are connected to the network interface; otherwise FALSE. + /// BOOLEAN MediaPresent; } EFI_SIMPLE_NETWORK_MODE; diff --git a/MdePkg/Include/Protocol/SimplePointer.h b/MdePkg/Include/Protocol/SimplePointer.h index 5d22bf6e44..9b5fb3127b 100644 --- a/MdePkg/Include/Protocol/SimplePointer.h +++ b/MdePkg/Include/Protocol/SimplePointer.h @@ -28,18 +28,53 @@ typedef struct _EFI_SIMPLE_POINTER_PROTOCOL EFI_SIMPLE_POINTER_PROTOCOL; // Data structures // typedef struct { + /// + /// The signed distance in counts that the pointer device has been moved along the x-axis. + /// INT32 RelativeMovementX; + /// + /// The signed distance in counts that the pointer device has been moved along the y-axis. + /// INT32 RelativeMovementY; + /// + /// The signed distance in counts that the pointer device has been moved along the z-axis. + /// INT32 RelativeMovementZ; + /// + /// If TRUE, then the left button of the pointer device is being + /// pressed. If FALSE, then the left button of the pointer device is not being pressed. + /// BOOLEAN LeftButton; + /// + /// If TRUE, then the right button of the pointer device is being + /// pressed. If FALSE, then the right button of the pointer device is not being pressed. + /// BOOLEAN RightButton; } EFI_SIMPLE_POINTER_STATE; typedef struct { + /// + /// The resolution of the pointer device on the x-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// UINT64 ResolutionX; + /// + /// The resolution of the pointer device on the y-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// UINT64 ResolutionY; + /// + /// The resolution of the pointer device on the z-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// UINT64 ResolutionZ; + /// + /// TRUE if a left button is present on the pointer device. Otherwise FALSE. + /// BOOLEAN LeftButton; + /// + /// TRUE if a right button is present on the pointer device. Otherwise FALSE. + /// BOOLEAN RightButton; } EFI_SIMPLE_POINTER_MODE; diff --git a/MdePkg/Include/Protocol/SimpleTextIn.h b/MdePkg/Include/Protocol/SimpleTextIn.h index 0716b73674..67786cefe9 100644 --- a/MdePkg/Include/Protocol/SimpleTextIn.h +++ b/MdePkg/Include/Protocol/SimpleTextIn.h @@ -25,20 +25,21 @@ 0x387477c1, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ } +typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL; + /// -/// Protocol GUID defined in EFI1.1. +/// Protocol GUID name defined in EFI1.1. /// #define SIMPLE_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID -typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL; - /// -/// Backward-compatible with EFI1.1. +/// Protocol name in EFI1.1 for backward-compatible. /// typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL SIMPLE_INPUT_INTERFACE; -// -// Data structures -// + +/// +/// The keystroke information for the key that was pressed. +/// typedef struct { UINT16 ScanCode; CHAR16 UnicodeChar; diff --git a/MdePkg/Include/Protocol/SimpleTextInEx.h b/MdePkg/Include/Protocol/SimpleTextInEx.h index 8dcb5e1419..95c5995ce8 100644 --- a/MdePkg/Include/Protocol/SimpleTextInEx.h +++ b/MdePkg/Include/Protocol/SimpleTextInEx.h @@ -60,42 +60,38 @@ EFI_STATUS ); -// -// EFI_KEY_TOGGLE_STATE -// +/// +/// EFI_KEY_TOGGLE_STATE. The toggle state are defined. +/// They are EFI_TOGGLE_STATE_VALID, EFI_SCROLL_LOCK_ACTIVE +/// EFI_NUM_LOCK_ACTIVE, EFI_CAPS_LOCK_ACTIVE +/// typedef UINT8 EFI_KEY_TOGGLE_STATE; -/** - Definition of EFI_KEY_STATE - - @param KeyShiftState Reflects the currently pressed shift - modifiers for the input device. The - returned value is valid only if the high - order bit has been set. - - @param KeyToggleState Reflects the current internal state of - various toggled attributes. The returned - value is valid only if the high order - bit has been set. - -**/ typedef struct _EFI_KEY_STATE { + /// + /// Reflects the currently pressed shift + /// modifiers for the input device. The + /// returned value is valid only if the high + /// order bit has been set. + /// UINT32 KeyShiftState; + /// + /// Reflects the current internal state of + /// various toggled attributes. The returned + /// value is valid only if the high order + /// bit has been set. + /// EFI_KEY_TOGGLE_STATE KeyToggleState; } EFI_KEY_STATE; -/** - Definition of EFI_KEY_DATA. - - @param Key The EFI scan code and Unicode value returned from - the input device. - - @param KeyState The current state of various toggled - attributes as well as input modifier values. - -**/ typedef struct { + /// + /// The EFI scan code and Unicode value returned from the input device. + /// EFI_INPUT_KEY Key; + /// + /// The current state of various toggled attributes as well as input modifier values. + /// EFI_KEY_STATE KeyState; } EFI_KEY_DATA; @@ -234,9 +230,9 @@ EFI_STATUS IN EFI_KEY_TOGGLE_STATE *KeyToggleState ); -// -// EFI_KEY_NOTIFY -// +/// +/// The function will be called when the key sequence is typed specified by KeyData. +/// typedef EFI_STATUS (EFIAPI *EFI_KEY_NOTIFY_FUNCTION)( diff --git a/MdePkg/Include/Protocol/SmbusHc.h b/MdePkg/Include/Protocol/SmbusHc.h index 67a174eec6..5431c49d5e 100644 --- a/MdePkg/Include/Protocol/SmbusHc.h +++ b/MdePkg/Include/Protocol/SmbusHc.h @@ -19,7 +19,7 @@ #ifndef __SMBUS_HC_H__ #define __SMBUS_HC_H__ -#include +#include #define EFI_SMBUS_HC_PROTOCOL_GUID \ {0xe49d33ed, 0x513d, 0x4634, { 0xb6, 0x98, 0x6f, 0x55, 0xaa, 0x75, 0x1c, 0x1b} } diff --git a/MdePkg/Include/Protocol/TcgService.h b/MdePkg/Include/Protocol/TcgService.h index 1c9c149d14..1f378535cf 100644 --- a/MdePkg/Include/Protocol/TcgService.h +++ b/MdePkg/Include/Protocol/TcgService.h @@ -23,9 +23,6 @@ typedef struct _EFI_TCG_PROTOCOL EFI_TCG_PROTOCOL; -// -// Set structure alignment to 1-byte -// typedef struct { UINT8 Major; UINT8 Minor; @@ -34,13 +31,13 @@ typedef struct { } TCG_VERSION; typedef struct _TCG_EFI_BOOT_SERVICE_CAPABILITY { - UINT8 Size; // Size of this structure + UINT8 Size; /// Size of this structure TCG_VERSION StructureVersion; TCG_VERSION ProtocolSpecVersion; - UINT8 HashAlgorithmBitmap; // Hash algorithms - // this protocol is capable of : 01=SHA-1 - BOOLEAN TPMPresentFlag; // 00h = TPM not present - BOOLEAN TPMDeactivatedFlag; // 01h = TPM currently deactivated + UINT8 HashAlgorithmBitmap; /// Hash algorithms + /// this protocol is capable of : 01=SHA-1 + BOOLEAN TPMPresentFlag; /// 00h = TPM not present + BOOLEAN TPMDeactivatedFlag; /// 01h = TPM currently deactivated } TCG_EFI_BOOT_SERVICE_CAPABILITY; typedef UINT32 TCG_ALGORITHM_ID; diff --git a/MdePkg/Include/Protocol/Usb2HostController.h b/MdePkg/Include/Protocol/Usb2HostController.h index 6687e323aa..bb550a381d 100644 --- a/MdePkg/Include/Protocol/Usb2HostController.h +++ b/MdePkg/Include/Protocol/Usb2HostController.h @@ -33,8 +33,8 @@ typedef struct _EFI_USB2_HC_PROTOCOL EFI_USB2_HC_PROTOCOL; typedef struct { - UINT16 PortStatus; /// Contains current port status bitmap. - UINT16 PortChangeStatus; /// Contains current port status change bitmap. + UINT16 PortStatus; ///< Contains current port status bitmap. + UINT16 PortChangeStatus; ///< Contains current port status change bitmap. } EFI_USB_PORT_STATUS; /// @@ -78,13 +78,13 @@ typedef enum { EfiUsbPortResetChange = 20 } EFI_USB_PORT_FEATURE; -#define EFI_USB_SPEED_FULL 0x0000 /// 12 Mb/s, USB 1.1 OHCI and UHCI HC. -#define EFI_USB_SPEED_LOW 0x0001 /// 1 Mb/s, USB 1.1 OHCI and UHCI HC. -#define EFI_USB_SPEED_HIGH 0x0002 /// 480 Mb/s, USB 2.0 EHCI HC. +#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC. +#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC. +#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC. typedef struct { - UINT8 TranslatorHubAddress; /// device address - UINT8 TranslatorPortNumber; /// the port number of the hub that device is connected to. + UINT8 TranslatorHubAddress; ///< device address + UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to. } EFI_USB2_HC_TRANSACTION_TRANSLATOR; // diff --git a/MdePkg/Include/Protocol/UsbIo.h b/MdePkg/Include/Protocol/UsbIo.h index 0c5bd70445..e29f60b19c 100644 --- a/MdePkg/Include/Protocol/UsbIo.h +++ b/MdePkg/Include/Protocol/UsbIo.h @@ -44,9 +44,9 @@ typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR; typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR; typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR; -// -// USB data transfer direction -// +/// +/// USB data transfer direction +/// typedef enum { EfiUsbDataIn, EfiUsbDataOut, diff --git a/MdePkg/Include/Uefi/UefiTcgPlatform.h b/MdePkg/Include/Uefi/UefiTcgPlatform.h index 4545f8fc2e..c99a905ed7 100644 --- a/MdePkg/Include/Uefi/UefiTcgPlatform.h +++ b/MdePkg/Include/Uefi/UefiTcgPlatform.h @@ -58,10 +58,8 @@ #pragma pack (1) typedef UINT32 TCG_EVENTTYPE; - -#define TCG_DIGEST TPM_DIGEST -#define TCG_PCRINDEX TPM_PCRINDEX - +typedef TPM_PCRINDEX TCG_PCRINDEX; +typedef TPM_DIGEST TCG_DIGEST; /// /// Event Log Entry Structure Definition ///