From: vanjeff Date: Tue, 7 Jul 2009 04:00:44 +0000 (+0000) Subject: Retired PciIncompatibleDeviceSupportLib from IntelFrameworkModulePkg. X-Git-Tag: edk2-stable201903~17535 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=9eb130ff8cd00411d5b84a7950bf03fa93ed267c Retired PciIncompatibleDeviceSupportLib from IntelFrameworkModulePkg. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8773 6f19259b-4bc3-4df7-8a09-765794883524 --- diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h index a587d9ee97..df224d12c4 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -41,7 +41,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include #include #include -#include #include #include diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 14fb83e6c4..a3a13d55a0 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -73,7 +73,6 @@ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec [LibraryClasses] - PciIncompatibleDeviceSupportLib PcdLib DevicePathLib UefiBootServicesTableLib @@ -103,9 +102,6 @@ [FeaturePcd.common] gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport -[Pcd.common] - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask - # [Event] # ## # # Notify event set by CreateEventForHpc () for PCI Hot Plug controller. diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c index ab9d3a0025..39f5271e9b 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c @@ -43,13 +43,13 @@ PciOperateRegister ( PciIo = &PciIoDevice->PciIo; if (Operation != EFI_SET_REGISTER) { - Status = PciIoRead ( - PciIo, - EfiPciIoWidthUint16, - Offset, - 1, - &OldCommand - ); + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &OldCommand + ); if (Operation == EFI_GET_REGISTER) { *PtrCommand = OldCommand; @@ -65,13 +65,13 @@ PciOperateRegister ( OldCommand = Command; } - return PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - Offset, - 1, - &OldCommand - ); + return PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &OldCommand + ); } /** @@ -134,33 +134,33 @@ LocateCapabilityRegBlock ( CapabilityPtr = 0; if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) { - PciIoRead ( - &PciIoDevice->PciIo, - EfiPciIoWidthUint8, - EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR, - 1, - &CapabilityPtr - ); + PciIoDevice->PciIo.Pci.Read ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint8, + EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR, + 1, + &CapabilityPtr + ); } else { - PciIoRead ( - &PciIoDevice->PciIo, - EfiPciIoWidthUint8, - PCI_CAPBILITY_POINTER_OFFSET, - 1, - &CapabilityPtr - ); + PciIoDevice->PciIo.Pci.Read ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint8, + PCI_CAPBILITY_POINTER_OFFSET, + 1, + &CapabilityPtr + ); } } while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) { - PciIoRead ( - &PciIoDevice->PciIo, - EfiPciIoWidthUint16, - CapabilityPtr, - 1, - &CapabilityEntry - ); + PciIoDevice->PciIo.Pci.Read ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + CapabilityPtr, + 1, + &CapabilityEntry + ); CapabilityID = (UINT8) CapabilityEntry; diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index 71a5cb3810..40bef06868 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -250,7 +250,7 @@ RegisterPciDevice ( // PciIo = &(PciIoDevice->PciIo); Data8 = PCI_INT_LINE_UNKNOWN; - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8); // // Process OpRom diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c index 8ee4b65106..bc4f8504aa 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c @@ -341,9 +341,8 @@ PciAssignBusNumber ( Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint16, Address, 1, @@ -354,9 +353,8 @@ PciAssignBusNumber ( // Initialize SubBusNumber to SecondBus // Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint8, Address, 1, @@ -368,9 +366,8 @@ PciAssignBusNumber ( if (IS_PCI_BRIDGE (&Pci)) { Register8 = 0xFF; - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint8, Address, 1, @@ -393,9 +390,8 @@ PciAssignBusNumber ( // Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint8, Address, 1, @@ -1083,16 +1079,11 @@ ConstructAcpiResourceRequestor ( // If there is at least one type of resource request, // allocate a acpi resource node // - Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); if (Configuration == NULL) { return EFI_OUT_OF_RESOURCES; } - ZeroMem ( - Configuration, - sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) - ); - Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; // @@ -1221,13 +1212,11 @@ ConstructAcpiResourceRequestor ( // // If there is no resource request // - Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); if (Configuration == NULL) { return EFI_OUT_OF_RESOURCES; } - ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration); Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; @@ -1356,7 +1345,7 @@ PciBridgeEnumerator ( SubBusNumber = 0; StartBusNumber = 0; PciIo = &(BridgeDev->PciIo); - Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber); + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber); if (EFI_ERROR (Status)) { return Status; diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 445d1cbbbc..c3157d4374 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -47,27 +47,25 @@ PciDevicePresent ( // // Read the Vendor ID register // - Status = PciRootBridgeIoRead ( - PciRootBridgeIo, - NULL, - EfiPciWidthUint32, - Address, - 1, - Pci - ); + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) { // // Read the entire config header for the device // - Status = PciRootBridgeIoRead ( - PciRootBridgeIo, - NULL, - EfiPciWidthUint32, - Address, - sizeof (PCI_TYPE00) / sizeof (UINT32), - Pci - ); + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + sizeof (PCI_TYPE00) / sizeof (UINT32), + Pci + ); return EFI_SUCCESS; } @@ -149,7 +147,7 @@ PciPciDeviceInfoCollector ( // PciIo = &(PciIoDevice->PciIo); - Status = PciIoRead (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus); + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus); if (EFI_ERROR (Status)) { return Status; @@ -446,10 +444,10 @@ GatherPpbInfo ( // // Test whether it support 32 decode or not // - PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); - PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value); - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); if (Value != 0) { if ((Value & 0x01) != 0) { @@ -629,20 +627,20 @@ BarExisted ( // // Preserve the original value // - PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); // // Raise TPL to high level to disable timer interrupt while the BAR is probed // OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); - PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); - PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value); // // Write back the original value // - PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); // // Restore TPL to its original level @@ -860,7 +858,7 @@ GetFastBackToBackSupport ( // Read the status register // PciIo = &PciIoDevice->PciIo; - Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister); + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister); if (EFI_ERROR (Status)) { return EFI_UNSUPPORTED; } @@ -1049,23 +1047,22 @@ DetermineDeviceAttribute ( /** This routine is used to update the bar information for those incompatible PCI device. - @param PciIoDevice Pci device instance. + @param PciIoDevice Input Pci device instance. Output Pci device instance with updated + Bar information. @retval EFI_SUCCESS Successfully updated bar information. @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list. - @retval other Failed to check incompatibility device. **/ EFI_STATUS UpdatePciInfo ( - IN PCI_IO_DEVICE *PciIoDevice + IN OUT PCI_IO_DEVICE *PciIoDevice ) { EFI_STATUS Status; UINTN BarIndex; UINTN BarEndIndex; BOOLEAN SetFlag; - EFI_PCI_DEVICE_INFO PciDeviceInfo; VOID *Configuration; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; @@ -1100,22 +1097,6 @@ UpdatePciInfo ( } - if (EFI_ERROR (Status)) { - // - // Check whether the device belongs to incompatible devices from library or not - // If it is , then get its special requirement in the ACPI table - // - if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) { - PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId; - PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId; - PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID; - PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID; - PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID; - - Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration); - } - } - if (EFI_ERROR (Status) || Configuration == NULL ) { return EFI_UNSUPPORTED; } @@ -1193,9 +1174,7 @@ UpdatePciInfo ( Ptr++; } - if (Configuration != NULL) { - FreePool (Configuration); - } + FreePool (Configuration); return EFI_SUCCESS; } @@ -1203,14 +1182,14 @@ UpdatePciInfo ( /** This routine will update the alignment with the new alignment. - @param Alignment Old alignment. + @param Alignment Input Old alignment. Output updated alignment. @param NewAlignment New alignment. **/ VOID SetNewAlign ( - IN UINT64 *Alignment, - IN UINT64 NewAlignment + IN OUT UINT64 *Alignment, + IN UINT64 NewAlignment ) { UINT64 OldAlignment; @@ -1298,11 +1277,11 @@ PciParseBar ( Value = 0; Status = BarExisted ( - PciIoDevice, - Offset, - &Value, - &OriginalValue - ); + PciIoDevice, + Offset, + &Value, + &OriginalValue + ); if (EFI_ERROR (Status)) { PciIoDevice->PciBar[BarIndex].BaseAddress = 0; @@ -1400,11 +1379,11 @@ PciParseBar ( Offset += 4; Status = BarExisted ( - PciIoDevice, - Offset, - &Value, - &OriginalValue - ); + PciIoDevice, + Offset, + &Value, + &OriginalValue + ); if (EFI_ERROR (Status)) { return Offset + 4; @@ -1482,7 +1461,7 @@ InitializePciDevice ( // has not been alloacted // for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { - PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne); } } @@ -1506,28 +1485,28 @@ InitializePpb ( // Io32, pMem32, pMem64 to quiescent state // Resource base all ones, Resource limit all zeros // - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero); // - // don't support use io32 as for now + // Don't support use io32 as for now // - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero); // // Force Interrupt line to zero for cards that come up randomly // - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); } /** @@ -1550,22 +1529,22 @@ InitializeP2C ( // Io32, pMem32, pMem64 to quiescent state( // Resource base all ones, Resource limit all zeros // - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne); - PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero); // // Force Interrupt line to zero for cards that come up randomly // - PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); } /** @@ -1722,9 +1701,9 @@ PciEnumeratorLight ( RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo; Status = PciPciDeviceInfoCollector ( - RootBridgeDev, - (UINT8) MinBus - ); + RootBridgeDev, + (UINT8) MinBus + ); if (!EFI_ERROR (Status)) { @@ -1995,25 +1974,24 @@ ResetAllPpbBusNumber ( // Check to see whether a pci device is present // Status = PciDevicePresent ( - PciRootBridgeIo, - &Pci, - StartBusNumber, - Device, - Func - ); + PciRootBridgeIo, + &Pci, + StartBusNumber, + Device, + Func + ); if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) { Register = 0; Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); - Status = PciRootBridgeIoRead ( - PciRootBridgeIo, - &Pci, - EfiPciWidthUint32, - Address, - 1, - &Register - ); + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + &Register + ); SecondaryBus = (UINT8)(Register >> 8); if (SecondaryBus != 0) { @@ -2024,9 +2002,8 @@ ResetAllPpbBusNumber ( // Reset register 18h, 19h, 1Ah on PCI Bridge // Register &= 0xFF000000; - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint32, Address, 1, diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h index 3bbd5431ad..6f2f1e6ea5 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h @@ -246,29 +246,29 @@ DetermineDeviceAttribute ( /** This routine is used to update the bar information for those incompatible PCI device. - @param PciIoDevice Pci device instance. + @param PciIoDevice Input Pci device instance. Output Pci device instance with updated + Bar information. @retval EFI_SUCCESS Successfully updated bar information. @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list. - @retval other Failed to check incompatibility device. **/ EFI_STATUS UpdatePciInfo ( - IN PCI_IO_DEVICE *PciIoDevice + IN OUT PCI_IO_DEVICE *PciIoDevice ); /** This routine will update the alignment with the new alignment. - @param Alignment Old alignment. + @param Alignment Input Old alignment. Output updated alignment. @param NewAlignment New alignment. **/ VOID SetNewAlign ( - IN UINT64 *Alignment, - IN UINT64 NewAlignment + IN OUT UINT64 *Alignment, + IN UINT64 NewAlignment ); /** diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c index 5bf7ba99da..5cc5967245 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -628,12 +628,12 @@ PciIoConfigRead ( } Status = PciIoDevice->PciRootBridgeIo->Pci.Read ( - PciIoDevice->PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Address, - Count, - Buffer - ); + PciIoDevice->PciRootBridgeIo, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); if (EFI_ERROR (Status)) { ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR); @@ -1628,16 +1628,11 @@ PciIoGetBarAttributes ( NumConfig = 1; } - Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); if (Configuration == NULL) { return EFI_OUT_OF_RESOURCES; } - ZeroMem ( - Configuration, - sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) - ); - Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; if (NumConfig == 1) { diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c index 615bbaa4dc..16c0cce99a 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -37,50 +37,50 @@ GetBackPcCardBar ( // if (!gFullEnumeration) { Address = 0; - PciIoRead ( - &(PciIoDevice->PciIo), - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_BASE_0, - 1, - &Address - ); + PciIoDevice->PciIo.Pci.Read ( + &(PciIoDevice->PciIo), + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_BASE_0, + 1, + &Address + ); (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address); (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000; (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32; Address = 0; - PciIoRead ( - &(PciIoDevice->PciIo), - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_BASE_1, - 1, - &Address - ); + PciIoDevice->PciIo.Pci.Read ( + &(PciIoDevice->PciIo), + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_BASE_1, + 1, + &Address + ); (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address); (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000; (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32; Address = 0; - PciIoRead ( - &(PciIoDevice->PciIo), - EfiPciIoWidthUint32, - PCI_CARD_IO_BASE_0_LOWER, - 1, - &Address - ); + PciIoDevice->PciIo.Pci.Read ( + &(PciIoDevice->PciIo), + EfiPciIoWidthUint32, + PCI_CARD_IO_BASE_0_LOWER, + 1, + &Address + ); (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address); (PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100; (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16; Address = 0; - PciIoRead ( - &(PciIoDevice->PciIo), - EfiPciIoWidthUint32, - PCI_CARD_IO_BASE_1_LOWER, - 1, - &Address - ); + PciIoDevice->PciIo.Pci.Read ( + &(PciIoDevice->PciIo), + EfiPciIoWidthUint32, + PCI_CARD_IO_BASE_1_LOWER, + 1, + &Address + ); (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address); (PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100; (PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16; @@ -891,9 +891,8 @@ PciScanBus ( Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint16, Address, 1, @@ -912,9 +911,8 @@ PciScanBus ( // Register = 0xFF; Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint8, Address, 1, @@ -962,9 +960,8 @@ PciScanBus ( // Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &Pci, EfiPciWidthUint8, Address, 1, @@ -1117,7 +1114,7 @@ PciHostBridgeP2CProcess ( **/ EFI_STATUS PciHostBridgeEnumerator ( - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc ) { EFI_HANDLE RootBridgeHandle; @@ -1331,892 +1328,3 @@ PciHostBridgeEnumerator ( return EFI_SUCCESS; } - -/** - Read PCI device configuration register by specified address. - - This function check the incompatiblilites on PCI device. Return the register - value. - - @param PciRootBridgeIo PCI root bridge io protocol instance. - @param PciIo PCI IO protocol instance. - @param PciDeviceInfo PCI device information. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge. - @retval other Some error occurred when reading PCI device configuration space - or checking incompatibility. - -**/ -EFI_STATUS -ReadConfigData ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL - IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 Width, - IN UINT64 Offset, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT64 AccessWidth; - EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData; - UINT64 AccessAddress; - UINTN Stride; - UINT64 TempBuffer; - UINT8 *Pointer; - - ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL)); - ASSERT (Buffer != NULL); - - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) { - // - // Check access compatibility at first time - // - Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData); - - if (Status == EFI_SUCCESS) { - // - // There exists incompatibility on this operation - // - AccessWidth = Width; - - if (PciRegisterAccessData->Width != VALUE_NOCARE) { - AccessWidth = PciRegisterAccessData->Width; - } - - AccessAddress = Offset & ~((1 << AccessWidth) - 1); - - TempBuffer = 0; - Stride = 0; - Pointer = (UINT8 *) &TempBuffer; - - while (TRUE) { - - if (PciRootBridgeIo != NULL) { - Status = PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth, - AccessAddress, - 1, - Pointer - ); - } else if (PciIo != NULL) { - Status = PciIo->Pci.Read ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth, - (UINT32) AccessAddress, - 1, - Pointer - ); - } - - if (Status != EFI_SUCCESS) { - return Status; - } - - Stride = (UINTN)1 << AccessWidth; - AccessAddress += Stride; - if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) { - // - // If all datas have been read, exit - // - break; - } - - Pointer += Stride; - - if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) { - // - // If current offset doesn't reach the end - // - continue; - } - - // - // Continue checking access incompatibility - // - Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData); - if (Status == EFI_SUCCESS) { - if (PciRegisterAccessData->Width != VALUE_NOCARE) { - AccessWidth = PciRegisterAccessData->Width; - } - } - } - - switch (Width) { - case EfiPciWidthUint8: - * (UINT8 *) Buffer = (UINT8) TempBuffer; - break; - case EfiPciWidthUint16: - * (UINT16 *) Buffer = (UINT16) TempBuffer; - break; - case EfiPciWidthUint32: - * (UINT32 *) Buffer = (UINT32) TempBuffer; - break; - default: - return EFI_UNSUPPORTED; - } - - return Status; - } - } - // - // AccessWidth incompatible check not supportted - // or, there doesn't exist incompatibility on this operation - // - if (PciRootBridgeIo != NULL) { - Status = PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Offset, - 1, - Buffer - ); - - } else { - Status = PciIo->Pci.Read ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) Width, - (UINT32) Offset, - 1, - Buffer - ); - } - - return Status; -} - -/** - Update register value by checking PCI device incompatibility. - - This function check register value incompatibilites on PCI device. Return the register - value. - - @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO. - @param AccessType Access type, READ or WRITE. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space. - @param Buffer Store the register data. - - @retval EFI_SUCCESS The data has been updated. - @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge. - @retval other Some error occurred when checking incompatibility. - -**/ -EFI_STATUS -UpdateConfigData ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 AccessType, - IN UINT64 Width, - IN UINT64 Offset, - IN OUT VOID *Buffer -) -{ - EFI_STATUS Status; - EFI_PCI_REGISTER_VALUE_DATA *PciRegisterData; - UINT32 AndValue; - UINT32 OrValue; - UINT32 TempValue; - - ASSERT (Buffer != NULL); - - // - // Check register value incompatibility - // - Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData); - if (Status == EFI_SUCCESS) { - - AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8); - OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Offset & 0x3) * 8); - - TempValue = * (UINT32 *) Buffer; - if (PciRegisterData->AndValue != VALUE_NOCARE) { - TempValue &= AndValue; - } - if (PciRegisterData->OrValue != VALUE_NOCARE) { - TempValue |= OrValue; - } - - switch (Width) { - case EfiPciWidthUint8: - *(UINT8 *)Buffer = (UINT8) TempValue; - break; - - case EfiPciWidthUint16: - *(UINT16 *)Buffer = (UINT16) TempValue; - break; - case EfiPciWidthUint32: - *(UINT32 *)Buffer = TempValue; - break; - - default: - return EFI_UNSUPPORTED; - } - } - - return Status; -} - -/** - Write PCI device configuration register by specified address. - - This function check the incompatiblilites on PCI device, and write date - into register. - - @param PciRootBridgeIo PCI root bridge io instance. - @param PciIo PCI IO protocol instance. - @param PciDeviceInfo PCI device information. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval other Some error occurred when writing PCI device information - or checking incompatibility. - -**/ -EFI_STATUS -WriteConfigData ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL - IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 Width, - IN UINT64 Offset, - IN VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT64 AccessWidth; - EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData; - UINT64 AccessAddress; - UINTN Stride; - UINT8 *Pointer; - UINT64 Data; - UINTN Shift; - - ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL)); - ASSERT (Buffer != NULL); - - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) { - // - // Check access compatibility at first time - // - Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData); - - if (Status == EFI_SUCCESS) { - // - // There exists incompatibility on this operation - // - AccessWidth = Width; - - if (PciRegisterAccessData->Width != VALUE_NOCARE) { - AccessWidth = PciRegisterAccessData->Width; - } - - AccessAddress = Offset & ~((1 << AccessWidth) - 1); - - Stride = 0; - Pointer = (UINT8 *) &Buffer; - Data = * (UINT64 *) Buffer; - - while (TRUE) { - - if (AccessWidth > Width) { - // - // If actual access width is larger than orignal one, additional data need to be read back firstly - // - Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data); - if (Status != EFI_SUCCESS) { - return Status; - } - - // - // Check data read incompatibility - // - UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data); - - Shift = (UINTN)(Offset - AccessAddress) * 8; - switch (Width) { - case EfiPciWidthUint8: - Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift)); - break; - - case EfiPciWidthUint16: - Data = (* (UINT16 *) Buffer) << Shift | (Data & ~(0xffff << Shift)); - break; - } - - // - // Check data write incompatibility - // - UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data); - } - - if (PciRootBridgeIo != NULL) { - Status = PciRootBridgeIo->Pci.Write ( - PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth, - AccessAddress, - 1, - &Data - ); - } else { - Status = PciIo->Pci.Write ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth, - (UINT32) AccessAddress, - 1, - &Data - ); - } - - if (Status != EFI_SUCCESS) { - return Status; - } - - Data = RShiftU64 (Data, ((1 << AccessWidth) * 8)); - - Stride = (UINTN)1 << AccessWidth; - AccessAddress += Stride; - if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) { - // - // If all datas have been written, exit - // - break; - } - - Pointer += Stride; - - if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) { - // - // If current offset doesn't reach the end - // - continue; - } - - // - // Continue checking access incompatibility - // - Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData); - if (Status == EFI_SUCCESS) { - if (PciRegisterAccessData->Width != VALUE_NOCARE) { - AccessWidth = PciRegisterAccessData->Width; - } - } - }; - - return Status; - } - - } - // - // AccessWidth incompatible check not supportted - // or, there doesn't exist incompatibility on this operation - // - if (PciRootBridgeIo != NULL) { - Status = PciRootBridgeIo->Pci.Write ( - PciRootBridgeIo, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Offset, - 1, - Buffer - ); - } else { - Status = PciIo->Pci.Write ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) Width, - (UINT32) Offset, - 1, - Buffer - ); - } - - return Status; -} - -/** - Abstract PCI device device information. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param PciIo A pointer to EFI_PCI_PROTOCOL. - @param Pci PCI device configuration space. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO. - - @retval EFI_SUCCESS Pci device device information has been abstracted. - @retval EFI_NOT_FOUND Cannot found the specified PCI device. - @retval other Some error occurred when reading PCI device information. - -**/ -EFI_STATUS -GetPciDeviceDeviceInfo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL - IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL - IN PCI_TYPE00 *Pci, OPTIONAL - IN UINT64 Offset, OPTIONAL - OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo -) -{ - EFI_STATUS Status; - UINT64 PciAddress; - UINT32 PciConfigData; - PCI_IO_DEVICE *PciIoDevice; - - ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL)); - ASSERT (PciDeviceInfo != NULL); - - if (PciIo != NULL) { - PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo); - - // - // Get pointer to PCI_TYPE00 from PciIoDevice - // - Pci = &PciIoDevice->Pci; - } - - if (Pci == NULL) { - // - // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly - // - PciAddress = Offset & 0xffffffffffffff00ULL; - Status = PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - EfiPciWidthUint32, - PciAddress, - 1, - &PciConfigData - ); - - if (EFI_ERROR (Status)) { - return Status; - } - - if ((PciConfigData & 0xffff) == 0xffff) { - return EFI_NOT_FOUND; - } - - PciDeviceInfo->VendorID = PciConfigData & 0xffff; - PciDeviceInfo->DeviceID = PciConfigData >> 16; - - Status = PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - EfiPciWidthUint32, - PciAddress + 8, - 1, - &PciConfigData - ); - if (EFI_ERROR (Status)) { - return Status; - } - - PciDeviceInfo->RevisionID = PciConfigData & 0xf; - - Status = PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - EfiPciWidthUint32, - PciAddress + 0x2c, - 1, - &PciConfigData - ); - - if (EFI_ERROR (Status)) { - return Status; - } - - PciDeviceInfo->SubsystemVendorID = PciConfigData & 0xffff; - PciDeviceInfo->SubsystemID = PciConfigData >> 16; - - } else { - PciDeviceInfo->VendorID = Pci->Hdr.VendorId; - PciDeviceInfo->DeviceID = Pci->Hdr.DeviceId; - PciDeviceInfo->RevisionID = Pci->Hdr.RevisionID; - PciDeviceInfo->SubsystemVendorID = Pci->Device.SubsystemVendorID; - PciDeviceInfo->SubsystemID = Pci->Device.SubsystemID; - } - - return EFI_SUCCESS; -} - -/** - Read PCI configuration space with incompatibility check. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_UNSUPPORTED Buffer is NULL. - @retval other Some error occurred when reading PCI configuration space. - -**/ -EFI_STATUS -PciIncompatibilityCheckRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL - IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL - IN PCI_TYPE00 *Pci, OPTIONAL - IN UINTN Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - EFI_PCI_DEVICE_INFO PciDeviceInfo; - UINT32 Stride; - - ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL)); - if (Buffer == NULL) { - return EFI_UNSUPPORTED; - } - - // - // get PCI device device information - // - Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo); - if (Status != EFI_SUCCESS) { - return Status; - } - - Stride = 1 << Width; - - for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) { - - // - // read configuration register - // - Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer); - - if (Status != EFI_SUCCESS) { - return Status; - } - - // - // update the data read from configuration register - // - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) { - UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer); - } - } - - return EFI_SUCCESS; -} - -/** - Write PCI configuration space with incompatibility check. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be write. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not - valid for the PCI configuration header of the PCI controller. - Buffer is NULL. - @retval other Some error occurred when writing PCI configuration space. - -**/ -EFI_STATUS -PciIncompatibilityCheckWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL - IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL - IN PCI_TYPE00 *Pci, OPTIONAL - IN UINTN Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - EFI_PCI_DEVICE_INFO PciDeviceInfo; - UINT32 Stride; - UINT64 Data; - - ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL)); - if (Buffer == NULL) { - return EFI_UNSUPPORTED; - } - - // - // Get PCI device device information - // - Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo); - if (Status != EFI_SUCCESS) { - return Status; - } - - Stride = 1 << Width; - - for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) { - - Data = 0; - - switch (Width) { - case EfiPciWidthUint8: - Data = * (UINT8 *) Buffer; - break; - case EfiPciWidthUint16: - Data = * (UINT16 *) Buffer; - break; - - case EfiPciWidthUint32: - Data = * (UINT32 *) Buffer; - break; - - default: - return EFI_UNSUPPORTED; - } - - // - // Update the data writen into configuration register - // - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) { - UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data); - } - - // - // Write configuration register - // - Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data); - - if (Status != EFI_SUCCESS) { - return Status; - } - } - - return EFI_SUCCESS; -} - -/** - Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -PciRootBridgeIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, - IN PCI_TYPE00 *Pci, OPTIONAL - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) { - // - // If PCI incompatibility check enabled - // - Status = PciIncompatibilityCheckRead ( - PciRootBridgeIo, - NULL, - Pci, - (UINTN) Width, - Offset, - Count, - Buffer - ); - if (Status == EFI_UNSUPPORTED) { - return EFI_INVALID_PARAMETER; - } else { - return Status; - } - } else { - return PciRootBridgeIo->Pci.Read ( - PciRootBridgeIo, - Width, - Offset, - Count, - Buffer - ); - } -} - -/** - Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -PciRootBridgeIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, - IN PCI_TYPE00 *Pci, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) { - // - // If PCI incompatibility check enabled - // - Status = PciIncompatibilityCheckWrite ( - PciRootBridgeIo, - NULL, - Pci, - Width, - Offset, - Count, - Buffer - ); - if (Status == EFI_UNSUPPORTED) { - return EFI_INVALID_PARAMETER; - } else { - return Status; - } - - } else { - return PciRootBridgeIo->Pci.Write ( - PciRootBridgeIo, - Width, - Offset, - Count, - Buffer - ); - } -} - -/** - Read PCI configuration space through EFI_PCI_IO_PROTOCOL. - - @param PciIo A pointer to the EFI_PCI_O_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI controller. - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not - valid for the PCI configuration header of the PCI controller. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. - -**/ -EFI_STATUS -PciIoRead ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) { - // - // If PCI incompatibility check enabled - // - return PciIncompatibilityCheckRead ( - NULL, - PciIo, - NULL, - (UINTN) Width, - Offset, - Count, - Buffer - ); - } else { - return PciIo->Pci.Read ( - PciIo, - Width, - Offset, - Count, - Buffer - ); - } -} - -/** - Write PCI configuration space through EFI_PCI_IO_PROTOCOL. - - If PCI incompatibility check is enabled, do incompatibility check. - - @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of PCI configuration operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI controller. - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not - valid for the PCI configuration header of the PCI controller. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. - -**/ -EFI_STATUS -PciIoWrite ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) { - // - // If PCI incompatibility check enabled - // - return PciIncompatibilityCheckWrite ( - NULL, - PciIo, - NULL, - Width, - Offset, - Count, - Buffer - ); - - } else { - return PciIo->Pci.Write ( - PciIo, - Width, - Offset, - Count, - Buffer - ); - } -} - diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h index 0dcfbef040..43e3e48f2b 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h @@ -15,14 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #ifndef _EFI_PCI_LIB_H_ #define _EFI_PCI_LIB_H_ -// -// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask -// -#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01 -#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02 -#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04 -#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08 -#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x10 typedef struct { EFI_HANDLE Handle; @@ -146,113 +138,7 @@ PciHostBridgeP2CProcess ( **/ EFI_STATUS PciHostBridgeEnumerator ( - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc - ); - -/** - Read PCI configuration space through EFI_PCI_IO_PROTOCOL. - - @param PciIo A pointer to the EFI_PCI_O_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI controller. - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not - valid for the PCI configuration header of the PCI controller. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. - -**/ -EFI_STATUS -PciIoRead ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -/** - Write PCI configuration space through EFI_PCI_IO_PROTOCOL. - - If PCI incompatibility check is enabled, do incompatibility check. - - @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of PCI configuration operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI controller. - @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not - valid for the PCI configuration header of the PCI controller. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. - -**/ -EFI_STATUS -PciIoWrite ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -/** - Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -PciRootBridgeIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, - IN PCI_TYPE00 *Pci, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -/** - Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pci A pointer to PCI_TYPE00. - @param Width Signifies the width of the memory operations. - @param Offset The offset within the PCI configuration space for the PCI controller. - @param Count The number of unit to be read. - @param Buffer For read operations, the destination buffer to store the results. For - write operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -PciRootBridgeIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, - IN PCI_TYPE00 *Pci, OPTIONAL - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc ); #endif diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c index 9365847eb5..19803efb2c 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c @@ -216,9 +216,10 @@ LoadFile2 ( } /** - Get Pci device's oprom infor bits. + Get Pci device's oprom information. - @param PciIoDevice Pci device instance. + @param PciIoDevice Input Pci device instance. + Output Pci device instance with updated OptionRom size. @retval EFI_NOT_FOUND Pci device has not Option Rom. @retval EFI_SUCCESS Pci device has Option Rom. @@ -226,7 +227,7 @@ LoadFile2 ( **/ EFI_STATUS GetOpRomInfo ( - IN PCI_IO_DEVICE *PciIoDevice + IN OUT PCI_IO_DEVICE *PciIoDevice ) { UINT8 RomBarIndex; @@ -255,11 +256,7 @@ GetOpRomInfo ( if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { // - // If is ppb - // - - // - // 0x38 + // If is ppb, 0x38 // RomBarIndex = PCI_BRIDGE_ROMBAR; } @@ -269,9 +266,8 @@ GetOpRomInfo ( AllOnes = 0xfffffffe; Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex); - Status = PciRootBridgeIoWrite ( + Status = PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, - &PciIoDevice->Pci, EfiPciWidthUint32, Address, 1, @@ -284,9 +280,8 @@ GetOpRomInfo ( // // Read back // - Status = PciRootBridgeIoRead ( + Status = PciRootBridgeIo->Pci.Read( PciRootBridgeIo, - &PciIoDevice->Pci, EfiPciWidthUint32, Address, 1, @@ -295,6 +290,7 @@ GetOpRomInfo ( if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; } + // // Bits [1, 10] are reserved // @@ -558,7 +554,7 @@ RomDecode ( // Clear all bars // for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { - PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero); + PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero); } // @@ -566,13 +562,13 @@ RomDecode ( // enable its decoder // Value32 = RomBar | 0x1; - PciIoWrite ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, - RomBarIndex, - 1, - &Value32 - ); + PciIo->Pci.Write ( + PciIo, + (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, + RomBarIndex, + 1, + &Value32 + ); // // Programe all upstream bridge @@ -600,13 +596,13 @@ RomDecode ( // disable rom decode // Value32 = 0xFFFFFFFE; - PciIoWrite ( - PciIo, - (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, - RomBarIndex, - 1, - &Value32 - ); + PciIo->Pci.Write ( + PciIo, + (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, + RomBarIndex, + 1, + &Value32 + ); } } diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h index 2190aa369d..4615a5fe33 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h @@ -78,9 +78,10 @@ ContainEfiImage ( /** - Get Pci device's oprom infor bits. + Get Pci device's oprom information. - @param PciIoDevice Pci device instance. + @param PciIoDevice Input Pci device instance. + Output Pci device instance with updated OptionRom size. @retval EFI_NOT_FOUND Pci device has not Option Rom. @retval EFI_SUCCESS Pci device has Option Rom. @@ -88,7 +89,7 @@ ContainEfiImage ( **/ EFI_STATUS GetOpRomInfo ( - IN PCI_IO_DEVICE *PciIoDevice + IN OUT PCI_IO_DEVICE *PciIoDevice ); /** diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c index d7321800fb..860d427f35 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c @@ -55,13 +55,13 @@ ResetPowerManagementFeature ( // // Write PMCSR // - PciIoWrite ( - &PciIoDevice->PciIo, - EfiPciIoWidthUint16, - PowerManagementRegBlock + 4, - 1, - &PowerManagementCSR - ); + PciIoDevice->PciIo.Pci.Write ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + PowerManagementRegBlock + 4, + 1, + &PowerManagementCSR + ); return EFI_SUCCESS; } diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 755abf80a9..40d02354eb 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -91,8 +91,8 @@ SkipIsaAliasAperture ( **/ VOID InsertResourceNode ( - IN PCI_RESOURCE_NODE *Bridge, - IN PCI_RESOURCE_NODE *ResNode + IN OUT PCI_RESOURCE_NODE *Bridge, + IN PCI_RESOURCE_NODE *ResNode ) { LIST_ENTRY *CurrentLink; @@ -352,7 +352,6 @@ CalculateResourceAperture ( // // Apply padding resource if available // - Offset = Aperture & (Node->Alignment); if (Offset != 0) { @@ -375,7 +374,6 @@ CalculateResourceAperture ( // // Consider the aperture alignment // - CurrentLink = CurrentLink->ForwardLink; } @@ -423,12 +421,12 @@ CalculateResourceAperture ( **/ VOID GetResourceFromDevice ( - IN PCI_IO_DEVICE *PciDev, - IN PCI_RESOURCE_NODE *IoNode, - IN PCI_RESOURCE_NODE *Mem32Node, - IN PCI_RESOURCE_NODE *PMem32Node, - IN PCI_RESOURCE_NODE *Mem64Node, - IN PCI_RESOURCE_NODE *PMem64Node + IN PCI_IO_DEVICE *PciDev, + IN OUT PCI_RESOURCE_NODE *IoNode, + IN OUT PCI_RESOURCE_NODE *Mem32Node, + IN OUT PCI_RESOURCE_NODE *PMem32Node, + IN OUT PCI_RESOURCE_NODE *Mem64Node, + IN OUT PCI_RESOURCE_NODE *PMem64Node ) { @@ -582,14 +580,12 @@ CreateResourceNode ( Node = NULL; - Node = AllocatePool (sizeof (PCI_RESOURCE_NODE)); + Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE)); ASSERT (Node != NULL); if (Node == NULL) { return NULL; } - ZeroMem (Node, sizeof (PCI_RESOURCE_NODE)); - Node->Signature = PCI_RESOURCE_SIGNATURE; Node->PciDev = PciDev; Node->Length = Length; @@ -617,12 +613,12 @@ CreateResourceNode ( **/ VOID CreateResourceMap ( - IN PCI_IO_DEVICE *Bridge, - IN PCI_RESOURCE_NODE *IoNode, - IN PCI_RESOURCE_NODE *Mem32Node, - IN PCI_RESOURCE_NODE *PMem32Node, - IN PCI_RESOURCE_NODE *Mem64Node, - IN PCI_RESOURCE_NODE *PMem64Node + IN PCI_IO_DEVICE *Bridge, + IN OUT PCI_RESOURCE_NODE *IoNode, + IN OUT PCI_RESOURCE_NODE *Mem32Node, + IN OUT PCI_RESOURCE_NODE *PMem32Node, + IN OUT PCI_RESOURCE_NODE *Mem64Node, + IN OUT PCI_RESOURCE_NODE *PMem64Node ) { PCI_IO_DEVICE *Temp; @@ -726,7 +722,7 @@ CreateResourceMap ( IoBridge ); } else { - gBS->FreePool (IoBridge); + FreePool (IoBridge); IoBridge = NULL; } @@ -742,7 +738,7 @@ CreateResourceMap ( Mem32Bridge ); } else { - gBS->FreePool (Mem32Bridge); + FreePool (Mem32Bridge); Mem32Bridge = NULL; } @@ -758,7 +754,7 @@ CreateResourceMap ( PMem32Bridge ); } else { - gBS->FreePool (PMem32Bridge); + FreePool (PMem32Bridge); PMem32Bridge = NULL; } @@ -774,7 +770,7 @@ CreateResourceMap ( Mem64Bridge ); } else { - gBS->FreePool (Mem64Bridge); + FreePool (Mem64Bridge); Mem64Bridge = NULL; } @@ -790,7 +786,7 @@ CreateResourceMap ( PMem64Bridge ); } else { - gBS->FreePool (PMem64Bridge); + FreePool (PMem64Bridge); PMem64Bridge = NULL; } @@ -799,7 +795,6 @@ CreateResourceMap ( // // If it is P2C, apply hard coded resource padding // - // if (IS_CARDBUS_BRIDGE (&Temp->Pci)) { ResourcePaddingForCardBusBridge ( Temp, @@ -813,7 +808,7 @@ CreateResourceMap ( CurrentLink = CurrentLink->ForwardLink; } - // + // // To do some platform specific resource padding ... // @@ -1120,13 +1115,13 @@ ProgramBar ( case PciBarTypeMem32: case PciBarTypePMem32: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - (Node->PciDev->PciBar[Node->Bar]).Offset, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + (Node->PciDev->PciBar[Node->Bar]).Offset, + 1, + &Address + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; @@ -1137,23 +1132,23 @@ ProgramBar ( Address32 = (UINT32) (Address & 0x00000000FFFFFFFF); - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - (Node->PciDev->PciBar[Node->Bar]).Offset, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + (Node->PciDev->PciBar[Node->Bar]).Offset, + 1, + &Address32 + ); Address32 = (UINT32) RShiftU64 (Address, 32); - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4), - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4), + 1, + &Address32 + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; @@ -1205,13 +1200,13 @@ ProgramPpbApperture ( case PPB_BAR_0: case PPB_BAR_1: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - (Node->PciDev->PciBar[Node->Bar]).Offset, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + (Node->PciDev->PciBar[Node->Bar]).Offset, + 1, + &Address + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; @@ -1221,41 +1216,41 @@ ProgramPpbApperture ( case PPB_IO_RANGE: Address32 = ((UINT32) (Address)) >> 8; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint8, - 0x1C, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + 0x1C, + 1, + &Address32 + ); Address32 >>= 8; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x30, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x30, + 1, + &Address32 + ); Address32 = (UINT32) (Address + Node->Length - 1); Address32 = ((UINT32) (Address32)) >> 8; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint8, - 0x1D, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + 0x1D, + 1, + &Address32 + ); Address32 >>= 8; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x32, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x32, + 1, + &Address32 + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; @@ -1264,23 +1259,23 @@ ProgramPpbApperture ( case PPB_MEM32_RANGE: Address32 = ((UINT32) (Address)) >> 16; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x20, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x20, + 1, + &Address32 + ); Address32 = (UINT32) (Address + Node->Length - 1); Address32 = ((UINT32) (Address32)) >> 16; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x22, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x22, + 1, + &Address32 + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; @@ -1290,41 +1285,41 @@ ProgramPpbApperture ( case PPB_PMEM64_RANGE: Address32 = ((UINT32) (Address)) >> 16; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x24, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x24, + 1, + &Address32 + ); Address32 = (UINT32) (Address + Node->Length - 1); Address32 = ((UINT32) (Address32)) >> 16; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - 0x26, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + 0x26, + 1, + &Address32 + ); Address32 = (UINT32) RShiftU64 (Address, 32); - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - 0x28, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + 0x28, + 1, + &Address32 + ); Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32); - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - 0x2C, - 1, - &Address32 - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + 0x2C, + 1, + &Address32 + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; @@ -1707,77 +1702,77 @@ ProgramP2C ( switch (Node->Bar) { case P2C_BAR_0: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - (Node->PciDev->PciBar[Node->Bar]).Offset, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + (Node->PciDev->PciBar[Node->Bar]).Offset, + 1, + &Address + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; break; case P2C_MEM_1: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_BASE_0, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_BASE_0, + 1, + &Address + ); TempAddress = Address + Node->Length - 1; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_LIMIT_0, - 1, - &TempAddress - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_LIMIT_0, + 1, + &TempAddress + ); if (Node->ResType == PciBarTypeMem32) { // // Set non-prefetchable bit // - PciIoRead ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); } else { // // Set pre-fetchable bit // - PciIoRead ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); } Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; @@ -1787,67 +1782,67 @@ ProgramP2C ( break; case P2C_MEM_2: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_BASE_1, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_BASE_1, + 1, + &Address + ); TempAddress = Address + Node->Length - 1; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_MEMORY_LIMIT_1, - 1, - &TempAddress - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_MEMORY_LIMIT_1, + 1, + &TempAddress + ); if (Node->ResType == PciBarTypeMem32) { // // Set non-prefetchable bit // - PciIoRead ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE); - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); } else { // // Set pre-fetchable bit // - PciIoRead ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint16, - PCI_CARD_BRIDGE_CONTROL, - 1, - &BridgeControl - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint16, + PCI_CARD_BRIDGE_CONTROL, + 1, + &BridgeControl + ); } Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; @@ -1856,22 +1851,22 @@ ProgramP2C ( break; case P2C_IO_1: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_IO_BASE_0_LOWER, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_IO_BASE_0_LOWER, + 1, + &Address + ); TempAddress = Address + Node->Length - 1; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_IO_LIMIT_0_LOWER, - 1, - &TempAddress - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_IO_LIMIT_0_LOWER, + 1, + &TempAddress + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; @@ -1880,22 +1875,22 @@ ProgramP2C ( break; case P2C_IO_2: - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_IO_BASE_1_LOWER, - 1, - &Address - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_IO_BASE_1_LOWER, + 1, + &Address + ); TempAddress = Address + Node->Length - 1; - PciIoWrite ( - PciIo, - EfiPciIoWidthUint32, - PCI_CARD_IO_LIMIT_1_LOWER, - 1, - &TempAddress - ); + PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint32, + PCI_CARD_IO_LIMIT_1_LOWER, + 1, + &TempAddress + ); Node->PciDev->PciBar[Node->Bar].BaseAddress = Address; Node->PciDev->PciBar[Node->Bar].Length = Node->Length; diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h index 3724dcd1f3..96396fe869 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h @@ -76,8 +76,8 @@ SkipIsaAliasAperture ( **/ VOID InsertResourceNode ( - IN PCI_RESOURCE_NODE *Bridge, - IN PCI_RESOURCE_NODE *ResNode + IN OUT PCI_RESOURCE_NODE *Bridge, + IN PCI_RESOURCE_NODE *ResNode ); /** @@ -142,12 +142,12 @@ CalculateResourceAperture ( **/ VOID GetResourceFromDevice ( - IN PCI_IO_DEVICE *PciDev, - IN PCI_RESOURCE_NODE *IoNode, - IN PCI_RESOURCE_NODE *Mem32Node, - IN PCI_RESOURCE_NODE *PMem32Node, - IN PCI_RESOURCE_NODE *Mem64Node, - IN PCI_RESOURCE_NODE *PMem64Node + IN PCI_IO_DEVICE *PciDev, + IN OUT PCI_RESOURCE_NODE *IoNode, + IN OUT PCI_RESOURCE_NODE *Mem32Node, + IN OUT PCI_RESOURCE_NODE *PMem32Node, + IN OUT PCI_RESOURCE_NODE *Mem64Node, + IN OUT PCI_RESOURCE_NODE *PMem64Node ); /** @@ -188,12 +188,12 @@ CreateResourceNode ( **/ VOID CreateResourceMap ( - IN PCI_IO_DEVICE *Bridge, - IN PCI_RESOURCE_NODE *IoNode, - IN PCI_RESOURCE_NODE *Mem32Node, - IN PCI_RESOURCE_NODE *PMem32Node, - IN PCI_RESOURCE_NODE *Mem64Node, - IN PCI_RESOURCE_NODE *PMem64Node + IN PCI_IO_DEVICE *Bridge, + IN OUT PCI_RESOURCE_NODE *IoNode, + IN OUT PCI_RESOURCE_NODE *Mem32Node, + IN OUT PCI_RESOURCE_NODE *PMem32Node, + IN OUT PCI_RESOURCE_NODE *Mem64Node, + IN OUT PCI_RESOURCE_NODE *PMem64Node ); /** diff --git a/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h b/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h deleted file mode 100644 index f490ae4106..0000000000 --- a/IntelFrameworkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h +++ /dev/null @@ -1,146 +0,0 @@ -/** @file - PCI Incompatible device support Libary. Platform can implement an - instance to support the incompatible PCI devices. - -Copyright (c) 2006 - 2009, Intel Corporation -All rights reserved. This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__ -#define __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__ - -#define PCI_REGISTER_READ 0xfffffffffffffff1ULL -#define PCI_REGISTER_WRITE 0xfffffffffffffff2ULL -#define VALUE_NOCARE 0xffffffffffffffffULL - -// -// PCI device device information -// -typedef struct { - UINT64 VendorID; - UINT64 DeviceID; - UINT64 RevisionID; - UINT64 SubsystemVendorID; - UINT64 SubsystemID; -} EFI_PCI_DEVICE_INFO; - - -// -// store hardcode value of resgister -// -typedef struct { - UINT64 AndValue; - UINT64 OrValue; -} EFI_PCI_REGISTER_VALUE_DATA; - -// -// store access width information -// -typedef struct { - UINT64 StartOffset; - UINT64 EndOffset; - UINT64 Width; -} EFI_PCI_REGISTER_ACCESS_DATA; - - -// -// ACPI resource descriptor -// -typedef struct { - UINT64 ResType; - UINT64 GenFlag; - UINT64 SpecificFlag; - UINT64 AddrSpaceGranularity; - UINT64 AddrRangeMin; - UINT64 AddrRangeMax; - UINT64 AddrTranslationOffset; - UINT64 AddrLen; -} EFI_PCI_RESOUCE_DESCRIPTOR; - -/** - Check the incompatible device list for ACPI resource update and return - the configuration. - - This function searches the incompatible device list according to request - information. If the PCI device belongs to the devices list, corresponding - configuration informtion will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to PCI device information. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_ABORTED No any resource type. - @retval EFI_OUT_OF_RESOURCES No memory available. - @retval EFI_UNSUPPORTED Invalid Tag encounted. - -**/ -EFI_STATUS -EFIAPI -PciResourceUpdateCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - OUT VOID *Configuration - ); - -/** - Check the incompatible device list and return configuraton register mask values. - - This function searches the incompatible device list according to request - information. If the PCI device belongs to the devices list, corresponding - configuration informtion will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO. - @param AccessType Access Type, READ or WRITE. - @param Offset The address within the PCI configuration space. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_UNSUPPORTED Failed to check incompatibility device. - -**/ -EFI_STATUS -EFIAPI -PciRegisterUpdateCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 AccessType, - IN UINT64 Offset, - OUT VOID *Configuration - ); - -/** - Check the incompatible device list for access width incompatibility and - return the configuration. - - This function searches the incompatible device list for access width - incompatibility according to request information. If the PCI device - belongs to the devices list, corresponding configuration informtion - will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to PCI device information. - @param AccessType Access type, READ or WRITE. - @param Offset The address within the PCI configuration space. - @param AccessWidth Access width needs to check incompatibility. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_UNSUPPORTED Failed to check incompatibility device. - -**/ -EFI_STATUS -EFIAPI -PciRegisterAccessCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 AccessType, - IN UINT64 Offset, - IN UINT64 AccessWidth, - OUT VOID *Configuration - ); - -#endif - diff --git a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec index 5e48c8d920..da4459022c 100644 --- a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec +++ b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec @@ -24,9 +24,6 @@ Include # Root include for the package [LibraryClasses.common] - ## @libraryclass This libary is used to support the incompatible PCI devices. - PciIncompatibleDeviceSupportLib|Include/Library/PciIncompatibleDeviceSupportLib.h - ## @libraryclass OEM status code libary is used to report status code to OEM device. OemHookStatusCodeLib|Include/Library/OemHookStatusCodeLib.h @@ -139,11 +136,6 @@ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusOnlySupportSlaveDma|FALSE|BOOLEAN|0x00010041 gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusSupportIsaMemory|TRUE|BOOLEAN|0x00010042 -[PcdsFixedAtBuild] - ## PCD marks PCI support incompatible operations: AcpiResource, Read, Write, RegisterUpdate, AccessWidth. - # BIT0:AcpiResource, BIT1:Read, BIT2:Write, BIT3:RegisterUpdate, BIT4:AccessWidth - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0|UINT8|0x0001003f - [PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic] ## PcdStatusCodeMemorySize is used when PcdStatusCodeUseMemory is set to true # (PcdStatusCodeMemorySize * KBytes) is the total taken memory size. diff --git a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc index eb6cb20c32..97224d2dad 100644 --- a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc +++ b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc @@ -3,7 +3,7 @@ # # This file is used to build all modules in IntelFrameworkModulePkg. # -# Copyright (c) 2007, Intel Corporation +# Copyright (c) 2007 - 2009, Intel Corporation # # All rights reserved. This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -90,7 +90,6 @@ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf - PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf [LibraryClasses.common.DXE_RUNTIME_DRIVER] @@ -118,7 +117,6 @@ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf - PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf ################################################################################ @@ -149,7 +147,6 @@ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xFFFB0000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 @@ -189,7 +186,6 @@ IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf IntelFrameworkModulePkg/Library/PeiRecoveryLib/PeiRecoveryLib.inf IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf diff --git a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h deleted file mode 100644 index 49ac0ad850..0000000000 --- a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h +++ /dev/null @@ -1,54 +0,0 @@ -/** @file - The incompatible PCI device list template. - -Copyright (c) 2006 - 2009, Intel Corporation -All rights reserved. This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_ -#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_ - -#include -#include -#include - -#include -#include - - -#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \ - VendorId, DeviceId, Revision, SubVendorId, SubDeviceId - -#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO -#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM - -#define DEVICE_INF_TAG 0xFFF2 -#define DEVICE_RES_TAG 0xFFF1 -#define LIST_END_TAG 0x0000 - -// -// descriptor for access width of incompatible PCI device -// -typedef struct { - UINT64 AccessType; - UINT64 AccessWidth; - EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData; -} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR; - -// -// descriptor for register value of incompatible PCI device -// -typedef struct { - UINT64 AccessType; - UINT64 Offset; - EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData; -} EFI_PCI_REGISTER_VALUE_DESCRIPTOR; - -#endif diff --git a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c deleted file mode 100644 index 21d527408b..0000000000 --- a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.c +++ /dev/null @@ -1,521 +0,0 @@ -/** @file - The template of PCI incompatible device support libary. - -Copyright (c) 2006 - 2009, Intel Corporation -All rights reserved. This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "IncompatiblePciDeviceList.h" - -// -// the incompatible PCI devices list template for ACPI resource -// -GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = { - // - // DEVICE_INF_TAG, - // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId), - // DEVICE_RES_TAG, - // ResType, GFlag , SFlag, Granularity, RangeMin, - // RangeMax, Offset, AddrLen - // - - // - // Sample Device 1 - // - //DEVICE_INF_TAG, - //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE), - //DEVICE_RES_TAG, - //PCI_BAR_TYPE_IO, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_BAR_EVEN_ALIGN, - //PCI_BAR_ALL, - //PCI_BAR_NOCHANGE, - - // - // Sample Device 2 - // - //DEVICE_INF_TAG, - //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE), - //DEVICE_RES_TAG, - //PCI_BAR_TYPE_IO, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_ACPI_UNUSED, - //PCI_BAR_EVEN_ALIGN, - //PCI_BAR_ALL, - //PCI_BAR_NOCHANGE, - - // - // The end of the list - // - LIST_END_TAG -}; - -// -// the incompatible PCI devices list template for the values of configuration registers -// -GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = { - // - // DEVICE_INF_TAG, - // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId), - // PCI_RES_TAG, - // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS, - // AND_VALUE, OR_VALUE - - // - // Sample Device 1 - // - //DEVICE_INF_TAG, - //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE), - //DEVICE_RES_TAG, - //PCI_REGISTER_READ, - //PCI_CAPBILITY_POINTER_OFFSET, - //0xffffff00, - //VALUE_NOCARE, - - // - // Sample Device 2 - // - //DEVICE_INF_TAG, - //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE), - //DEVICE_RES_TAG, - //PCI_REGISTER_READ, - //PCI_CAPBILITY_POINTER_OFFSET, - //0xffffff00, - //VALUE_NOCARE, - - // - // The end of the list - // - LIST_END_TAG -}; - -// -// the incompatible PCI devices list template for the access width of configuration registers -// -GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = { - // - // DEVICE_INF_TAG, - // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId), - // DEVICE_RES_TAG, - // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH, - // START_ADDRESS, END_ADDRESS, - // ACTUAL_PCI_ACCESS_WIDTH, - // - - // - // Sample Device - // - //DEVICE_INF_TAG, - //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE), - //DEVICE_RES_TAG, - //PCI_REGISTER_READ, - //EfiPciWidthUint8, - //0, - //0xFF, - //EfiPciWidthUint32, - // - - // - // The end of the list - // - LIST_END_TAG -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0}; - - -/** - Check whether two PCI devices matched. - - @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO. - @param Header A pointer to EFI_PCI_DEVICE_INFO. - - @retval EFI_SUCCESS Two PCI devices matched. - @retval EFI_UNSUPPORTED Two PCI devices don't match. - -**/ -EFI_STATUS -DeviceCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN EFI_PCI_DEVICE_INFO *Header - ) -{ - // - // See if the Header matches the parameters passed in - // - if (Header->VendorID != DEVICE_ID_NOCARE) { - if (PciDeviceInfo->VendorID != Header->VendorID) { - return EFI_UNSUPPORTED; - } - } - - if (Header->DeviceID != DEVICE_ID_NOCARE) { - if (PciDeviceInfo->DeviceID != Header->DeviceID) { - return EFI_UNSUPPORTED; - } - } - - if (Header->RevisionID != DEVICE_ID_NOCARE) { - if (PciDeviceInfo->RevisionID != Header->RevisionID) { - return EFI_UNSUPPORTED; - } - } - - if (Header->SubsystemVendorID != DEVICE_ID_NOCARE) { - if (PciDeviceInfo->SubsystemVendorID != Header->SubsystemVendorID) { - return EFI_UNSUPPORTED; - } - } - - if (Header->SubsystemID != DEVICE_ID_NOCARE) { - if (PciDeviceInfo->SubsystemID != Header->SubsystemID) { - return EFI_UNSUPPORTED; - } - } - - return EFI_SUCCESS; -} - - -/** - Check the incompatible device list for ACPI resource update and return - the configuration. - - This function searches the incompatible device list according to request - information. If the PCI device belongs to the devices list, corresponding - configuration informtion will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to PCI device information. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_ABORTED No any resource type. - @retval EFI_OUT_OF_RESOURCES No memory available. - @retval EFI_UNSUPPORTED Invalid Tag encounted. - -**/ -EFI_STATUS -EFIAPI -PciResourceUpdateCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - OUT VOID *Configuration - ) -{ - UINT64 Tag; - UINT64 *ListPtr; - UINT64 *TempListPtr; - EFI_PCI_DEVICE_INFO *Header; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr; - EFI_PCI_RESOUCE_DESCRIPTOR *Dsc; - EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd; - UINTN Index; - - ASSERT (PciDeviceInfo != NULL); - - // - // Initialize the return value to NULL - // - * (VOID **) Configuration = NULL; - - ListPtr = gIncompatiblePciDeviceListForResource; - while (*ListPtr != LIST_END_TAG) { - - Tag = *ListPtr; - - switch (Tag) { - case DEVICE_INF_TAG: - Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1); - ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64); - - if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) { - continue; - } - - // - // Matched an item, so construct the ACPI descriptor for the resource. - // - // - // Count the resource items so that to allocate space - // - for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) { - TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64)); - } - // - // If there is at least one type of resource request, - // allocate a acpi resource node - // - if (Index == 0) { - return EFI_ABORTED; - } - - AcpiPtr = AllocateZeroPool ( - sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) - ); - if (AcpiPtr == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - OldAcpiPtr = AcpiPtr; - - // - // Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure - // according to the EFI_PCI_RESOUCE_DESCRIPTOR structure - // - for (; *ListPtr == DEVICE_RES_TAG;) { - - Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1); - - AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; - AcpiPtr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - AcpiPtr->ResType = (UINT8) Dsc->ResType; - AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag; - AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag; - AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;; - AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin; - AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax; - AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset; - AcpiPtr->AddrLen = Dsc->AddrLen; - - ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64)); - AcpiPtr++; - } - // - // put the checksum - // - PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr); - PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR; - PtrEnd->Checksum = 0; - - *(VOID **) Configuration = OldAcpiPtr; - - return EFI_SUCCESS; - - case DEVICE_RES_TAG: - // - // Adjust the pointer to the next PCI resource descriptor item - // - ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64)); - break; - - default: - return EFI_UNSUPPORTED; - } - } - - return EFI_UNSUPPORTED; - -} - -/** - Check the incompatible device list and return configuraton register mask values. - - This function searches the incompatible device list according to request - information. If the PCI device belongs to the devices list, corresponding - configuration informtion will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO. - @param AccessType Access Type, READ or WRITE. - @param Offset The address within the PCI configuration space. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_UNSUPPORTED Failed to check incompatibility device. - -**/ -EFI_STATUS -EFIAPI -PciRegisterUpdateCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 AccessType, - IN UINT64 Offset, - OUT VOID *Configuration - ) -{ - EFI_PCI_DEVICE_INFO *Header; - UINT64 Tag; - UINT64 *ListPtr; - EFI_PCI_REGISTER_VALUE_DATA *RegisterPtr; - EFI_PCI_REGISTER_VALUE_DATA *Dsc; - - ASSERT (PciDeviceInfo != NULL); - - ListPtr = gIncompatiblePciDeviceListForRegister; - - // - // Initialize the return value to NULL - // - * (VOID **) Configuration = NULL; - - while (*ListPtr != LIST_END_TAG) { - - Tag = *ListPtr; - - switch (Tag) { - case DEVICE_INF_TAG: - Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1); - ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64); - - // - // Check whether the PCI device matches the device in the incompatible devices list? - // If not, ship next - // - if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) { - continue; - } - - // - // Matched an item, check whether access matches? - // - for (; *ListPtr == DEVICE_RES_TAG;) { - ListPtr ++; - if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->Offset == (Offset & 0xfc)) { - if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) { - - Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2); - - RegisterPtr = &mPciRegisterValueData; - - RegisterPtr->AndValue = Dsc->AndValue; - RegisterPtr->OrValue = Dsc->OrValue; - - *(VOID **) Configuration = RegisterPtr; - - return EFI_SUCCESS; - } - } - ListPtr += sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR) / (sizeof (UINT64)); - } - return EFI_UNSUPPORTED; - - case DEVICE_RES_TAG: - // - // Adjust the pointer to the next item - // - ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR)) / sizeof (UINT64)); - break; - - default: - return EFI_UNSUPPORTED; - } - } - - return EFI_UNSUPPORTED; -} - -/** - Check the incompatible device list for access width incompatibility and - return the configuration. - - This function searches the incompatible device list for access width - incompatibility according to request information. If the PCI device - belongs to the devices list, corresponding configuration informtion - will be returned, in the meantime return EFI_SUCCESS. - - @param PciDeviceInfo A pointer to PCI device information. - @param AccessType Access type, READ or WRITE. - @param Offset The address within the PCI configuration space. - @param AccessWidth Access width needs to check incompatibility. - @param Configuration Returned information. - - @retval EFI_SUCCESS If check incompatible device successfully. - @retval EFI_UNSUPPORTED Failed to check incompatibility device. - -**/ -EFI_STATUS -EFIAPI -PciRegisterAccessCheck ( - IN EFI_PCI_DEVICE_INFO *PciDeviceInfo, - IN UINT64 AccessType, - IN UINT64 Offset, - IN UINT64 AccessWidth, - OUT VOID *Configuration - ) -{ - EFI_PCI_DEVICE_INFO *Header; - UINT64 Tag; - UINT64 *ListPtr; - EFI_PCI_REGISTER_ACCESS_DATA *RegisterPtr; - EFI_PCI_REGISTER_ACCESS_DATA *Dsc; - - ASSERT (PciDeviceInfo != NULL); - - ListPtr = gDeviceListForAccessWidth; - - // - // Initialize the return value to NULL - // - * (VOID **) Configuration = NULL; - - while (*ListPtr != LIST_END_TAG) { - - Tag = *ListPtr; - - switch (Tag) { - case DEVICE_INF_TAG: - Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1); - ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64); - - // - // Check whether the PCI device matches the device in the incompatible devices list? - // If not, ship next - // - if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) { - continue; - } - - // - // Matched an item, check whether access matches? - // - for (; *ListPtr == DEVICE_RES_TAG;) { - ListPtr ++; - if (((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessType == AccessType && - ((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessWidth == AccessWidth ) { - - Dsc = (EFI_PCI_REGISTER_ACCESS_DATA *) (ListPtr + 2); - - if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) { - - RegisterPtr = &mPciRegisterAccessData; - - RegisterPtr->StartOffset = Dsc->StartOffset; - RegisterPtr->EndOffset = Dsc->EndOffset; - RegisterPtr->Width = Dsc->Width; - - *(VOID **) Configuration = RegisterPtr; - - return EFI_SUCCESS; - } - } - ListPtr += sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR) / (sizeof (UINT64)); - } - return EFI_UNSUPPORTED; - - case DEVICE_RES_TAG: - // - // Adjust the pointer to the next item - // - ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR)) / sizeof (UINT64)); - break; - - default: - return EFI_UNSUPPORTED; - } - } - - return EFI_UNSUPPORTED; -} - diff --git a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf b/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf deleted file mode 100644 index 50b0c13f73..0000000000 --- a/IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf +++ /dev/null @@ -1,42 +0,0 @@ -#/** @file -# PCI Incompatible device support Library template. -# -# Check PCI incompatible devices and set necessary configuration. -# Copyright (c) 2007 - 2009, Intel Corporation. -# -# All rights reserved. This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PciIncompatibleDeviceSupportLib - FILE_GUID = 1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciIncompatibleDeviceSupportLib|DXE_DRIVER UEFI_DRIVER - EFI_SPECIFICATION_VERSION = 0x00020000 - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 X64 IPF EBC -# - -[Sources.common] - IncompatiblePciDeviceList.h - PciIncompatibleDeviceSupportLib.c - -[Packages] - MdePkg/MdePkg.dec - IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec - -[LibraryClasses] - MemoryAllocationLib - DebugLib