From: Tom Lendacky Date: Wed, 12 Aug 2020 20:21:35 +0000 (-0500) Subject: MdePkg: Add the MSR definition for the GHCB register X-Git-Tag: edk2-stable202008~96 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=a80e887819ac27800551811e2943181ad811effa MdePkg: Add the MSR definition for the GHCB register BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 For SEV-ES, the GHCB page address is stored in the GHCB MSR register (0xc0010130). Define the register and the format used for register during GHCB protocol negotiation. Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky Regression-tested-by: Laszlo Ersek --- diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h index 6ef45a9b21..e4db09c518 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -17,6 +17,52 @@ #ifndef __FAM17_MSR_H__ #define __FAM17_MSR_H__ +/** + Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register + +**/ +#define MSR_SEV_ES_GHCB 0xc0010130 + +/** + MSR information returned for #MSR_SEV_ES_GHCB +**/ +typedef union { + struct { + UINT32 Function:12; + UINT32 Reserved1:20; + UINT32 Reserved2:32; + } GhcbInfo; + + struct { + UINT8 Reserved[3]; + UINT8 SevEncryptionBitPos; + UINT16 SevEsProtocolMin; + UINT16 SevEsProtocolMax; + } GhcbProtocol; + + struct { + UINT32 Function:12; + UINT32 ReasonCodeSet:4; + UINT32 ReasonCode:8; + UINT32 Reserved1:8; + UINT32 Reserved2:32; + } GhcbTerminate; + + VOID *Ghcb; + + UINT64 GhcbPhysicalAddress; +} MSR_SEV_ES_GHCB_REGISTER; + +#define GHCB_INFO_SEV_INFO 1 +#define GHCB_INFO_SEV_INFO_GET 2 +#define GHCB_INFO_CPUID_REQUEST 4 +#define GHCB_INFO_CPUID_RESPONSE 5 +#define GHCB_INFO_TERMINATE_REQUEST 256 + +#define GHCB_TERMINATE_GHCB 0 +#define GHCB_TERMINATE_GHCB_GENERAL 0 +#define GHCB_TERMINATE_GHCB_PROTOCOL 1 + /** Secure Encrypted Virtualization (SEV) status register