From: oliviermartin Date: Tue, 12 Mar 2013 00:54:02 +0000 (+0000) Subject: ArmPlatformPkg: Moved ARMv7 specific files to a 'Arm' subdirectory X-Git-Tag: edk2-stable201903~12663 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=a9d7090fc217dad23330ddc54cad4d4987cab65a ArmPlatformPkg: Moved ARMv7 specific files to a 'Arm' subdirectory Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14182 6f19259b-4bc3-4df7-8a09-765794883524 --- diff --git a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.S b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.S new file mode 100644 index 0000000000..a00fac4f81 --- /dev/null +++ b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.S @@ -0,0 +1,47 @@ +// +// Copyright (c) 2011-2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ASM_PFX(ArmPlatformSecBootAction): + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformSecBootMemoryInit): + // The SMC does not need to be initialized for RTSM + bx lr diff --git a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.asm b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.asm new file mode 100644 index 0000000000..ead0868740 --- /dev/null +++ b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/Arm/ArmPlatformLibNullBoot.asm @@ -0,0 +1,49 @@ +// +// Copyright (c) 2011-2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include + + EXPORT ArmPlatformSecBootAction + EXPORT ArmPlatformSecBootMemoryInit + + PRESERVE8 + AREA ArmPlatformSecLibBoot, CODE, READONLY + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ArmPlatformSecBootAction + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformSecBootMemoryInit + // The SMC does not need to be initialized for RTSM + bx lr + + END diff --git a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.S b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.S deleted file mode 100644 index a00fac4f81..0000000000 --- a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.S +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright (c) 2011-2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include - -.text -.align 3 - -GCC_ASM_EXPORT(ArmPlatformSecBootAction) -GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) - -/** - Call at the beginning of the platform boot up - - This function allows the firmware platform to do extra actions at the early - stage of the platform power up. - - Note: This function must be implemented in assembler as there is no stack set up yet - -**/ -ASM_PFX(ArmPlatformSecBootAction): - bx lr - -/** - Initialize the memory where the initial stacks will reside - - This memory can contain the initial stacks (Secure and Secure Monitor stacks). - In some platform, this region is already initialized and the implementation of this function can - do nothing. This memory can also represent the Secure RAM. - This function is called before the satck has been set up. Its implementation must ensure the stack - pointer is not used (probably required to use assembly language) - -**/ -ASM_PFX(ArmPlatformSecBootMemoryInit): - // The SMC does not need to be initialized for RTSM - bx lr diff --git a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.asm b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.asm deleted file mode 100644 index ead0868740..0000000000 --- a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.asm +++ /dev/null @@ -1,49 +0,0 @@ -// -// Copyright (c) 2011-2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include - - EXPORT ArmPlatformSecBootAction - EXPORT ArmPlatformSecBootMemoryInit - - PRESERVE8 - AREA ArmPlatformSecLibBoot, CODE, READONLY - -/** - Call at the beginning of the platform boot up - - This function allows the firmware platform to do extra actions at the early - stage of the platform power up. - - Note: This function must be implemented in assembler as there is no stack set up yet - -**/ -ArmPlatformSecBootAction - bx lr - -/** - Initialize the memory where the initial stacks will reside - - This memory can contain the initial stacks (Secure and Secure Monitor stacks). - In some platform, this region is already initialized and the implementation of this function can - do nothing. This memory can also represent the Secure RAM. - This function is called before the satck has been set up. Its implementation must ensure the stack - pointer is not used (probably required to use assembly language) - -**/ -ArmPlatformSecBootMemoryInit - // The SMC does not need to be initialized for RTSM - bx lr - - END diff --git a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullSec.inf b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullSec.inf index ba55ed5199..f399547574 100644 --- a/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullSec.inf +++ b/ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullSec.inf @@ -33,8 +33,8 @@ ArmPlatformLibNullSec.c [Sources.ARM] - ArmPlatformLibNullBoot.asm | RVCT - ArmPlatformLibNullBoot.S | GCC + Arm/ArmPlatformLibNullBoot.asm | RVCT + Arm/ArmPlatformLibNullBoot.S | GCC [FixedPcd] gArmTokenSpaceGuid.PcdFvBaseAddress diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.S b/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.S new file mode 100644 index 0000000000..94660c97fe --- /dev/null +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.S @@ -0,0 +1,106 @@ +// +// Copyright (c) 2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformStackSet) +GCC_ASM_EXPORT(ArmPlatformStackSetPrimary) +GCC_ASM_EXPORT(ArmPlatformStackSetSecondary) + +GCC_ASM_IMPORT(ArmPlatformGetCorePosition) + +GCC_ASM_IMPORT(gPcd_FixedAtBuild_PcdCoreCount) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) + +//VOID +//ArmPlatformStackSet ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ASM_PFX(ArmPlatformStackSet): + // Identify Stack + // Mask for ClusterId|CoreId + LoadConstantToReg (0xFFFF, r4) + and r1, r1, r4 + // Is it the Primary Core ? + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4) + ldr r4, [r4] + cmp r1, r4 + beq ASM_PFX(ArmPlatformStackSetPrimary) + bne ASM_PFX(ArmPlatformStackSetSecondary) + +//VOID +//ArmPlatformStackSetPrimary ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ASM_PFX(ArmPlatformStackSetPrimary): + mov r4, lr + + // Add stack of primary stack to StackBase + add r0, r0, r2 + + // Compute SecondaryCoresCount * SecondaryCoreStackSize + LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1) + ldr r1, [r1] + sub r1, #1 + mul r3, r3, r1 + + // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize)) + add sp, r0, r3 + + bx r4 + +//VOID +//ArmPlatformStackSetSecondary ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ASM_PFX(ArmPlatformStackSetSecondary): + mov r4, lr + mov sp, r0 + + // Get Core Position + mov r0, r1 + bl ASM_PFX(ArmPlatformGetCorePosition) + mov r5, r0 + + // Get Primary Core Position + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) + ldr r0, [r0] + bl ASM_PFX(ArmPlatformGetCorePosition) + + // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1) + cmp r5, r0 + subhi r5, r5, #1 + add r5, r5, #1 + + // Compute top of the secondary stack + mul r3, r3, r5 + + // Set stack + add sp, sp, r3 + + bx r4 + diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.asm b/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.asm new file mode 100644 index 0000000000..db92023922 --- /dev/null +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/Arm/ArmPlatformStackLib.asm @@ -0,0 +1,112 @@ +// +// Copyright (c) 2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformStackSet + EXPORT ArmPlatformStackSetPrimary + EXPORT ArmPlatformStackSetSecondary + + IMPORT ArmPlatformGetCorePosition + + IMPORT _gPcd_FixedAtBuild_PcdCoreCount + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore + + PRESERVE8 + AREA ArmPlatformStackLib, CODE, READONLY + +//VOID +//ArmPlatformStackSet ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ArmPlatformStackSet FUNCTION + // Identify Stack + // Mask for ClusterId|CoreId + LoadConstantToReg (0xFFFF, r4) + and r1, r1, r4 + // Is it the Primary Core ? + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4) + ldr r4, [r4] + cmp r1, r4 + beq ArmPlatformStackSetPrimary + bne ArmPlatformStackSetSecondary + ENDFUNC + +//VOID +//ArmPlatformStackSetPrimary ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ArmPlatformStackSetPrimary FUNCTION + mov r4, lr + + // Add stack of primary stack to StackBase + add r0, r0, r2 + + // Compute SecondaryCoresCount * SecondaryCoreStackSize + LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1) + ldr r1, [r1] + sub r1, #1 + mul r3, r3, r1 + + // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize)) + add sp, r0, r3 + + bx r4 + ENDFUNC + +//VOID +//ArmPlatformStackSetSecondary ( +// IN UINTN StackBase, +// IN UINTN MpId, +// IN UINTN PrimaryStackSize, +// IN UINTN SecondaryStackSize +// ); +ArmPlatformStackSetSecondary FUNCTION + mov r4, lr + mov sp, r0 + + // Get Core Position + mov r0, r1 + bl ArmPlatformGetCorePosition + mov r5, r0 + + // Get Primary Core Position + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) + ldr r0, [r0] + bl ArmPlatformGetCorePosition + + // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1) + cmp r5, r0 + subhi r5, r5, #1 + add r5, r5, #1 + + // Compute top of the secondary stack + mul r3, r3, r5 + + // Set stack + add sp, sp, r3 + + bx r4 + ENDFUNC + + END diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.S b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.S deleted file mode 100644 index 94660c97fe..0000000000 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.S +++ /dev/null @@ -1,106 +0,0 @@ -// -// Copyright (c) 2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include - -.text -.align 3 - -GCC_ASM_EXPORT(ArmPlatformStackSet) -GCC_ASM_EXPORT(ArmPlatformStackSetPrimary) -GCC_ASM_EXPORT(ArmPlatformStackSetSecondary) - -GCC_ASM_IMPORT(ArmPlatformGetCorePosition) - -GCC_ASM_IMPORT(gPcd_FixedAtBuild_PcdCoreCount) -GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) - -//VOID -//ArmPlatformStackSet ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ASM_PFX(ArmPlatformStackSet): - // Identify Stack - // Mask for ClusterId|CoreId - LoadConstantToReg (0xFFFF, r4) - and r1, r1, r4 - // Is it the Primary Core ? - LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4) - ldr r4, [r4] - cmp r1, r4 - beq ASM_PFX(ArmPlatformStackSetPrimary) - bne ASM_PFX(ArmPlatformStackSetSecondary) - -//VOID -//ArmPlatformStackSetPrimary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ASM_PFX(ArmPlatformStackSetPrimary): - mov r4, lr - - // Add stack of primary stack to StackBase - add r0, r0, r2 - - // Compute SecondaryCoresCount * SecondaryCoreStackSize - LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1) - ldr r1, [r1] - sub r1, #1 - mul r3, r3, r1 - - // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize)) - add sp, r0, r3 - - bx r4 - -//VOID -//ArmPlatformStackSetSecondary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ASM_PFX(ArmPlatformStackSetSecondary): - mov r4, lr - mov sp, r0 - - // Get Core Position - mov r0, r1 - bl ASM_PFX(ArmPlatformGetCorePosition) - mov r5, r0 - - // Get Primary Core Position - LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) - ldr r0, [r0] - bl ASM_PFX(ArmPlatformGetCorePosition) - - // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1) - cmp r5, r0 - subhi r5, r5, #1 - add r5, r5, #1 - - // Compute top of the secondary stack - mul r3, r3, r5 - - // Set stack - add sp, sp, r3 - - bx r4 - diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.asm b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.asm deleted file mode 100644 index db92023922..0000000000 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.asm +++ /dev/null @@ -1,112 +0,0 @@ -// -// Copyright (c) 2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include - - INCLUDE AsmMacroIoLib.inc - - EXPORT ArmPlatformStackSet - EXPORT ArmPlatformStackSetPrimary - EXPORT ArmPlatformStackSetSecondary - - IMPORT ArmPlatformGetCorePosition - - IMPORT _gPcd_FixedAtBuild_PcdCoreCount - IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore - - PRESERVE8 - AREA ArmPlatformStackLib, CODE, READONLY - -//VOID -//ArmPlatformStackSet ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSet FUNCTION - // Identify Stack - // Mask for ClusterId|CoreId - LoadConstantToReg (0xFFFF, r4) - and r1, r1, r4 - // Is it the Primary Core ? - LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r4) - ldr r4, [r4] - cmp r1, r4 - beq ArmPlatformStackSetPrimary - bne ArmPlatformStackSetSecondary - ENDFUNC - -//VOID -//ArmPlatformStackSetPrimary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSetPrimary FUNCTION - mov r4, lr - - // Add stack of primary stack to StackBase - add r0, r0, r2 - - // Compute SecondaryCoresCount * SecondaryCoreStackSize - LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, r1) - ldr r1, [r1] - sub r1, #1 - mul r3, r3, r1 - - // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize)) - add sp, r0, r3 - - bx r4 - ENDFUNC - -//VOID -//ArmPlatformStackSetSecondary ( -// IN UINTN StackBase, -// IN UINTN MpId, -// IN UINTN PrimaryStackSize, -// IN UINTN SecondaryStackSize -// ); -ArmPlatformStackSetSecondary FUNCTION - mov r4, lr - mov sp, r0 - - // Get Core Position - mov r0, r1 - bl ArmPlatformGetCorePosition - mov r5, r0 - - // Get Primary Core Position - LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) - ldr r0, [r0] - bl ArmPlatformGetCorePosition - - // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1) - cmp r5, r0 - subhi r5, r5, #1 - add r5, r5, #1 - - // Compute top of the secondary stack - mul r3, r3, r5 - - // Set stack - add sp, sp, r3 - - bx r4 - ENDFUNC - - END diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf index a41dae2b4f..e48a65801d 100644 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf @@ -26,9 +26,9 @@ ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec -[Sources.common] - ArmPlatformStackLib.asm | RVCT - ArmPlatformStackLib.S | GCC +[Sources.ARM] + Arm/ArmPlatformStackLib.asm | RVCT + Arm/ArmPlatformStackLib.S | GCC [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.c b/ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.c index e82584e6dc..1f950d78f1 100644 --- a/ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.c +++ b/ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.c @@ -30,8 +30,9 @@ ArmSecureMonitorWorldInitialize ( ) { // Ensure the Monitor Table is 32bit aligned - ASSERT (IS_ALIGNED(MonitorVectorTable, BIT5)); + ASSERT (((UINTN)&MonitorVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); // Write the Monitor Mode Vector Table Address ArmWriteMVBar ((UINTN) &MonitorVectorTable); } + diff --git a/ArmPlatformPkg/Library/EblCmdLib/Arm/EblCmdMmu.c b/ArmPlatformPkg/Library/EblCmdLib/Arm/EblCmdMmu.c new file mode 100644 index 0000000000..138216e9b7 --- /dev/null +++ b/ArmPlatformPkg/Library/EblCmdLib/Arm/EblCmdMmu.c @@ -0,0 +1,370 @@ +/** @file +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GET_TT_ATTRIBUTES(TTEntry) ((TTEntry) & ~(TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)) +#define GET_TT_PAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFF) +#define GET_TT_LARGEPAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFFF) + +// Section +#define TT_DESCRIPTOR_SECTION_STRONGLY_ORDER (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ + TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ + TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ + TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ + TT_DESCRIPTOR_SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED) + +// Small Page +#define TT_DESCRIPTOR_PAGE_STRONGLY_ORDER (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED) + +// Large Page +#define TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC) +#define TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) +#define TT_DESCRIPTOR_LARGEPAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE) +#define TT_DESCRIPTOR_LARGEPAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ + TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ + TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ + TT_DESCRIPTOR_PAGE_AP_RW_RW | \ + TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE) + + +typedef enum { Level0, Level1,Level2 } MMU_LEVEL; + +typedef struct { + MMU_LEVEL Level; + UINT32 Value; + UINT32 Index; + UINT32* Table; +} MMU_ENTRY; + +MMU_ENTRY +MmuEntryCreate ( + IN MMU_LEVEL Level, + IN UINT32* Table, + IN UINT32 Index + ) +{ + MMU_ENTRY Entry; + Entry.Level = Level; + Entry.Value = Table[Index]; + Entry.Table = Table; + Entry.Index = Index; + return Entry; +} + +UINT32 +MmuEntryIsValidAddress ( + IN MMU_LEVEL Level, + IN UINT32 Entry + ) +{ + if (Level == Level0) { + return 0; + } else if (Level == Level1) { + if ((Entry & 0x3) == 0) { // Ignored + return 0; + } else if ((Entry & 0x3) == 2) { // Section Type + return 1; + } else { // Page Type + return 0; + } + } else if (Level == Level2){ + if ((Entry & 0x3) == 0) { // Ignored + return 0; + } else { // Page Type + return 1; + } + } else { + DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry)); + ASSERT(0); + return 0; + } +} + +UINT32 +MmuEntryGetAddress ( + IN MMU_ENTRY Entry + ) +{ + if (Entry.Level == Level1) { + if ((Entry.Value & 0x3) == 0) { + return 0; + } else if ((Entry.Value & 0x3) == 2) { // Section Type + return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK; + } else if ((Entry.Value & 0x3) == 1) { // Level2 Table + MMU_ENTRY Level2Entry = MmuEntryCreate (Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0); + return MmuEntryGetAddress (Level2Entry); + } else { // Page Type + return 0; + } + } else if (Entry.Level == Level2) { + if ((Entry.Value & 0x3) == 0) { // Ignored + return 0; + } else if ((Entry.Value & 0x3) == 1) { // Large Page + return Entry.Value & 0xFFFF0000; + } else if ((Entry.Value & 0x2) == 2) { // Small Page + return Entry.Value & 0xFFFFF000; + } else { + return 0; + } + } else { + ASSERT(0); + return 0; + } +} + +UINT32 +MmuEntryGetSize ( + IN MMU_ENTRY Entry + ) +{ + if (Entry.Level == Level1) { + if ((Entry.Value & 0x3) == 0) { + return 0; + } else if ((Entry.Value & 0x3) == 2) { + if (Entry.Value & (1 << 18)) + return 16*SIZE_1MB; + else + return SIZE_1MB; + } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section + return SIZE_1MB; + } else { + DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value)); + ASSERT(0); + return 0; + } + } else if (Entry.Level == Level2) { + if ((Entry.Value & 0x3) == 0) { // Ignored + return 0; + } else if ((Entry.Value & 0x3) == 1) { // Large Page + return SIZE_64KB; + } else if ((Entry.Value & 0x2) == 2) { // Small Page + return SIZE_4KB; + } else { + ASSERT(0); + return 0; + } + } else { + ASSERT(0); + return 0; + } +} + +CONST CHAR8* +MmuEntryGetAttributesName ( + IN MMU_ENTRY Entry + ) +{ + UINT32 Value; + + if (Entry.Level == Level1) { + Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK; + if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0)) + return "TT_DESCRIPTOR_SECTION_WRITE_BACK"; + else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0)) + return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH"; + else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0)) + return "TT_DESCRIPTOR_SECTION_DEVICE"; + else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0)) + return "TT_DESCRIPTOR_SECTION_UNCACHED"; + else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER) + return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED"; + else { + return "SectionUnknown"; + } + } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page + Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value); + if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK) + return "TT_DESCRIPTOR_PAGE_WRITE_BACK"; + else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) + return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH"; + else if (Value == TT_DESCRIPTOR_PAGE_DEVICE) + return "TT_DESCRIPTOR_PAGE_DEVICE"; + else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED) + return "TT_DESCRIPTOR_PAGE_UNCACHED"; + else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER) + return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED"; + else { + return "PageUnknown"; + } + } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page + Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value); + if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK) + return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK"; + else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH) + return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH"; + else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE) + return "TT_DESCRIPTOR_LARGEPAGE_DEVICE"; + else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED) + return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED"; + else { + return "LargePageUnknown"; + } + } else { + ASSERT(0); + return ""; + } +} + +UINT32 +MmuEntryGetAttributes ( + IN MMU_ENTRY Entry + ) +{ + if (Entry.Level == Level1) { + if ((Entry.Value & 0x3) == 0) { + return 0; + } else if ((Entry.Value & 0x3) == 2) { + return GET_TT_ATTRIBUTES(Entry.Value); + } else { + return 0; + } + } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page + if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK) + return TT_DESCRIPTOR_SECTION_WRITE_BACK(0); + else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) + return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); + else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE) + return TT_DESCRIPTOR_SECTION_DEVICE(0); + else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED) + return TT_DESCRIPTOR_SECTION_UNCACHED(0); + else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER) + return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER; + else { + return 0; + } + } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page + if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK) + return TT_DESCRIPTOR_SECTION_WRITE_BACK(0); + else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH) + return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); + else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE) + return TT_DESCRIPTOR_SECTION_DEVICE(0); + else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED) + return TT_DESCRIPTOR_SECTION_UNCACHED(0); + else { + return 0; + } + } else { + return 0; + } +} + + +MMU_ENTRY +DumpMmuLevel ( + IN MMU_LEVEL Level, + IN UINT32* Table, + IN MMU_ENTRY PreviousEntry + ) +{ + UINT32 Index = 0, Count; + MMU_ENTRY LastEntry, Entry; + + ASSERT((Level == Level1) || (Level == Level2)); + + if (Level == Level1) Count = 4096; + else Count = 256; + + // At Level1, we will get into this function because PreviousEntry is not valid + if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) { + // Find the first valid address + for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++); + + LastEntry = MmuEntryCreate(Level,Table,Index); + Index++; + } else { + LastEntry = PreviousEntry; + } + + for (; Index < Count; Index++) { + Entry = MmuEntryCreate(Level,Table,Index); + if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection + LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry); + } else if (!MmuEntryIsValidAddress(Level,Table[Index])) { + if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) { + AsciiPrint("0x%08X-0x%08X\t%a\n", + MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, + MmuEntryGetAttributesName(LastEntry)); + } + LastEntry = Entry; + } else { + if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) { + if (MmuEntryIsValidAddress(Level,LastEntry.Value)) { + AsciiPrint("0x%08X-0x%08X\t%a\n", + MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, + MmuEntryGetAttributesName(LastEntry)); + } + LastEntry = Entry; + } else { + ASSERT(LastEntry.Value != 0); + } + } + PreviousEntry = Entry; + } + + if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) { + AsciiPrint("0x%08X-0x%08X\t%a\n", + MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, + MmuEntryGetAttributesName(LastEntry)); + } + + return LastEntry; +} + + +EFI_STATUS +EblDumpMmu ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + UINT32 *TTEntry; + MMU_ENTRY NoEntry; + + TTEntry = ArmGetTTBR0BaseAddress(); + + AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry); + AsciiPrint ("Address Range\t\tAttributes\n"); + AsciiPrint ("____________________________________________________\n"); + + NoEntry.Level = (MMU_LEVEL)200; + DumpMmuLevel(Level1,TTEntry,NoEntry); + + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf b/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf index 9ddc9e82d1..33508c26ea 100644 --- a/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf +++ b/ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf @@ -29,9 +29,11 @@ [Sources.common] EblCmdLib.c - EblCmdMmu.c EblCmdFdt.c +[Sources.ARM] + Arm/EblCmdMmu.c + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c b/ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c deleted file mode 100644 index 138216e9b7..0000000000 --- a/ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c +++ /dev/null @@ -1,370 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2012, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define GET_TT_ATTRIBUTES(TTEntry) ((TTEntry) & ~(TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)) -#define GET_TT_PAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFF) -#define GET_TT_LARGEPAGE_ATTRIBUTES(TTEntry) ((TTEntry) & 0xFFFF) - -// Section -#define TT_DESCRIPTOR_SECTION_STRONGLY_ORDER (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \ - TT_DESCRIPTOR_SECTION_NG_GLOBAL | \ - TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \ - TT_DESCRIPTOR_SECTION_DOMAIN(0) | \ - TT_DESCRIPTOR_SECTION_AP_RW_RW | \ - TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED) - -// Small Page -#define TT_DESCRIPTOR_PAGE_STRONGLY_ORDER (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \ - TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ - TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ - TT_DESCRIPTOR_PAGE_AP_RW_RW | \ - TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED) - -// Large Page -#define TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ - TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ - TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ - TT_DESCRIPTOR_PAGE_AP_RW_RW | \ - TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC) -#define TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ - TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ - TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ - TT_DESCRIPTOR_PAGE_AP_RW_RW | \ - TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) -#define TT_DESCRIPTOR_LARGEPAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ - TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ - TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ - TT_DESCRIPTOR_PAGE_AP_RW_RW | \ - TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE) -#define TT_DESCRIPTOR_LARGEPAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE | \ - TT_DESCRIPTOR_PAGE_NG_GLOBAL | \ - TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \ - TT_DESCRIPTOR_PAGE_AP_RW_RW | \ - TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE) - - -typedef enum { Level0, Level1,Level2 } MMU_LEVEL; - -typedef struct { - MMU_LEVEL Level; - UINT32 Value; - UINT32 Index; - UINT32* Table; -} MMU_ENTRY; - -MMU_ENTRY -MmuEntryCreate ( - IN MMU_LEVEL Level, - IN UINT32* Table, - IN UINT32 Index - ) -{ - MMU_ENTRY Entry; - Entry.Level = Level; - Entry.Value = Table[Index]; - Entry.Table = Table; - Entry.Index = Index; - return Entry; -} - -UINT32 -MmuEntryIsValidAddress ( - IN MMU_LEVEL Level, - IN UINT32 Entry - ) -{ - if (Level == Level0) { - return 0; - } else if (Level == Level1) { - if ((Entry & 0x3) == 0) { // Ignored - return 0; - } else if ((Entry & 0x3) == 2) { // Section Type - return 1; - } else { // Page Type - return 0; - } - } else if (Level == Level2){ - if ((Entry & 0x3) == 0) { // Ignored - return 0; - } else { // Page Type - return 1; - } - } else { - DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry)); - ASSERT(0); - return 0; - } -} - -UINT32 -MmuEntryGetAddress ( - IN MMU_ENTRY Entry - ) -{ - if (Entry.Level == Level1) { - if ((Entry.Value & 0x3) == 0) { - return 0; - } else if ((Entry.Value & 0x3) == 2) { // Section Type - return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK; - } else if ((Entry.Value & 0x3) == 1) { // Level2 Table - MMU_ENTRY Level2Entry = MmuEntryCreate (Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0); - return MmuEntryGetAddress (Level2Entry); - } else { // Page Type - return 0; - } - } else if (Entry.Level == Level2) { - if ((Entry.Value & 0x3) == 0) { // Ignored - return 0; - } else if ((Entry.Value & 0x3) == 1) { // Large Page - return Entry.Value & 0xFFFF0000; - } else if ((Entry.Value & 0x2) == 2) { // Small Page - return Entry.Value & 0xFFFFF000; - } else { - return 0; - } - } else { - ASSERT(0); - return 0; - } -} - -UINT32 -MmuEntryGetSize ( - IN MMU_ENTRY Entry - ) -{ - if (Entry.Level == Level1) { - if ((Entry.Value & 0x3) == 0) { - return 0; - } else if ((Entry.Value & 0x3) == 2) { - if (Entry.Value & (1 << 18)) - return 16*SIZE_1MB; - else - return SIZE_1MB; - } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section - return SIZE_1MB; - } else { - DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value)); - ASSERT(0); - return 0; - } - } else if (Entry.Level == Level2) { - if ((Entry.Value & 0x3) == 0) { // Ignored - return 0; - } else if ((Entry.Value & 0x3) == 1) { // Large Page - return SIZE_64KB; - } else if ((Entry.Value & 0x2) == 2) { // Small Page - return SIZE_4KB; - } else { - ASSERT(0); - return 0; - } - } else { - ASSERT(0); - return 0; - } -} - -CONST CHAR8* -MmuEntryGetAttributesName ( - IN MMU_ENTRY Entry - ) -{ - UINT32 Value; - - if (Entry.Level == Level1) { - Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK; - if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0)) - return "TT_DESCRIPTOR_SECTION_WRITE_BACK"; - else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0)) - return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH"; - else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0)) - return "TT_DESCRIPTOR_SECTION_DEVICE"; - else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0)) - return "TT_DESCRIPTOR_SECTION_UNCACHED"; - else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER) - return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED"; - else { - return "SectionUnknown"; - } - } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page - Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value); - if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK) - return "TT_DESCRIPTOR_PAGE_WRITE_BACK"; - else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) - return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH"; - else if (Value == TT_DESCRIPTOR_PAGE_DEVICE) - return "TT_DESCRIPTOR_PAGE_DEVICE"; - else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED) - return "TT_DESCRIPTOR_PAGE_UNCACHED"; - else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER) - return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED"; - else { - return "PageUnknown"; - } - } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page - Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value); - if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK) - return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK"; - else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH) - return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH"; - else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE) - return "TT_DESCRIPTOR_LARGEPAGE_DEVICE"; - else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED) - return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED"; - else { - return "LargePageUnknown"; - } - } else { - ASSERT(0); - return ""; - } -} - -UINT32 -MmuEntryGetAttributes ( - IN MMU_ENTRY Entry - ) -{ - if (Entry.Level == Level1) { - if ((Entry.Value & 0x3) == 0) { - return 0; - } else if ((Entry.Value & 0x3) == 2) { - return GET_TT_ATTRIBUTES(Entry.Value); - } else { - return 0; - } - } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page - if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK) - return TT_DESCRIPTOR_SECTION_WRITE_BACK(0); - else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) - return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); - else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE) - return TT_DESCRIPTOR_SECTION_DEVICE(0); - else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED) - return TT_DESCRIPTOR_SECTION_UNCACHED(0); - else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER) - return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER; - else { - return 0; - } - } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page - if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK) - return TT_DESCRIPTOR_SECTION_WRITE_BACK(0); - else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH) - return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); - else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE) - return TT_DESCRIPTOR_SECTION_DEVICE(0); - else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED) - return TT_DESCRIPTOR_SECTION_UNCACHED(0); - else { - return 0; - } - } else { - return 0; - } -} - - -MMU_ENTRY -DumpMmuLevel ( - IN MMU_LEVEL Level, - IN UINT32* Table, - IN MMU_ENTRY PreviousEntry - ) -{ - UINT32 Index = 0, Count; - MMU_ENTRY LastEntry, Entry; - - ASSERT((Level == Level1) || (Level == Level2)); - - if (Level == Level1) Count = 4096; - else Count = 256; - - // At Level1, we will get into this function because PreviousEntry is not valid - if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) { - // Find the first valid address - for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++); - - LastEntry = MmuEntryCreate(Level,Table,Index); - Index++; - } else { - LastEntry = PreviousEntry; - } - - for (; Index < Count; Index++) { - Entry = MmuEntryCreate(Level,Table,Index); - if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection - LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry); - } else if (!MmuEntryIsValidAddress(Level,Table[Index])) { - if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) { - AsciiPrint("0x%08X-0x%08X\t%a\n", - MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, - MmuEntryGetAttributesName(LastEntry)); - } - LastEntry = Entry; - } else { - if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) { - if (MmuEntryIsValidAddress(Level,LastEntry.Value)) { - AsciiPrint("0x%08X-0x%08X\t%a\n", - MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, - MmuEntryGetAttributesName(LastEntry)); - } - LastEntry = Entry; - } else { - ASSERT(LastEntry.Value != 0); - } - } - PreviousEntry = Entry; - } - - if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) { - AsciiPrint("0x%08X-0x%08X\t%a\n", - MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1, - MmuEntryGetAttributesName(LastEntry)); - } - - return LastEntry; -} - - -EFI_STATUS -EblDumpMmu ( - IN UINTN Argc, - IN CHAR8 **Argv - ) -{ - UINT32 *TTEntry; - MMU_ENTRY NoEntry; - - TTEntry = ArmGetTTBR0BaseAddress(); - - AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry); - AsciiPrint ("Address Range\t\tAttributes\n"); - AsciiPrint ("____________________________________________________\n"); - - NoEntry.Level = (MMU_LEVEL)200; - DumpMmuLevel(Level1,TTEntry,NoEntry); - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c b/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c new file mode 100644 index 0000000000..b0594ae2cd --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c @@ -0,0 +1,62 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2012, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include + +#include "PrePeiCore.h" + +VOID +PeiCommonExceptionEntry ( + IN UINT32 Entry, + IN UINTN LR + ) +{ + CHAR8 Buffer[100]; + UINTN CharCount; + + switch (Entry) { + case 0: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); + break; + case 1: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); + break; + case 2: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); + break; + case 3: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); + break; + case 4: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); + break; + case 5: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); + break; + case 6: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); + break; + case 7: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); + break; + default: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); + break; + } + SerialPortWrite ((UINT8 *) Buffer, CharCount); + while(1); +} + diff --git a/ArmPlatformPkg/PrePeiCore/Arm/Exception.S b/ArmPlatformPkg/PrePeiCore/Arm/Exception.S new file mode 100644 index 0000000000..abce21d0a5 --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/Exception.S @@ -0,0 +1,102 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include +#include +#include + +#start of the code section +.text +.align 5 + +# IMPORT +GCC_ASM_IMPORT(PeiCommonExceptionEntry) + +# EXPORT +GCC_ASM_EXPORT(PeiVectorTable) + +//============================================================ +//Default Exception Handlers +//============================================================ + + +ASM_PFX(PeiVectorTable): + b _DefaultResetHandler + b _DefaultUndefined + b _DefaultSWI + b _DefaultPrefetchAbort + b _DefaultDataAbort + b _DefaultReserved + b _DefaultIrq + b _DefaultFiq + +// +// Default Exception handlers: There is no plan to return from any of these exceptions. +// No context saving at all. +// +_DefaultResetHandler: + mov r1, lr + # Switch to SVC for common stack + cps #0x13 + mov r0, #0 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultUndefined: + sub r1, LR, #4 + # Switch to SVC for common stack + cps #0x13 + mov r0, #1 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultSWI: + sub r1, LR, #4 + # Switch to SVC for common stack + cps #0x13 + mov r0, #2 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultPrefetchAbort: + sub r1, LR, #4 + # Switch to SVC for common stack + cps #0x13 + mov r0, #3 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultDataAbort: + sub r1, LR, #8 + # Switch to SVC for common stack + cps #0x13 + mov r0, #4 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultReserved: + mov r1, lr + # Switch to SVC for common stack + cps #0x13 + mov r0, #5 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultIrq: + sub r1, LR, #4 + # Switch to SVC for common stack + cps #0x13 + mov r0, #6 + blx ASM_PFX(PeiCommonExceptionEntry) + +_DefaultFiq: + sub r1, LR, #4 + # Switch to SVC for common stack + cps #0x13 + mov r0, #7 + blx ASM_PFX(PeiCommonExceptionEntry) + diff --git a/ArmPlatformPkg/PrePeiCore/Arm/Exception.asm b/ArmPlatformPkg/PrePeiCore/Arm/Exception.asm new file mode 100644 index 0000000000..55bd4af1dd --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/Exception.asm @@ -0,0 +1,91 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include + + IMPORT PeiCommonExceptionEntry + EXPORT PeiVectorTable + + PRESERVE8 + AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5 + +//============================================================ +//Default Exception Handlers +//============================================================ + + +PeiVectorTable + b _DefaultResetHandler + b _DefaultUndefined + b _DefaultSWI + b _DefaultPrefetchAbort + b _DefaultDataAbort + b _DefaultReserved + b _DefaultIrq + b _DefaultFiq + +// +// Default Exception handlers: There is no plan to return from any of these exceptions. +// No context saving at all. +// +_DefaultResetHandler + mov r1, lr + cps #0x13 ; Switch to SVC for common stack + mov r0, #0 + blx PeiCommonExceptionEntry + +_DefaultUndefined + sub r1, LR, #4 + cps #0x13 ; Switch to SVC for common stack + mov r0, #1 + blx PeiCommonExceptionEntry + +_DefaultSWI + sub r1, LR, #4 + cps #0x13 ; Switch to SVC for common stack + mov r0, #2 + blx PeiCommonExceptionEntry + +_DefaultPrefetchAbort + sub r1, LR, #4 + cps #0x13 ; Switch to SVC for common stack + mov r0, #3 + blx PeiCommonExceptionEntry + +_DefaultDataAbort + sub r1, LR, #8 + cps #0x13 ; Switch to SVC for common stack + mov r0, #4 + blx PeiCommonExceptionEntry + +_DefaultReserved + mov r1, lr + cps #0x13 ; Switch to SVC for common stack + mov r0, #5 + blx PeiCommonExceptionEntry + +_DefaultIrq + sub r1, LR, #4 + cps #0x13 ; Switch to SVC for common stack + mov r0, #6 + blx PeiCommonExceptionEntry + +_DefaultFiq + sub r1, LR, #4 + cps #0x13 ; Switch to SVC for common stack + mov r0, #7 + blx PeiCommonExceptionEntry + + END diff --git a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S new file mode 100644 index 0000000000..f902a251c2 --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S @@ -0,0 +1,85 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include +#include + +.text +.align 3 + +GCC_ASM_IMPORT(CEntryPoint) +GCC_ASM_IMPORT(ArmReadMpidr) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +StartupAddr: .word CEntryPoint + +ASM_PFX(_ModuleEntryPoint): + // Identify CPU ID + bl ASM_PFX(ArmReadMpidr) + // Get ID of this CPU in Multicore system + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r5, r0, r1 + + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + add r1, r1, r2 + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) + cmp r5, r3 + beq _SetupPrimaryCoreStack + +_SetupSecondaryCoreStack: + // r1 contains the base of the secondary stacks + + // Get the Core Position (ClusterId * 4) + CoreId + GetCorePositionFromMpId(r0, r5, r2) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add r0, r0, #1 + + // StackOffset = CorePos * StackSize + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2) + mul r0, r0, r2 + // SP = StackBase + StackOffset + add sp, r1, r0 + +_PrepareArguments: + // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector + LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2) + add r2, r2, #4 + ldr r1, [r2] + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r3, StartupAddr + + // Jump to PrePeiCore C code + // r0 = mp_id + // r1 = pei_core_address + mov r0, r5 + blx r3 + +_SetupPrimaryCoreStack: + // r1 contains the top of the primary stack + LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2) + + // The reserved space for global variable must be 8-bytes aligned for pushing + // 64-bit variable on the stack + SetPrimaryStack (r1, r2, r3) + b _PrepareArguments + +_NeverReturn: + b _NeverReturn diff --git a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm new file mode 100644 index 0000000000..a3dd1fb2c6 --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.asm @@ -0,0 +1,89 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include +#include + + INCLUDE AsmMacroIoLib.inc + + IMPORT CEntryPoint + IMPORT ArmReadMpidr + EXPORT _ModuleEntryPoint + + PRESERVE8 + AREA PrePeiCoreEntryPoint, CODE, READONLY + +StartupAddr DCD CEntryPoint + +_ModuleEntryPoint + // Identify CPU ID + bl ArmReadMpidr + // Get ID of this CPU in Multicore system + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r5, r0, r1 + + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + add r1, r1, r2 + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) + cmp r5, r3 + beq _SetupPrimaryCoreStack + +_SetupSecondaryCoreStack + // r1 contains the base of the secondary stacks + + // Get the Core Position (ClusterId * 4) + CoreId + GetCorePositionFromMpId(r0, r5, r2) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add r0, r0, #1 + + // StackOffset = CorePos * StackSize + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2) + mul r0, r0, r2 + // SP = StackBase + StackOffset + add sp, r1, r0 + +_PrepareArguments + // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector + LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2) + add r2, r2, #4 + ldr r1, [r2] + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r3, StartupAddr + + // Jump to PrePeiCore C code + // r0 = mp_id + // r1 = pei_core_address + mov r0, r5 + blx r3 + +_SetupPrimaryCoreStack + // r1 contains the top of the primary stack + LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2) + + // The reserved space for global variable must be 8-bytes aligned for pushing + // 64-bit variable on the stack + SetPrimaryStack (r1, r2, r3) + b _PrepareArguments + +_NeverReturn + b _NeverReturn + + END diff --git a/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.S b/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.S new file mode 100644 index 0000000000..2543f58414 --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.S @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +.text +.align 3 + +GCC_ASM_EXPORT(SecSwitchStack) + + + +#/** +# This allows the caller to switch the stack and return +# +# @param StackDelta Signed amount by which to modify the stack pointer +# +# @return Nothing. Goes to the Entry Point passing in the new parameters +# +#**/ +#VOID +#EFIAPI +#SecSwitchStack ( +# VOID *StackDelta +# )# +# +ASM_PFX(SecSwitchStack): + mov R1, R13 + add R1, R0, R1 + mov R13, R1 + bx LR + + + diff --git a/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm b/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm new file mode 100644 index 0000000000..10da81d6ac --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.asm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT SecSwitchStack + + AREA Switch_Stack, CODE, READONLY + +;/** +; This allows the caller to switch the stack and return +; +; @param StackDelta Signed amount by which to modify the stack pointer +; +; @return Nothing. Goes to the Entry Point passing in the new parameters +; +;**/ +;VOID +;EFIAPI +;SecSwitchStack ( +; VOID *StackDelta +; ); +; +SecSwitchStack + MOV R1, SP + ADD R1, R0, R1 + MOV SP, R1 + BX LR + END diff --git a/ArmPlatformPkg/PrePeiCore/Exception.S b/ArmPlatformPkg/PrePeiCore/Exception.S deleted file mode 100644 index abce21d0a5..0000000000 --- a/ArmPlatformPkg/PrePeiCore/Exception.S +++ /dev/null @@ -1,102 +0,0 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# - -#include -#include -#include - -#start of the code section -.text -.align 5 - -# IMPORT -GCC_ASM_IMPORT(PeiCommonExceptionEntry) - -# EXPORT -GCC_ASM_EXPORT(PeiVectorTable) - -//============================================================ -//Default Exception Handlers -//============================================================ - - -ASM_PFX(PeiVectorTable): - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq - -// -// Default Exception handlers: There is no plan to return from any of these exceptions. -// No context saving at all. -// -_DefaultResetHandler: - mov r1, lr - # Switch to SVC for common stack - cps #0x13 - mov r0, #0 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultUndefined: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #1 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultSWI: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #2 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultPrefetchAbort: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #3 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultDataAbort: - sub r1, LR, #8 - # Switch to SVC for common stack - cps #0x13 - mov r0, #4 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultReserved: - mov r1, lr - # Switch to SVC for common stack - cps #0x13 - mov r0, #5 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultIrq: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #6 - blx ASM_PFX(PeiCommonExceptionEntry) - -_DefaultFiq: - sub r1, LR, #4 - # Switch to SVC for common stack - cps #0x13 - mov r0, #7 - blx ASM_PFX(PeiCommonExceptionEntry) - diff --git a/ArmPlatformPkg/PrePeiCore/Exception.asm b/ArmPlatformPkg/PrePeiCore/Exception.asm deleted file mode 100644 index 55bd4af1dd..0000000000 --- a/ArmPlatformPkg/PrePeiCore/Exception.asm +++ /dev/null @@ -1,91 +0,0 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include - - IMPORT PeiCommonExceptionEntry - EXPORT PeiVectorTable - - PRESERVE8 - AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5 - -//============================================================ -//Default Exception Handlers -//============================================================ - - -PeiVectorTable - b _DefaultResetHandler - b _DefaultUndefined - b _DefaultSWI - b _DefaultPrefetchAbort - b _DefaultDataAbort - b _DefaultReserved - b _DefaultIrq - b _DefaultFiq - -// -// Default Exception handlers: There is no plan to return from any of these exceptions. -// No context saving at all. -// -_DefaultResetHandler - mov r1, lr - cps #0x13 ; Switch to SVC for common stack - mov r0, #0 - blx PeiCommonExceptionEntry - -_DefaultUndefined - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #1 - blx PeiCommonExceptionEntry - -_DefaultSWI - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #2 - blx PeiCommonExceptionEntry - -_DefaultPrefetchAbort - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #3 - blx PeiCommonExceptionEntry - -_DefaultDataAbort - sub r1, LR, #8 - cps #0x13 ; Switch to SVC for common stack - mov r0, #4 - blx PeiCommonExceptionEntry - -_DefaultReserved - mov r1, lr - cps #0x13 ; Switch to SVC for common stack - mov r0, #5 - blx PeiCommonExceptionEntry - -_DefaultIrq - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #6 - blx PeiCommonExceptionEntry - -_DefaultFiq - sub r1, LR, #4 - cps #0x13 ; Switch to SVC for common stack - mov r0, #7 - blx PeiCommonExceptionEntry - - END diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index f1300e0e8c..fdd8697edf 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -1,7 +1,7 @@ /** @file * Main file supporting the transition to PEI Core in Normal World for Versatile Express * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -15,9 +15,7 @@ #include #include -#include #include -#include #include @@ -74,10 +72,10 @@ CEntryPoint ( ) { //Clean Data cache - ArmCleanInvalidateDataCache(); + ArmCleanInvalidateDataCache (); //Invalidate instruction cache - ArmInvalidateInstructionCache(); + ArmInvalidateInstructionCache (); // Enable Instruction & Data caches ArmEnableDataCache (); @@ -88,9 +86,9 @@ CEntryPoint ( // as Non-secure interface is already enabled in Secure world. // - // Write VBAR - The Vector table must be 32-byte aligned - ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0); - ArmWriteVBar((UINT32)PeiVectorTable); + // Write VBAR - The Exception Vector table must be aligned to its requirement + ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); + ArmWriteVBar ((UINTN)PeiVectorTable); //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. @@ -162,44 +160,3 @@ PrePeiCoreGetGlobalVariableMemory ( return EFI_SUCCESS; } -VOID -PeiCommonExceptionEntry ( - IN UINT32 Entry, - IN UINT32 LR - ) -{ - CHAR8 Buffer[100]; - UINTN CharCount; - - switch (Entry) { - case 0: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); - break; - case 1: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); - break; - case 2: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); - break; - case 3: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); - break; - case 4: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); - break; - case 5: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); - break; - case 6: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); - break; - case 7: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); - break; - default: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); - break; - } - SerialPortWrite ((UINT8 *) Buffer, CharCount); - while(1); -} diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h index 9f7c9c3339..20684e2f90 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -74,4 +74,10 @@ SecondaryMain ( IN UINTN MpId ); +VOID +PeiCommonExceptionEntry ( + IN UINT32 Entry, + IN UINTN LR + ); + #endif diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S deleted file mode 100644 index f902a251c2..0000000000 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S +++ /dev/null @@ -1,85 +0,0 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include -#include - -.text -.align 3 - -GCC_ASM_IMPORT(CEntryPoint) -GCC_ASM_IMPORT(ArmReadMpidr) -GCC_ASM_EXPORT(_ModuleEntryPoint) - -StartupAddr: .word CEntryPoint - -ASM_PFX(_ModuleEntryPoint): - // Identify CPU ID - bl ASM_PFX(ArmReadMpidr) - // Get ID of this CPU in Multicore system - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r5, r0, r1 - - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - add r1, r1, r2 - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) - cmp r5, r3 - beq _SetupPrimaryCoreStack - -_SetupSecondaryCoreStack: - // r1 contains the base of the secondary stacks - - // Get the Core Position (ClusterId * 4) + CoreId - GetCorePositionFromMpId(r0, r5, r2) - // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack - add r0, r0, #1 - - // StackOffset = CorePos * StackSize - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2) - mul r0, r0, r2 - // SP = StackBase + StackOffset - add sp, r1, r0 - -_PrepareArguments: - // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector - LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2) - add r2, r2, #4 - ldr r1, [r2] - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r3, StartupAddr - - // Jump to PrePeiCore C code - // r0 = mp_id - // r1 = pei_core_address - mov r0, r5 - blx r3 - -_SetupPrimaryCoreStack: - // r1 contains the top of the primary stack - LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2) - - // The reserved space for global variable must be 8-bytes aligned for pushing - // 64-bit variable on the stack - SetPrimaryStack (r1, r2, r3) - b _PrepareArguments - -_NeverReturn: - b _NeverReturn diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm deleted file mode 100644 index a3dd1fb2c6..0000000000 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm +++ /dev/null @@ -1,89 +0,0 @@ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include -#include - - INCLUDE AsmMacroIoLib.inc - - IMPORT CEntryPoint - IMPORT ArmReadMpidr - EXPORT _ModuleEntryPoint - - PRESERVE8 - AREA PrePeiCoreEntryPoint, CODE, READONLY - -StartupAddr DCD CEntryPoint - -_ModuleEntryPoint - // Identify CPU ID - bl ArmReadMpidr - // Get ID of this CPU in Multicore system - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r5, r0, r1 - - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - add r1, r1, r2 - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) - cmp r5, r3 - beq _SetupPrimaryCoreStack - -_SetupSecondaryCoreStack - // r1 contains the base of the secondary stacks - - // Get the Core Position (ClusterId * 4) + CoreId - GetCorePositionFromMpId(r0, r5, r2) - // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack - add r0, r0, #1 - - // StackOffset = CorePos * StackSize - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2) - mul r0, r0, r2 - // SP = StackBase + StackOffset - add sp, r1, r0 - -_PrepareArguments - // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector - LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2) - add r2, r2, #4 - ldr r1, [r2] - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r3, StartupAddr - - // Jump to PrePeiCore C code - // r0 = mp_id - // r1 = pei_core_address - mov r0, r5 - blx r3 - -_SetupPrimaryCoreStack - // r1 contains the top of the primary stack - LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2) - - // The reserved space for global variable must be 8-bytes aligned for pushing - // 64-bit variable on the stack - SetPrimaryStack (r1, r2, r3) - b _PrepareArguments - -_NeverReturn - b _NeverReturn - - END diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf index efdc4b7544..91f9b3a784 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -20,16 +20,19 @@ MODULE_TYPE = SEC VERSION_STRING = 1.0 -[Sources.ARM] - PrePeiCoreEntryPoint.asm | RVCT - PrePeiCoreEntryPoint.S | GCC - PrePeiCore.c +[Sources.common] MainMPCore.c - SwitchStack.asm | RVCT - SwitchStack.S | GCC - Exception.asm | RVCT - Exception.S | GCC - + PrePeiCore.c + +[Sources.ARM] + Arm/ArchPrePeiCore.c + Arm/PrePeiCoreEntryPoint.asm | RVCT + Arm/PrePeiCoreEntryPoint.S | GCC + Arm/SwitchStack.asm | RVCT + Arm/SwitchStack.S | GCC + Arm/Exception.asm | RVCT + Arm/Exception.S | GCC + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index 90582d8922..bf590dbac0 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -20,15 +20,18 @@ MODULE_TYPE = SEC VERSION_STRING = 1.0 -[Sources.ARM] - PrePeiCoreEntryPoint.asm | RVCT - PrePeiCoreEntryPoint.S | GCC +[Sources.common] PrePeiCore.c MainUniCore.c - SwitchStack.asm | RVCT - SwitchStack.S | GCC - Exception.asm | RVCT - Exception.S | GCC + +[Sources.ARM] + Arm/ArchPrePeiCore.c + Arm/PrePeiCoreEntryPoint.asm | RVCT + Arm/PrePeiCoreEntryPoint.S | GCC + Arm/SwitchStack.asm | RVCT + Arm/SwitchStack.S | GCC + Arm/Exception.asm | RVCT + Arm/Exception.S | GCC [Packages] MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/PrePeiCore/SwitchStack.S b/ArmPlatformPkg/PrePeiCore/SwitchStack.S deleted file mode 100644 index 2543f58414..0000000000 --- a/ArmPlatformPkg/PrePeiCore/SwitchStack.S +++ /dev/null @@ -1,43 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -.text -.align 3 - -GCC_ASM_EXPORT(SecSwitchStack) - - - -#/** -# This allows the caller to switch the stack and return -# -# @param StackDelta Signed amount by which to modify the stack pointer -# -# @return Nothing. Goes to the Entry Point passing in the new parameters -# -#**/ -#VOID -#EFIAPI -#SecSwitchStack ( -# VOID *StackDelta -# )# -# -ASM_PFX(SecSwitchStack): - mov R1, R13 - add R1, R0, R1 - mov R13, R1 - bx LR - - - diff --git a/ArmPlatformPkg/PrePeiCore/SwitchStack.asm b/ArmPlatformPkg/PrePeiCore/SwitchStack.asm deleted file mode 100644 index 10da81d6ac..0000000000 --- a/ArmPlatformPkg/PrePeiCore/SwitchStack.asm +++ /dev/null @@ -1,38 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -;------------------------------------------------------------------------------ - - EXPORT SecSwitchStack - - AREA Switch_Stack, CODE, READONLY - -;/** -; This allows the caller to switch the stack and return -; -; @param StackDelta Signed amount by which to modify the stack pointer -; -; @return Nothing. Goes to the Entry Point passing in the new parameters -; -;**/ -;VOID -;EFIAPI -;SecSwitchStack ( -; VOID *StackDelta -; ); -; -SecSwitchStack - MOV R1, SP - ADD R1, R0, R1 - MOV SP, R1 - BX LR - END diff --git a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S new file mode 100644 index 0000000000..c0c20a9206 --- /dev/null +++ b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S @@ -0,0 +1,149 @@ +// +// Copyright (c) 2011-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include +#include + +#include + +.text +.align 3 + +GCC_ASM_IMPORT(CEntryPoint) +GCC_ASM_IMPORT(ArmReadMpidr) +GCC_ASM_IMPORT(ArmPlatformStackSet) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +StartupAddr: .word CEntryPoint + + +ASM_PFX(_ModuleEntryPoint): + // Get ID of this CPU in Multicore system + bl ASM_PFX(ArmReadMpidr) + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r6, r0, r1 + +_SetSVCMode: + // Enter SVC mode, Disable FIQ and IRQ + mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ) + msr CPSR_c, r1 + +// Check if we can install the stack at the top of the System Memory or if we need +// to install the stacks at the bottom of the Firmware Device (case the FD is located +// at the top of the DRAM) +_SetupStackPosition: + // Compute Top of System Memory + LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2) + sub r2, r2, #1 + add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize + + // Calculate Top of the Firmware Device + LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2) + LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3) + sub r3, r3, #1 + add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize + + // UEFI Memory Size (stacks are allocated in this region) + LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4) + + // + // Reserve the memory for the UEFI region (contain stacks on its top) + // + + // Calculate how much space there is between the top of the Firmware and the Top of the System Memory + subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop + bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM + cmp r0, r4 + bge _SetupStack + + // Case the top of stacks is the FdBaseAddress + mov r1, r2 + +_SetupStack: + // r1 contains the top of the stack (and the UEFI Memory) + + // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment + // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the + // top of the memory space) + adds r7, r1, #1 + bcs _SetupOverflowStack + +_SetupAlignedStack: + mov r1, r7 + b _GetBaseUefiMemory + +_SetupOverflowStack: + // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE + // aligned (4KB) + LoadConstantToReg (EFI_PAGE_MASK, r7) + and r7, r7, r1 + sub r1, r1, r7 + +_GetBaseUefiMemory: + // Calculate the Base of the UEFI Memory + sub r7, r1, r4 + +_GetStackBase: + // r1 = The top of the Mpcore Stacks + // Stack for the primary core = PrimaryCoreStack + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + sub r8, r1, r2 + + // Stack for the secondary core = Number of Cores - 1 + LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0) + sub r0, r0, #1 + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1) + mul r1, r1, r0 + sub r8, r8, r1 + + // r8 = The base of the MpCore Stacks (primary stack & secondary stacks) + mov r0, r8 + mov r1, r6 + //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize) + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) + bl ASM_PFX(ArmPlatformStackSet) + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4) + cmp r6, r4 + bne _PrepareArguments + +_ReserveGlobalVariable: + LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0) + // InitializePrimaryStack($GlobalVariableSize, $Tmp1) + InitializePrimaryStack(r0, r1) + +_PrepareArguments: + mov r0, r6 + mov r1, r7 + mov r2, r8 + mov r3, sp + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r4, StartupAddr + + // Jump to PrePiCore C code + // r0 = MpId + // r1 = UefiMemoryBase + // r2 = StacksBase + // r3 = GlobalVariableBase + blx r4 + +_NeverReturn: + b _NeverReturn + diff --git a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm new file mode 100644 index 0000000000..5efdb532af --- /dev/null +++ b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.asm @@ -0,0 +1,152 @@ +// +// Copyright (c) 2011-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include +#include + +#include + + INCLUDE AsmMacroIoLib.inc + + IMPORT CEntryPoint + IMPORT ArmReadMpidr + IMPORT ArmPlatformStackSet + + EXPORT _ModuleEntryPoint + + PRESERVE8 + AREA PrePiCoreEntryPoint, CODE, READONLY + +StartupAddr DCD CEntryPoint + +_ModuleEntryPoint + // Get ID of this CPU in Multicore system + bl ArmReadMpidr + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r6, r0, r1 + +_SetSVCMode + // Enter SVC mode, Disable FIQ and IRQ + mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ) + msr CPSR_c, r1 + +// Check if we can install the stack at the top of the System Memory or if we need +// to install the stacks at the bottom of the Firmware Device (case the FD is located +// at the top of the DRAM) +_SetupStackPosition + // Compute Top of System Memory + LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2) + sub r2, r2, #1 + add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize + + // Calculate Top of the Firmware Device + LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2) + LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3) + sub r3, r3, #1 + add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize + + // UEFI Memory Size (stacks are allocated in this region) + LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4) + + // + // Reserve the memory for the UEFI region (contain stacks on its top) + // + + // Calculate how much space there is between the top of the Firmware and the Top of the System Memory + subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop + bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM + cmp r0, r4 + bge _SetupStack + + // Case the top of stacks is the FdBaseAddress + mov r1, r2 + +_SetupStack + // r1 contains the top of the stack (and the UEFI Memory) + + // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment + // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the + // top of the memory space) + adds r7, r1, #1 + bcs _SetupOverflowStack + +_SetupAlignedStack + mov r1, r7 + b _GetBaseUefiMemory + +_SetupOverflowStack + // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE + // aligned (4KB) + LoadConstantToReg (EFI_PAGE_MASK, r7) + and r7, r7, r1 + sub r1, r1, r7 + +_GetBaseUefiMemory + // Calculate the Base of the UEFI Memory + sub r7, r1, r4 + +_GetStackBase + // r1 = The top of the Mpcore Stacks + // Stack for the primary core = PrimaryCoreStack + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + sub r8, r1, r2 + + // Stack for the secondary core = Number of Cores - 1 + LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0) + sub r0, r0, #1 + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1) + mul r1, r1, r0 + sub r8, r8, r1 + + // r8 = The base of the MpCore Stacks (primary stack & secondary stacks) + mov r0, r8 + mov r1, r6 + //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize) + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) + bl ArmPlatformStackSet + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4) + cmp r6, r4 + bne _PrepareArguments + +_ReserveGlobalVariable + LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0) + // InitializePrimaryStack($GlobalVariableSize, $Tmp1) + InitializePrimaryStack r0, r1 + +_PrepareArguments + mov r0, r6 + mov r1, r7 + mov r2, r8 + mov r3, sp + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r4, StartupAddr + + // Jump to PrePiCore C code + // r0 = MpId + // r1 = UefiMemoryBase + // r2 = StacksBase + // r3 = GlobalVariableBase + blx r4 + +_NeverReturn + b _NeverReturn + + END diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S deleted file mode 100755 index c0c20a9206..0000000000 --- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S +++ /dev/null @@ -1,149 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include -#include - -#include - -.text -.align 3 - -GCC_ASM_IMPORT(CEntryPoint) -GCC_ASM_IMPORT(ArmReadMpidr) -GCC_ASM_IMPORT(ArmPlatformStackSet) -GCC_ASM_EXPORT(_ModuleEntryPoint) - -StartupAddr: .word CEntryPoint - - -ASM_PFX(_ModuleEntryPoint): - // Get ID of this CPU in Multicore system - bl ASM_PFX(ArmReadMpidr) - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r6, r0, r1 - -_SetSVCMode: - // Enter SVC mode, Disable FIQ and IRQ - mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ) - msr CPSR_c, r1 - -// Check if we can install the stack at the top of the System Memory or if we need -// to install the stacks at the bottom of the Firmware Device (case the FD is located -// at the top of the DRAM) -_SetupStackPosition: - // Compute Top of System Memory - LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2) - sub r2, r2, #1 - add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize - - // Calculate Top of the Firmware Device - LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2) - LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3) - sub r3, r3, #1 - add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize - - // UEFI Memory Size (stacks are allocated in this region) - LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4) - - // - // Reserve the memory for the UEFI region (contain stacks on its top) - // - - // Calculate how much space there is between the top of the Firmware and the Top of the System Memory - subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop - bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM - cmp r0, r4 - bge _SetupStack - - // Case the top of stacks is the FdBaseAddress - mov r1, r2 - -_SetupStack: - // r1 contains the top of the stack (and the UEFI Memory) - - // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment - // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the - // top of the memory space) - adds r7, r1, #1 - bcs _SetupOverflowStack - -_SetupAlignedStack: - mov r1, r7 - b _GetBaseUefiMemory - -_SetupOverflowStack: - // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE - // aligned (4KB) - LoadConstantToReg (EFI_PAGE_MASK, r7) - and r7, r7, r1 - sub r1, r1, r7 - -_GetBaseUefiMemory: - // Calculate the Base of the UEFI Memory - sub r7, r1, r4 - -_GetStackBase: - // r1 = The top of the Mpcore Stacks - // Stack for the primary core = PrimaryCoreStack - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - sub r8, r1, r2 - - // Stack for the secondary core = Number of Cores - 1 - LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0) - sub r0, r0, #1 - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1) - mul r1, r1, r0 - sub r8, r8, r1 - - // r8 = The base of the MpCore Stacks (primary stack & secondary stacks) - mov r0, r8 - mov r1, r6 - //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize) - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) - bl ASM_PFX(ArmPlatformStackSet) - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4) - cmp r6, r4 - bne _PrepareArguments - -_ReserveGlobalVariable: - LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0) - // InitializePrimaryStack($GlobalVariableSize, $Tmp1) - InitializePrimaryStack(r0, r1) - -_PrepareArguments: - mov r0, r6 - mov r1, r7 - mov r2, r8 - mov r3, sp - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r4, StartupAddr - - // Jump to PrePiCore C code - // r0 = MpId - // r1 = UefiMemoryBase - // r2 = StacksBase - // r3 = GlobalVariableBase - blx r4 - -_NeverReturn: - b _NeverReturn - diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm b/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm deleted file mode 100644 index 5efdb532af..0000000000 --- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm +++ /dev/null @@ -1,152 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include -#include - -#include - - INCLUDE AsmMacroIoLib.inc - - IMPORT CEntryPoint - IMPORT ArmReadMpidr - IMPORT ArmPlatformStackSet - - EXPORT _ModuleEntryPoint - - PRESERVE8 - AREA PrePiCoreEntryPoint, CODE, READONLY - -StartupAddr DCD CEntryPoint - -_ModuleEntryPoint - // Get ID of this CPU in Multicore system - bl ArmReadMpidr - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r6, r0, r1 - -_SetSVCMode - // Enter SVC mode, Disable FIQ and IRQ - mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ) - msr CPSR_c, r1 - -// Check if we can install the stack at the top of the System Memory or if we need -// to install the stacks at the bottom of the Firmware Device (case the FD is located -// at the top of the DRAM) -_SetupStackPosition - // Compute Top of System Memory - LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2) - sub r2, r2, #1 - add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize - - // Calculate Top of the Firmware Device - LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2) - LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3) - sub r3, r3, #1 - add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize - - // UEFI Memory Size (stacks are allocated in this region) - LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4) - - // - // Reserve the memory for the UEFI region (contain stacks on its top) - // - - // Calculate how much space there is between the top of the Firmware and the Top of the System Memory - subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop - bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM - cmp r0, r4 - bge _SetupStack - - // Case the top of stacks is the FdBaseAddress - mov r1, r2 - -_SetupStack - // r1 contains the top of the stack (and the UEFI Memory) - - // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment - // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the - // top of the memory space) - adds r7, r1, #1 - bcs _SetupOverflowStack - -_SetupAlignedStack - mov r1, r7 - b _GetBaseUefiMemory - -_SetupOverflowStack - // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE - // aligned (4KB) - LoadConstantToReg (EFI_PAGE_MASK, r7) - and r7, r7, r1 - sub r1, r1, r7 - -_GetBaseUefiMemory - // Calculate the Base of the UEFI Memory - sub r7, r1, r4 - -_GetStackBase - // r1 = The top of the Mpcore Stacks - // Stack for the primary core = PrimaryCoreStack - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - sub r8, r1, r2 - - // Stack for the secondary core = Number of Cores - 1 - LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0) - sub r0, r0, #1 - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1) - mul r1, r1, r0 - sub r8, r8, r1 - - // r8 = The base of the MpCore Stacks (primary stack & secondary stacks) - mov r0, r8 - mov r1, r6 - //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize) - LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) - bl ArmPlatformStackSet - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4) - cmp r6, r4 - bne _PrepareArguments - -_ReserveGlobalVariable - LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0) - // InitializePrimaryStack($GlobalVariableSize, $Tmp1) - InitializePrimaryStack r0, r1 - -_PrepareArguments - mov r0, r6 - mov r1, r7 - mov r2, r8 - mov r3, sp - - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r4, StartupAddr - - // Jump to PrePiCore C code - // r0 = MpId - // r1 = UefiMemoryBase - // r2 = StacksBase - // r3 = GlobalVariableBase - blx r4 - -_NeverReturn - b _NeverReturn - - END diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf index f4cec0d606..3a3614192a 100755 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -19,11 +19,13 @@ MODULE_TYPE = SEC VERSION_STRING = 1.0 -[Sources.ARM] +[Sources] PrePi.c - ModuleEntryPoint.S | GCC - ModuleEntryPoint.asm | RVCT MainMPCore.c + +[Sources.ARM] + Arm/ModuleEntryPoint.S | GCC + Arm/ModuleEntryPoint.asm | RVCT [Packages] MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/PeiUniCore.inf index 34a068632b..823a956074 100755 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -19,11 +19,13 @@ MODULE_TYPE = SEC VERSION_STRING = 1.0 -[Sources.ARM] +[Sources] PrePi.c - ModuleEntryPoint.S | GCC - ModuleEntryPoint.asm | RVCT MainUniCore.c + +[Sources.ARM] + Arm/ModuleEntryPoint.S | GCC + Arm/ModuleEntryPoint.asm | RVCT [Packages] MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/Sec/Arm/Helper.S b/ArmPlatformPkg/Sec/Arm/Helper.S new file mode 100644 index 0000000000..4eede5faba --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/Helper.S @@ -0,0 +1,87 @@ +#======================================================================================== +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#======================================================================================= + +#start of the code section +.text +.align 3 + +GCC_ASM_EXPORT(return_from_exception) +GCC_ASM_EXPORT(enter_monitor_mode) +GCC_ASM_EXPORT(copy_cpsr_into_spsr) +GCC_ASM_EXPORT(set_non_secure_mode) + +# r0: Monitor World EntryPoint +# r1: MpId +# r2: SecBootMode +# r3: Secure Monitor mode stack +ASM_PFX(enter_monitor_mode): + cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack + moveq r3, sp + + mrs r4, cpsr @ Save current mode (SVC) in r4 + bic r5, r4, #0x1f @ Clear all mode bits + orr r5, r5, #0x16 @ Set bits for Monitor mode + msr cpsr_cxsf, r5 @ We are now in Monitor Mode + + mov sp, r3 @ Set the stack of the Monitor Mode + + mov lr, r0 @ Use the pass entrypoint as lr + + msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel + + mov r4, r0 @ Swap EntryPoint and MpId registers + mov r0, r1 + mov r1, r2 + mov r2, r3 + + bx r4 + +# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler. +# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into +# 'pc'; we will not change the CPSR flag and it will crash. +# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'. +ASM_PFX(return_from_exception): + ldr lr, returned_exception + + #The following instruction breaks the code. + #movs pc, lr + mrs r2, cpsr + bic r2, r2, #0x1f + orr r2, r2, #0x13 + msr cpsr_c, r2 + +returned_exception: @ We are now in non-secure state + bx r0 + +# Save the current Program Status Register (PSR) into the Saved PSR +ASM_PFX(copy_cpsr_into_spsr): + mrs r0, cpsr + msr spsr_cxsf, r0 + bx lr + +# Set the Non Secure Mode +ASM_PFX(set_non_secure_mode): + push { r1 } + and r0, r0, #0x1f @ Keep only the mode bits + mrs r1, spsr @ Read the spsr + bic r1, r1, #0x1f @ Clear all mode bits + orr r1, r1, r0 + msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch) + isb + pop { r1 } + bx lr @ return (hopefully thumb-safe!) + +dead: + b dead + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/Sec/Arm/Helper.asm b/ArmPlatformPkg/Sec/Arm/Helper.asm new file mode 100644 index 0000000000..b31cc31a97 --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/Helper.asm @@ -0,0 +1,79 @@ +// +// Copyright (c) 2011-2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + + EXPORT return_from_exception + EXPORT enter_monitor_mode + EXPORT copy_cpsr_into_spsr + EXPORT set_non_secure_mode + + AREA Helper, CODE, READONLY + +// r0: Monitor World EntryPoint +// r1: MpId +// r2: SecBootMode +// r3: Secure Monitor mode stack +enter_monitor_mode FUNCTION + cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack + moveq r3, sp + + mrs r4, cpsr // Save current mode (SVC) in r4 + bic r5, r4, #0x1f // Clear all mode bits + orr r5, r5, #0x16 // Set bits for Monitor mode + msr cpsr_cxsf, r5 // We are now in Monitor Mode + + mov sp, r3 // Set the stack of the Monitor Mode + + mov lr, r0 // Use the pass entrypoint as lr + + msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel + + mov r4, r0 // Swap EntryPoint and MpId registers + mov r0, r1 + mov r1, r2 + mov r2, r3 + + bx r4 + ENDFUNC + +// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler. +// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into +// 'pc'; we will not change the CPSR flag and it will crash. +// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'. +return_from_exception + adr lr, returned_exception + movs pc, lr +returned_exception // We are now in non-secure state + bx r0 + +// Save the current Program Status Register (PSR) into the Saved PSR +copy_cpsr_into_spsr + mrs r0, cpsr + msr spsr_cxsf, r0 + bx lr + +// Set the Non Secure Mode +set_non_secure_mode + push { r1 } + and r0, r0, #0x1f // Keep only the mode bits + mrs r1, spsr // Read the spsr + bic r1, r1, #0x1f // Clear all mode bits + orr r1, r1, r0 + msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch) + isb + pop { r1 } + bx lr // return (hopefully thumb-safe!) + +dead + B dead + + END diff --git a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S new file mode 100644 index 0000000000..92035a1ffe --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S @@ -0,0 +1,123 @@ +// +// Copyright (c) 2011-2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include "SecInternal.h" + +.text +.align 3 + +GCC_ASM_IMPORT(CEntryPoint) +GCC_ASM_IMPORT(ArmPlatformSecBootAction) +GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit) +GCC_ASM_IMPORT(ArmDisableInterrupts) +GCC_ASM_IMPORT(ArmDisableCachesAndMmu) +GCC_ASM_IMPORT(ArmReadMpidr) +GCC_ASM_IMPORT(ArmCallWFE) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +StartupAddr: .word ASM_PFX(CEntryPoint) + +ASM_PFX(_ModuleEntryPoint): + // First ensure all interrupts are disabled + bl ASM_PFX(ArmDisableInterrupts) + + // Ensure that the MMU and caches are off + bl ASM_PFX(ArmDisableCachesAndMmu) + + // By default, we are doing a cold boot + mov r10, #ARM_SEC_COLD_BOOT + + // Jump to Platform Specific Boot Action function + blx ASM_PFX(ArmPlatformSecBootAction) + +_IdentifyCpu: + // Identify CPU ID + bl ASM_PFX(ArmReadMpidr) + // Get ID of this CPU in Multicore system + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r5, r0, r1 + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) + cmp r5, r3 + // Only the primary core initialize the memory (SMC) + beq _InitMem + +_WaitInitMem: + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized + // Otherwise we have to wait the Primary Core to finish the initialization + cmp r10, #ARM_SEC_COLD_BOOT + bne _SetupSecondaryCoreStack + + // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT) + bl ASM_PFX(ArmCallWFE) + // Now the Init Mem is initialized, we setup the secondary core stacks + b _SetupSecondaryCoreStack + +_InitMem: + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized + cmp r10, #ARM_SEC_COLD_BOOT + bne _SetupPrimaryCoreStack + + // Initialize Init Boot Memory + bl ASM_PFX(ArmPlatformSecBootMemoryInit) + + // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) + +_SetupPrimaryCoreStack: + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) + add r1, r1, r2 + + LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2) + + // The reserved space for global variable must be 8-bytes aligned for pushing + // 64-bit variable on the stack + SetPrimaryStack (r1, r2, r3) + b _PrepareArguments + +_SetupSecondaryCoreStack: + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) + add r1, r1, r2 + + // Get the Core Position (ClusterId * 4) + CoreId + GetCorePositionFromMpId(r0, r5, r2) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add r0, r0, #1 + + // StackOffset = CorePos * StackSize + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) + mul r0, r0, r2 + // SP = StackBase + StackOffset + add sp, r1, r0 + +_PrepareArguments: + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r3, StartupAddr + + // Jump to SEC C code + // r0 = mp_id + // r1 = Boot Mode + mov r0, r5 + mov r1, r10 + blx r3 + +_NeverReturn: + b _NeverReturn diff --git a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm new file mode 100644 index 0000000000..42d2b0268f --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm @@ -0,0 +1,127 @@ +// +// Copyright (c) 2011-2012, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include +#include "SecInternal.h" + + INCLUDE AsmMacroIoLib.inc + + IMPORT CEntryPoint + IMPORT ArmPlatformSecBootAction + IMPORT ArmPlatformSecBootMemoryInit + IMPORT ArmDisableInterrupts + IMPORT ArmDisableCachesAndMmu + IMPORT ArmReadMpidr + IMPORT ArmCallWFE + EXPORT _ModuleEntryPoint + + PRESERVE8 + AREA SecEntryPoint, CODE, READONLY + +StartupAddr DCD CEntryPoint + +_ModuleEntryPoint FUNCTION + // First ensure all interrupts are disabled + blx ArmDisableInterrupts + + // Ensure that the MMU and caches are off + blx ArmDisableCachesAndMmu + + // By default, we are doing a cold boot + mov r10, #ARM_SEC_COLD_BOOT + + // Jump to Platform Specific Boot Action function + blx ArmPlatformSecBootAction + +_IdentifyCpu + // Identify CPU ID + bl ArmReadMpidr + // Get ID of this CPU in Multicore system + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) + and r5, r0, r1 + + // Is it the Primary Core ? + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) + cmp r5, r3 + // Only the primary core initialize the memory (SMC) + beq _InitMem + +_WaitInitMem + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized + // Otherwise we have to wait the Primary Core to finish the initialization + cmp r10, #ARM_SEC_COLD_BOOT + bne _SetupSecondaryCoreStack + + // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT) + bl ArmCallWFE + // Now the Init Mem is initialized, we setup the secondary core stacks + b _SetupSecondaryCoreStack + +_InitMem + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized + cmp r10, #ARM_SEC_COLD_BOOT + bne _SetupPrimaryCoreStack + + // Initialize Init Boot Memory + bl ArmPlatformSecBootMemoryInit + + // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) + +_SetupPrimaryCoreStack + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) + add r1, r1, r2 + + LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2) + + // The reserved space for global variable must be 8-bytes aligned for pushing + // 64-bit variable on the stack + SetPrimaryStack (r1, r2, r3) + b _PrepareArguments + +_SetupSecondaryCoreStack + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) + add r1, r1, r2 + + // Get the Core Position (ClusterId * 4) + CoreId + GetCorePositionFromMpId(r0, r5, r2) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add r0, r0, #1 + + // StackOffset = CorePos * StackSize + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) + mul r0, r0, r2 + // SP = StackBase + StackOffset + add sp, r1, r0 + +_PrepareArguments + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr r3, StartupAddr + + // Jump to SEC C code + // r0 = mp_id + // r1 = Boot Mode + mov r0, r5 + mov r1, r10 + blx r3 + ENDFUNC + +_NeverReturn + b _NeverReturn + END diff --git a/ArmPlatformPkg/Sec/Helper.S b/ArmPlatformPkg/Sec/Helper.S deleted file mode 100644 index 4eede5faba..0000000000 --- a/ArmPlatformPkg/Sec/Helper.S +++ /dev/null @@ -1,87 +0,0 @@ -#======================================================================================== -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http:#opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#======================================================================================= - -#start of the code section -.text -.align 3 - -GCC_ASM_EXPORT(return_from_exception) -GCC_ASM_EXPORT(enter_monitor_mode) -GCC_ASM_EXPORT(copy_cpsr_into_spsr) -GCC_ASM_EXPORT(set_non_secure_mode) - -# r0: Monitor World EntryPoint -# r1: MpId -# r2: SecBootMode -# r3: Secure Monitor mode stack -ASM_PFX(enter_monitor_mode): - cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack - moveq r3, sp - - mrs r4, cpsr @ Save current mode (SVC) in r4 - bic r5, r4, #0x1f @ Clear all mode bits - orr r5, r5, #0x16 @ Set bits for Monitor mode - msr cpsr_cxsf, r5 @ We are now in Monitor Mode - - mov sp, r3 @ Set the stack of the Monitor Mode - - mov lr, r0 @ Use the pass entrypoint as lr - - msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel - - mov r4, r0 @ Swap EntryPoint and MpId registers - mov r0, r1 - mov r1, r2 - mov r2, r3 - - bx r4 - -# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler. -# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into -# 'pc'; we will not change the CPSR flag and it will crash. -# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'. -ASM_PFX(return_from_exception): - ldr lr, returned_exception - - #The following instruction breaks the code. - #movs pc, lr - mrs r2, cpsr - bic r2, r2, #0x1f - orr r2, r2, #0x13 - msr cpsr_c, r2 - -returned_exception: @ We are now in non-secure state - bx r0 - -# Save the current Program Status Register (PSR) into the Saved PSR -ASM_PFX(copy_cpsr_into_spsr): - mrs r0, cpsr - msr spsr_cxsf, r0 - bx lr - -# Set the Non Secure Mode -ASM_PFX(set_non_secure_mode): - push { r1 } - and r0, r0, #0x1f @ Keep only the mode bits - mrs r1, spsr @ Read the spsr - bic r1, r1, #0x1f @ Clear all mode bits - orr r1, r1, r0 - msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch) - isb - pop { r1 } - bx lr @ return (hopefully thumb-safe!) - -dead: - b dead - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/Sec/Helper.asm b/ArmPlatformPkg/Sec/Helper.asm deleted file mode 100644 index b31cc31a97..0000000000 --- a/ArmPlatformPkg/Sec/Helper.asm +++ /dev/null @@ -1,79 +0,0 @@ -// -// Copyright (c) 2011-2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - - EXPORT return_from_exception - EXPORT enter_monitor_mode - EXPORT copy_cpsr_into_spsr - EXPORT set_non_secure_mode - - AREA Helper, CODE, READONLY - -// r0: Monitor World EntryPoint -// r1: MpId -// r2: SecBootMode -// r3: Secure Monitor mode stack -enter_monitor_mode FUNCTION - cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack - moveq r3, sp - - mrs r4, cpsr // Save current mode (SVC) in r4 - bic r5, r4, #0x1f // Clear all mode bits - orr r5, r5, #0x16 // Set bits for Monitor mode - msr cpsr_cxsf, r5 // We are now in Monitor Mode - - mov sp, r3 // Set the stack of the Monitor Mode - - mov lr, r0 // Use the pass entrypoint as lr - - msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel - - mov r4, r0 // Swap EntryPoint and MpId registers - mov r0, r1 - mov r1, r2 - mov r2, r3 - - bx r4 - ENDFUNC - -// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler. -// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into -// 'pc'; we will not change the CPSR flag and it will crash. -// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'. -return_from_exception - adr lr, returned_exception - movs pc, lr -returned_exception // We are now in non-secure state - bx r0 - -// Save the current Program Status Register (PSR) into the Saved PSR -copy_cpsr_into_spsr - mrs r0, cpsr - msr spsr_cxsf, r0 - bx lr - -// Set the Non Secure Mode -set_non_secure_mode - push { r1 } - and r0, r0, #0x1f // Keep only the mode bits - mrs r1, spsr // Read the spsr - bic r1, r1, #0x1f // Clear all mode bits - orr r1, r1, r0 - msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch) - isb - pop { r1 } - bx lr // return (hopefully thumb-safe!) - -dead - B dead - - END diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf index 55ad00744c..3cf9f339e0 100644 --- a/ArmPlatformPkg/Sec/Sec.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -20,12 +20,14 @@ MODULE_TYPE = SEC VERSION_STRING = 1.0 -[Sources.ARM] - Helper.asm | RVCT - Helper.S | GCC +[Sources] Sec.c - SecEntryPoint.S | GCC - SecEntryPoint.asm | RVCT + +[Sources.ARM] + Arm/Helper.asm | RVCT + Arm/Helper.S | GCC + Arm/SecEntryPoint.S | GCC + Arm/SecEntryPoint.asm | RVCT [Packages] MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.S b/ArmPlatformPkg/Sec/SecEntryPoint.S deleted file mode 100644 index 92035a1ffe..0000000000 --- a/ArmPlatformPkg/Sec/SecEntryPoint.S +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright (c) 2011-2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include "SecInternal.h" - -.text -.align 3 - -GCC_ASM_IMPORT(CEntryPoint) -GCC_ASM_IMPORT(ArmPlatformSecBootAction) -GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit) -GCC_ASM_IMPORT(ArmDisableInterrupts) -GCC_ASM_IMPORT(ArmDisableCachesAndMmu) -GCC_ASM_IMPORT(ArmReadMpidr) -GCC_ASM_IMPORT(ArmCallWFE) -GCC_ASM_EXPORT(_ModuleEntryPoint) - -StartupAddr: .word ASM_PFX(CEntryPoint) - -ASM_PFX(_ModuleEntryPoint): - // First ensure all interrupts are disabled - bl ASM_PFX(ArmDisableInterrupts) - - // Ensure that the MMU and caches are off - bl ASM_PFX(ArmDisableCachesAndMmu) - - // By default, we are doing a cold boot - mov r10, #ARM_SEC_COLD_BOOT - - // Jump to Platform Specific Boot Action function - blx ASM_PFX(ArmPlatformSecBootAction) - -_IdentifyCpu: - // Identify CPU ID - bl ASM_PFX(ArmReadMpidr) - // Get ID of this CPU in Multicore system - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r5, r0, r1 - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) - cmp r5, r3 - // Only the primary core initialize the memory (SMC) - beq _InitMem - -_WaitInitMem: - // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized - // Otherwise we have to wait the Primary Core to finish the initialization - cmp r10, #ARM_SEC_COLD_BOOT - bne _SetupSecondaryCoreStack - - // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT) - bl ASM_PFX(ArmCallWFE) - // Now the Init Mem is initialized, we setup the secondary core stacks - b _SetupSecondaryCoreStack - -_InitMem: - // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized - cmp r10, #ARM_SEC_COLD_BOOT - bne _SetupPrimaryCoreStack - - // Initialize Init Boot Memory - bl ASM_PFX(ArmPlatformSecBootMemoryInit) - - // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) - -_SetupPrimaryCoreStack: - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) - add r1, r1, r2 - - LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2) - - // The reserved space for global variable must be 8-bytes aligned for pushing - // 64-bit variable on the stack - SetPrimaryStack (r1, r2, r3) - b _PrepareArguments - -_SetupSecondaryCoreStack: - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) - add r1, r1, r2 - - // Get the Core Position (ClusterId * 4) + CoreId - GetCorePositionFromMpId(r0, r5, r2) - // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack - add r0, r0, #1 - - // StackOffset = CorePos * StackSize - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) - mul r0, r0, r2 - // SP = StackBase + StackOffset - add sp, r1, r0 - -_PrepareArguments: - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r3, StartupAddr - - // Jump to SEC C code - // r0 = mp_id - // r1 = Boot Mode - mov r0, r5 - mov r1, r10 - blx r3 - -_NeverReturn: - b _NeverReturn diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm deleted file mode 100644 index 42d2b0268f..0000000000 --- a/ArmPlatformPkg/Sec/SecEntryPoint.asm +++ /dev/null @@ -1,127 +0,0 @@ -// -// Copyright (c) 2011-2012, ARM Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// - -#include -#include -#include "SecInternal.h" - - INCLUDE AsmMacroIoLib.inc - - IMPORT CEntryPoint - IMPORT ArmPlatformSecBootAction - IMPORT ArmPlatformSecBootMemoryInit - IMPORT ArmDisableInterrupts - IMPORT ArmDisableCachesAndMmu - IMPORT ArmReadMpidr - IMPORT ArmCallWFE - EXPORT _ModuleEntryPoint - - PRESERVE8 - AREA SecEntryPoint, CODE, READONLY - -StartupAddr DCD CEntryPoint - -_ModuleEntryPoint FUNCTION - // First ensure all interrupts are disabled - blx ArmDisableInterrupts - - // Ensure that the MMU and caches are off - blx ArmDisableCachesAndMmu - - // By default, we are doing a cold boot - mov r10, #ARM_SEC_COLD_BOOT - - // Jump to Platform Specific Boot Action function - blx ArmPlatformSecBootAction - -_IdentifyCpu - // Identify CPU ID - bl ArmReadMpidr - // Get ID of this CPU in Multicore system - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) - and r5, r0, r1 - - // Is it the Primary Core ? - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3) - cmp r5, r3 - // Only the primary core initialize the memory (SMC) - beq _InitMem - -_WaitInitMem - // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized - // Otherwise we have to wait the Primary Core to finish the initialization - cmp r10, #ARM_SEC_COLD_BOOT - bne _SetupSecondaryCoreStack - - // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT) - bl ArmCallWFE - // Now the Init Mem is initialized, we setup the secondary core stacks - b _SetupSecondaryCoreStack - -_InitMem - // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized - cmp r10, #ARM_SEC_COLD_BOOT - bne _SetupPrimaryCoreStack - - // Initialize Init Boot Memory - bl ArmPlatformSecBootMemoryInit - - // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) - LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) - -_SetupPrimaryCoreStack - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) - add r1, r1, r2 - - LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2) - - // The reserved space for global variable must be 8-bytes aligned for pushing - // 64-bit variable on the stack - SetPrimaryStack (r1, r2, r3) - b _PrepareArguments - -_SetupSecondaryCoreStack - // Get the top of the primary stacks (and the base of the secondary stacks) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) - add r1, r1, r2 - - // Get the Core Position (ClusterId * 4) + CoreId - GetCorePositionFromMpId(r0, r5, r2) - // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack - add r0, r0, #1 - - // StackOffset = CorePos * StackSize - LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) - mul r0, r0, r2 - // SP = StackBase + StackOffset - add sp, r1, r0 - -_PrepareArguments - // Move sec startup address into a data register - // Ensure we're jumping to FV version of the code (not boot remapped alias) - ldr r3, StartupAddr - - // Jump to SEC C code - // r0 = mp_id - // r1 = Boot Mode - mov r0, r5 - mov r1, r10 - blx r3 - ENDFUNC - -_NeverReturn - b _NeverReturn - END