From: Michael Kinney Date: Tue, 8 Mar 2016 22:02:30 +0000 (-0800) Subject: UefiCpuPkg/Include: Add Broadwell MSR include file X-Git-Tag: edk2-stable201903~7627 X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=d57201c0a3f201c75d295fab9e1f1110dd09256f UefiCpuPkg/Include: Add Broadwell MSR include file Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney Reviewed-by: Jeff Fan --- diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h new file mode 100644 index 0000000000..69c404eccd --- /dev/null +++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h @@ -0,0 +1,265 @@ +/** @file + MSR Definitions for Intel processors based on the Broadwell microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, + December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. + +**/ + +#ifndef __BROADWELL_MSR_H__ +#define __BROADWELL_MSR_H__ + +#include + +/** + Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control + Facilities.". + + @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER. + + Example usage + @code + MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS); + AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64); + @endcode +**/ +#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical + /// Addresses (ToPA).". + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:5; + /// + /// [Bit 61] Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Ovf_BufDSSAVE. + /// + UINT32 OvfBuf:1; + /// + /// [Bit 63] CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI C-states. `See http://biosbits.org. `__. + + @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode +**/ +#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 0000b: + /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 + /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10. + /// + UINT32 Limit:4; + UINT32 Reserved1:6; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + /// + /// [Bit 29] Enable Package C-State Auto-demotion (R/W). + /// + UINT32 CStateAutoDemotion:1; + /// + /// [Bit 30] Enable Package C-State Undemotion (R/W). + /// + UINT32 CStateUndemotion:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT); + @endcode +**/ +#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6core active. + /// + UINT32 Maximum6C:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER; + +#endif