From: Olivier Martin <olivier.martin@arm.com>
Date: Mon, 1 Jul 2013 14:14:37 +0000 (+0000)
Subject: ArmPlatformPkg/ArmVExpressLibCTA15-A7: Mapped the extra 1GB of DRAM in the MMU
X-Git-Tag: edk2-stable201903~12457
X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=commitdiff_plain;h=e8ee4b2d43334ebd47a6565e6ea5c964fa88c203

ArmPlatformPkg/ArmVExpressLibCTA15-A7: Mapped the extra 1GB of DRAM in the MMU

ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or
the 2GB DRAM core tile profiles.
By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it declares
this additional 1GB resource system memory to UEFI. But the previous code did
not map this memory in the MMU Page Table.
So, the memory was allocatable by UEFI modules, but was not accessible by the CPU
(because not mapped).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <Leif.Lindholm@linaro.org>




git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14449 6f19259b-4bc3-4df7-8a09-765794883524
---

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
index d71e58ae89..473b3f323e 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
@@ -59,20 +59,6 @@ ArmPlatformGetVirtualMemoryMap (
     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
   }
 
-  // Detect if it is a 1GB or 2GB Test Chip
-  //   [16:19]: 0=1GB TC2, 1=2GB TC2
-  if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
-    DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
-    BuildResourceDescriptorHob (
-        EFI_RESOURCE_SYSTEM_MEMORY,
-        EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
-          EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
-          EFI_RESOURCE_ATTRIBUTE_TESTED,
-        PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
-        0x40000000
-    );
-  }
-
 #ifdef ARM_BIGLITTLE_TC2
   // Secure NOR0 Flash
   VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SEC_NOR0_BASE;
@@ -164,6 +150,26 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length          = PcdGet32 (PcdSystemMemorySize);
   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 
+  // Detect if it is a 1GB or 2GB Test Chip
+  //   [16:19]: 0=1GB TC2, 1=2GB TC2
+  if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
+    DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
+    BuildResourceDescriptorHob (
+        EFI_RESOURCE_SYSTEM_MEMORY,
+        EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+          EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+          EFI_RESOURCE_ATTRIBUTE_TESTED,
+        PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
+        SIZE_1GB
+    );
+
+    // Map the additional 1GB into the MMU
+    VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
+    VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
+    VirtualMemoryTable[Index].Length          = SIZE_1GB;
+    VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+  }
+
   // End of Table
   VirtualMemoryTable[++Index].PhysicalBase  = 0;
   VirtualMemoryTable[Index].VirtualBase     = 0;