Michael Kinney [Thu, 30 Apr 2015 07:25:07 +0000 (07:25 +0000)]
MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlushCacheLine()
The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack
after CPUID.
The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the
LinearAddress parameter value on the stack. The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.
Ye Ting [Thu, 30 Apr 2015 02:57:10 +0000 (02:57 +0000)]
Add IPV6 support from UNDI
Add new information block ‘IPV6 support from UNDI’ in AIP protocol and provide sample implementation in UNDI driver.
Update PXE driver to get ‘Ipv6Available’ of PXE BC Mode data from UNDI driver, if unsupported then not to start PXE over IPv6 path.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17275 6f19259b-4bc3-4df7-8a09-765794883524
Fu Siyuan [Wed, 29 Apr 2015 05:47:03 +0000 (05:47 +0000)]
Remove duplicate DAD entry in IP6 driver to fix DAD fail issue.
The IP6 driver may create duplicate IP6_DAD_ENTRY in DupAddrDetectList in some situation like:
1. Address policy switch but not clear the delay node list, OR
2. Set manual address repeatedly before the previous DAD is finished.
The NS sent out by duplicate DAD entry will mix up with the loop back multicast packet, result in DAD fail.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17263 6f19259b-4bc3-4df7-8a09-765794883524
Ma, Maurice [Wed, 29 Apr 2015 03:50:20 +0000 (03:50 +0000)]
Add dual FSP binaries support.
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.
Ma, Maurice [Wed, 29 Apr 2015 03:10:24 +0000 (03:10 +0000)]
Add dual FSP binaries support.
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.
MdeModulePkg: fix some issues in ScsiDisk to co-work with UFS stack
The changes in ScsiDisk include:
1. Add UFS disk info support.
2. Remove the wrong block size calculation.
3. Get sense data for TEST_UNIT_READY cmd immediately rather than sending a REQUEST_SENSE cmd again.
It includes 4 drivers:
1. UfsPassThruDxe, which is a UEFI driver and consumes EFI_UFS_HOST_CONTROLLER_PROTOCOL and produces EFI_EXT_SCSI_PASS_THRU_PROTOCOL
2. UfsPciHcDxe, which is specific for pci-based UFS HC implementation and is a UEFI driver to produce EFI_UFS_HOST_CONTROLLER_PROTOCOL.
3. UfsBlockIoPei, which is a PEI driver and consumes EFI_UFS_HOST_CONTROLLER_PPI and produces EFI_PEI_VIRTUAL_BLOCK_IO_PPI.
4. UfsPciHcPei, which is specific for pci-based UFS HC implementation and is a PEI driver to produce EFI_UFS_HOST_CONTROLLER_PPI.
MdePkg: Add PI 1.4 Graphics HOB and PPI header files
The PeiGraphicsPpi is the main interface exposed by the Graphics PEIM to
be used by the other firmware modules.
When graphics capability is included in PEI, it produces a
EFI_PEI_GRAPHICS_INFO_HOB which provides information about the graphics
mode and the framebuffer.
Michael Kinney [Mon, 27 Apr 2015 19:54:52 +0000 (19:54 +0000)]
UefiCpuPkg/CpuExceptionHandlerLib: Support IA32 processors without DE or FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17221 6f19259b-4bc3-4df7-8a09-765794883524
Michael Kinney [Mon, 27 Apr 2015 19:53:36 +0000 (19:53 +0000)]
SourceLevelDebugPkg/DebugAgent: Support IA32 processors without DE or FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
Michael Kinney [Mon, 27 Apr 2015 19:48:00 +0000 (19:48 +0000)]
MdePkg/BaseXApicX2ApicLib: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESS
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
Michael Kinney [Mon, 27 Apr 2015 19:47:26 +0000 (19:47 +0000)]
MdePkg/BaseXApicLib: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESS
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17216 6f19259b-4bc3-4df7-8a09-765794883524
Michael Kinney [Mon, 27 Apr 2015 19:44:40 +0000 (19:44 +0000)]
MdePkg/BaseSerialPortLib16550: Support UARTs with a register stride greater than 1 byte.
Add stride PCD to MdeModulePkg to support 16550 UARTs with a register stride that is not 1 byte.
The default value is 1 byte.
Quark SoC uses a stride of 4 bytes.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17215 6f19259b-4bc3-4df7-8a09-765794883524
Clear EFLAGS.IF before executing Stepping command and save original
value in DEBUG_AGENT_FLAG. It could avoid pending interrupt issued
during executing Stepping command. Restore EFLAGS.IF after Stepping
command execution finished.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17204 6f19259b-4bc3-4df7-8a09-765794883524
ShellPkg: Refine the logic about allocating memory for variable name and data.
The run time service 'QueryVariableInfo' is not proper to be used to get the variable name size. This patch refine the logic about allocating memory for variable name and data.
-- Add BootLoaderTolumSize support
-- Extend FspApiCallingCheck with ApiParam for BootLoaderTolumSize
-- Rename all Bootloader to BootLoader as official name
-- Rename Ucode to Microcode
-- Remove FspSelfCheck API, because it is merged into SecPlatformInit
-- Add GetFspVpdDataPointer() in FspCommonLib.h
-- Document FspSecPlatformLib.h
-- Reorg FSP_PLAT_DATA data structure to let it match FSP spec.
-- Move helper function in FspSecCore to reduce platform enabling effort
-- Fix LibraryClasses declaration in DEC file.
-- Enhance PatchFv to check if it is valid FSP bin.
MdeModulePkg: PCD/Pei: eliminate unused but set variable
- SVN r14866:
MdePkg and MdeModulePkg Pcd: Add the new EFI_GET_PCD_INFO_PROTOCOL and
EFI_GET_PCD_INFO_PPI support for PI 1.2.1 compliance.
added the "DataBase" local variable to PcdPeimInit(), and both set it and
used it.
- SVN r14869:
MdeModulePkg and Nt32Pkg Pcd: Add the new EFI_GET_PCD_INFO_PROTOCOL and
EFI_GET_PCD_INFO_PPI support for PI 1.2.1 compliance.
changed the PcdPeimInit() function, but "DataBase" remained both set and
used.
- SVN r17173:
MdeModulePkg Pcd: Check the input SkuId in SetSku()
changed the function again; and this time "DataBase" became
set-but-unused. It triggers the following build error, when building
ArmVirtualizationQemu.dsc with gcc-4.8:
MdeModulePkg/Universal/PCD/Pei/Pcd.c:150:21: error: variable 'DataBase'
set but not used [-Werror=unused-but-set-variable]
PEI_PCD_DATABASE *DataBase;
^
cc1: all warnings being treated as errors
Fix the error by removing the DataBase variable, restoring the pre-r14866
state locally, when the BuildPcdDatabase() function was called, but its
return value was thrown away.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17179 6f19259b-4bc3-4df7-8a09-765794883524
ArmVirtualizationPkg: Xen: shuffle init order to deal with incoherency
In order to prevent memory corruption issues caused by the fact that,
under virtualization, the guest is incoherent with the hypervisor's view
of memory until it enables its caches and MMU, this patch reshuffles the
init sequence so that the Xen shared memory regions are not touched
before the caches and MMU are enabled.
In addition, the loaded image itself is invalidated by virtual address,
to ensure that any runtime changes (such as the applied relocations) will
not suddenly become invisible once we turn the caches on.
ArmVirtualizationPkg: invalidate PEI memory region by VA
This updates ArmVirtualizationMemoryInitPeiLib so that the PEI memory
region, i.e., the region that is used both before and after the MMU
and caches are enabled, is invalidated by virtual address before
enabling the MMU.
This prevents issues where data we modified with the caches and MMU
off may be shadowed by clean cachelines in system caches or in lower
level caches on other CPUs, resulting in the this data to become
invisible once we turn the MMU and caches on.
ArmPkg: remove cache maintenance by VA operation range size threshold
This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.
Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.
To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""
ArmPlatformPkg: do not fulfil MemoryInitPeiLib dependency directly via .c file
MemoryInitPeim short-circuits its MemoryInitPeiLib dependency by including
the .c file directly. This prevents us from having a special implementation
for ArmVirtualizationPkg that performs additional cache maintenance before
enabling the MMU. So instead, make it depend on the library class.
ArmVirtualizationPkg: make ArmVirtualizationMemoryInitPeiLib the default
This updates ArmVirtualization.dsc.inc to use the MemoryInitPeiLib
implementation for virt targets. The only difference between that one
and the original one is that the original one removes memory from the
available list if it overlaps the FD region (which may be the case when
shadowing NOR flash with system RAM). This is never the case for the
Qemu target, which is the only platform affected by this change, since
the Xen target already uses this library explicitly.
This allows us to remove the Xen-specific declaration of this library
dependency. For the Qemu target, this change will not take effect until
after the MemoryInitPeim<->MemoryInitPeiLib dependency resolution is
fixed in a subsequent patch.
Save initial TSVal from TCP connection initiation packets.
RFC1323 says the most recently received TSVal must be echoed in TSecr in ACK packets
which was not done at first connection because the code saving the TSVal from the peer
was skipped at this point. This resulted in sending an ACK reply with a 0 TSecr that
was rejected at least by FreeBSD. This patch fixes this by updating the saved TSVal
also for connection initiation packets.
Thanks to Laszlo Ersek for analysis and help in debugging.
Maurice Ma [Fri, 10 Apr 2015 22:08:57 +0000 (22:08 +0000)]
CorebootPayloadPkg: Remove empty folder reference in DEC file
In current CorebootPayloadPkg.dec an empty 'Include' directory is
listed in [includes] section. However, this empty directory will
not be mirrored into git repo. If the source tree is pulled from git,
the 'Include' empty folder will not exist and it will cause build
failure. The fix is to remove the whole [Includes] section in the
DEC file.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17164 6f19259b-4bc3-4df7-8a09-765794883524
Bob Feng [Fri, 10 Apr 2015 06:59:47 +0000 (06:59 +0000)]
BaseTools/Build: Add SDL support
1.BaseTool add ATTRIBUTE (+/-RT, RO) support in PCD declaration in DSC file
2.BaseTool collect valid PCD value in DEC file and generate data base for runtime sanity check
3.BaseTool support SetPcd error.
Scott Duplichan [Fri, 10 Apr 2015 03:00:40 +0000 (03:00 +0000)]
MdePkg: Fix build fail when DDK3790 tool chain is used
Modify the preprocessor check for variadic macro support. The existing
check assumes all Microsoft compilers with major version of 14 and greater
support variadic macros. This is almost correct. An exception is the X64
compiler from DDK3790. This compiler has version 14.00.40310.41, yet does
not support variadic macros. Both VS2005 compilers have version number
14.00.50727.762 and do support variadic macros. For simplicity, this change
suppresses the use of variadic macros for all Microsoft compilers with
version 14 or smaller. If the variadic macro support needs to be restored
for VS2005, that could be done using new logic invloving _MSC_FULL_VER.
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