mirror_edk2.git
5 months agoIntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.
Chasel Chiu [Tue, 28 May 2019 13:51:39 +0000 (21:51 +0800)]
IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308

Support rebasing FSP 1.x binary.
FSP 1.x has single component in binary so not supported
by split command and rebase can be done with the same
command for rebasing FSP-T component in FSP 2.x image.

Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary
      can be rebased successfully.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
5 months agoMaintainers.txt: Remove Yonghong from BaseTools Reviewer
Zhu, Yonghong [Wed, 5 Jun 2019 00:51:27 +0000 (08:51 +0800)]
Maintainers.txt: Remove Yonghong from BaseTools Reviewer

As Yonghong has some other focus, remove him from the reviewer.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
5 months agoOvmfPkg: Drop build flag USE_LEGACY_ISA_STACK and legacy ISA stack
Hao A Wu [Fri, 24 May 2019 01:10:42 +0000 (09:10 +0800)]
OvmfPkg: Drop build flag USE_LEGACY_ISA_STACK and legacy ISA stack

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1842

According to the discussion at:
https://edk2.groups.io/g/devel/topic/30918343#38093

For OVMF, we keep both ISA stacks:
* The legacy one in PcAtChipsetPkg/IntelFrameworkModulePkg
* The Sio bus based OVMF-specified one introduced by commit a5cc178aeb

for a period of time (includes 1 stable tag: edk2-stable201905). And we
also keep the Sio bus based OVMF-specified stack as the default one (via a
build option 'USE_LEGACY_ISA_STACK') to validate its stability.

This commit will propose to drop the legacy ISA stack from OVMF and remove
the usage of the build flag 'USE_LEGACY_ISA_STACK' at the same time. This
is considered as a preparation for the removal of
PcAtChipsetPkg/IsaAcpiDxe & IntelFrameworkModulePkg.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
5 months agoDynamicTablesPkg: Add ACPI 6.3 SPE support to MADT generator
Krzysztof Koch [Tue, 9 Apr 2019 13:44:37 +0000 (14:44 +0100)]
DynamicTablesPkg: Add ACPI 6.3 SPE support to MADT generator

The Dynamic Tables Framework now supports generating Multiple APIC
Description Table (MADT) revision 5 for ARM platforms while maintaining
backward-compatibility with ACPI 6.2.

The relevant change is the enablement of the Statistical Profiling
Extension (SPE).

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
5 months agoDynamicTablesPkg: Test for duplicate GT Block frame numbers
Krzysztof Koch [Tue, 9 Apr 2019 13:44:37 +0000 (14:44 +0100)]
DynamicTablesPkg: Test for duplicate GT Block frame numbers

Check for duplicate frame numbers when populating the GT Block Timer
Frames inside the GTDT table generator.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
5 months agoDynamicTablesPkg: Test for duplicate UIDs in MADT generator
Krzysztof Koch [Tue, 9 Apr 2019 11:58:47 +0000 (12:58 +0100)]
DynamicTablesPkg: Test for duplicate UIDs in MADT generator

Check for duplicate ACPI Processor UIDs when populating the GIC CPU
(GICC) Interface structures inside the MADT table generator.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
5 months agoDynamicTablesPkg: Add code for finding duplicate values in arrays
Krzysztof Koch [Tue, 9 Apr 2019 09:41:40 +0000 (10:41 +0100)]
DynamicTablesPkg: Add code for finding duplicate values in arrays

Added generic function for detecting duplicate values in an array.

Also defined a function prototype to test if two objects are equal.
The prototype is used as an argument to the 'FindDuplicateValues'
function.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
5 months agoDynamicTablesPkg: Add frame number validation to GTDT generator
Krzysztof Koch [Wed, 10 Apr 2019 10:28:55 +0000 (11:28 +0100)]
DynamicTablesPkg: Add frame number validation to GTDT generator

Added code to check if the Generic Timer Block Structure's frame number
provided by the platform repository is within the allowed range (0-7).

References:
- ACPI 6.2 Errata A, Table 5-122, September 2017

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
5 months agoShellPkg/acpiview: GTDT updates for ACPI 6.3
Pierre Gondois [Tue, 19 Mar 2019 16:58:17 +0000 (16:58 +0000)]
ShellPkg/acpiview: GTDT updates for ACPI 6.3

The ACPI 6.3 specification introduces support to describe
the ARMv8.1 virtual EL2 timers. This patch updates the GTDT parser
of acpiview to decode the EL2 virtual timer fields.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
5 months agoBaseTools: Refactor hash tracking after checking for Sources section
Rodriguez, Christian [Wed, 29 May 2019 16:26:49 +0000 (00:26 +0800)]
BaseTools: Refactor hash tracking after checking for Sources section

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1804

After adding a check to see if [Sources] section lists all the header
type files of a module, track module and library hashes for --hash
feature. If above check is not in compilance for a library or module,
force hash invalidation on that library or module.

Signed-off-by: Christian Rodriguez <christian.rodriguez@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
5 months agoBaseTools: Add a checking for Sources section in INF file
Rodriguez, Christian [Wed, 29 May 2019 16:26:48 +0000 (00:26 +0800)]
BaseTools: Add a checking for Sources section in INF file

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1804

Add a check to see if [Sources] section lists all the header type
files of a module. Performance impact should be minimal with this patch
since information is already being fetched for Makefile purposes. All
other information is already cached in memory. No extra IO time is needed.

Signed-off-by: Christian Rodriguez <christian.rodriguez@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
5 months agoBaseTools:Make BaseTools support new rules to generate RAW FFS FILE
Fan, ZhijuX [Wed, 29 May 2019 05:29:34 +0000 (13:29 +0800)]
BaseTools:Make BaseTools support new rules to generate RAW FFS FILE

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1765

If RAW FFS File Rule has no section for its data.For RAW FFS File,
directly call GenFfs tool to generate FFS file.

Ffs Rule:
[Rule.Common.USER_DEFINED.MicroCode]
  FILE RAW = $(NAMED_GUID) {
        $(INF_OUTPUT)/$(MODULE_NAME).bin
  }
[Rule.Common.USER_DEFINED.LOGO]
  FILE RAW = $(NAMED_GUID) {
                       |.bmp
  }

As shown in the rule above,if SectionType and FileType not defined,
FFS files are generated directly, and no other type of file is
generated.

The patch is to make the BaseTools support these two rules

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
5 months agoSecurityPkg/OpalPassword: Add PCD to skip password prompt
Chu, Maggie [Wed, 22 May 2019 07:04:43 +0000 (15:04 +0800)]
SecurityPkg/OpalPassword: Add PCD to skip password prompt

https://bugzilla.tianocore.org/show_bug.cgi?id=1801
Add a PCD for skipping password prompt in device unlocked status.
Previous change only support if storage device is in locked status.
This change is added to support the case that security status of the
storage device is unlocked.

Signed-off-by: Maggie Chu <maggie.chu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
5 months agoUefiCpuPkg/MpInitLib: Decrease NumApsExecuting only for ApInitConfig
Ray Ni [Fri, 31 May 2019 09:42:09 +0000 (17:42 +0800)]
UefiCpuPkg/MpInitLib: Decrease NumApsExecuting only for ApInitConfig

The patch fixes the bug that the memory under 1MB is modified by
firmware in S3 boot.

Root cause is a racing condition in MpInitLib:
1. BSP: WakeUpByInitSipiSipi is set by NotifyOnS3SmmInitDonePpi()
2. BSP: WakeUpAP() wakes all APs to run certain procedure.
  2.1. AllocateResetVector() uses <1MB memory for wake up vector.
  2.1. FillExchangeInfoData() resets NumApsExecuting to 0.
  2.2. WaitApWakeup() waits AP to clear WAKEUP_AP_SIGNAL.
3. AP: ApWakeupFunction() clears WAKEUP_AP_SIGNAL to inform BSP.
5. BSP: FreeResetVector() restores the <1MB memory
4. AP: ApWakeupFunction() calls the certain procedure.
  4.1. NumApsExecuting is decreased.

#4.1 happens after the 1MB memory is restored so the result is
memory below 1MB is changed by #4.1
It happens only when the AP executes procedure a bit longer.
AP returns back to ApWakeupFunction() from procedure after
BSP restores the <1MB memory.

Since NumApsExecuting is only used when InitFlag == ApInitConfig
for counting the processor count.
The patch moves the NumApsExecuting decrease to the path when
InitFlag == ApInitConfig.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Nandagopal Sathyanarayanan <nandagopal.sathyanarayanan@intel.com>
5 months agoUefiCpuPkg/MpInitLib: increase NumApsExecuting only for ApInitConfig
Ray Ni [Tue, 4 Jun 2019 10:49:25 +0000 (18:49 +0800)]
UefiCpuPkg/MpInitLib: increase NumApsExecuting only for ApInitConfig

NumApsExecuting is only used when InitFlag == ApInitConfig for
counting the processor count.

The patch changes Ia32 version of waking up vector assembly code
to align to x64 version of waking up vector assembly code.
After the change both versions of waking up vector increase
NumApsExecuting when InitFlag == ApInitConfig.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
6 months agoCryptoPkg/BaseCryptLib: Wrap OpenSSL SM3 algorithm
Lu, XiaoyuX [Fri, 31 May 2019 08:13:22 +0000 (16:13 +0800)]
CryptoPkg/BaseCryptLib: Wrap OpenSSL SM3 algorithm

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1861

1. Implement OpenSSL SM3 wrapped functions in CryptSm3.c file.
2. Add wrapped SM3 functions declaration to BaseCryptLib.h file.
3. Add CryptSm3.c to each module information file.

Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoUefiCpuPkg CpuCommFeaturesLib: Reduce to set MSR_IA32_CLOCK_MODULATION
Star Zeng [Sat, 18 May 2019 08:55:27 +0000 (16:55 +0800)]
UefiCpuPkg CpuCommFeaturesLib: Reduce to set MSR_IA32_CLOCK_MODULATION

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1810

This patch covers two problems.

1. Current code gets CPUID_THERMAL_POWER_MANAGEMENT in
ClockModulationInitialize() and uses its ECMD bit for all processors.
But ClockModulationInitialize() is only executed by BSP, that means
the bit is just for BSP.
It may have no functionality issue as all processors may have same
bit value in a great possibility. But for good practice, the code
should get CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationSupport
(executed by all processors), and then use them in
ClockModulationInitialize() for all processors.
We can see that Aesni.c (and others) have used this good practice.

2. Current code uses 3 CPU_REGISTER_TABLE_WRITE_FIELD for
MSR_IA32_CLOCK_MODULATION in ClockModulationInitialize(), they can
be reduced to 1 CPU_REGISTER_TABLE_WRITE64 by getting
MSR_IA32_CLOCK_MODULATION for all processors in
ClockModulationSupport() and then update fields for register table
write in ClockModulationInitialize().

We may argue that there may be more times of MSR_IA32_CLOCK_MODULATION
getting. But actually the times of MSR_IA32_CLOCK_MODULATION getting
could be also reduced.

The reason is in ProgramProcessorRegister() of CpuFeaturesInitialize.c,
AsmMsrBitFieldWrite64 (AsmReadMsr64 + AsmWriteMsr64) will be used for
CPU_REGISTER_TABLE_WRITE_FIELD, and AsmWriteMsr64 will be used for
CPU_REGISTER_TABLE_WRITE64.

The times of MSR accessing could be reduced with this patch.
Without the patch:
3 CPU_REGISTER_TABLE_WRITE_FIELD (in ClockModulationInitialize)
  ==> 3 AsmMsrBitFieldWrite64
    ==> 3 AsmReadMsr64 + 3 AsmWriteMsr64

With the patch:
1 AsmReadMsr64 (in ClockModulationSupport) +
1 CPU_REGISTER_TABLE_WRITE64 (in ClockModulationInitialize)
  ==> 1 AsmWriteMsr64

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Kevin Li <kevin.y.li@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
6 months agoUefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supported
Star Zeng [Wed, 22 May 2019 03:21:22 +0000 (11:21 +0800)]
UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supported

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1829

There will be ASSERT if LMCE is supported as below.
DXE_ASSERT!: [CpuFeaturesDxe]
  XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342):
    ConfigData != ((void *) 0)

The code should get Config Data and FeatureControlGetConfigData
could be used.

This issue is there since the code was added at the commit below.

Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0
Date: 2017/8/4 8:46:41
UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature.

The commits below are also related to move the code.

Revision: 023387144299741d727521b425ef443438aecc1f
Date: 2017/9/1 10:12:38
UefiCpuPkg/Lmce.c Remove useless file.

Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f
Date: 2017/8/17 11:40:38
UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file.

So, the code may not be tested at all on a platform
that supports LMCE.

BTW: A typo in LmceInitialize is also fixed.
The typo is introduced by the commit below.

Revision: d28daaddb3e732468e930a809d3d3943a5de9558
Date: 2018/10/17 9:24:05
UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Kevin Li <kevin.y.li@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
6 months agoUefiCpuPkg CpuCommFeaturesLib: Fix GP fault issue about ProcTrace
Star Zeng [Sat, 25 May 2019 07:39:23 +0000 (15:39 +0800)]
UefiCpuPkg CpuCommFeaturesLib: Fix GP fault issue about ProcTrace

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1808

In current code, the values of TopaEntryPtr->Uint64 for TopaTable
and the values of OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64
to register table write for RTIT_OUTPUT_BASE and RTIT_OUTPUT_MASK_PTRS
are not been initialized in whole. For example, the reserved bits in
OutputBaseReg.Uint64 are random that will cause GP fault like below
when SetProcessorRegister (in CpuFeaturesInitialize.c) sets register
based on register table.

!!!! X64 Exception Type - 0D(#GP - General Protection)
  CPU Apic ID - 00000000 !!!!
ExceptionData - 0000000000000000
RIP  -0000000064D69576, CS  -0000000000000038, RFLAGS -0000000000010246
RAX  -000000006B9F1001, RCX -0000000000000560, RDX -0000000000000000
RBX  -0000000064EECA18, RSP -000000006CB82BA0, RBP -0000000000000008
RSI  -0000000080000000, RDI -0000000000000011
R8   -000000006B9493D0, R9  -0000000000000010, R10 -00000000000000FF
R11  -000000006CB82A50, R12 -0000000064D70F50, R13 -0000000066547050
R14  -0000000064E3E198, R15 -0000000000000000
DS   -0000000000000030, ES  -0000000000000030, FS  -0000000000000030
GS   -0000000000000030, SS  -0000000000000030
CR0  -0000000080010013, CR2 -0000000000000000, CR3 -000000006C601000
CR4  -0000000000000628, CR8 -0000000000000000
DR0  -0000000000000000, DR1 -0000000000000000, DR2 -0000000000000000
DR3  -0000000000000000, DR6 -00000000FFFF0FF0, DR7 -0000000000000400
GDTR -000000006B8CCF18 0000000000000047, LDTR -0000000000000000
IDTR -000000006687E018 0000000000000FFF,   TR -0000000000000000
FXSAVE_STATE -000000006CB82800

And current code gets MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and
MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceInitialize() and uses their
values for all processors. But ProcTraceInitialize() is only executed
by BSP, that means the values just for BSP. For good practice, the code
should get MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and
MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceSupport (executed by all
processors), and then use them in ProcTraceInitialize() for all
processors. This can also resolve the issue that the values of
OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64 are not been
initialized in whole.

For TopaEntryPtr->Uint64, this patch updates code to initialize it
in whole explicitly by TopaEntryPtr->Uint64 = 0 before updating its
fields.

At the same time, this patch also eliminates the ProcTraceSupported
field in PROC_TRACE_PROCESSOR_DATA and the TopaMemArrayCount field in
PROC_TRACE_DATA.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Kevin Li <kevin.y.li@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
6 months agoUefiCpuPkg CpuCommFeaturesLib: Disable TraceEn at the beginning
Star Zeng [Sat, 25 May 2019 07:05:47 +0000 (15:05 +0800)]
UefiCpuPkg CpuCommFeaturesLib: Disable TraceEn at the beginning

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1809

Current code disables TraceEn at the end of ProcTraceInitialize(),
then there will be much memory allocated even when ProcTrace feature
is disabled.

This patch updates code to disable TraceEn and return at the beginning
of ProcTraceInitialize() when when ProcTrace feature is disabled.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Kevin Li <kevin.y.li@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
6 months agoEmbeddedPkg/PrePiLib: remove dead status code reporting code
Ard Biesheuvel [Fri, 17 May 2019 16:14:41 +0000 (18:14 +0200)]
EmbeddedPkg/PrePiLib: remove dead status code reporting code

The status code reporting functionality in PrePiLib is never invoked
so let's just remove it.

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoOvmfPkg/QemuVideoDxe: Shouldn't assume system in VGA alias mode.
Marc W Chen [Thu, 6 Jun 2019 07:42:37 +0000 (15:42 +0800)]
OvmfPkg/QemuVideoDxe: Shouldn't assume system in VGA alias mode.

Query the supported attributes firstly, then bitwise AND (&) both VGA_IO
and VGA_IO_16. Since the supported attributes should only have one of
VGA_IO or VGA_IO_16 set, the result of bitwise AND (&) is either VGA_IO
or IO_16. Then the result can be passed to PciIo->Attributes() to set the
attributes.

Device driver should consider both since the mReserveVgaAliases in
PciBusDxe driver is default FALSE(implies that device driver can only set
VGA_IO_16 to PCI_ROOT_BRIDGE), and Platform code may not return
EFI_RESERVE_VGA_IO_ALIAS in GetPlatformPolicy of PciPlatformProtocol to
make mReserveVgaAliases become TRUE(implies that device driver can only
set VGA_IO to PCI_ROOT_BRIDGE), Currently OvmfPkg doesn't have problem
due to it has hard code value for PCI_ROOT_BRIDGE's attributes field, so
an IO access by PciIoProtocol will be successed due to
RootBridgeIoCheckParameter of PciRootBridgeIo.c will always get pass
result for legacy IO access.

Usually the attributes field of PCI_ROOT_BRIDGE should be 0, in that case
it will have issue since the VGA_IO may not be able to be enabled, then
IO access by PciIoProtocol will be failed, hence the QemuVideoDxe driver
will not work fine.

Signed-off-by: Marc Chen <marc.w.chen@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien.grall@arm.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1880
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190606074237.81492-1-marc.w.chen@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
6 months agoCryptoPkg/OpensslLib: fix build break caused by missing library edk2-stable201905
Wang, Jian J [Thu, 6 Jun 2019 02:57:17 +0000 (10:57 +0800)]
CryptoPkg/OpensslLib: fix build break caused by missing library

CryptoPkg\Library\Include\CrtLibSupport.h maps strxxxx interfaces to
edk2 PrintLib interfaces but related module inf file don't claim the
use of it. This will cause unresolved symbol issue with VS2017 build
which has enabled strict symbol check. This patch resolves the problem
by adding PrintLib to inf files.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoRevert "UefiPayloadPkg: Remove legacy PIC 8259 driver"
Liming Gao [Wed, 5 Jun 2019 07:48:09 +0000 (15:48 +0800)]
Revert "UefiPayloadPkg: Remove legacy PIC 8259 driver"

This reverts commit a1539c46958fb896dee8f7987f4a98e9f9d10796.
This change will be pushed after edk2-stable201905

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
6 months agoCryptoPkg/IntrinsicLib: Fix CLANG38 IA32 build problem
Xiaoyu Lu [Wed, 5 Jun 2019 05:24:55 +0000 (13:24 +0800)]
CryptoPkg/IntrinsicLib: Fix CLANG38 IA32 build problem

When use clang-3.8 to build the NetworkPkg, compiler optimization
may use memcpy for memory copy. For example:

 CryptoPkg/Library/OpensslLib/openssl/ssl/ssl_rsa.c:918: undefined
 reference to `memcpy'`

Compiler optimization is sophisticated, but we can work around it
use __attribute__((__used__)) to informs the compiler that symbol
should be retained in the object file, even if it may be
unreferenced.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoedk2: Update additional licenses in Readme.md
Michael D Kinney [Tue, 4 Jun 2019 17:10:16 +0000 (10:10 -0700)]
edk2: Update additional licenses in Readme.md

Update the list of additional licenses in Readme.md.  For additional
licenses from a git submodule, provide a link to the license file
in the remote git repository.  This makes the links in Readme.md
when viewed from the edk2 repository GitHub landing page
https://github.com/tianocore/edk2/ functional from a web browser.

* Remove references EdkCompatibilityPkg
* Update link to OpenSSL to license file in the git submodule link
  to https://github.com/openssl/openssl
* Add link to license file in the git submodule like to
  https://github.com/ucb-bar/berkeley-softfloat-3 for
  ArmSoftFloatLib

Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
6 months agoCryptoPkg/OpensslLib: fix VS2017 build failure
Wang, Jian J [Tue, 4 Jun 2019 21:18:44 +0000 (05:18 +0800)]
CryptoPkg/OpensslLib: fix VS2017 build failure

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1878

This issue is specific to VS2017 which tries to resolve symbol referenced
by a symbol not really referenced eventually.

ossl_init_load_crypto_strings
-> err_load_crypto_strings_int (not really referenced)
-> ERR_load_OSSL_STORE_strings

Because OPENSSL_NO_ERR and OPENSSL_NO_AUTOERRINIT are not defined by
default, err_load_crypto_strings_int() will not be actually referenced
by ossl_init_load_crypto_strings().

Since err_load_crypto_strings_int() is not actually referenced at all,
the fix can be done simply by removing crypto/err/err_all.c from build.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoMaintainers.txt: Remove Network maintainers for MdeModulePkg/Universal/Network
Liming Gao [Tue, 4 Jun 2019 14:10:59 +0000 (22:10 +0800)]
Maintainers.txt: Remove Network maintainers for MdeModulePkg/Universal/Network

MdeModulePkg/Universal/Network has been moved to NetworkPkg. So,
MdeModulePkg/Universal/Network can be removed in Maintainers.txt.

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6 months agoRevert "EmulatorPkg: don't display the cpu current speed"
Laszlo Ersek [Tue, 4 Jun 2019 18:17:48 +0000 (20:17 +0200)]
Revert "EmulatorPkg: don't display the cpu current speed"

This reverts commit 7cea4d71a8a87a93924a07ab32348332f5881ef9.

Said commit was not suitable for pushing during the edk2-stable201905 hard
feature freeze; it was pushed only by mistake. The subject line referenced
EmulatorPkg, but the patch changed MdeModulePkg/UiApp, regressing the
display of the CPU speed from SMBIOS in multiple platforms.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1877
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoUefiPayloadPkg: Remove legacy PIC 8259 driver
Dong, Guo [Wed, 29 May 2019 18:52:20 +0000 (11:52 -0700)]
UefiPayloadPkg: Remove legacy PIC 8259 driver

Since legacy PIC 8259 driver would be removed from edk2,
update UEFI payload to remove 8259 driver.
If required, bootloader could disable 8259.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
6 months agoEmulatorPkg: don't display the cpu current speed
Zhiguang Liu [Mon, 3 Jun 2019 06:35:35 +0000 (14:35 +0800)]
EmulatorPkg: don't display the cpu current speed

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1686

The bug reporter wish to display nothing as the CPU is virtual

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
6 months agoFmpDevicePkg: Add TimerLib to DSC file
Xiaoyu Lu [Mon, 3 Jun 2019 12:33:43 +0000 (20:33 +0800)]
FmpDevicePkg: Add TimerLib to DSC file

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

FmpDevicePkg use OpensslLib and when OpenSSL upgrade to 1.1.1b,
TimerLib is required by OpensslLib in CryptoPkg(commit 456dd8b99f,
CryptoPkg: Upgrade OpenSSL to 1.1.1b)

So add TimerLib to DSC file.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
6 months agoCryptoPkg: Fix build problem with XCODE
Xiaoyu Lu [Mon, 3 Jun 2019 09:52:38 +0000 (17:52 +0800)]
CryptoPkg: Fix build problem with XCODE

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

When building CryptoPkg with XCODE, blow error may result

* usr/lib/clang/9.0.0/include/stdatomic.h:105:17:
error: unknown type name 'wchar_t'

Since the C native atomics are C11 feature we can explicitly
use C99 to work around it.
add -std=c99 to avoid it

* openssl/crypto/conf/conf_sap.c:71:12: error: variable 'ret' is
    uninitialized
    when used here [-Werror,-Wuninitialized]

Suppress warnings in OpenSSL so we don't break the build with -Werror.
add -Wno-error=uninitialized to disalbe this warning

Cc: Jian Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoOvmfPkg/PlatformPei: set 32-bit UC area at PciBase / PciExBarBase (pc/q35)
Laszlo Ersek [Wed, 29 May 2019 12:49:55 +0000 (14:49 +0200)]
OvmfPkg/PlatformPei: set 32-bit UC area at PciBase / PciExBarBase (pc/q35)

(This is a replacement for commit 39b9a5ffe661 ("OvmfPkg/PlatformPei: fix
MTRR for low-RAM sizes that have many bits clear", 2019-05-16).)

Reintroduce the same logic as seen in commit 39b9a5ffe661 for the pc
(i440fx) board type.

For q35, the same approach doesn't work any longer, given that (a) we'd
like to keep the PCIEXBAR in the platform DSC a fixed-at-build PCD, and
(b) QEMU expects the PCIEXBAR to reside at a lower address than the 32-bit
PCI MMIO aperture.

Therefore, introduce a helper function for determining the 32-bit
"uncacheable" (MMIO) area base address:

- On q35, this function behaves statically. Furthermore, the MTRR setup
  exploits that the range [0xB000_0000, 0xFFFF_FFFF] can be marked UC with
  just two variable MTRRs (one at 0xB000_0000 (size 256MB), another at
  0xC000_0000 (size 1GB)).

- On pc (i440fx), the function behaves dynamically, implementing the same
  logic as commit 39b9a5ffe661 did. The PciBase value is adjusted to the
  value calculated, similarly to commit 39b9a5ffe661. A further
  simplification is that we show that the UC32 area size truncation to a
  whole power of two automatically guarantees a >=2GB base address.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoOvmfPkg: raise the PCIEXBAR base to 2816 MB on Q35
Laszlo Ersek [Wed, 29 May 2019 09:59:02 +0000 (11:59 +0200)]
OvmfPkg: raise the PCIEXBAR base to 2816 MB on Q35

(This is a replacement for commit 75136b29541b, "OvmfPkg/PlatformPei:
reorder the 32-bit PCI window vs. the PCIEXBAR on q35", 2019-05-16).

Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG
/ ECAM) on Q35", 2016-03-10) claimed that,

  On Q35 machine types that QEMU intends to support in the long term, QEMU
  never lets the RAM below 4 GB exceed 2 GB.

Alas, this statement came from a misunderstanding that occurred while we
worked out the interface contract. In fact QEMU does allow the 32-bit RAM
extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the
range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than
2048MB and smaller than 2816MB).

In turn, such a RAM size (justifiedly) triggers

  ASSERT (TopOfLowRam <= PciExBarBase);

in MemMapInitialization(), because we placed the 256MB PCIEXBAR at
0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the
32-bit PCI window would follow the PCIEXBAR, covering the [0x9000_0000,
0xFC00_0000) range.)

In order to fix this, place the PCIEXBAR at 2816MB (0xB000_0000), and
start the 32-bit PCI window at 3 GB (0xC000_0000). This shrinks the 32-bit
PCI window to

  0xFC00_0000 - 0xC000_0000 = 0x3C00_0000 = 960 MB.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoRevert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly"
Laszlo Ersek [Wed, 29 May 2019 09:52:03 +0000 (11:52 +0200)]
Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly"

This reverts commit 60e95bf5094fbb9b728729ccfaf32184b3662317.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
6 months agoRevert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching"
Laszlo Ersek [Wed, 29 May 2019 09:51:44 +0000 (11:51 +0200)]
Revert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching"

This reverts commit 9a2e8d7c65ef7f39c6754d27e52954b616bc6628.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoRevert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35"
Laszlo Ersek [Wed, 29 May 2019 09:51:26 +0000 (11:51 +0200)]
Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35"

This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoRevert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear"
Laszlo Ersek [Wed, 29 May 2019 09:49:07 +0000 (11:49 +0200)]
Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear"

This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
6 months agoCryptoPkg CLANG35: add -std=c99 to dodge OpenSSL C atomics issue
Ard Biesheuvel [Mon, 3 Jun 2019 16:19:41 +0000 (18:19 +0200)]
CryptoPkg CLANG35: add -std=c99 to dodge OpenSSL C atomics issue

Commit c51f8bae7cabe ("CryptoPkg: Fix possible build problem with
Clang") added -std=c99 to the CLANG38 compiler command line of
packages that incorporate parts of OpenSSL, to ensure that the new
C atomics code used by OpenSSL for refcounting (which we don't care
about) does not pull in system C library headers, which we cannot
rely on when (cross)building EDK2 code.

Unsurprisingly, CLANG35 (which is only defined for ARM and AARCH64)
suffers from the exact same issue, so let's add the same flags
there as well.

Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoCryptoPkg/BaseCryptLib: Make HMAC_CTX size backward compatible
Xiaoyu Lu [Wed, 29 May 2019 18:40:38 +0000 (18:40 +0000)]
CryptoPkg/BaseCryptLib: Make HMAC_CTX size backward compatible

Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

OpenSSL internally redefines the size of HMAC_CTX at
crypto/hmac/hmac_lcl.h(OpenSSL commit e0810e35).
Ref: https://github.com/openssl/openssl/pull/4338

We should not use it directly and should remove relevant
functions(Hmac*GetContextSize).
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=1792

But for compatiblility, temporarily change these definition
of HMAC_*_CTX_SIZE.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg: Upgrade OpenSSL to 1.1.1b
XiaoyuX Lu [Wed, 29 May 2019 18:40:37 +0000 (18:40 +0000)]
CryptoPkg: Upgrade OpenSSL to 1.1.1b

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

* Update OpenSSL submodule to OpenSSL_1_1_1b
   OpenSSL_1_1_1b(50eaac9f3337667259de725451f201e784599687)

* Run process_files.pl script to regenerate OpensslLib[Crypto].inf
  and opensslconf.h

* Remove -DNO_SYSLOG from OPENSSL_FLAGS in OpensslLib[Crypto].inf,
  due to upstream OpenSSL commit cff55b90e95e("Cleaning UEFI
  Build with additional OPENSSL_SYS_UEFI flags", 2017-03-29),
  which was first released as part of OpenSSL_1_1_1.

* Starting with OpenSSL commit 8a8d9e1905(first release in
  OpenSSL_1_1_1), the OpenSSL_version() function can no longer
  return a pointer to the string literal "compiler: information
  not available", in the case CFLAGS macro is not defined.
  Instead, the function now has a hard dependency on the global
  variable 'compiler_flags'. This variable is normally placed
  by "util/mkbuildinf.pl" into "buildinf.h". In edk2 we don't
  run that script whenever we build OpenSSL, therefore we
  must provide our own dummy 'compiler_flags'.

* BUFSIZ is used by crypto/evp/evp_key.c(OpenSSL_1_1_1b)
  And it is declared in stdio.h. So add it to CrtLibSupport.h.
  Here's a discussion about this.
  Ref: https://github.com/openssl/openssl/issues/8904

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/OpensslLib: Add functions for upgrading OpenSSL1_1_1b
XiaoyuX Lu [Wed, 29 May 2019 18:40:36 +0000 (18:40 +0000)]
CryptoPkg/OpensslLib: Add functions for upgrading OpenSSL1_1_1b

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

* From OpenSSL_1_1_0i(97c0959f27b294fe1eb10b547145ebef2524b896) to
  OpenSSL_1_1_1b(50eaac9f3337667259de725451f201e784599687), OpenSSL
  updated DRBG / RAND to request nonce and additional low entropy
  randomness from system(line 229 openssl/CHANGES).

  Since OpenSSL_1_1_1b doesn't fully implement rand pool functions
  for UEFI. We must provide a method to implenet these method.
  TSC is used as first entropy source if it's availabe otherwise
  fallback to TimerLib. But we are not sure the amount of randomness
  they provide. If you really care about the security, one choice is
  overrided it with hardware generator.

  Add rand_pool.c to implement these functions required by OpenSSL
    rand_pool_acquire_entropy
    rand_pool_add_nonce_data
    rand_pool_add_additional_data
    rand_pool_init
    rand_pool_cleanup
    rand_pool_keep_random_devices_open

  And add rand_pool_noise.* for getting entropy noise from different
  architecture.

* We don't need ossl_store functions. We exclude relative files
  through process_files.pl. And ossl_store_cleanup_int was first
  added in crypto/init.c OpenSSL_1_1_1(71a5516d).
  So add a new file(ossl_store.c) to implement ossl_store_cleanup_int
  function.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg: Fix possible build problem with Clang
XiaoyuX Lu [Wed, 29 May 2019 18:40:35 +0000 (18:40 +0000)]
CryptoPkg: Fix possible build problem with Clang

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

When building CryptoPkg with Clang, blow error may result

* /usr/lib/llvm-3.8/lib/clang/3.8.0/include/stdatomic.h:105:17: error:
    unknown type name 'wchar_t'

Since the C native atomics are C11 feature we can explicitly
use C99 to work around it.
add -std=c99 to avoid it

* openssl/crypto/conf/conf_sap.c:71:12: error: variable 'ret' is
  uninitialized
  when used here [-Werror,-Wuninitialized]

Suppress warnings in OpenSSL so we don't break the build with -Werror.
add -Wno-error=uninitialized to disalbe this warning

Cc: Ting Ye <ting.ye@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/OpensslLib: Fix cross-build problem for AARCH64
Laszlo Ersek [Wed, 29 May 2019 18:40:34 +0000 (18:40 +0000)]
CryptoPkg/OpensslLib: Fix cross-build problem for AARCH64

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

Thanks Laszlo Ersek <lersek@redhat.com>.
Ref: https://edk2.groups.io/g/devel/message/40375

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/OpensslLib: Prepare for upgrading OpenSSL
XiaoyuX Lu [Wed, 29 May 2019 18:40:33 +0000 (18:40 +0000)]
CryptoPkg/OpensslLib: Prepare for upgrading OpenSSL

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

Disable warning for building OpenSSL_1_1_1b

add /wd4132 /wd4700 /wd4310 for Visual Studio in OpensslLib[Crypto].inf

add -Wno-error=unused-but-set-variable for GCC in OpensslLib[Crypto].inf
Although this option is set in some build environments by default.
But this is only for OpenSSL compilation, no matter how the
default options change.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/IntrinsicLib: Fix possible unresolved external symbol issue
Xiaoyu Lu [Wed, 29 May 2019 18:40:32 +0000 (18:40 +0000)]
CryptoPkg/IntrinsicLib: Fix possible unresolved external symbol issue

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

This is for the upcoming upgrade to OpenSSL_1_1_1b

Compiler optimization(Visual Studio) may automatically use _ftol2
instead of some type conversion. For example:

 OpensslLib.lib(drbg_lib.obj) : error LNK2001:
    unresolved external symbol __ftol2

This patch add _ftol2 function for the compiler intrinsic.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/OpensslLib: Exclude unnecessary files in process_files.pl
Xiaoyu Lu [Wed, 29 May 2019 18:40:31 +0000 (18:40 +0000)]
CryptoPkg/OpensslLib: Exclude unnecessary files in process_files.pl

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

When running process_files.py to configure OpenSSL, we can exclude
some unnecessary files. This can reduce porting time, compiling
time and library size.

Upstream OpenSSL commit 71a5516dcc8a which was as part of
OpenSSL_1_1_1b, Add the STORE module(crypto/store/*).
But UEFI don't use them. So exclude these files.

Functions in crypto/rand/randfile.c OpenSSL and edk2 don't
call them. And it requires more crt runtime support.
So exclude it.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoCryptoPkg/OpensslLib: Modify process_files.pl for upgrading OpenSSL
Xiaoyu Lu [Wed, 29 May 2019 18:40:30 +0000 (18:40 +0000)]
CryptoPkg/OpensslLib: Modify process_files.pl for upgrading OpenSSL

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1089

OpenSSL configure mechanism use --with-rand-seed=xxx option to configure
random number generation.

OpenSSL_1_1_0j(74f2d9c1ec5f5510e1d3da5a9f03c28df0977762)
we use default --with-rand-seed=os option to for building it.

But OpenSSL_1_1_1b(50eaac9f3337667259de725451f201e784599687)
only support seeding NONE for UEFI(rand_unix.c line 93).

This OpenSSL change was introduced in commit
8389ec4b4950 ("Add --with-rand-seed", 2017-07-22).

So add --with-rand-seed=none to process_files.pl.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
6 months agoArmPkg/ArmSoftFloatLib GCC4x: fix build failure
Ard Biesheuvel [Fri, 31 May 2019 20:46:30 +0000 (22:46 +0200)]
ArmPkg/ArmSoftFloatLib GCC4x: fix build failure

The upstream SoftFloat code that was recently incorporated into
ArmSoftFloatLib uses some parameterization to tweak the inlining
and optimization behavior for different compilers.

The custom platform.h file that sets these parameters is based on
the upstream version for Linux/ARM, but was updated to include the
'always_inline' GCC attribute into the INLINE macro, to ensure that
all definitions that are marked as inline are not only inlined into
their callers, but also to ensure that no version of the function is
ever emitted into the object file.

This works fine on recent GCC and Clang, but the latter part turns
out to break on GCC 4.x, resulting duplicate definition linker errors.
Fortunately, the synticatically more appriopriate 'static inline'
works fine on both the recent and the older compilers, so let's switch
to that instead.

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoArmPkg/ArmLib ARM: set .fpu to let Clang 7 assemble ArmV7Support.S
Ard Biesheuvel [Thu, 20 Dec 2018 19:16:53 +0000 (20:16 +0100)]
ArmPkg/ArmLib ARM: set .fpu to let Clang 7 assemble ArmV7Support.S

Clang 7 complains about the vmsr instruction in ArmV7Support.S,
which is only available on cores that implement some flavour of
VFP. So set the .fpu to NEON like we do in some other places.

Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoArmPkg/ArmSoftFloatLib: remove source files that are no longer used
Ard Biesheuvel [Fri, 24 May 2019 14:58:40 +0000 (16:58 +0200)]
ArmPkg/ArmSoftFloatLib: remove source files that are no longer used

Now that we have switched to a new version of the SoftFloat code,
remove the source files that make up the old implementation, and
are no longer referenced.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1845
Acked-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoArmPkg/ArmSoftFloatLib: switch to new version of softfloat library
Ard Biesheuvel [Fri, 24 May 2019 14:52:13 +0000 (16:52 +0200)]
ArmPkg/ArmSoftFloatLib: switch to new version of softfloat library

Update the INF description and the top level .c files in order to
switch to the new version of the SoftFloat library imported as a
Git submodule in the previous patch.

Note that we no longer use the code that travelled a long way from
the 2002 version of the softfloat library via NetBsd and the StdLib
package. Instead, we are using the upstream version unmodified, with
the glue .c file adopted from the OP-TEE project. This approach is
much cleaner and much more maintainable.

Note that support for the RVCT toolchains is being dropped at the same
time. RVCT is mostly untested, and planned to be removed, and so it
makes little sense to go to the trouble of upgrading this library for
RVCT as well.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1845
Acked-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoArmPkg: import Berkeley Softfloat library as git submodule
Ard Biesheuvel [Fri, 24 May 2019 14:05:02 +0000 (16:05 +0200)]
ArmPkg: import Berkeley Softfloat library as git submodule

In preparation of bringing ArmSoftFloatLib up to date in order
to provide some missing routines, import the Berkely SoftFloat
library into the tree as a git submodule.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1845
Acked-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoBaseTools:Update binary cache restore time to current time
Steven Shi [Tue, 28 May 2019 08:35:14 +0000 (16:35 +0800)]
BaseTools:Update binary cache restore time to current time

https://bugzilla.tianocore.org/show_bug.cgi?id=1742

Current Binary Cache doesn't update the restored file
creation and modification times to the current time.
Preserve the new restored file creation time as old
cached time might has potential issue to block the make
to build updated files based on the time stamp.
Enhance to update the restored file creation time to
current time.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Zhiju Fan <zhijux.fan@intel.com>
Signed-off-by: Steven Shi <steven.shi@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoBaseTools:Extend the binary cache to support library cache
Steven Shi [Thu, 30 May 2019 02:31:27 +0000 (10:31 +0800)]
BaseTools:Extend the binary cache to support library cache

https://bugzilla.tianocore.org/show_bug.cgi?id=1797

Current binary cache doesn't support to save and restore
the library module. If a driver module cache miss happen,
all its dependency library modules need rebuild which
is very time-consuming. This patch is to extend the binary
cache to support library.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Christian Rodriguez <christian.rodriguez@intel.com>
Signed-off-by: Steven Shi <steven.shi@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoMdeModulePkg/AhciPei: Fix device cannot be found in non-S3 path
Hao A Wu [Thu, 30 May 2019 01:17:22 +0000 (09:17 +0800)]
MdeModulePkg/AhciPei: Fix device cannot be found in non-S3 path

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1862

Current implementation of function AhciModeInitialization() has an
incorrect assumption that the value in the CAP (offset 00h) register will
always be greater than the highest bit set for the value in the PI (offset
0Ch) register.

This will lead to an issue that hard disk devices may not be found in the
non-S3 boot path for some AHCI controller capabilities.

More specifically, variable 'PortInitializeBitMap' will have the value
from 'Private->PortBitMap', which will be 0xFFFFFFFF in non-S3 boot path.
When the CAP register is of value 0x1 and PI register with value 0x4
(meaning port 2 is available), the current logic will only enumerate port
0. And the device attached behind port 2 will not be enumerated.

To address this issue, variable 'PortInitializeBitMap' will now take the
bitwise and result between 'Private->PortBitMap' and the value read from
the PI register.

Please note that there will be no function impact for S3 path, since in
this case, the bits being set in 'Private->PortBitMap' will be a subset
of the bits being set in the PI register. Their bitwise and operation will
still be the value of 'Private->PortBitMap'.

Cc: Maggie Chu <maggie.chu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
6 months agoIntelFsp2Pkg/SplitFspBin.py: Revert FSP 1.x support.
Chasel Chiu [Fri, 31 May 2019 06:46:41 +0000 (14:46 +0800)]
IntelFsp2Pkg/SplitFspBin.py: Revert FSP 1.x support.

This reverts commit:
  591b8cb7f3d026d2fa4483c59f3d5fb14be181bf.
Will submit again after freeze done.

Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoIntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.
Chasel Chiu [Tue, 28 May 2019 13:51:39 +0000 (21:51 +0800)]
IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308

Support rebasing FSP 1.x binary.
FSP 1.x has single component in binary so not supported
by split command and rebase can be done with the same
command for rebasing FSP-T component in FSP 2.x image.

Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary
      can be rebased successfully.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
6 months agoMaintainers.txt: update UEFI payload information
Guo Dong [Wed, 29 May 2019 19:07:29 +0000 (03:07 +0800)]
Maintainers.txt: update UEFI payload information

Remove CorebootModulePkg and CorebootPayloadPkg, and add
UefiPayloadPkg to reflect recently change in UEFI payload.
wiki link for UefiPayloadPkg would be available soon.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
6 months agoMaintainers.txt: update mailing list information
Leif Lindholm [Tue, 28 May 2019 10:15:31 +0000 (11:15 +0100)]
Maintainers.txt: update mailing list information

The devel mailing list has moved from 01.org to groups.io - update
the mailing list information to reflect this.

Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6 months agoSignedCapsulePkg: Update Package DSC to remove unused network libs
Liming Gao [Tue, 28 May 2019 11:35:09 +0000 (19:35 +0800)]
SignedCapsulePkg: Update Package DSC to remove unused network libs

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoArmPkg: Update Package DSC to remove unused NetLib
Liming Gao [Tue, 28 May 2019 11:34:40 +0000 (19:34 +0800)]
ArmPkg: Update Package DSC to remove unused NetLib

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoUefiPayloadPkg: Update Package DSC files to refer to NetworkLibs.dsc.inc
Liming Gao [Tue, 28 May 2019 11:33:43 +0000 (19:33 +0800)]
UefiPayloadPkg: Update Package DSC files to refer to NetworkLibs.dsc.inc

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoMdeModulePkg: Remove network library header file from package DEC file
Liming Gao [Wed, 15 May 2019 12:02:20 +0000 (20:02 +0800)]
MdeModulePkg: Remove network library header file from package DEC file

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
6 months agoNetworkPkg: Move Network library header file from MdeModulePkg to NetworkPkg
Liming Gao [Wed, 15 May 2019 12:02:19 +0000 (20:02 +0800)]
NetworkPkg: Move Network library header file from MdeModulePkg to NetworkPkg

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
6 months agoNetworkPkg: Move Network library and drivers from MdeModulePkg to NetworkPkg
Liming Gao [Wed, 15 May 2019 12:02:18 +0000 (20:02 +0800)]
NetworkPkg: Move Network library and drivers from MdeModulePkg to NetworkPkg

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
6 months agoBaseTools:Change the path of the file that Binary Cache
Fan, ZhijuX [Fri, 24 May 2019 05:02:18 +0000 (13:02 +0800)]
BaseTools:Change the path of the file that Binary Cache

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1806

Current Binary Cache use the PlatformInfo.Name to distinguish
the different platform cache paths in the database folder.

But the different platforms might use the same PLATFORM_NAME
in the DSC files. Different platform caches might overlay each
other inside Binary Cache database if they use same platform name

Use the PlatformInfo.Platform.OutputDirectory instead of the
PlatformInfo.Name can solve the problem.

This patch is going to fix that issue.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Steven Shi <steven.shi@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoBaseTools: Remove './SecMain' from 'run' target
Bob Feng [Thu, 23 May 2019 09:06:35 +0000 (17:06 +0800)]
BaseTools: Remove './SecMain' from 'run' target

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1561

This patch is related to commit 9ca1f1
It's to remove the second .SecMain call from 'run' target.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
6 months agoMdeModulePkg: Update MdeModulePkg.dsc to remove Network related modules
Liming Gao [Tue, 21 May 2019 15:21:52 +0000 (23:21 +0800)]
MdeModulePkg: Update MdeModulePkg.dsc to remove Network related modules

Network related modules have been included in NetworkPkg.dsc.
They can be removed from MdeModulePkg.dsc.

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
6 months agoBaseTools: Update Conf/target.template with the default EmulatorPkg.dsc
Liming Gao [Tue, 21 May 2019 15:09:05 +0000 (23:09 +0800)]
BaseTools: Update Conf/target.template with the default EmulatorPkg.dsc

Nt32Pkg has been removed. The default platform is changed to EmulatorPkg.dsc.

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoIntelFrameworkModulePkg/DebugLib: Fix string copy issue
Gao, Zhichao [Tue, 21 May 2019 07:49:52 +0000 (15:49 +0800)]
IntelFrameworkModulePkg/DebugLib: Fix string copy issue

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1826

There is a bug to use AsciiStrCpyS to copy a truncated
string. If would cause an assert because the truncated
length is always less than the source string length. It
should use the AsciiStrnCpyS instead.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoBaseTools: Remove './SecMain' from 'run' target
Feng, Bob C [Fri, 10 May 2019 06:33:36 +0000 (14:33 +0800)]
BaseTools: Remove './SecMain' from 'run' target

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1561

When a target of 'run' is passed into build.py,
BaseTools unconditionally attempts to execute the
application called './SecMain' in the build output directory.

This behavior applies to the Nt32Pkg which is being
replaced with features in the EmulatorPkg.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
6 months agoBaseTools:Update mailing list address in BaseTools error messages
Fan, ZhijuX [Tue, 21 May 2019 02:06:52 +0000 (10:06 +0800)]
BaseTools:Update mailing list address in BaseTools error messages

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1815

The edk2 source tree contains four instances of the outdated mailing
list address "edk2-devel@lists.01.org".
I created a new variable, MSG_EDKII_MAIL_ADDR, to receive the
new email address and replaced the old one with this variable

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoBaseTools: Library hashing fix and optimization for --hash feature
Rodriguez, Christian [Mon, 20 May 2019 14:17:54 +0000 (22:17 +0800)]
BaseTools: Library hashing fix and optimization for --hash feature

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1788

In V3: Must generate hashes before attempting to copy from cache for
hash verifcation
In V2: Build failure caused by passing incorrect boolean parameter to
SaveFileOnChange(). Fixed for patch instances.

Library hashing is now supported by the --hash feature. The --hash
feature implementation assumed that the hashing could be done in
place once per module, but that isn't true for libraries due to the
fact that they are built as dependencies. So on a clean build, we now
generate the .hash after the library dependencies are complete.
Added early escape as optimization, if hash already exists in memory.

Signed-off-by: Christian Rodriguez <christian.rodriguez@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoBaseTools: Fix private includes for FILE_GUID override
Michael D Kinney [Fri, 22 Mar 2019 00:27:20 +0000 (17:27 -0700)]
BaseTools: Fix private includes for FILE_GUID override

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1648

When a module in a DSC file uses a FILE_GUID override in the
module scoped <Defines> section, a copy of the modified INF file
is placed in the Conf/.cache directory.  The check for private
includes uses the INF path to determine if the module is allowed
to use the private includes.  Since the INF path in this case is
not in any package, this check always fails, and no private
include paths are possible.

The fix is to keep both the OriginalPath and the new Path in
the PathClass object, and always use the OriginalPath to see if
the module INF is in the package with private includes.

Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
6 months agoMaintainers.txt: remove UTF-8 BOM wrongly added in commit 147e6e70
Ray Ni [Fri, 17 May 2019 15:03:59 +0000 (23:03 +0800)]
Maintainers.txt: remove UTF-8 BOM wrongly added in commit 147e6e70

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6 months agoEmulatorPkg: Add NetworkPkg/NetworkPkg.dec as the package dependency
Liming Gao [Mon, 20 May 2019 12:06:43 +0000 (20:06 +0800)]
EmulatorPkg: Add NetworkPkg/NetworkPkg.dec as the package dependency

NetLib will be moved from MdeModulePkg and NetworkPkg.
So, the module that consumes NetLib need to depend on NetworkPkg.dec.

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
6 months agoShellPkg: Add NetworkPkg/NetworkPkg.dec as the package dependency
Liming Gao [Mon, 20 May 2019 01:57:37 +0000 (09:57 +0800)]
ShellPkg: Add NetworkPkg/NetworkPkg.dec as the package dependency

NetLib will be moved from MdeModulePkg and NetworkPkg.
So, the module that consumes NetLib need to depend on NetworkPkg.dec.

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
6 months agoShellPkg: Display VENDOR_ID in ASCII when parsing PPTT
Krzysztof Koch [Wed, 8 May 2019 13:13:54 +0000 (06:13 -0700)]
ShellPkg: Display VENDOR_ID in ASCII when parsing PPTT

The ID Type Structure (Type 2) inside the Processor Properties
Topology Table (PPTT) has a VENDOR_ID field which identifies the
node vendor. The approved values are listed in the ACPI ID Registry
and they are meant to be interpreted as arrays of ASCII characters.

This change to the acpiview parser for PPTT aims to reflect that.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
6 months agoEmbeddedPkg: Update DSC to use NetworkPkg's include fragment file
Liming Gao [Fri, 17 May 2019 08:50:35 +0000 (16:50 +0800)]
EmbeddedPkg: Update DSC to use NetworkPkg's include fragment file

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
6 months agoShellPkg: Update DSC to use NetworkPkg's include fragment file
Liming Gao [Fri, 17 May 2019 08:50:34 +0000 (16:50 +0800)]
ShellPkg: Update DSC to use NetworkPkg's include fragment file

Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
6 months agoUefiCpuPkg CpuCommonFeaturesLib: Remove CPU generation check
Star Zeng [Thu, 16 May 2019 10:30:03 +0000 (18:30 +0800)]
UefiCpuPkg CpuCommonFeaturesLib: Remove CPU generation check

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1679

The checking to CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI is enough,
the checking to CPU generation could be removed, then the code
could be reused by more platforms.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
6 months agoShellPkg/UefiShellAcpiViewCommandLib: Fix PPTT cache attributes validation
Krzysztof Koch [Fri, 17 May 2019 15:50:50 +0000 (08:50 -0700)]
ShellPkg/UefiShellAcpiViewCommandLib: Fix PPTT cache attributes validation

Removed conditional pre-compiling for ARM CPUs because function
ValidateCacheAttributes(..) is based on ACPI PPTT specification.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reported-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Bi Dandan <dandan.bi@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
6 months agoShellPkg: acpiview: Add GT Frame Number validation to GTDT parser
Krzysztof Koch [Thu, 16 May 2019 08:43:35 +0000 (01:43 -0700)]
ShellPkg: acpiview: Add GT Frame Number validation to GTDT parser

The ACPI 6.2 specification mandates that the Generic Timer (GT) Block
Timer Structures must have a frame number in the range 0-7.

Update the GTDT parser to warn if this condition is violated.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
6 months agoMaintainers.txt: Add 'Zhichao Gao' for ShellPkg review
Zhichao Gao [Fri, 17 May 2019 00:55:35 +0000 (08:55 +0800)]
Maintainers.txt: Add 'Zhichao Gao' for ShellPkg review

Add 'Zhichao Gao' as a reviewer for ShellPkg.

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
6 months agoCryptoPkg/BaseCryptLib: remove unused code for IPF
Jian J Wang [Tue, 14 May 2019 14:28:33 +0000 (22:28 +0800)]
CryptoPkg/BaseCryptLib: remove unused code for IPF

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1805

CryptRandItc.c is only for IPF arch, which has not been supported any
more in edk2. And no module actually reference this file. This patch
just removes it from tree.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoMaintainers.txt: Remove Nt32Pkg reference after Nt32Pkg is removed
Ray Ni [Fri, 17 May 2019 04:56:35 +0000 (12:56 +0800)]
Maintainers.txt: Remove Nt32Pkg reference after Nt32Pkg is removed

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
6 months agoNt32Pkg: Remove it
Ray Ni [Fri, 17 May 2019 04:55:16 +0000 (12:55 +0800)]
Nt32Pkg: Remove it

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1812

Now since EmulatorPkg supports to run in Windows environment,
this patch removes Nt32Pkg to remove duplicate code in edk2 repo.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
6 months agoUefiCpuPkg: Remove double \r
Joe Richey [Fri, 10 May 2019 09:36:33 +0000 (17:36 +0800)]
UefiCpuPkg: Remove double \r

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Joe Richey <joerichey@google.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
6 months agoOvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear
Laszlo Ersek [Fri, 3 May 2019 14:01:48 +0000 (16:01 +0200)]
OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear

Assume that we boot OVMF in a QEMU guest with 1025 MB of RAM. The
following assertion will fire:

> ASSERT_EFI_ERROR (Status = Out of Resources)
> ASSERT OvmfPkg/PlatformPei/MemDetect.c(696): !EFI_ERROR (Status)

That's because the range [1025 MB, 4 GB) that we try to mark as
uncacheable with MTRRs has size 3071 MB:

   0x1_0000_0000
  -0x0_4010_0000
  --------------
   0x0_BFF0_0000

The integer that stands for the uncacheable area size has 11 (eleven) bits
set to 1. As a result, covering this size requires 11 variable MTRRs (each
MTRR must cover a naturally aligned, power-of-two sized area). But, if we
need more variable MTRRs than the CPU can muster (such as 8), then
MtrrSetMemoryAttribute() fails, and we refuse to continue booting (which
is justified, in itself).

Unfortunately, this is not difficult to trigger, and the error message is
well-hidden from end-users, in the OVMF debug log. The following
mitigation is inspired by SeaBIOS:

Truncate the uncacheable area size to a power-of-two, while keeping the
end fixed at 4 GB. Such an interval can be covered by just one variable
MTRR.

This may leave such an MMIO gap, between the end of low-RAM and the start
of the uncacheable area, that is marked as WB (through the MTRR default).
Raise the base of the 32-bit PCI MMIO aperture accordingly -- the gap will
not be used for anything.

On Q35, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 2815
MB) shrinks from

  0xE000_0000 - 0xAFF0_0000 = 769 MB

to

  0xE000_0000 - 0xC000_0000 = 512 MB

On i440fx, the minimal 32-bit PCI MMIO aperture (triggered by RAM size
3583 MB) shrinks from

  0xFC00_0000 - 0xDFF0_0000 = 449 MB

to

  0xFC00_0000 - 0xE000_0000 = 448 MB

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoOvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35
Laszlo Ersek [Tue, 22 Jan 2019 19:56:36 +0000 (20:56 +0100)]
OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35

Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG
/ ECAM) on Q35", 2016-03-10) claimed that,

  On Q35 machine types that QEMU intends to support in the long term, QEMU
  never lets the RAM below 4 GB exceed 2 GB.

Alas, this statement came from a misunderstanding that occurred while we
worked out the interface contract. In fact QEMU does allow the 32-bit RAM
extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the
range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than
2048MB and smaller than 2816MB).

In turn, such a RAM size (justifiedly) triggers

  ASSERT (TopOfLowRam <= PciExBarBase);

in MemMapInitialization(), because we placed the 256MB PCIEXBAR at
0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the
32-bit PCI window would follow the PCIEXBAR, covering the [0x9000_0000,
0xFC00_0000) range.)

In order to fix this, reorder the 32-bit PCI window against the PCIEXBAR,
as follows:

- start the 32-bit PCI window where it starts on i440fx as well, that is,
  at 2GB or TopOfLowRam, whichever is higher;

- unlike on i440fx, where the 32-bit PCI window extends up to 0xFC00_0000,
  stop it at 0xE000_0000 on q35,

- place the PCIEXBAR at 0xE000_0000.

(We cannot place the PCIEXBAR at 0xF000_0000 because the 256MB MMIO area
that starts there is not entirely free.)

Before this patch, the 32-bit PCI window used to only *end* at the same
spot (namely, 0xFC00_0000) between i440fx and q35; now it will only
*start* at the same spot (namely, 2GB or TopOfLowRam, whichever is higher)
between both boards.

On q35, the maximal window shrinks from

  0xFC00_0000 - 0x9000_0000 = 0x6C00_0000 == 1728 MB

to

  0xE000_0000 - 0x8000_0000 == 1536 MB.

We lose 192 MB of the aperture; however, the aperture is now aligned at
1GB, rather than 256 MB, and so it could fit a 1GB BAR even.

Regarding the minimal window (triggered by RAM size 2815MB), its size is

  0xE000_0000 - 0xAFF0_0000 = 769 MB

which is not great, but probably better than a failed ASSERT.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
6 months agoOvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching
Laszlo Ersek [Tue, 22 Jan 2019 19:44:47 +0000 (20:44 +0100)]
OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching

In the MemMapInitialization() function, we currently assign PciBase
different values, on both branches of the board type check. Hoist the
PciBase assignment from the i440fx branch in front of the "if". This is a
no-op for the i440fx branch. On the q35 branch, we overwrite this value,
hence the change is a no-op on q35 as well.

This is another refactoring for simplifying the rest of this series.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoOvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly
Laszlo Ersek [Tue, 22 Jan 2019 19:37:31 +0000 (20:37 +0100)]
OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly

In the MemMapInitialization() function, we currently have a common
PciSize assignment, shared between i440fx and q35. In order to simplify
the rest of this series, lift and duplicate the assignment identically to
both board-specific branches.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
6 months agoEmulatorPkg: Update DSC/FDF to use NetworkPkg's include fragment file.
Fu Siyuan [Thu, 16 May 2019 08:18:10 +0000 (16:18 +0800)]
EmulatorPkg: Update DSC/FDF to use NetworkPkg's include fragment file.

This patch updates the platform DSC/FDF files to use the include fragment
files provided by NetworkPkg.
The feature enabling flags in [Defines] section have been updated to use
the NetworkPkg's terms, and the value has been overridden with the original
default value on this platform.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Message-Id: <20190516081810.27840-5-shenglei.zhang@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1293
[lersek@redhat.com: add TianoCore Bugzilla reference]

6 months agoArmVirtPkg: Update DSC/FDF to use NetworkPkg's include fragment file.
Fu Siyuan [Thu, 16 May 2019 08:18:09 +0000 (16:18 +0800)]
ArmVirtPkg: Update DSC/FDF to use NetworkPkg's include fragment file.

This patch updates the platform DSC/FDF files to use the include fragment
files provided by NetworkPkg.
The feature enabling flags in [Defines] section have been updated to use
the NetworkPkg's terms, and the value has been overridden with the original
default value on this platform.

v2:Add check for NETWORK_SNP_ENABLE and NETWORK_TLS_ENABLE.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Julien Grall <julien.grall@linaro.org>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Message-Id: <20190516081810.27840-4-shenglei.zhang@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1293
[lersek@redhat.com: add TianoCore Bugzilla reference]
[lersek@redhat.com: undo spurious whitespace changes]
[lersek@redhat.com: clarify SNP and TLS rejection messages]
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
6 months agoNt32Pkg: Update DSC/FDF to use NetworkPkg's include fragment file.
Fu Siyuan [Thu, 16 May 2019 08:18:08 +0000 (16:18 +0800)]
Nt32Pkg: Update DSC/FDF to use NetworkPkg's include fragment file.

This patch updates the platform DSC/FDF files to use the include fragment
files provided by NetworkPkg.
The feature enabling flags in [Defines] section have be updated to use the
NetworkPkg's terms, and the value have been overridden with the original
default value on this platform.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Message-Id: <20190516081810.27840-3-shenglei.zhang@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1293
[lersek@redhat.com: add TianoCore Bugzilla reference]

6 months agoOvmfPkg: Update DSC/FDF to use NetworkPkg's include fragment file.
Fu Siyuan [Thu, 16 May 2019 08:18:07 +0000 (16:18 +0800)]
OvmfPkg: Update DSC/FDF to use NetworkPkg's include fragment file.

This patch updates the platform DSC/FDF files to use the include fragment
files provided by NetworkPkg.
The feature enabling flags in [Defines] section have been updated to use
the NetworkPkg's terms, and the value has been overridden with the original
default value on this platform.

v2:1.Make the comments before Network definition align other parts.
   2.Set NETWORK_ALLOW_HTTP_CONNECTIONS true.
   3.Remove TcpIoLib in lib classes section.
   4.Withdraw the removal of [PcdsFixedAtBuild.X64].

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien.grall@linaro.org>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Message-Id: <20190516081810.27840-2-shenglei.zhang@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1293
[lersek@redhat.com: add TianoCore Bugzilla reference]

6 months agoOvmfPkg/EnrollDefaultKeys: import the non-default key into db
Gary Lin [Thu, 16 May 2019 03:08:34 +0000 (11:08 +0800)]
OvmfPkg/EnrollDefaultKeys: import the non-default key into db

For QA test and development, we may need to test Secure Boot with a
devel key instead of UEFI CA.

This commit adds an argument, "--no-default", to EnrollDefaultKeys.efi.
With the argument, the key from SMBIOS Type 11 will also be enrolled
into db. Besides, the keys in AuthData.c, i.e. Microsoft KEK CA,
Microsoft PCA, and Microsoft UEFI CA will be excluded, so the developer
can easily create a varstore template for a specific key.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Gary Lin <glin@suse.com>
Message-Id: <20190516030834.12203-1-glin@suse.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6 months agoMdeModulePkg/Library: Remove BaseUefiTianoCustomDecompressLib
Dandan Bi [Fri, 10 May 2019 14:17:56 +0000 (22:17 +0800)]
MdeModulePkg/Library: Remove BaseUefiTianoCustomDecompressLib

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1722

Since we have merged this one into MdePkg,
remove it now.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>