mirror_edk2.git
4 years agoIntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 Pkgs
Satya Yarlagadda [Sat, 17 Sep 2016 03:24:49 +0000 (11:24 +0800)]
IntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 Pkgs

Changed the GenCfgOpt.py script to insert pragma pack(1) instead of
pragma pack (push, 1) in the upd header files generated during fsp build.
This is to align with rest of the EDKII pkgs pragma pack usage.

Also, this scripts generates UnusedUpdSpace for UPD address gaps.
Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[],
thus causing upd space waste to have Natural Alignment. Hence changed the
script to use UINT8[] for any unusedUpd fields above 1 byte.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoNetworkPkg: Correct the DNS token return status by RCODE
Jiaxin Wu [Wed, 14 Sep 2016 06:43:45 +0000 (14:43 +0800)]
NetworkPkg: Correct the DNS token return status by RCODE

When HostNameToIp() and GeneralLookUp() are called with a invalid
host name, RCODE (4 bit field is set as part of responses) error
will returned in packet to identify the domain name referenced in
the query does not exist. So, EFI_NOT_FOUND should be returned
directly.

Current implementation only check the RCODE in successful condition.
Need update the code for more error check according to RFC 1035 4.1.1
section.

Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
Reviewed-by: Sriram Subramanian <sriram-s@hpe.com>
4 years agoArmVirtPkg/HighMemDxe: move to FDT client protocol
Ard Biesheuvel [Thu, 15 Sep 2016 13:23:11 +0000 (14:23 +0100)]
ArmVirtPkg/HighMemDxe: move to FDT client protocol

Use the FDT client protocol rather than parsing the DT directly using
fdtlib. While we're at it, update the code so it deals correctly with
memory nodes that describe multiple disjoint regions in their "reg"
properties, and make the code work with #address-cells/#size-cells
properties of <1> as well as <2>.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoArmVirtPkg/FdtClientDxe: add methods to iterate over memory nodes
Ard Biesheuvel [Thu, 15 Sep 2016 12:33:23 +0000 (13:33 +0100)]
ArmVirtPkg/FdtClientDxe: add methods to iterate over memory nodes

Add high level methods to iterate over all 'reg' properties of all DT
nodes whose device_type properties have the value "memory". Since we are
modifying the FdtClient protocol, update the protocol and the only existing
implementation at the same time.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoArmVirtPkg/FdtClientDxe: report address and size cell count directly
Ard Biesheuvel [Thu, 15 Sep 2016 13:15:14 +0000 (14:15 +0100)]
ArmVirtPkg/FdtClientDxe: report address and size cell count directly

The FDT client protocol methods dealing with "reg" properties return
the size of a "reg" element. Currently, we have hardcoded this as '8',
since #address-cells == #size-cells == 2 in most cases. However, for
different values, have a single 'reg' element size is not unambiguous,
since - however unlikely - if #address-cells != #size-cells, we do not
know which is which.

So before adding more methods to the protocol, fix up this oversight.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoArmVirtPkg/FdtClientDxe: fix check for size of "reg" properties
Ard Biesheuvel [Thu, 15 Sep 2016 12:48:15 +0000 (13:48 +0100)]
ArmVirtPkg/FdtClientDxe: fix check for size of "reg" properties

Currently, the code in FdtClientDxe assumes #address-cells/#size-cells
values of <2>. Since DT "reg" properties always consist of <base, size>
tuples, this means the size of the entire property should always be a
multiple of 16 bytes (i.e, 4 * sizeof(UINT32), not 8. So fix this.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoBaseTools: Fix the bug to handle the read-only file
Yonghong Zhu [Wed, 14 Sep 2016 05:59:01 +0000 (13:59 +0800)]
BaseTools: Fix the bug to handle the read-only file

change the 'r+b' to 'rb' for some file's open, since these files we only
read it and no need to write. It can fix the bug that the file's attribute
had been set to read-only.

Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoIntelFrameworkPkg/FrameworkSpecConformance.txt: Update the URL
Yonghong Zhu [Wed, 14 Sep 2016 05:36:07 +0000 (13:36 +0800)]
IntelFrameworkPkg/FrameworkSpecConformance.txt: Update the URL

Update the URL since http://edk2.tianocore.org is not valid

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
4 years agoedksetup.sh: update the URL in edksetup.sh
Yonghong Zhu [Wed, 14 Sep 2016 05:27:06 +0000 (13:27 +0800)]
edksetup.sh: update the URL in edksetup.sh

Update the URL since http://edk2.tianocore.org is not valid

Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoArmPkg/DefaultExceptionHandlerLib: improve formatting of backtrace
Ard Biesheuvel [Fri, 9 Sep 2016 17:58:56 +0000 (18:58 +0100)]
ArmPkg/DefaultExceptionHandlerLib: improve formatting of backtrace

Implement the backtrace formattting suggested by Andrew, i.e.,

  IRQ Exception at 0x000000005BE182B0
  PC 0x00005BE182B0 (0x00005BE14000+0x000042B0) [ 0] ArmCpuDxe.dll
  PC 0x00005BE15770 (0x00005BE14000+0x00001770) [ 0] ArmCpuDxe.dll
  PC 0x00005EF08CC8 (0x00005EEEB000+0x0001DCC8) [ 1] DxeCore.dll
  PC 0x00005EF09008 (0x00005EEEB000+0x0001E008) [ 1] DxeCore.dll
  PC 0x00005EEF6ACC (0x00005EEEB000+0x0000BACC) [ 1] DxeCore.dll
  PC 0x00005EF0963C (0x00005EEEB000+0x0001E63C) [ 1] DxeCore.dll
  PC 0x00005EF09A38 (0x00005EEEB000+0x0001EA38) [ 1] DxeCore.dll
  PC 0x00005EF01560 (0x00005EEEB000+0x00016560) [ 1] DxeCore.dll
  PC 0x00005EF02FB4 (0x00005EEEB000+0x00017FB4) [ 1] DxeCore.dll
  PC 0x00005EF03098 (0x00005EEEB000+0x00018098) [ 1] DxeCore.dll
  PC 0x00005EF0460C (0x00005EEEB000+0x0001960C) [ 1] DxeCore.dll
  PC 0x00005EF005C4 (0x00005EEEB000+0x000155C4) [ 1] DxeCore.dll
  PC 0x00005EF00360 (0x00005EEEB000+0x00015360) [ 1] DxeCore.dll
  PC 0x00005EF003C8 (0x00005EEEB000+0x000153C8) [ 1] DxeCore.dll
  PC 0x00005EF128D0 (0x00005EEEB000+0x000278D0) [ 1] DxeCore.dll
  PC 0x00005EF12930 (0x00005EEEB000+0x00027930) [ 1] DxeCore.dll
  PC 0x00005EEEF594 (0x00005EEEB000+0x00004594) [ 1] DxeCore.dll
  PC 0x00005EF0CF18 (0x00005EEEB000+0x00021F18) [ 1] DxeCore.dll
  PC 0x00005EF1A310 (0x00005EEEB000+0x0002F310) [ 1] DxeCore.dll
  PC 0x00005EEF1808 (0x00005EEEB000+0x00006808) [ 1] DxeCore.dll
  PC 0x00005EEF1E48 (0x00005EEEB000+0x00006E48) [ 1] DxeCore.dll
  PC 0x00005EF0A838 (0x00005EEEB000+0x0001F838) [ 1] DxeCore.dll
  PC 0x00005EEED70C (0x00005EEEB000+0x0000270C) [ 1] DxeCore.dll
  PC 0x00005EEEC93C (0x00005EEEB000+0x0000193C) [ 1] DxeCore.dll
  PC 0x00005EEEC024 (0x00005EEEB000+0x00001024) [ 1] DxeCore.dll

  [ 0] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/ArmPkg/Drivers/CpuDxe/CpuDxe/DEBUG/ArmCpuDxe.dll
  [ 1] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/DxeCore.dll

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoVlv2TbltDevicePkg:Signal End of Dxe Event.
lushifex [Thu, 1 Sep 2016 05:02:55 +0000 (13:02 +0800)]
Vlv2TbltDevicePkg:Signal End of Dxe Event.

According to PI spec,DxeSmmReadyToLock protocol is published immediately after signaling of the End of Dxe Event.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex <shifeix.a.lu@intel.com>
4 years agoUefiCpuPkg/SecCore: Re-install SEC platform information(2) PPI
Jeff Fan [Fri, 9 Sep 2016 07:14:32 +0000 (15:14 +0800)]
UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPI

In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST
Data and re-install SEC platform information(2) PPI. Then other PEI drivers
could get CPU BIST data from the private GUIDed-HOB by new installed PPI.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()
Jeff Fan [Fri, 9 Sep 2016 07:08:56 +0000 (15:08 +0800)]
UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()

Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add
SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke
GetBistFromHob(). Add in/out for parameter in function header.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/SecCore: Add SecBist.c
Jeff Fan [Fri, 9 Sep 2016 07:00:30 +0000 (15:00 +0800)]
UefiCpuPkg/SecCore: Add SecBist.c

Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from
UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and
UefiCpuPkg.dsc accordinlgy to pass build.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST Data
Jeff Fan [Fri, 9 Sep 2016 06:36:39 +0000 (14:36 +0800)]
UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST Data

Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data
that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe
driver to get CPU BIST data.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/CpuMpPei: Fix BistData ouput error
Jeff Fan [Fri, 9 Sep 2016 06:17:57 +0000 (14:17 +0800)]
UefiCpuPkg/CpuMpPei: Fix BistData ouput error

ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x
only output the low 4 bytes and keep the high 4 bytes in stack that will be
output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to
UINT32 could make BistData output correctly.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/CpuMpPei: Add parameter BistInformationSize
Jeff Fan [Fri, 9 Sep 2016 06:08:33 +0000 (14:08 +0800)]
UefiCpuPkg/CpuMpPei: Add parameter BistInformationSize

Add one OPTIONAL parameter BistInformationSize for GetBistInfoFromPpi().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoUefiCpuPkg/CpuDxe: Fix duplicated status code report
Jeff Fan [Fri, 9 Sep 2016 05:39:50 +0000 (13:39 +0800)]
UefiCpuPkg/CpuDxe: Fix duplicated status code report

If CPU Bist data is not zero, we will report Status code. But there is one bug
that will report each processor's status code duplicated with NumberOfData
times. This fix is to exchange the loop order on NumberOfData and
mNumberOfProcessors. It could make sure the report status code only once for
each processor.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoMdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases
Ard Biesheuvel [Fri, 9 Sep 2016 12:55:34 +0000 (13:55 +0100)]
MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases

The new accelerated ARM and AARCH64 implementations take advantage of
features that are only available when the MMU and Dcache are on. So
restrict the use of this library to the DXE phase or later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoMdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines
Ard Biesheuvel [Fri, 2 Sep 2016 11:34:22 +0000 (12:34 +0100)]
MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines

This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoMdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines
Ard Biesheuvel [Tue, 6 Sep 2016 14:06:38 +0000 (15:06 +0100)]
MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines

This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.

All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoMdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits
Ard Biesheuvel [Fri, 2 Sep 2016 07:26:23 +0000 (08:26 +0100)]
MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits

Since the default BaseMemoryLib should be callable from any context,
including ones where unaligned accesses are not allowed, it implements
InternalCopyMem() and InternalSetMem() using byte accesses only.
However, especially in a context where the MMU is off, such narrow
accesses may be disproportionately costly, and so if the size and
alignment of the access allow it, use 32-bit or even 64-bit loads and
stores (the latter may be beneficial even on a 32-bit architectures like
ARM, which has load pair/store pair instructions)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoArmVirtPkg/FdtParser: avoid unaligned accesses with the MMU off
Ard Biesheuvel [Tue, 13 Sep 2016 14:13:31 +0000 (15:13 +0100)]
ArmVirtPkg/FdtParser: avoid unaligned accesses with the MMU off

When parsing the device tree to find the memory node, we are still running
with the MMU off, which means unaligned memory accesses are not allowed.
Since the FDT only mandates 32-bit alignment, 64-bit quantities are not
guaranteed to appear naturally aligned, and so should be accessed using
32-bit accesses instead.

Reported-by: Julien Grall <julien.grall@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoArmPkg/ArmMmuLib: base page table VA size on GCD memory map size
Ard Biesheuvel [Fri, 9 Sep 2016 08:01:56 +0000 (09:01 +0100)]
ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size

As reported by Eugene, the practice of sizing the address space in the
virtual memory system based on the maximum address in the table passed
to ArmConfigureMmu() is problematic, since it fails to take into account
the fact that the GCD memory space may be extended at a later time, both
for memory and for MMIO. So instead, choose the VA size identical to the
GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM
systems.

Reported-by: Eugene Cohen <eugene@hp.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmMmuLib: use a pool allocation for the root table
Ard Biesheuvel [Fri, 9 Sep 2016 08:50:21 +0000 (09:50 +0100)]
ArmPkg/ArmMmuLib: use a pool allocation for the root table

Currently, we allocate a full page for the root translation table, even
if the configured translation only requires two entries (16 bytes) for
the root level, which happens to be the case for a 40 bit VA. Likewise,
for a 36-bit VA space, the root table only needs 16 entries of 8 bytes
each, adding up to 128 bytes.

So switch to a pool allocation for the root table if we can, but take into
account that the architecture requires it to be naturally aligned to its
size, i.e., a 64 byte table requires 64 byte alignment, whereas pool
allocations in general are only guaranteed to be aligned to 8 bytes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmMmuLib: remove bogus alignment of page allocations
Ard Biesheuvel [Fri, 9 Sep 2016 10:19:18 +0000 (11:19 +0100)]
ArmPkg/ArmMmuLib: remove bogus alignment of page allocations

In commit 7d189f99d81c ("ArmPkg/Mmu: Fix bug of aligning new allocated
page table"), we fixed a flaw in the logic regarding alignment of newly
allocated translation table pages. However, we all failed to spot that
aligning page based allocations to page size is rather pointless to
begin with, so simply allocate a single page each time we add new pages
to the translation tables.

Also, drop the unnecessary cast.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()
Ard Biesheuvel [Fri, 9 Sep 2016 09:52:25 +0000 (10:52 +0100)]
ArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()

The relations between T0SZ, the number of translation levels and the
size/alignment of the root table can be expressed in simple arithmetic
expressions, so get rid of the lookup table.

Note that this disregards the fact that the maximum value of T0SZ is
39 not 42 (as one would expect for the smallest VA size using 2 levels)
but since this corresponds to a VA size of 32 MB and 4 MB, respectively,
neither of which are sufficient to run UEFI, we can safely ignore the
distinction.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoOvmfPkg: Fix typing errors in header files
Thomas Huth [Tue, 13 Sep 2016 08:33:20 +0000 (10:33 +0200)]
OvmfPkg: Fix typing errors in header files

Correct some typos in the header files of the OvmfPkg
(which have been discovered with the codespell utility).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoOvmfPkg: Fix typing errors
Thomas Huth [Fri, 9 Sep 2016 20:32:15 +0000 (22:32 +0200)]
OvmfPkg: Fix typing errors

Correct some typos (discovered with the codespell utility)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Thomas Huth <thuth@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
4 years agoOvmfPkg: convert C files with LF line terminators to CRLF
Laszlo Ersek [Fri, 9 Sep 2016 21:32:05 +0000 (23:32 +0200)]
OvmfPkg: convert C files with LF line terminators to CRLF

Run "unix2dos" on the affected files. "git show -b" produces no diff for
this patch.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Thomas Huth <thuth@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
4 years agoOvmfPkg/IndustryStandard: make "Xen/grant_table.h" pure ASCII
Laszlo Ersek [Fri, 9 Sep 2016 21:24:54 +0000 (23:24 +0200)]
OvmfPkg/IndustryStandard: make "Xen/grant_table.h" pure ASCII

The header file includes the UTF-8 encoding (0xE2 0x80 0x99) of the U+2019
(RIGHT SINGLE QUOTATION MARK) code point. Replace it with a simple
apostrophe (U+0027, ASCII 0x27).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Thomas Huth <thuth@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
4 years agoMdeModulePkg/HiiDB: Handle the "&READONLY" tag in <KeywordResp> correctly
Dandan Bi [Mon, 5 Sep 2016 06:55:49 +0000 (14:55 +0800)]
MdeModulePkg/HiiDB: Handle the "&READONLY" tag in <KeywordResp> correctly

This patch is to fix the incorrect logic when handling the "&READONLY" tag
in <KeywordResp>.
1. In UEFI spec, the "&READONLY" tag is in upper case, but using the lower
case in current codes by mistake.
2. The logic in checking the ReadOnly flag is not correct. Whether having
"&READONLY" tag must be consistent with the result of
"ExtractReadOnlyFromOpCode" function.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoMdeModulePkg/UiApp: Fix incorrect question id
Dandan Bi [Thu, 8 Sep 2016 07:04:51 +0000 (15:04 +0800)]
MdeModulePkg/UiApp: Fix incorrect question id

For a question, its question id can not be zero.
This patch is to fix the issue that using zero as question id.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
4 years agoNt32Pkg: Fix VS2010/VS2012 build failure
Dandan Bi [Tue, 6 Sep 2016 05:15:21 +0000 (13:15 +0800)]
Nt32Pkg: Fix VS2010/VS2012 build failure

Initialize the variable "OptionNumber".

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
4 years agoOptionRomPkg: .dsc fixes for ARM/AARCH64 and USB drivers
Leif Lindholm [Sun, 4 Sep 2016 13:16:19 +0000 (14:16 +0100)]
OptionRomPkg: .dsc fixes for ARM/AARCH64 and USB drivers

Drivers under OptionRomPkg wouldn't build standalone, since ARM and
AARCH64 were missing from SUPPORTED_ARCHITECTURES. So add them.
Also, add some compiler libraries needed for ARM/AARCH64 GCC
toolchains (CompilerIntrinsicsLib and BaseSwStackCheckLib).

Also, the UsbNetworking drivers were not listed under [Components],
so failed to build standalone. This patch adds them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
4 years agoArmPkg/ArmGicLib: use correct loop variable
Ard Biesheuvel [Wed, 7 Sep 2016 07:01:31 +0000 (08:01 +0100)]
ArmPkg/ArmGicLib: use correct loop variable

The ArmGicLib API function GicGetCpuRedistributorBase () declares
GicCpuRedistributorBase to iterate over the redistributors of all
CPUs, but then inadvertently advances GicRedistributorBase instead.

Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/DefaultExceptionHandlerLib: trim module name in backtrace output
Ard Biesheuvel [Fri, 9 Sep 2016 07:28:53 +0000 (08:28 +0100)]
ArmPkg/DefaultExceptionHandlerLib: trim module name in backtrace output

As reported by Vishal, the new backtrace output would be more useful if
it did not contain the full absolute path of each module in the list.
So strip off everything up to the last forward slash or backslash in the
string.

Example output:

  IRQ Exception at 0x000000005EF110E0
  DxeCore.dll loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF121F0) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF1289C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFB6B4) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFAA44) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFB450) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF938C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF8D04) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFA8E8) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF3C14) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF3E48) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF0C838) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEF70C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEE93C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEE024) loaded at 0x000000005EEED000

Suggested-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPlatformPkg/NorFlashDxe: use strictly aligned CopyMem()
Ard Biesheuvel [Wed, 7 Sep 2016 10:32:42 +0000 (11:32 +0100)]
ArmPlatformPkg/NorFlashDxe: use strictly aligned CopyMem()

The UEFI spec stipulates that unaligned accesses should be enabled
on CPUs that support them, which means all of them, given that we
no longer support pre-v7 ARM cores, and the AARCH64 bindings mandate
support for unaligned accesses unconditionally.

This means that one should not assume that CopyMem () is safe to call
on regions that may be mapped using device attributes, which is the
case for the NOR flash. Since we have no control over the mappings when
running under the OS, and given that write accesses require device
mappings, we should not call CopyMem () in the read path either, but
use our own implementation that is guaranteed to take alignment into
account.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoMdePkg/BaseLib AARCH64: terminate stack frame list on stack switch
Ard Biesheuvel [Fri, 9 Sep 2016 07:17:40 +0000 (08:17 +0100)]
MdePkg/BaseLib AARCH64: terminate stack frame list on stack switch

When switching to the DXE phase stack, set the frame pointer to zero so
that code walking the stack frame will not try to access stack frames
belonging to the old stack.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoBaseTools/EfiRom: supply missing machine type lookup strings
Laszlo Ersek [Thu, 8 Sep 2016 19:47:19 +0000 (21:47 +0200)]
BaseTools/EfiRom: supply missing machine type lookup strings

"EfiRom --dump" does not recognize the 0x8664 machine type:

>   EFI ROM header contents
>     EFI Signature          0x0EF1
>     Compression Type       0x0001 (compressed)
>     Machine type           0x8664 (unknown)
>     Subsystem              0x000B (EFI boot service driver)
>     EFI image offset       0x0050 (@0xF650)

Add lookup strings for the remaining EFI_IMAGE_MACHINE_* numeric macros
that can be found in
"BaseTools/Source/C/Include/IndustryStandard/PeImage.h". The strings
follow Table 12. "UEFI Image Types" from the UEFI v2.6 spec.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
4 years agoShellPkg/UefiHandleParsingLib: fix retval for empty child controller array
Laszlo Ersek [Thu, 8 Sep 2016 14:57:02 +0000 (16:57 +0200)]
ShellPkg/UefiHandleParsingLib: fix retval for empty child controller array

The ParseHandleDatabaseForChildControllers() function intends to work like
this:

(1) It allocates a "HandleBufferForReturn" local array that's guaranteed
    to be big enough for all found handles,

(2) it collects the handles, both counting them in the (mandatory)
    "MatchingHandleCount" output parameter, and saving them in the local
    "HandleBufferForReturn" array,

(3) if the caller is not interested in the actual handles, then
    "HandleBufferForReturn" is released,

(4) if the caller is interested in the handles, and we've found some, then
    "HandleBufferForReturn" is passed out through the
    "MatchingHandleBuffer" output parameter,

(5) if the caller is interested in the actual handles, but we've found
    none, then the "MatchingHandleBuffer" output parameter is set to NULL.

The ASSERT() at the end of the function makes this clear, but the
implementation does not conform to (5). Fix it.

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Tapan Shah <tapandshah@hpe.com>
Reported-by: Tapan Shah <tapandshah@hpe.com>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=112
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Tapan Shah <tapandshah@hpe.com>
4 years agoShellPkg/UefiHandleParsingLib: fix IN/OUT notation in child ctrlr parsing
Laszlo Ersek [Thu, 8 Sep 2016 15:10:47 +0000 (17:10 +0200)]
ShellPkg/UefiHandleParsingLib: fix IN/OUT notation in child ctrlr parsing

"MatchingHandleCount" is an output parameter of
ParseHandleDatabaseForChildControllers().

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Tapan Shah <tapandshah@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Tapan Shah <tapandshah@hpe.com>
4 years agoShellPkg: pci -i -_e to print next capability
Abdul Lateef Attar [Sat, 10 Sep 2016 06:31:35 +0000 (23:31 -0700)]
ShellPkg: pci -i -_e to print next capability

According to PCI spec the next AER capability is relative to
the beginning of PCI configuration space. Hence substract the
base offset to get the next capability.

"-_e" option is changed from TypeFlag to TypeValue, so that
user can specify individual AER capability to print.
e.g. pci 00 00 01 -i -_e <capability-id>

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
4 years agoArmPkg/ArmBaseLib: clean up directory structure
Ard Biesheuvel [Mon, 5 Sep 2016 14:12:01 +0000 (15:12 +0100)]
ArmPkg/ArmBaseLib: clean up directory structure

For historical reasons, the files under ArmLib are split up into 'common'
files under Common/, containing common C files as well as AArch64 and Arm
specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/,
respectively. This presumably dates back to the time when ArmLib supported
different revisions of the 32-bit architecture (i.e., pre-V7)

Since the PI spec requires V7 or later, we can simplify this to Arm/ and
AArch64, which aligns ArmLib with the majority of other modules that carry
ARM or AArch64 specific code.

So move the files around so that shared files live at the same level as
ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/,
respectively.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includes
Ard Biesheuvel [Mon, 5 Sep 2016 14:03:20 +0000 (15:03 +0100)]
ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includes

The ArmBaseLib timer code does not depend on MemoryAllocationLib at
all, so remove the #includes referring to it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoMaintainers.txt: Add Giri as IntelFsp2*Pkg, IntelSiliconPkg maintainer
Jiewen Yao [Wed, 7 Sep 2016 01:19:45 +0000 (09:19 +0800)]
Maintainers.txt: Add Giri as IntelFsp2*Pkg, IntelSiliconPkg maintainer

Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoArmPlatformPkg: remove EFI_MEMORY_UC attribute from normal memory
Ard Biesheuvel [Thu, 8 Sep 2016 08:05:45 +0000 (09:05 +0100)]
ArmPlatformPkg: remove EFI_MEMORY_UC attribute from normal memory

On ARM systems, mapping normal memory as device memory may have unintended
side effects, given that unaligned accesses or loads and stores with special
semantics (e.g., load/store exclusive) may fault or may not work as expected.
Similarly, DC ZVA instructions are only supported on normal memory, not
device memory.

So remove the EFI_MEMORY_UC attribute that we set by default on system RAM.
If any region requires this attribute, it is up to the driver to set this
attribute, and to ensure that no offending operations are performed on it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmVirtPkg: restrict mapping attributes of normal memory to EFI_MEMORY_WB
Ard Biesheuvel [Thu, 8 Sep 2016 07:40:09 +0000 (08:40 +0100)]
ArmVirtPkg: restrict mapping attributes of normal memory to EFI_MEMORY_WB

In general, on an ARM system, mapping normal memory as device memory may
have unintended side effects, given that unaligned accesses or loads and
stores with special semantics (e.g., load/store exclusive) may fault or
may not work as expected.

Under KVM, the situation is even worse, since the host may not expect the
guest to perform uncached accesses, and so writes to such an uncached
region may get lost completely.

Since the only safe mapping type under KVM is EFI_MEMORY_WB, remove all
other memory type attributes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoArmPkg/ArmLib: remove all ArmLib flavors except ArmBaseLib
Ard Biesheuvel [Mon, 5 Sep 2016 10:53:57 +0000 (11:53 +0100)]
ArmPkg/ArmLib: remove all ArmLib flavors except ArmBaseLib

This removes the following ArmLib implementation, which were, apart from
the fact that they targeted either ARM or AARCH64, fully identical:

  ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf

Only ArmBaseLib remains, which can fulfil the dependencies upon each of
the listed flavors.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmVirtPkg: replace all ArmLib resolutions with ArmBaseLib
Ard Biesheuvel [Mon, 5 Sep 2016 10:48:17 +0000 (11:48 +0100)]
ArmVirtPkg: replace all ArmLib resolutions with ArmBaseLib

The various ArmLib flavors are identical in practice, and a new
ArmBaseLib has been introduced that can replace all of them. So replace
all occurrences with ArmBaseLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoBeagleBoardPkg EmbeddedPkg Omap35xxPkg: move to ArmBaseLib
Ard Biesheuvel [Mon, 5 Sep 2016 10:49:37 +0000 (11:49 +0100)]
BeagleBoardPkg EmbeddedPkg Omap35xxPkg: move to ArmBaseLib

The various ArmLib flavors are identical in practice, and a new
ArmBaseLib has been introduced that can replace all of them. So replace
all occurrences with ArmBaseLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmLib: introduce ArmBaseLib
Ard Biesheuvel [Mon, 5 Sep 2016 10:25:18 +0000 (11:25 +0100)]
ArmPkg/ArmLib: introduce ArmBaseLib

Introduce a new ArmLib version ArmBaseLib, which encapsulates the ARM
version ArmV7Lib and the AArch64 version AArch64Lib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg/ArmLib: remove NullArmLib
Ard Biesheuvel [Mon, 5 Sep 2016 10:13:19 +0000 (11:13 +0100)]
ArmPkg/ArmLib: remove NullArmLib

Remove the NULL instance of ArmLib: it is not currently used, and its
usefulness its dubious.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-up
Dennis Chen [Mon, 5 Sep 2016 11:38:20 +0000 (19:38 +0800)]
ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-up

According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC
base address PCDs to 64-bit, and fix up all users.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
4 years agoOvmfPkg/QemuBootOrderLib: drop too strict "/HD(" suffix from vblk prefix
Laszlo Ersek [Wed, 7 Sep 2016 10:47:19 +0000 (12:47 +0200)]
OvmfPkg/QemuBootOrderLib: drop too strict "/HD(" suffix from vblk prefix

Translating QEMU's virtio-block OpenFirmware device path to a UEFI device
path prefix was one of the earliest case handled in QemuBootOrderLib. At
that time, I terminated the translation output (the UEFI devpath prefix)
with a "/HD(" suffix.

The intent was for the translation to prefix-match only boot options with
HD() device path nodes in them, that is, no auto-generated "device level"
boot options. This was motivated by prioritizing specific boot options
created by OS installers over auto-generated "device level" options.

However, practice has shown that:

- OS installers place their installed boot options first in the boot order
  anyway,

- other device types (SATA disks, virtio-scsi disks), where "/HD(" is not
  appended, work just fine,

- requiring "/HD(" actually causes problems: after the OS-installed
  specific boot option has been lost (or purposely removed), the
  auto-generated "device level" boot option does the right thing (see the
  Default Boot Behavior under
  <http://blog.uncooperative.org/blog/2014/02/06/the-efi-system-partition/>).
  The "/HD(" requirement causes such boot options to be dropped, which
  prevents "fallback.efi" from running.

Relax the matching by removing the "/HD(" suffix from the translated
prefix.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Fixes: e06a4cd134064590aa1a855ff4b973023279e805
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1373812
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
4 years agoBaseTools VfrCompile Pccts: Update GCC Flags to the specific one with BUILD_ prefix
Liming Gao [Thu, 1 Sep 2016 07:59:57 +0000 (15:59 +0800)]
BaseTools VfrCompile Pccts: Update GCC Flags to the specific one with BUILD_ prefix

This change is also applied to VfrCompile Pccts antlr and dlg tool.

In V2, add the missing C rules.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
4 years agoBaseTools VfrCompile GNU makefile: Replace CXX with BUILD_CXX
Liming Gao [Thu, 1 Sep 2016 07:47:04 +0000 (15:47 +0800)]
BaseTools VfrCompile GNU makefile: Replace CXX with BUILD_CXX

The change is missing in VfrComile GNUmakefile.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
4 years agoBaseTools GNU makefile: remove unused .S rule
Liming Gao [Wed, 31 Aug 2016 04:46:17 +0000 (12:46 +0800)]
BaseTools GNU makefile: remove unused .S rule

Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
4 years agoBaseTools GNU makefile: Add BUILD_CXXFLAGS to align make built-in rule
Liming Gao [Wed, 31 Aug 2016 04:44:50 +0000 (12:44 +0800)]
BaseTools GNU makefile: Add BUILD_CXXFLAGS to align make built-in rule

GNU make built-in rule to Compiling C++ programs with
ā€˜$(CXX) $(CPPFLAGS) $(CXXFLAGS) -cā€™.
To align to it, add empty BUILD_CXXFLAGS in cpp rule.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
4 years agoUefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:52:00 +0000 (18:52 +0800)]
UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:51:46 +0000 (18:51 +0800)]
UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:51:32 +0000 (18:51 +0800)]
UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:51:19 +0000 (18:51 +0800)]
UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:51:04 +0000 (18:51 +0800)]
UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:50:51 +0000 (18:50 +0800)]
UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:50:30 +0000 (18:50 +0800)]
UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:50:14 +0000 (18:50 +0800)]
UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:49:59 +0000 (18:49 +0800)]
UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:49:45 +0000 (18:49 +0800)]
UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:49:27 +0000 (18:49 +0800)]
UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:49:12 +0000 (18:49 +0800)]
UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:48:58 +0000 (18:48 +0800)]
UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:48:39 +0000 (18:48 +0800)]
UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:48:24 +0000 (18:48 +0800)]
UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:48:08 +0000 (18:48 +0800)]
UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:47:50 +0000 (18:47 +0800)]
UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:47:34 +0000 (18:47 +0800)]
UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 10:47:14 +0000 (18:47 +0800)]
UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoUefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
Jeff Fan [Tue, 6 Sep 2016 08:59:56 +0000 (16:59 +0800)]
UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
4 years agoArmPkg/DefaultExceptionHandlerLib AARCH64: add minimal backtrace to crash dump
Ard Biesheuvel [Wed, 7 Sep 2016 08:12:29 +0000 (09:12 +0100)]
ArmPkg/DefaultExceptionHandlerLib AARCH64: add minimal backtrace to crash dump

When dumping the CPU state after an unhandled fault, walk the stack
frames and decode the return addresses so we can show a minimal
backtrace. Unfortunately, we do not have sufficient information to
show the function names, but at least we can see the modules and the
return addresses inside the modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoBaseTools/tools_def AARCH64: enable frame pointers for DEBUG builds
Ard Biesheuvel [Wed, 7 Sep 2016 08:19:37 +0000 (09:19 +0100)]
BaseTools/tools_def AARCH64: enable frame pointers for DEBUG builds

Enable frame pointers on DEBUG builds so we can support backtraces in
crash dumps.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmPlatformPkg/PrePi: fix secondary stack base
Michael Zimmermann [Wed, 7 Sep 2016 12:16:18 +0000 (13:16 +0100)]
ArmPlatformPkg/PrePi: fix secondary stack base

this bug was introduced by:
d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
4 years agoVlv2TbltDevicePkg/dec: Correct wrong default value.
Jiewen Yao [Tue, 6 Sep 2016 08:21:15 +0000 (16:21 +0800)]
Vlv2TbltDevicePkg/dec: Correct wrong default value.

The default PcdPeiIchEhciControllerMemoryBaseAddress value 0xFD000000
conflict with the default TXE SECUMA MMIO address.
So we update to 0xFC000000 to avoid conflict.

Cc: David Wei <david.wei@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
4 years agoVlv2TbltDevicePkg/PlatformInitPei: Support USB init
Jiewen Yao [Tue, 6 Sep 2016 08:24:31 +0000 (16:24 +0800)]
Vlv2TbltDevicePkg/PlatformInitPei: Support USB init

In order to support recovery in PEI phase, a platform need initialize
USB controller. This logic is missing in current PchInitPeim.

We removed MultiPlatformInfoInit() because it is already done in
PlatformEarlyInitEntry().

We also initialize XhciMemBaseAddr to 0, or it is garbage value.

Cc: David Wei <david.wei@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
4 years agoNetworkPkg/DnsDxe: Handle CNAME type responded from the name server
Jiaxin Wu [Tue, 6 Sep 2016 03:23:38 +0000 (11:23 +0800)]
NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

v2:
* Code refine.
* For DnsCache, the minimum value of TTL is selected between CNAME and A/AAAA record.

According RFC 1034 - 3.6.2, if the query name is an alias, the name server
will include the CNAME record in the response and restart the query at the
domain name specified in the data field of the CNAME record. RFC also provides
one example server action when A query received:

Suppose a name server was processing a query with for USCISIC.ARPA, asking for
type A information, and had the following resource records:
USC-ISIC.ARPA IN CNAME C.ISI.EDU
C.ISI.EDU     IN A     10.0.0.52
Both of these RRs would be returned in the response to the type A query.

Currently, DnsDxe driver doesn't handle the CNAME type response, which will cause
any exception result. The driver need continue the packet parsing while CNAME type
record parsed. So, this patch is used to handle it correctly.

Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
4 years agoArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attribute
Ard Biesheuvel [Tue, 6 Sep 2016 14:25:03 +0000 (15:25 +0100)]
ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attribute

Clang does not like separate definitions for the __alias__ and the
__weak__ attributes, so merge the definitions into one.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
4 years agoArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 09:00:37 +0000 (10:00 +0100)]
ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA

Now that the PCI root bridge driver and various host controller drivers
have been fixed, remove the 4 GB limit on PCI DMA allocation for QEMU's
ECAM PCI host bridge.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
4 years agoMdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support it
Ard Biesheuvel [Mon, 5 Sep 2016 08:55:16 +0000 (09:55 +0100)]
MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support it

Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely
ignored by the PCI host bridge driver, which means that, on an implementation
that supports DMA above 4 GB, allocations above 4 GB may be provided to
devices that have not expressed support for it.

So in addition to checking 'RootBridge->DmaAbove4G' to establish whether the
root bridge itself supports DMA above 4 GB, we must also take into account
the operation type (EfiPciOperationBusMaster{Read|Write|CommonBuffer}64),
and the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, when mapping and
allocating DMA memory, respectively.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
4 years agoMdeModulePkg/XhciDxe: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 08:52:10 +0000 (09:52 +0100)]
MdeModulePkg/XhciDxe: enable 64-bit PCI DMA

PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoMdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 08:51:48 +0000 (09:51 +0100)]
MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA

PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoMdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 08:51:32 +0000 (09:51 +0100)]
MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA

PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoMdeModulePkg/EhciDxe: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 08:51:16 +0000 (09:51 +0100)]
MdeModulePkg/EhciDxe: enable 64-bit PCI DMA

PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoMdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
Ard Biesheuvel [Mon, 5 Sep 2016 08:49:44 +0000 (09:49 +0100)]
MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA

PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
4 years agoNetworkPkg/IpSecDxe: Generate SPI randomly and correct IKE_SPI_BASE value
Jiaxin Wu [Wed, 20 Jul 2016 02:53:31 +0000 (10:53 +0800)]
NetworkPkg/IpSecDxe: Generate SPI randomly and correct IKE_SPI_BASE value

This path made the following update:
* Generate SPI randomly.
* Correct IKE_SPI_BASE value according RFC 4302/4303.

Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
4 years agoMdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()
Jiaxin Wu [Thu, 18 Aug 2016 05:31:07 +0000 (13:31 +0800)]
MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()

The IP address should not be treated as classful one if DHCP options
contain a classless IP with its true subnet mask. Otherwise, DHCPv4
TransmitReceive() will failed. This real subnet mask will be parsed
and recorded in DhcpSb->Netmask. So, we need check it before get the
IP's corresponding subnet mask.

Cc: Santhapur Naveen <naveens@amiindia.co.in>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
4 years agoMdeModulePkg NvmExpressDxe: Set the non-blocking I/O feature support bit
Hao Wu [Tue, 30 Aug 2016 11:57:44 +0000 (19:57 +0800)]
MdeModulePkg NvmExpressDxe: Set the non-blocking I/O feature support bit

Since current codes in NvmExpressDxe already support the non-blocking I/O
feature for EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface, the relative bit
in the 'Attributes' field of EFI_NVM_EXPRESS_PASS_THRU_MODE should be set
to reflect this.

Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
4 years agoMdeModulePkg NvmExpressDxe: Fix 'Event' won't be signaled for Admin cmds
Hao Wu [Thu, 1 Sep 2016 02:17:43 +0000 (10:17 +0800)]
MdeModulePkg NvmExpressDxe: Fix 'Event' won't be signaled for Admin cmds

This commit fixes the issue that the caller event passed to
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() will not be signaled for
NVME Admin commands.

Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
4 years agoMdeModulePkg NvmExpressDxe: Add NamespaceId validity check in PassThru
Hao Wu [Tue, 30 Aug 2016 08:34:09 +0000 (16:34 +0800)]
MdeModulePkg NvmExpressDxe: Add NamespaceId validity check in PassThru

According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru()
should return EFI_INVALID_PARAMETER if the input 'NamespaceId' is invalid
for the NVM Express controller. This commit adds check in PassThru() to
follow this rule.

Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
4 years agoMdeModulePkg NvmExpressDxe: Add check for command packet in PassThru
Hao Wu [Mon, 29 Aug 2016 02:12:42 +0000 (10:12 +0800)]
MdeModulePkg NvmExpressDxe: Add check for command packet in PassThru

This commit adds serveral checks for the 'Packet' parameter passed to the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() API:

The check for the 'TransferLength' field in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value will not
exceed the maximum data transfer size allowed by a controller.

The check for the 'TransferBuffer' and 'TransferLength' fields in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET when the Opcode of an NVME
command indicates a data transfer between controller and host.

The check for the 'MetadataLength' field in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value is not 0
when the corresponding 'MetadataBuffer' field has a non-NULL value.

Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
4 years agoMdeModulePkg NvmExpressDxe: Add check on the attributes of NVME controller
Hao Wu [Mon, 22 Aug 2016 06:11:23 +0000 (14:11 +0800)]
MdeModulePkg NvmExpressDxe: Add check on the attributes of NVME controller

According to UEFI spec, an EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL with neither
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set in the Attributes field
is an illegal configuration.

This commit adds this check in the PassThru API to follow the spec.

Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>