mirror_edk2.git
5 years agoVlv2TbltDevicePkg: Add /m flag for multi-processor build
Michael Kinney [Tue, 29 Nov 2016 20:01:44 +0000 (12:01 -0800)]
Vlv2TbltDevicePkg: Add /m flag for multi-processor build

https://bugzilla.tianocore.org/show_bug.cgi?id=274

Add support for multi-processor builds using a /m flag.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Add /y flag to generate report files
Michael Kinney [Tue, 29 Nov 2016 19:28:07 +0000 (11:28 -0800)]
Vlv2TbltDevicePkg: Add /y flag to generate report files

https://bugzilla.tianocore.org/show_bug.cgi?id=273

Update build script to generate a report file and put
both the report file and the log file in the directory
Vlv2TbltDevicePkg with an EDK2_Vlv2TbltDevicePkg prefix.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Fix typo in name of nul output file
Michael Kinney [Tue, 29 Nov 2016 19:19:20 +0000 (11:19 -0800)]
Vlv2TbltDevicePkg: Fix typo in name of nul output file

https://bugzilla.tianocore.org/show_bug.cgi?id=272

Fix typo in script file.  To prevent output from being
shown, then output file should be 'nul', not 'null'.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Use 4K aligned PE/COFF sections
Michael Kinney [Tue, 29 Nov 2016 18:33:36 +0000 (10:33 -0800)]
Vlv2TbltDevicePkg: Use 4K aligned PE/COFF sections

Update [BuildOptions] to use of 4K aligned PE/COFF
image sections to support page level protection of
DXE_RUNTIME_DRIVER, SMM_CORE, and DXE_SMM_DRIVER
modules.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoArmPkg/ArmDmaLib: add support for fixed host-to-device DMA offset
Ard Biesheuvel [Sat, 12 Nov 2016 13:02:28 +0000 (14:02 +0100)]
ArmPkg/ArmDmaLib: add support for fixed host-to-device DMA offset

Some devices, such as the Raspberry Pi3, have a fixed offset between memory
addresses as seen by the host and as seen by the other bus masters. So add
a new PCD that allows this fixed offset to be recorded, and to be used when
returning device addresses from the DmaLib mapping routines.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
5 years agoArmPkg/ArmDmaLib: clean up abuse of device address
Ard Biesheuvel [Sat, 12 Nov 2016 13:02:27 +0000 (14:02 +0100)]
ArmPkg/ArmDmaLib: clean up abuse of device address

In preparation of adding support to ArmDmalib for DMA bus masters whose
view of memory is offset by a constant compared to the CPU's view, clean
up some abuse of the device address.

The device address is not defined in terms of the CPU's address space,
and so it should not be used in CopyMem () or cache maintenance operations
that require a valid mapping. This not only applies to the above use case,
but also to the DebugUncachedMemoryAllocationLib that unmaps the
primary, cached mapping of an allocation, and returns a host address
which is an uncached alias offset by a constant.

Since we should never access the device address from the CPU, there is
no need to record it in the MAPINFO struct. Instead, record the buffer
address in case of double buffering, since we do need to copy the contents
(in case of a bus master write) and free the buffer (in all cases) when
DmaUnmap() is called.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
5 years agoArmPkg/ArmDmaLib: fix incorrect device address of double buffer
Ard Biesheuvel [Sat, 12 Nov 2016 13:02:26 +0000 (14:02 +0100)]
ArmPkg/ArmDmaLib: fix incorrect device address of double buffer

If double buffering is not required in DmaMap(), the returned device
address is passed through ConvertToPhysicalAddress () to convert the
host address (which in case of DebugUncachedMemoryAllocationLib is not
1:1 mapped) to a physical address, which is what a device would expect
to be able to perform DMA.

By the same reasoning, a double buffer allocated using DmaAllocateBuffer ()
should be converted in the same way, considering that the buffer is allocated
using UncachedAllocatePages (), to which the above equally applies.

So add the missing ConvertToPhysicalAddress () invocation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
5 years agoArmPkg/ArmDmaLib: use DMA buffer alignment from CPU arch protocol
Ard Biesheuvel [Sat, 12 Nov 2016 13:02:25 +0000 (14:02 +0100)]
ArmPkg/ArmDmaLib: use DMA buffer alignment from CPU arch protocol

Instead of depending on ArmLib to retrieve the CWG directly, use
the DMA buffer alignment exposed by the CPU arch protocol. This
removes our dependency on ArmLib, which makes the library a bit
more architecture independent.

While we're in there, rename gCpu to mCpu to better reflect its
local scope, and reflow some lines that we're modifying anyway.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
5 years agoArmPkg/ArmMmuLib: support page tables in cacheable memory only
Ard Biesheuvel [Sun, 20 Nov 2016 17:12:50 +0000 (17:12 +0000)]
ArmPkg/ArmMmuLib: support page tables in cacheable memory only

Translation table walks are always cache coherent on ARMv8-A, so cache
maintenance on page tables is never needed. Since there is a risk of
loss of coherency when using mismatched attributes, and given that memory
is mapped cacheable except for extraordinary cases (such as non-coherent
DMA), restrict the page table walker to performing cacheable accesses to
the translation tables.

For DEBUG builds, retain some of the logic so that we can double check
that the memory holding the root translation table is indeed located in
memory that is mapped cacheable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
5 years agoUefiCpuPkg/MicrocodeUpdate: Fix GetImage API
Jiewen Yao [Tue, 29 Nov 2016 07:54:57 +0000 (15:54 +0800)]
UefiCpuPkg/MicrocodeUpdate: Fix GetImage API

Current GetImage API forgets to return data to caller.

Add code to fix it.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoUefiCpuPkg/PiSmmCpu: relax superpage protection on page split.
Jiewen Yao [Mon, 28 Nov 2016 13:45:40 +0000 (21:45 +0800)]
UefiCpuPkg/PiSmmCpu: relax superpage protection on page split.

PiSmmCpu driver may split page for page attribute request.
Current logic not only propagates the super page attribute to
the leaf page attribut, but also to the directory page attribute.

However, the later might be wrong because we cannot clear protection
without touching directory page attribute.
The effective protection is the strictest combination
across the levels.

We should always clear protection on directory page and set
protection on leaf page for easy clearing later.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoSignedCapsulePkg: GetImage() return EFI_UNSUPPORTED.
Jiewen Yao [Tue, 29 Nov 2016 04:55:03 +0000 (12:55 +0800)]
SignedCapsulePkg: GetImage() return EFI_UNSUPPORTED.

According to UEFI spec, unsupported function should return EFI_UNSUPPORTED
directly.

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
5 years agoIntelFsp2Pkg: Add PACKAGES_PATH support
Thomaiyar, Richard Marian [Fri, 25 Nov 2016 09:21:06 +0000 (17:21 +0800)]
IntelFsp2Pkg: Add PACKAGES_PATH support

Add PACKAGES_PATH support in GenCfgOpt.py

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
5 years agoSourceLevelDebugPkg: Avoid to re-init IDT table again at SMI entry
Jeff Fan [Tue, 29 Nov 2016 06:51:18 +0000 (14:51 +0800)]
SourceLevelDebugPkg: Avoid to re-init IDT table again at SMI entry

Current SmmDebugAgentLib will initialize IDT table to support source debugging
at each time SMI entry on SMM BSP. Actually, we only need to initialize IDT
table at first time SMI entry.

Add one flag to avoid re-initializing IDT table.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
5 years agoMdeModulePkg/SdMmcPciHcDxe: Replace deprecated debug level macros
Feng Tian [Wed, 30 Nov 2016 05:45:17 +0000 (13:45 +0800)]
MdeModulePkg/SdMmcPciHcDxe: Replace deprecated debug level macros

EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced
with currently recommended values.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
5 years agoBaseTools: fix the bug to add PaletteSize info into AutoGen
Yonghong Zhu [Tue, 29 Nov 2016 02:09:17 +0000 (10:09 +0800)]
BaseTools: fix the bug to add PaletteSize info into AutoGen

Fix the bug to add PaletteSize info into AutoGen.c when the flag
UEFI_HII_RESOURCE_SECTION is set to FALSE.

Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoBaseTools CommonLib: Update ReadMemoryFileLine() to read line in file scope
Liming Gao [Fri, 25 Nov 2016 06:57:31 +0000 (14:57 +0800)]
BaseTools CommonLib: Update ReadMemoryFileLine() to read line in file scope

https://bugzilla.tianocore.org/show_bug.cgi?id=255

Check CurrentFilePointer to make sure it not exceed the end of file.

Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
5 years agoVlv2TbltDevicePkg: Fix IA32 boot timeouts
Michael Kinney [Tue, 29 Nov 2016 09:15:28 +0000 (01:15 -0800)]
Vlv2TbltDevicePkg: Fix IA32 boot timeouts

https://bugzilla.tianocore.org/show_bug.cgi?id=264

The IA32 build gets timeouts booting to the UEFI Shell.
Update the IA32 DSC file to match the X64 DSC file
disabling the fTPM feature.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg/PlatformFlashAccessLib: Fix IA32 build issues
Michael Kinney [Tue, 29 Nov 2016 09:13:21 +0000 (01:13 -0800)]
Vlv2TbltDevicePkg/PlatformFlashAccessLib: Fix IA32 build issues

https://bugzilla.tianocore.org/show_bug.cgi?id=263

Fix IA32 build issues in the PlatformFlashAccessLib.  Some of the
UINT64 FLASH addresses values need to be typecast to UINTN.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Remove SMM binary modules from FDF
Michael Kinney [Tue, 29 Nov 2016 09:11:43 +0000 (01:11 -0800)]
Vlv2TbltDevicePkg: Remove SMM binary modules from FDF

https://bugzilla.tianocore.org/show_bug.cgi?id=261
https://bugzilla.tianocore.org/show_bug.cgi?id=262

Remove the PowerManagement2 binary SMM module that generates an
ASSERT() and the DigitalThermalSensor binary SMM module that
causes an AP to be stuck in the busy state.

This is a workaround until these two SMM binary modules can be
updated.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg/PlatformInitPei: Workaround unaligned SMRAM size
Michael Kinney [Tue, 29 Nov 2016 09:05:05 +0000 (01:05 -0800)]
Vlv2TbltDevicePkg/PlatformInitPei: Workaround unaligned SMRAM size

https://bugzilla.tianocore.org/show_bug.cgi?id=260

The PiSmmCPuDxeSmm module requires the SMRR base address and length
to be aligned.  The memory initialization for Vlv2TbltDevicePkg
produces an SMRAM base address that is on a 16MB boundary and an
SMRAM length of 12MB.  The SMRAM length is rounded up to 16MB.

This is a workaround until the binary module that produces the
gEfiSmmPeiSmramMemoryReserveGuid HOB is updated

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Set CAPSULE_ENABLE to TRUE
Michael Kinney [Tue, 29 Nov 2016 08:54:31 +0000 (00:54 -0800)]
Vlv2TbltDevicePkg: Set CAPSULE_ENABLE to TRUE

https://bugzilla.tianocore.org/show_bug.cgi?id=259

Set CAPSULE_ENABLE to TRUE so the standard Vlv2TbltDevicePkg
platform builds can complete.  Build_IFWI.bat assumes this
flag is TRUE.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoVlv2TbltDevicePkg: Allow BaseTools to run from sources
Michael Kinney [Tue, 29 Nov 2016 08:51:26 +0000 (00:51 -0800)]
Vlv2TbltDevicePkg: Allow BaseTools to run from sources

https://bugzilla.tianocore.org/show_bug.cgi?id=258

Update bld_vlv.bat to run BaseTools build command with a call
statement to support running the build command from python
sources.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: David Wei <david.wei@intel.com>
Cc: Mang Guo <mang.guo@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoBaseTools: Fix bug for decimal value of VPDPCD offset display in report
Yonghong Zhu [Thu, 24 Nov 2016 15:19:57 +0000 (23:19 +0800)]
BaseTools: Fix bug for decimal value of VPDPCD offset display in report

current if we set VPD PCD's offset to a decimal value, eg: 22, this
value is displayed incorrectly in the "FD VPD Region" section in the
report.txt.

Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoOvmfPkg/PlatformPei: take VCPU count from QEMU and configure MpInitLib
Laszlo Ersek [Thu, 24 Nov 2016 14:18:44 +0000 (15:18 +0100)]
OvmfPkg/PlatformPei: take VCPU count from QEMU and configure MpInitLib

These settings will allow CpuMpPei and CpuDxe to wait for the initial AP
check-ins exactly as long as necessary.

It is safe to set PcdCpuMaxLogicalProcessorNumber and
PcdCpuApInitTimeOutInMicroSeconds in OvmfPkg/PlatformPei.
OvmfPkg/PlatformPei installs the permanent PEI RAM, producing
gEfiPeiMemoryDiscoveredPpiGuid, and UefiCpuPkg/CpuMpPei has a depex on
gEfiPeiMemoryDiscoveredPpiGuid.

It is safe to read the fw_cfg item QemuFwCfgItemSmpCpuCount (0x0005). It
was added to QEMU in 2008 as key FW_CFG_NB_CPUS, in commit 905fdcb5264c
("Add common keys to firmware configuration"). Even if the key is
unavailable (or if fw_cfg is entirely unavailable, for example on Xen),
QemuFwCfgRead16() will return 0, and then we stick with the current
behavior.

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoUefiCpuPkg/MpInitLib: wait no longer than necessary for initial AP startup
Laszlo Ersek [Thu, 24 Nov 2016 11:19:54 +0000 (12:19 +0100)]
UefiCpuPkg/MpInitLib: wait no longer than necessary for initial AP startup

Sometimes a platform knows exactly how many CPUs it has at boot. It should
be able to
- set PcdCpuMaxLogicalProcessorNumber dynamically to this number,
- set PcdCpuApInitTimeOutInMicroSeconds to a very long time (for example
  MAX_UINT32, approx. 71 minutes),
- and expect that MpInitLib wait exactly as long as necessary for all APs
  to report in.

Other platforms should be able to continue setting a reasonably large
upper bound on supported CPUs, and waiting for a reasonable, fixed amount
of time for all APs to report in.

Add this functionality. The TimedWaitForApFinish() function will return
when all APs have reported in, or the timeout has expired -- whichever
happens first.

(Accessing these PCDs dynamically is safe. The PEI and DXE phase instances
of this library are restricted to PEIM and DXE_DRIVER client modules, thus
the PCD accesses cannot be linked into runtime code.)

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=116
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoMdeModulePkg/EbcDxe: add EBC Debugger configuration application
Pete Batard [Thu, 24 Nov 2016 17:00:18 +0000 (01:00 +0800)]
MdeModulePkg/EbcDxe: add EBC Debugger configuration application

* Introduce a generic Debugger Configuration protocol.
* Add private configuration data in the EBC Debugger and make it
  register the Debugger Configuration protocol on initialization.
* Add a shell application that uses the protocol above to access
  the private data in order to configure the EBC debugger.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Pete Batard <pete@akeo.ie>
reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

5 years agoMdeModulePkg PeiCore: Make SetPeiServicesTablePointer() early in EntryPoint
Liming Gao [Wed, 23 Nov 2016 04:51:29 +0000 (12:51 +0800)]
MdeModulePkg PeiCore: Make SetPeiServicesTablePointer() early in EntryPoint

Make SetPeiServicesTablePointer() earlier than ProcessLibraryConstructorList()
so the constructor() function can get the correct pei service table pointer.

https://bugzilla.tianocore.org/show_bug.cgi?id=238

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
5 years agoMdeModulePkg: Fix GCC build failure
Dandan Bi [Fri, 25 Nov 2016 01:00:39 +0000 (09:00 +0800)]
MdeModulePkg: Fix GCC build failure

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen.yao@intel.com
5 years agoUefiCpuPkg/PiSmmCpuDxeSmm: handle dynamic PcdCpuMaxLogicalProcessorNumber
Laszlo Ersek [Thu, 24 Nov 2016 19:49:43 +0000 (20:49 +0100)]
UefiCpuPkg/PiSmmCpuDxeSmm: handle dynamic PcdCpuMaxLogicalProcessorNumber

"UefiCpuPkg/UefiCpuPkg.dec" already allows platforms to make
PcdCpuMaxLogicalProcessorNumber dynamic, however PiSmmCpuDxeSmm does not
take this into account everywhere. As soon as a platform turns the PCD
into a dynamic one, at least S3 fails. When the PCD is dynamic, all
PcdGet() calls translate into PCD DXE protocol calls, which are only
permitted at boot time, not at runtime or during S3 resume.

We already have a variable called mMaxNumberOfCpus; it is initialized in
the entry point function like this:

> //
> // If support CPU hot plug, we need to allocate resources for possibly
> // hot-added processors
> //
> if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
>   mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
> } else {
>   mMaxNumberOfCpus = mNumberOfCpus;
> }

There's another use of the PCD a bit higher up, also in the entry point
function:

> //
> // Use MP Services Protocol to retrieve the number of processors and
> // number of enabled processors
> //
> Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus,
>                        &NumberOfEnabledProcessors);
> ASSERT_EFI_ERROR (Status);
> ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));

Preserve these calls in the entry point function, and replace all other
uses of PcdCpuMaxLogicalProcessorNumber -- there are only reads -- with
mMaxNumberOfCpus.

For PcdCpuHotPlugSupport==TRUE, this is an unobservable change.

For PcdCpuHotPlugSupport==FALSE, we even save SMRAM, because we no longer
allocate resources needlessly for CPUs that can never appear in the
system.

PcdCpuMaxLogicalProcessorNumber is also retrieved in
"UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c",  but only in
the library instance constructor, which runs even before the entry point
function is called.

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=116
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoSecurityPkg Tcg2ConfigDxe: Align Attempt TPM Device help with options
Star Zeng [Fri, 25 Nov 2016 02:38:02 +0000 (10:38 +0800)]
SecurityPkg Tcg2ConfigDxe: Align Attempt TPM Device help with options

Current options only have TPM 1.2 and TPM 2.0,
but help shows Disable, TPM1.2, or TPM2.0,
they are mismatched.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg Tcg2ConfigDxe: Remove BlockSID actions and related strings
Star Zeng [Wed, 23 Nov 2016 07:28:38 +0000 (15:28 +0800)]
SecurityPkg Tcg2ConfigDxe: Remove BlockSID actions and related strings

Tcg2ConfigDxe has no related code to handle BlockSID related actions
that have been covered by OpalPasswordDxe driver.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg OpalPasswordDxe: Use PP actions to enable BlockSID
Eric Dong [Thu, 2 Jun 2016 07:20:17 +0000 (15:20 +0800)]
SecurityPkg OpalPasswordDxe: Use PP actions to enable BlockSID

Update the implementation to use PP BlockSID related actions.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg Tcg2PPLib: Support BlockSID related actions
Star Zeng [Wed, 23 Nov 2016 08:38:33 +0000 (16:38 +0800)]
SecurityPkg Tcg2PPLib: Support BlockSID related actions

Then Tcg2PhysicalPresenceLib can support TCG2 PP TPM2,
storage management and vendor specific requests according
to Physical Presence Interface Specification.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
5 years agoMdePkg IndustryStandard: Add DDR3, DDR4 and LPDDR definition per SPD spec
Liming Gao [Wed, 23 Nov 2016 07:03:08 +0000 (15:03 +0800)]
MdePkg IndustryStandard: Add DDR3, DDR4 and LPDDR definition per SPD spec

https://bugzilla.tianocore.org/show_bug.cgi?id=201

In V3, Use Odt to replace ODT, Cke to replace CKE, Id to replace ID,
and Cl to replace CL in structure field name.

In V2, separate DDR3, DDR4 and LPDDR definition into the different files;
use the different SPD prefix as structure definitions for each SPD type.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
5 years agoMdeModulePkg/NetLib: Handle an invalid IPv6 address case
Jiaxin Wu [Fri, 25 Nov 2016 06:14:23 +0000 (14:14 +0800)]
MdeModulePkg/NetLib: Handle an invalid IPv6 address case

Handle an invalid IPv6 address in NetLibAsciiStrToIp6(),
like '2000:aaaa::1com'.

Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Zhang Lubo <lubo.zhang@intel.com>
5 years agoUefiCpuPkg/DxeMpLib: Remove unnecessary ret instruction
Jeff Fan [Fri, 25 Nov 2016 05:21:20 +0000 (13:21 +0800)]
UefiCpuPkg/DxeMpLib: Remove unnecessary ret instruction

Reported-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoUefiCpuPkg/DxeMpLib: Fix bug when getting target C-State from eax
Jeff Fan [Fri, 25 Nov 2016 04:58:36 +0000 (12:58 +0800)]
UefiCpuPkg/DxeMpLib: Fix bug when getting target C-State from eax

AP will get target C-State from eax[7:4]. We do shift in ebx firstly before set
to eax. It will lead ebx is incorrect in the next time.

The fix is to set ebx to eax firstly and does shift in eax. Thus, ebx could keep
original value.

Reported-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoUefiCpuPkg/DxeMpLib: Make sure APs in safe loop code
Jeff Fan [Fri, 25 Nov 2016 05:18:57 +0000 (13:18 +0800)]
UefiCpuPkg/DxeMpLib: Make sure APs in safe loop code

Add one semaphore to make sure BSP to wait till all APs run in AP safe loop
code.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoUefiCpuPkg/DxeMpLib: Allocate new safe stack < 4GB
Jeff Fan [Wed, 23 Nov 2016 13:52:24 +0000 (21:52 +0800)]
UefiCpuPkg/DxeMpLib: Allocate new safe stack < 4GB

For long mode DXE, we will disable paging on AP to protected mode to execute AP
safe loop code in reserved memory range under 4GB. But we forget to allocate
stack for AP under 4GB and AP still are using original AP stack. If original AP
stack is larger than 4GB, it cannot be used after AP is transferred to protected
mode. Besides MwaitSupport == TRUE, AP stack is still required during phase of
disabling paging in long mode DXE.

Moreover, even though AP stack is always under 4GB (a) in Ia32 DXE and (b) with
this patch, after transferring to protected mode from X64 DXE, AP stack
(in BootServiceData) maybe crashed by OS after Exit Boot Service event.

This fix is to allocate reserved memory range under 4GB together with AP safe
loop code. APs will switch to new stack in safe loop code.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoUefiCpuPkg/DxeMpLib: Get safe AP loop handler from global variable
Jeff Fan [Wed, 23 Nov 2016 13:33:20 +0000 (21:33 +0800)]
UefiCpuPkg/DxeMpLib: Get safe AP loop handler from global variable

AP loop function is already saved into global variable, needn't to get it from
AP function parameter.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoArmPlatformPkg: Fix VE RTSM mem map descriptor count
Sami Mujawar [Thu, 24 Nov 2016 19:56:12 +0000 (19:56 +0000)]
ArmPlatformPkg: Fix VE RTSM mem map descriptor count

The number of memory map entries used exceeded the allocated count,
thereby causing memory corruption.

Fixed the number of Virtual Memory Map Descriptors allocated in
describing the RTSM Memory Map. Also added an assert to confirm
that the descriptor count has not been exceeded, in the hope that it may
help highlight the problem should a new entry be added.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoArmPlatformPkg: Reformat VE Memory Map code
Evan Lloyd [Thu, 24 Nov 2016 19:56:11 +0000 (19:56 +0000)]
ArmPlatformPkg: Reformat VE Memory Map code

This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
    Some indentation is adjusted.
    Overlength lines are re-flowed.
    alignment on = is adjusted as some lines exceeded 80 columns.
    if statement converted to conditional assignment.
    Redundant re-calculation of CacheAttributes removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoArmPkg: remove the LinuxLoader application
Ard Biesheuvel [Mon, 21 Nov 2016 12:21:38 +0000 (12:21 +0000)]
ArmPkg: remove the LinuxLoader application

The LinuxLoader application boots Linux in a way that prevents the OS
from accessing UEFI runtime services. Since we have better ways now
of invoking the kernel (via GRUB, or directly via the kernel's UEFI
stub), remove the obsolete LinuxLoader so that people will no longer
mistake it for a suitable reference of how to invoke the OS from UEFI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
5 years agoBeagleBoardPkg/BeagleBoardPkg.dsc: remove the LinuxLoader application
Ard Biesheuvel [Mon, 21 Nov 2016 12:19:54 +0000 (12:19 +0000)]
BeagleBoardPkg/BeagleBoardPkg.dsc: remove the LinuxLoader application

The LinuxLoader should no longer be used now that both the ARM and arm64
kernels as well as GRUB have full support for acting as an OS loader in
the UEFI spec sense. So remove it from the Beagle build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
5 years agoEmbeddedPkg/AndroidFastboot: drop dependency on the LinuxLoader
Ard Biesheuvel [Mon, 21 Nov 2016 12:13:18 +0000 (12:13 +0000)]
EmbeddedPkg/AndroidFastboot: drop dependency on the LinuxLoader

When booting the kernel via Fastboot, invoke the kernel image directly
rather than passing it to the LinuxLoader app. This requires the kernel
image to be built with UEFI stub support.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
5 years agoMdeModulePkg/EbcDebugger: Compare ASCII char with '\0'
Hao Wu [Thu, 24 Nov 2016 02:49:46 +0000 (10:49 +0800)]
MdeModulePkg/EbcDebugger: Compare ASCII char with '\0'

Current code is using L'\0' to compare with a ASCII char.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDebugger: Add ASSERT to ensure FieldBuffer is not NULL
Hao Wu [Thu, 24 Nov 2016 02:43:33 +0000 (10:43 +0800)]
MdeModulePkg/EbcDebugger: Add ASSERT to ensure FieldBuffer is not NULL

In function EdbLoadCodBySymbolByIec(), AsciiStrGetNewTokenField() at line
1589 will return NULL if the first character in 'LineBuffer' is '\0'. But
the previous if statement at line 1576 ensures the above case will not
happen.

This commit adds ASSERT as warnings for the case that will not happen.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDebugger: Add missing check for symbol not found
Hao Wu [Thu, 24 Nov 2016 02:37:55 +0000 (10:37 +0800)]
MdeModulePkg/EbcDebugger: Add missing check for symbol not found

In function DebuggerDisplaySymbolAccrodingToAddress(), when variable
'CandidateAddress' (returned by EbdFindSymbolAddress function) equals
(UINTN) -1, it also indicates that the symbol is not found at the given
address.

This commit adds this missing check.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDebugger: Add check for invalid 'CommandArg'
Hao Wu [Thu, 24 Nov 2016 02:26:06 +0000 (10:26 +0800)]
MdeModulePkg/EbcDebugger: Add check for invalid 'CommandArg'

Add checks for the return value of function Atoi() in EdbCmdBreakpoint.c.
If the input parameter 'CommandArg' contains non-digit character, print
corresponding error message.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDebugger: Operands of same size for bitwise operation
Hao Wu [Thu, 24 Nov 2016 02:18:19 +0000 (10:18 +0800)]
MdeModulePkg/EbcDebugger: Operands of same size for bitwise operation

Operands in a bitwise operation should have the same size to eliminate
unexpected results.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/DriverSample: Remove the password related codes
Dandan Bi [Thu, 17 Nov 2016 05:15:33 +0000 (13:15 +0800)]
MdeModulePkg/DriverSample: Remove the password related codes

In current DriverSampleDxe, the sample code of password is
not a good example, so we plan to remove it.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoMdeModulePkg/DriverSampleDxe: Remove the non-interactive password
Dandan Bi [Thu, 2 Jun 2016 01:53:04 +0000 (09:53 +0800)]
MdeModulePkg/DriverSampleDxe: Remove the non-interactive password

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoMdeModulePkg: Clear the buffer after using it
Dandan Bi [Fri, 27 May 2016 08:00:28 +0000 (16:00 +0800)]
MdeModulePkg: Clear the buffer after using it

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoMdeModulePkg/SetupBrowser:Don't support password without interactive flag
Dandan Bi [Tue, 15 Nov 2016 11:13:33 +0000 (19:13 +0800)]
MdeModulePkg/SetupBrowser:Don't support password without interactive flag

In current SetupBrowser, the logic related to non-interative password
is not correct. How to support it correctly or whether support it
is still under investigation. First step remove the incorrect logic.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoMdeModulePkg/DisplayEngine: Popup dialogue when password is not supported
Dandan Bi [Tue, 15 Nov 2016 11:10:59 +0000 (19:10 +0800)]
MdeModulePkg/DisplayEngine: Popup dialogue when password is not supported

when the password is not supported, pop up a dialogue
to let user know the reason.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoEmbeddedPkg/MmcDxe: expand to support multiple blocks
Haojian Zhuang [Wed, 23 Nov 2016 13:36:24 +0000 (21:36 +0800)]
EmbeddedPkg/MmcDxe: expand to support multiple blocks

Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoEmbeddedPkg/MmcDxe: set I/O speed and bus width in SD stack
Haojian Zhuang [Wed, 23 Nov 2016 13:36:22 +0000 (21:36 +0800)]
EmbeddedPkg/MmcDxe: set I/O speed and bus width in SD stack

Add more SD commands to support 4-bit bus width & iospeed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoEmbeddedPkg/MmcDxe: invoke SetIos() protocol method to set speed and width
Haojian Zhuang [Wed, 23 Nov 2016 13:36:21 +0000 (21:36 +0800)]
EmbeddedPkg/MmcDxe: invoke SetIos() protocol method to set speed and width

Add the interface to change the bus width and speed.

By default, MMC is initialized with 1-bit mode and less than 400KHz bus
clock. It causes MMC working inefficiently.

Set I/O bus width on both MMC controller and EXTCSD. Otherwise, it may
cause unmatched failure case. And support more timing mode, high speed,
HS200 & HS400 mode.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoArmPlatformPkg/PL180MciDxe: update for identifying SD
Haojian Zhuang [Wed, 23 Nov 2016 13:36:23 +0000 (21:36 +0800)]
ArmPlatformPkg/PL180MciDxe: update for identifying SD

When CMD6 & ACMD51 are added into identifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it will hang when
system tries to read expected data.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
5 years agoEmbeddedPkg/Protocol/MmcHost: add new methods for I/O width and multiblock
Haojian Zhuang [Wed, 23 Nov 2016 13:36:21 +0000 (21:36 +0800)]
EmbeddedPkg/Protocol/MmcHost: add new methods for I/O width and multiblock

Add new protocol methods to change the bus width, speed and check
for multiblock support.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Split off protocol changes from implementation changes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoMdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci
Marcin Wojtas [Thu, 24 Nov 2016 07:54:33 +0000 (08:54 +0100)]
MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci

According to AHCI Spec 1.3 GHC.AE bit description:
"The implementation of this bit is dependent upon the value of the
CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall
have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only
and shall have a reset value of '1'."

Being in AhciMode, for proper operation it is required, that GHC.AE bit
is always set, before any other AHCI registers are written to. Current
AhciMode implementation, both in AhciReset() and AhciModeInitialization()
functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition,
assuming (according to the AHCI spec), that otherwise it has to be set
anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE
requires updating by software.

This patch enables in AhciMode setting GHC.AE in case its initial value
is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC
families. The change is transparent to all other platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
5 years agoOvmfPkg/build.sh: Make GCC5 the default toolchain, catch GCC43 and earlier
Konrad Rzeszutek Wilk [Thu, 24 Nov 2016 01:15:23 +0000 (20:15 -0500)]
OvmfPkg/build.sh: Make GCC5 the default toolchain, catch GCC43 and earlier

v2:
 * Changes suggested by Laszlo:
   - change the catch-all (*) to GCC5, from GCC44
   - remove the (5.*.*) pattern from GCC49
   - generate error for GCC < 4.4

In v3, also generate error for really GCC < 4.4, like GCC 1.

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=62
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Konrad Rzeszutek Wilk <konrad@kernel.org>
Tested-by: Laszlo Ersek <lersek@redhat.com>
5 years agoIntelFsp2Pkg: Use FspSiliconInitDone2 API
Thomaiyar, Richard Marian [Wed, 16 Nov 2016 09:47:04 +0000 (17:47 +0800)]
IntelFsp2Pkg: Use FspSiliconInitDone2 API

Use FspSiliconInitDone2 API in Notify Phase

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to dev
Feng Tian [Wed, 23 Nov 2016 01:46:32 +0000 (09:46 +0800)]
MdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to dev

We send ADDRESS DEVICE CMD in XhcInitializeDeviceSlot(), which will
cause XHC issue a USB SET_ADDRESS request to the USB Device.

According to USB spec, there should have a 10ms delay before this
operation after resetting a given port.

But in original code, there is a possible path which may have no such
10ms delay:
UsbHubResetPort()->UsbHubSetPortFeature()->Stall(20)->UsbHubGetPortSt
atus()->XhcPollPortStatusChange()->(if RESET_C bit is set)->
XhcInitializeDeviceSlot()->(if RESET_C bit is set)->Stall(10)

So this patch is used to fix above issue.

Cc: Star Zeng <star.zeng@intel.com>
Cc: Baraneedharan Anbazhagan <anbazhagan@hp.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Tested-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
5 years agoUefiCpuPkg/PiSmmCpu: Correct exception message.
Jiewen Yao [Tue, 22 Nov 2016 07:05:11 +0000 (15:05 +0800)]
UefiCpuPkg/PiSmmCpu: Correct exception message.

This patch fixes the first part of
https://bugzilla.tianocore.org/show_bug.cgi?id=242

Previously, when SMM exception happens, "stack overflow" is misreported.
This patch checked the PF address to see it is stack overflow, or
it is caused by SMM page protection.

It dumps exception data, PF address and the module trigger the issue.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoUefiCpuPkg/MpInitLib: fix feature test for Extended Topology CPUID leaf
Laszlo Ersek [Tue, 22 Nov 2016 12:58:54 +0000 (13:58 +0100)]
UefiCpuPkg/MpInitLib: fix feature test for Extended Topology CPUID leaf

According to the Intel SDM (325462-060US / September 2016),

> INPUT EAX = 0BH: Returns Extended Topology Information
>
> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]

The "GetApicId" sections in the Ia32 and X64 "MpFuncs.nasm" files do not
perform check (b).

This causes an actual bug in the following OVMF setup:

- Intel W3550 host processor <http://ark.intel.com/products/39720/>,

- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
  visible to the guest should be exactly the same as the host CPU".

Under "GetApicId", check (a) passes: the CPUID level of the W3550 is
exactly 11 decimal. However, leaf 11 itself is not supported, therefore
EDX is set to zero:

> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.

Because we don't check (b), the "GetProcessorNumber" section of the code
is reached with an initial APIC ID of 0 in EDX on all of the APs. Given
that "GetProcessorNumber" searches the
"MP_CPU_EXCHANGE_INFO.CpuInfo[*].InitialApicId" fields for a match, all
APs enter ApWakeupFunction() with an identical "NumApsExecuting"
parameter. This results in unpredictable guest behavior (crashes, reboots,
hangs etc).

Reorganize the "GetApicId" section and add the missing check in both
assembly files.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoUefiCpuPkg/LocalApicLib: fix feature test for Extended Topology CPUID leaf
Laszlo Ersek [Tue, 22 Nov 2016 11:43:17 +0000 (12:43 +0100)]
UefiCpuPkg/LocalApicLib: fix feature test for Extended Topology CPUID leaf

According to the Intel SDM (325462-060US / September 2016),

> INPUT EAX = 0BH: Returns Extended Topology Information
>
> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]

The LocalApicLib instances in UefiCpuPkg do not perform check (b).

This causes an actual bug in the following OVMF setup:

- Intel W3550 host processor <http://ark.intel.com/products/39720/>,

- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
  visible to the guest should be exactly the same as the host CPU".

In the GetInitialApicId() function, check (a) passes: the CPUID level of
the W3550 is exactly 11 decimal. However, leaf 11 itself is not supported,
therefore EDX is set to zero:

> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.

Because we don't check (b), we return 0 as initial APIC ID on the BSP and
on all of the APs as well.

Add the missing check.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoSecurityPkg DxeTcg2PPLib: Lock Tcg2PhysicalPresenceFlags variable on S4
Star Zeng [Fri, 18 Nov 2016 07:34:54 +0000 (15:34 +0800)]
SecurityPkg DxeTcg2PPLib: Lock Tcg2PhysicalPresenceFlags variable on S4

The code updates Tcg2PhysicalPresenceLibProcessRequest() to also lock
Tcg2PhysicalPresenceFlags variable on S4.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
5 years agoRevert old "Enable BlockSid related PP actions" patch series.
Eric Dong [Wed, 23 Nov 2016 08:26:36 +0000 (16:26 +0800)]
Revert old "Enable BlockSid related PP actions" patch series.

New solution for this issue will be provided.

This reverts commits from d1947ce509d745f32db6b7fecc03dc9c778b9350
to bda034c34deea6eb43edcef28018a9ace8f04637.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoMdeModulePkg/DxeNetLib: Allow the IPv4/prefix case when AsciiStrToIp4
Jiaxin Wu [Fri, 18 Nov 2016 07:38:32 +0000 (15:38 +0800)]
MdeModulePkg/DxeNetLib: Allow the IPv4/prefix case when AsciiStrToIp4

This patch is used to allow the IPv4 with prefix case.

Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
5 years agoShellPkg: update ping6 to use timer service instead of timer arch protocol .
Zhang Lubo [Tue, 8 Nov 2016 09:24:12 +0000 (17:24 +0800)]
ShellPkg: update ping6 to use timer service instead of timer arch protocol .

This patch update the shell ping command to use timer service to calculate the
RTT time, instead of using the timer arch protocol.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Cc: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
5 years agoBaseTools: report error for same Guid's Private definition conflict
Yonghong Zhu [Sat, 19 Nov 2016 09:06:18 +0000 (17:06 +0800)]
BaseTools: report error for same Guid's Private definition conflict

Add error check for the same Guid/Protocol/PPIs/Includes defined as both
Private and non-Private attribute.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=209
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
5 years agoMdeModulePkg/EbcDxe: reorganize EBC header definitions
Pete Batard [Wed, 16 Nov 2016 13:24:10 +0000 (21:24 +0800)]
MdeModulePkg/EbcDxe: reorganize EBC header definitions

VM related defs are now in EbcVmTest.h, and opocode related definitions in
Ebc.h.
Because it is used by both the EBC Debugger and driver,
EbcDebugSignalException() sees its definition factorized in
EbcDebuggerHook.h.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDxe: add EBC Debugger
Pete Batard [Wed, 16 Nov 2016 13:24:09 +0000 (21:24 +0800)]
MdeModulePkg/EbcDxe: add EBC Debugger

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/EbcDxe: prepare support for EBC Debugger
Pete Batard [Wed, 16 Nov 2016 13:24:08 +0000 (21:24 +0800)]
MdeModulePkg/EbcDxe: prepare support for EBC Debugger

* This patch introduces EbcDebuggerHook.c/h and inserts the required
  EBCDebugger references into the existing EBC source files.
* With all the hooks defined to their empty version in EbcDebuggerHook.c
  the existing EBC VM behaviour is left unaffected.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg/DisplayEngine: Return the selectable menu correctly
Dandan Bi [Tue, 22 Nov 2016 02:39:38 +0000 (10:39 +0800)]
MdeModulePkg/DisplayEngine: Return the selectable menu correctly

When returning selectable menu, should return the menu in current form,
the codes miss to do the check. Now returning the selectable menu behind
the codes "if ((UINTN) Distance + NextMenuOption->Skip > GapToTop)".
Then can cover the check, can return the menu correctly.

https://bugzilla.tianocore.org/show_bug.cgi?id=232

Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
5 years agoMdeModulePkg/DxeCapsuleLibFmp: Use AllocatePool for CapsuleResultVariable
Dandan Bi [Fri, 18 Nov 2016 10:33:02 +0000 (18:33 +0800)]
MdeModulePkg/DxeCapsuleLibFmp: Use AllocatePool for CapsuleResultVariable

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: jiewen.yao@intel.com
5 years agoSecurityPkg Tcg2Dxe: ASSERT to ensure 'VarData' is not NULL
Hao Wu [Mon, 21 Nov 2016 07:38:11 +0000 (15:38 +0800)]
SecurityPkg Tcg2Dxe: ASSERT to ensure 'VarData' is not NULL

The logic in functions ReadAndMeasureVariable() and MeasureVariable()
within Tcg2Dxe ensure that 'VarData' will not be NULL before calling
TcgDxeHashLogExtendEvent() at line 1716.

This commit adds ASSERT as warnings for the case that will not happen.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
5 years agoSecurityPkg TcgStorageCoreLib: ASSERT to ensure 'ByteSeq' is not NULL
Hao Wu [Mon, 21 Nov 2016 06:00:44 +0000 (14:00 +0800)]
SecurityPkg TcgStorageCoreLib: ASSERT to ensure 'ByteSeq' is not NULL

Add ASSERT to make sure 'ByteSeq' is not NULL before comsumed by
CopyMem().

Cc: Eric Dong <eric.dong@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoMdeModulePkg CapsuleApp: ASSERT to ensure 'CapsuleIndex' is not NULL
Hao Wu [Mon, 21 Nov 2016 05:44:59 +0000 (13:44 +0800)]
MdeModulePkg CapsuleApp: ASSERT to ensure 'CapsuleIndex' is not NULL

Function GetVariable2() ensures its third (output) parameter will not be
NULL when the return status is EFI_SUCCESS.

This commit adds ASSERT as warnings for the case that will not happen.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoUefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncMode
Laszlo Ersek [Thu, 17 Nov 2016 20:13:29 +0000 (21:13 +0100)]
UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncMode

Move the declaration of these PCDs from the

  [PcdsFixedAtBuild, PcdsPatchableInModule]

section of "UefiCpuPkg/UefiCpuPkg.dec" to the

  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]

section. Their types, default values, and token values remain unchanged.

Only UefiCpuPkg/PiSmmCpuDxeSmm consumes these PCDs, specifically on the
call stack of its entry point function, and it turns them into static or
dynamically allocated data in SMRAM:

  PiCpuSmmEntry()                            [PiSmmCpuDxeSmm.c]
    InitializeSmmTimer()                     [SyncTimer.c]
      PcdCpuSmmApSyncTimeout
      -> mTimeoutTicker
    InitializeMpServiceData()                [MpService.c]
      InitializeMpSyncData()                 [MpService.c]
        PcdCpuSmmSyncMode
        -> mSmmMpSyncData->EffectiveSyncMode

However, there's another call path to fetching "PcdCpuSmmSyncMode", namely

  SmmInitHandler()                           [PiSmmCpuDxeSmm.c]
    InitializeMpSyncData()                   [MpService.c]
      PcdCpuSmmSyncMode
      -> mSmmMpSyncData->EffectiveSyncMode

and this path is exercised during S3 resume (as stated by the comment in
SmmInitHandler() too, "Initialize private data during S3 resume").

While we can call the PCD protocol (via PcdLib) for fetching dynamic PCDs
in the entry point function, we cannot do that at S3 resume. Therefore
pre-fetch PcdCpuSmmSyncMode into a new global variable (which lives in
SMRAM) in InitializeMpServiceData(), just before calling
InitializeMpSyncData(). This way InitializeMpSyncData() can retrieve the
stashed PCD value from SMRAM, regardless of the boot mode.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=230
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
5 years agoMdeModulePkg/PiSmmCore: Cache CommunicationBuffer info before using it
Jeff Fan [Fri, 18 Nov 2016 02:46:43 +0000 (10:46 +0800)]
MdeModulePkg/PiSmmCore: Cache CommunicationBuffer info before using it

gSmmCorePrivate->CommunicationBuffer and gSmmCorePrivate->BufferSize locate at
runtime memory region. That means they could be modified by non-SMM code during
runtime.

We should cache them into SMM local variables before we verify them. After
verification, we should use the cached ones directly instead of the ones in
gSmmCorePrivate.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
5 years agoSecurityPkg OpalPasswordDxe: Clean PSID buffer.
Eric Dong [Mon, 21 Nov 2016 06:38:31 +0000 (14:38 +0800)]
SecurityPkg OpalPasswordDxe: Clean PSID buffer.

Change callback handler type to avoid saving PSID info in
browser temp buffer. Also clean the buffer after using it.

Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg OpalPasswordDxe: Clean password buffer.
Eric Dong [Wed, 16 Nov 2016 06:15:29 +0000 (14:15 +0800)]
SecurityPkg OpalPasswordDxe: Clean password buffer.

Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg Tcg2Config: Remove the empty options.
Eric Dong [Thu, 2 Jun 2016 07:20:30 +0000 (15:20 +0800)]
SecurityPkg Tcg2Config: Remove the empty options.

The BlockSID actions not has code related to
them. Now we implement the BlockSID feature in
OpalPasswordDxe driver. So remove these actions
here.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg OpalPasswordDxe: Use PP actions to enable BlockSID.
Eric Dong [Thu, 2 Jun 2016 07:20:17 +0000 (15:20 +0800)]
SecurityPkg OpalPasswordDxe: Use PP actions to enable BlockSID.

Update the implementation, use physical presence defined actions to
update the BlockSid related status.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg TcgSmm: Enable Storage actions.
Eric Dong [Mon, 14 Nov 2016 06:47:41 +0000 (14:47 +0800)]
SecurityPkg TcgSmm: Enable Storage actions.

After enable storage related actions in the
TcgPhysicalPresenceStorageLib, use this library to support
storage related actions in this driver.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg SmmTcg2PhysicalPresenceLib: Enable Storage actions.
Eric Dong [Wed, 16 Nov 2016 05:45:21 +0000 (13:45 +0800)]
SecurityPkg SmmTcg2PhysicalPresenceLib: Enable Storage actions.

After enable storage related actions in the
TcgPhysicalPresenceStorageLib, use this library to support
storage related actions in this library.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg DxeTcgPhysicalPresenceLib: Enable Storage actions.
Eric Dong [Thu, 2 Jun 2016 07:17:59 +0000 (15:17 +0800)]
SecurityPkg DxeTcgPhysicalPresenceLib: Enable Storage actions.

After enable storage related actions in the
TcgPhysicalPresenceStorageLib, use this library to support
storage related actions in this library.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg DxeTcg2PhysicalPresenceLib: Enable Storage actions.
Eric Dong [Thu, 2 Jun 2016 07:17:42 +0000 (15:17 +0800)]
SecurityPkg DxeTcg2PhysicalPresenceLib: Enable Storage actions.

After enable storage related actions in the
TcgPhysicalPresenceStorageLib, use this library to support
storage related actions in this library.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg: Add SmmTcgPhysicalPresenceStorageLib.
Eric Dong [Mon, 21 Nov 2016 06:52:49 +0000 (14:52 +0800)]
SecurityPkg: Add SmmTcgPhysicalPresenceStorageLib.

Tcg Physical Presence spec defined some actions used
for storage device. Add Smm version library to handles
these actions.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg: Add DxeTcgPhysicalPresenceStorageLib.
Eric Dong [Wed, 16 Nov 2016 05:49:50 +0000 (13:49 +0800)]
SecurityPkg: Add DxeTcgPhysicalPresenceStorageLib.

Tcg Physical Presence spec defined some actions used
for storage device. Add Dxe version library to handles
 these actions.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg: Add header file for TcgPhysicalPresenceStorageLib.
Eric Dong [Thu, 2 Jun 2016 07:15:35 +0000 (15:15 +0800)]
SecurityPkg: Add header file for TcgPhysicalPresenceStorageLib.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg: Add definition for Physical Presence storage flag.
Eric Dong [Thu, 2 Jun 2016 07:14:56 +0000 (15:14 +0800)]
SecurityPkg: Add definition for Physical Presence storage flag.

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
5 years agoSecurityPkg Tcg2Pei: Add comments into LogHashEvent()
Star Zeng [Fri, 18 Nov 2016 02:58:35 +0000 (10:58 +0800)]
SecurityPkg Tcg2Pei: Add comments into LogHashEvent()

Add comments into LogHashEvent() to describe the usage
of GetDigestListSize (DigestList).

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg Tcg2Dxe: Get correct digest list size
Star Zeng [Wed, 16 Nov 2016 09:17:36 +0000 (17:17 +0800)]
SecurityPkg Tcg2Dxe: Get correct digest list size

Current code uses GetDigestListSize(DigestList) to get
digest list size, that is incorrect.
The code should get digest list size of digests copied
into event2 log, those digests are compacted, so
GetDigestListBinSize() should be used.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg Tcg2Dxe: Filter inactive digest in event2 log from PEI HOB
Star Zeng [Thu, 17 Nov 2016 08:54:15 +0000 (16:54 +0800)]
SecurityPkg Tcg2Dxe: Filter inactive digest in event2 log from PEI HOB

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by : Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg TPM2: Update desc for param Buffer of GetDigestListSize()
Star Zeng [Fri, 18 Nov 2016 01:54:21 +0000 (09:54 +0800)]
SecurityPkg TPM2: Update desc for param Buffer of GetDigestListSize()

To make the description more clear, update the description
for parameter Buffer of GetDigestListSize() to
"Buffer to hold copied TPML_DIGEST_VALUES compact binary.".

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by : Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
5 years agoSecurityPkg TPM2: Add GetHashMaskFromAlgo() into Tpm2CommandLib
Star Zeng [Fri, 18 Nov 2016 05:13:21 +0000 (13:13 +0800)]
SecurityPkg TPM2: Add GetHashMaskFromAlgo() into Tpm2CommandLib

Add GetHashMaskFromAlgo() into Tpm2CommandLib for coming consumer.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by : Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>