Ard Biesheuvel [Sat, 8 Dec 2018 09:32:42 +0000 (10:32 +0100)]
BaseTools/Conf/tools_def.template: drop ARM/AARCH support from GCC46/GCC47
This drops ARM and AARCH64 support from the GCC46 and GCC47 toolchain
definitions, which are on the list to be removed, along with VS2003,
VS2005, VS2008, VS2010, DDK3790, UNIXGCC, GCC44, GCC45, ELFGCC, CYGGCC,
ICC, ICC11 and MYTOOLS.
Since GCC46 and GCC47 are the only ones on that list that support ARM
and/or AARCH64, let's give Liming a hand and cover the ARM side of
things first, so that everything that remains to be removed is x86
only.
Laszlo Ersek [Wed, 2 Jan 2019 19:49:41 +0000 (20:49 +0100)]
Vlv2TbltDevicePkg: assume GCC48 or later
We're about to remove BaseTools support for GCC44..GCC47. Bump the
assumption about the minimum gcc version to GCC48 in
"Vlv2TbltDevicePkg/bld_vlv.sh".
No GCC44..GCC47 references remain under Vlv2TbltDevicePkg after this
patch.
Cc: Zailiang Sun <zailiang.sun@intel.com> Cc: Yi Qian <yi.qian@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1377
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Zailiang Sun <zailiang.sun@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Laszlo Ersek [Wed, 2 Jan 2019 19:37:02 +0000 (20:37 +0100)]
OvmfPkg: require GCC48 or later
We're about to remove BaseTools support for GCC44..GCC47. Reject those gcc
versions cleanly in "OvmfPkg/build.sh". In "OvmfPkg/README", upgrade any
mentions of the same gcc versions to GCC48.
No GCC44..GCC47 references remain under OvmfPkg after this patch.
Laszlo Ersek [Wed, 2 Jan 2019 19:22:14 +0000 (20:22 +0100)]
EmulatorPkg: require GCC48 or later
We're about to remove BaseTools support for GCC44..GCC47. Reject those gcc
versions cleanly in "EmulatorPkg/build.sh", and drop build flags too that
are specific to them.
No GCC44..GCC47 references remain under EmulatorPkg after this patch.
Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1377
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
The standalone MM core is executed in place, and resides in a
separate execution context which may be space constrained.
Since code and data may be mapped with different attributes for
security reasons, the PE/COFF binary could have a section
alignment of 4 KB.
This means that any relocation data is not only useless, but it
will also take up 4 KB of valuable space.
So add support for the RELOCS_STRIPPED attribute on FFS files of
this type, so that we can get rid of the .reloc section altogether.
Feng, Bob C [Mon, 24 Dec 2018 10:24:46 +0000 (18:24 +0800)]
BaseTools: Correct PcdArray value assigment statement
https://bugzilla.tianocore.org/show_bug.cgi?id=1410
BaseTools should not generate C structure array initial value
if the value is not specified with CODE style.
This patch is going to remove the incorrect initial value statement
and correct the Pcd Array value assignment statement.
Ashish Singhal [Wed, 2 Jan 2019 15:46:48 +0000 (23:46 +0800)]
MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.
Add SDMA, ADMA2 and 26b data length support.
If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
SDMA registers supporting 64 bit addresses.
If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
ADMA descriptors supporting 64 bit addresses.
If host controller version is above V4.0, enable ADMA2 with 26b data
length support for better performance. HC 2 register is configured to
use 26 bit data lengths and ADMA2 descriptors are configured appropriately.
Alex James [Tue, 18 Dec 2018 04:25:12 +0000 (20:25 -0800)]
StdLib/sys/termios: Define cc_t as unsigned
According to the POSIX standard, cc_t, speed_t, and tcflag_t should be
unsigned integer types. Define cc_t as unsigned to match POSIX and fix
an implicit conversion error when building StdLib with XCODE5/CLANG38.
Previously, when compiling NASM source files, BaseTools did not support
including files outside of the NASM source file directory. As a result, we
duplicated multiple copies of "StuffRsb.inc" files in UefiCpuPkg. Those
INC files contain the common logic to stuff the Return Stack Buffer and
are identical.
After the fix of BZ 1085:
https://bugzilla.tianocore.org/show_bug.cgi?id=1085
The above support was introduced.
Thus, this commit will merge all the StuffRsb.inc files in UefiCpuPkg into
one file. The merged file will be named 'StuffRsbNasm.inc' and be placed
under folder UefiCpuPkg/Include/.
Feng, Bob C [Thu, 20 Dec 2018 11:12:12 +0000 (19:12 +0800)]
BaseTools: Reset FdsGlobalVariable
https://bugzilla.tianocore.org/show_bug.cgi?id=1418
This patch is going to fix a regression issue that is introduced
by commit b3497bad1221704a5dbc5da0b10f42625f1ad2ed.
Before commit b3497b, build launched a external GenFds.py to generate
Fd, so the global variable in GenFds.py was reset in each execution.
After commit b3497b, each GenFds run in the same python interpeter, so
we need to explicitly reset global variable in each GenFdsApi call.
Since BaseLib API AsmLfence() is a x86 arch specific API and should be
avoided using in generic codes, this commit replaces the usage of
AsmLfence() with arch-generic API SpeculationBarrier().
Since BaseLib API AsmLfence() is a x86 arch specific API and should be
avoided using in generic codes, this commit replaces the usage of
AsmLfence() with arch-generic API SpeculationBarrier().
Please note that speculation execution barriers are intended to be
asserted for SMM codes, hence, this commit still preserve an empty
implementation of the speculation execution barrier for the DXE codes.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Since BaseLib API AsmLfence() is a x86 arch specific API and should be
avoided using in generic codes, this commit replaces the usage of
AsmLfence() with arch-generic API SpeculationBarrier().
Since BaseLib API AsmLfence() is a x86 arch specific API and should be
avoided using in generic codes, this commit replaces the usage of
AsmLfence() with arch-generic API SpeculationBarrier().
X86 specific BaseLib API AsmLfence() was introduced to address the Spectre
Variant 1 (CVE-2017-5753) issue. The purpose of this API is to insert
barriers to stop speculative execution. However, the API is highly
architecture (X86) specific, and thus should be avoided using across
generic code.
To address this issue, this patch will add a new BaseLib API called
SpeculationBarrier(). Different architectures will have different
implementations for this API.
For IA32 and x64, the implementation of SpeculationBarrier() will
directly call AsmLfence().
For ARM and AARCH64, this patch will add a temporary empty implementation
as a placeholder. We hope experts in ARM can help to contribute the actual
implementation.
For EBC, similar to the ARM and AARCH64 cases, a temporary empty
implementation is added.
This patch is to remove the clarification about usage/difference between
those drivers in MdeModulePkg and NetworkPkg, since the MdeModulePkg one
have been deleted.
This patch is to delete the UefiPxeBcDxe driver in MdeModulePkg. The
driver will not be maintained and can't co-work with the dual-stack
UefiPxeBcDxe in NetworkPkg.
People should use below NetworkPkg drivers instead:
NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
Which is actively maintained with more bug fixes and new feature support.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
This patch is to remove the clarification about usage/difference between
those drivers in MdeModulePkg and NetworkPkg, since the MdeModulePkg one
have been deleted.
This patch is to delete the IScsiDxe driver in MdeModulePkg. The driver
will not be maintained and can't co-work with the dual-stack IScsiDxe in
NetworkPkg.
People should use below NetworkPkg drivers instead:
NetworkPkg/IScsiDxe/IScsiDxe.inf
Which is actively maintained with more bug fixes and new feature support.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This patch is to remove the clarification about usage/difference between
those drivers in MdeModulePkg and NetworkPkg, since the MdeModulePkg one
have been deleted.
This patch is to delete the Tcp4Dxe driver in MdeModulePkg. The driver
will not be maintained and can't co-work with the dual-stack TcpDxe in
NetworkPkg.
People should use below NetworkPkg drivers instead:
NetworkPkg/TcpDxe/TcpDxe.inf
Which is actively maintained with more bug fixes and new feature support.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Ard Biesheuvel [Wed, 19 Dec 2018 14:50:23 +0000 (15:50 +0100)]
BaseTools/tools_def ARM: use softfloat target for CLANG3x
The 'arm-linux-gnueabihf' target triplet we use for CLANG35 and
CLANG38 specifies a hardfloat target, and so the binaries that are
emitted are annotated as using VFP registers for passing floating
point arguments, even though no VFP is used anywhere in the code.
This works fine as long as we don't try to link against code
that uses software floating point, but combining object files
with different floating point calling conventions is not permitted.
So switch to the softfloat arm-linux-gnueabi triplet instead.
This affects both the name Clang uses when invoking the linker,
and the arguments it passes to it, and we are mostly interested
in the latter (since any version of GNU ld.bfd will do the right
thing as long as it targets EABI ARM)
For native builds, this change has no effect, since the unprefixed
system linker will take priority, and so Clang will pass the right
arguments to whichever linker happens to be the system linker.
For cross builds, the fact that Clang composes the name of the
linker by prefixing '-ld' with the target triplet implies that
users will have to switch to a version of binutils that targets
arm-linux-gnueabi rather than arm-linux-gnueabihf. Note that the
GCCx toolchain targets can use either when building for ARM so this
does not create a need to install two versions of the ARM cross
toolchain. Also, note that all ARM toolchains in the GCC family
are already documented as requiring a toolchain that targets
arm-linux-gnueabi and not arm-linux-gnueabihf.
Jeff Brasen [Thu, 13 Dec 2018 23:48:44 +0000 (16:48 -0700)]
ArmPkg/ArmScmiDxe: Add clock enable function
Add function to allow enabling and disabling of the clock using the SCMI
interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that
support new API from those that just have the older protocol.
SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future
changes. It is placed after the functions that are present in the
existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to
SCMI_CLOCK_PROTOCOL so that only a single implementation of those
function are needed.
BZ#1089 (https://bugzilla.tianocore.org/show_bug.cgi?id=1089) requests
to upgrade the OpenSSL to the latest 1.1.1 release. Since OpenSSL-1.1.1
has many changes, more porting efforts and feature evaluation are needed.
This might lead to a situation that it cannot catch the Q1'19 stable tag.
One of the solution is upgrade current version (1.1.0h) to 1.1.0j.
According to following web page in openssl.org, all security issues
solved in 1.1.1 have been also back-ported to 1.1.0.j. This can make
sure that no security vulnerabilities left in edk2 master before 1.1.1.
Ard Biesheuvel [Mon, 17 Dec 2018 18:51:45 +0000 (19:51 +0100)]
ArmPlatformPkg/PL011SerialPortLib: use untyped PCD for register base
Use an untyped PCD reference for PcdSerialRegisterBase, so that the
library gets built without hardcoded values, permitting modules to
override the default serial port. This allows SerialDxe to use a
different serial port from the one used for DEBUG output (which
often gets occluded due to the console driver clearing the screen).
Even though UEFI does not appear to use it, let's implement the
complete PI watchdog protocol, including handler registration,
which will be invoked before the ResetSystem() runtime service
when the watchdog timer expires.
Ard Biesheuvel [Tue, 18 Dec 2018 13:10:13 +0000 (14:10 +0100)]
ArmPkg/GenericWatchdogDxe: clean up the code
Clean up the code, by adding missing STATIC modifiers, drop
redundant casts, and get rid of the 'success handling' anti
pattern in the entry point code.
Ard Biesheuvel [Tue, 18 Dec 2018 13:10:12 +0000 (14:10 +0100)]
ArmPlatformPkg/SP805WatchdogDxe: switch to interrupt mode
The SP805 watchdog driver doesn't implement the PI watchdog protocol
fully, but always simply resets the system if the watchdog time runs
out.
However, the hardware does support the intended usage model, as long
as the SP805 is wired up correctly. So let's implement interrupt based
mode involving a handler that is registered by the DXE core and invoked
when the watchdog runs out. In the interrupt handler, we invoke the
notify function if one was registered, before calling the ResetSystem()
runtime service (as per the UEFI spec)
Ard Biesheuvel [Fri, 7 Dec 2018 11:01:25 +0000 (12:01 +0100)]
ArmVirtPkg/MemoryInitPeiLib: split memory HOB based on MAX_ALLOC_ADDRESS
The current ArmVirtMemoryInitPeiLib code splits the memory region passed
via PcdSystemMemoryBase/PcdSystemMemorySize in two if the region extends
beyond the MAX_ADDRESS limit. This was introduced for 32-bit ARM, which
may support more than 4 GB of physical address space, but cannot address
all of it via a 1:1 mapping, and a single region that is not mappable
in its entirety is unusable by the PEI core.
AArch64 is in a similar situation now: platforms may support more than
256 TB of physical address space, but only 256 TB is addressable by the
CPU, and so a memory region that extends from below this limit to above
it should be split.
Ard Biesheuvel [Fri, 7 Dec 2018 10:57:22 +0000 (11:57 +0100)]
ArmPkg/ArmMmuLib: take MAX_ALLOC_ADDRESS into account
When creating the page tables for the 1:1 mapping, ensure that we don't
attempt to map more than what is architecturally permitted when running
with 4 KB pages, which is 48 bits of VA. This will be reflected in the
value of MAX_ALLOC_ADDRESS once we override it for AArch64, so use that
macro instead of MAX_ADDRESS.
Ard Biesheuvel [Fri, 7 Dec 2018 10:55:19 +0000 (11:55 +0100)]
MdeModulePkg/Dxe/Page: take MAX_ALLOC_ADDRESS into account
Take MAX_ALLOC_ADDRESS into account in the implementation of the
page allocation routines, so that they will only return memory
that is addressable by the CPU at boot time, even if more memory
is available in the GCD memory map.
Update the GCD memory map initialization code so it disregards
memory that is not addressable by the CPU at boot time. This
only affects the first memory descriptor that is added, other
memory descriptors are permitted that describe memory ranges
that may be accessible to the CPU itself only when executing
under the OS.
Ard Biesheuvel [Fri, 7 Dec 2018 10:27:32 +0000 (11:27 +0100)]
MdePkg/Base: introduce MAX_ALLOC_ADDRESS
On some architectures, the maximum representable address deviates from
the virtual address range that is accessible by the firmware at boot
time. For instance, on AArch64, UEFI mandates a 4 KB page size, which
limits the address space to 48 bits, while more than that may be
populated on a particular platform, for use by the OS.
So introduce a new macro MAX_ALLOC_ADDRESS, which represent the maximum
address the firmware should take into account when allocating memory
ranges that need to be accessible by the CPU at boot time.
Ard Biesheuvel [Tue, 11 Dec 2018 13:23:28 +0000 (14:23 +0100)]
ArmPkg/DefaultExceptionHandlerLib ARM: avoid endless loop in RELEASE builds
Ensure that we prevent the CPU from proceeding after having taken an
unhandled exception on a RELEASE build, which does not contain the
ASSERT() which ensures this on DEBUG and NOOPT builds.
Retain the code following the deadloop so that we can keep going when
running in a debugger.
Ard Biesheuvel [Wed, 12 Dec 2018 12:11:04 +0000 (13:11 +0100)]
BaseTools/tools_def ARM: emit PIC veneers
The ARM linker may emit veneers, i.e., trampolines, when ordinary
direct relative branches cannot be used, e.g., for Thumb interworking
or branch targets that are out of range.
Usually, such veneers carry an absolute reference to the branch
target, which is problematic for us, since these absolute references
are not covered by annotations that are visible to GenFw in the
PE/COFF conversion, and so these absolute references are not fixed
up by the PE/COFF loader at runtime.
So switch to all ARM GNU ld toolchains to position independent veneers.
Leif Lindholm [Tue, 18 Dec 2018 18:25:49 +0000 (18:25 +0000)]
ArmPkg: drop ArmBds remnant Pcds from .dec
The following Pcds
- gArmTokenSpaceGuid.PcdArmLinuxSpinTable
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment
remained defined, without actual users.
So get rid of them.
One reference to be deleted separately from edk2-platforms.
The codes have been updated to not use PcdPeiCoreMaxFvSupported,
PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported, so their
statement in platform DSC could be removed.
Cc: Zailiang Sun <zailiang.sun@intel.com> Cc: Yi Qian <yi.qian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Zailiang Sun <zailiang.sun@intel.com> Reviewed-by: Yi Qian <yi.qian@intel.com>
The codes have been updated to not use PcdPeiCoreMaxFvSupported,
PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported, so their
statement in platform DSC could be removed.
Problem:
As static configuration from the PCDs, the binary PeiCore (for example
in FSP binary with dispatch mode) could not predict how many FVs,
Files or PPIs for different platforms.
Burden:
Platform developers need configure the PCDs accordingly for different
platforms.
To solve the problem and remove the burden, we can update code to
remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv
and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV,
File and PPI management.
This patch removes the using of PcdPeiCoreMaxPpiSupported in PeiCore.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Problem:
As static configuration from the PCDs, the binary PeiCore (for example
in FSP binary with dispatch mode) could not predict how many FVs,
Files or PPIs for different platforms.
Burden:
Platform developers need configure the PCDs accordingly for different
platforms.
To solve the problem and remove the burden, we can update PeiCore to
remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv
and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV,
File and PPI management.
This patch removes the using of PcdPeiCoreMaxFvSupported in PeiCore.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Problem:
As static configuration from the PCDs, the binary PeiCore (for example
in FSP binary with dispatch mode) could not predict how many FVs,
Files or PPIs for different platforms.
Burden:
Platform developers need configure the PCDs accordingly for different
platforms.
To solve the problem and remove the burden, we can update PeiCore to
remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv
and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV,
File and PPI management.
This patch removes the using of PcdPeiCoreMaxFvSupported in Tcg(2)Pei.
Problem:
As static configuration from the PCDs, the binary PeiCore (for example
in FSP binary with dispatch mode) could not predict how many FVs,
Files or PPIs for different platforms.
Burden:
Platform developers need configure the PCDs accordingly for different
platforms.
To solve the problem and remove the burden, we can update code to
remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv
and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV,
File and PPI management.
This patch removes the using of PcdPeiCoreMaxPeimPerFv in PeiCore.
Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Zhiju.Fan [Tue, 18 Dec 2018 16:13:12 +0000 (00:13 +0800)]
BaseTools: Add $(INC)-like support when compiling .nasm files
current edk2\BaseTools\Conf\build_rule.template, the compile of nasm
source files does not have the $(INC) support.
The '-I' option only includes the directory of the nasm source file
(${s_path}(+)). Hence, it will be impossible for nasm files to include
files outside of the nasm source file directory.
As a comparison, the compile of both .s and .asm have $(INC) support
in their compile commands.
Feng, Bob C [Thu, 13 Dec 2018 08:16:25 +0000 (16:16 +0800)]
BaseTools: Fixed metafile parser issues
https://bugzilla.tianocore.org/show_bug.cgi?id=1406
This patch is going to fix the regressions that
is introduced by commit 2f818ed0fb57d98985d151781a2ce9b8683129ee
The internal array for storing the metadata info should be cached
so that the meta file is parsed only once in one build.
1. support hex number for array index
2. support Non-Dynamic Pcd for array data type
3. support {} and {CODE()} for array data type
4. Change GetStructurePcdMaxSize to be a static function since it need to
be called in another static function. And this function does not depend on
it's class instance.
5. Add unittest for RemoveCComments function and
ArrayIndex regular expression.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Philippe Mathieu-Daud? <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Fu Siyuan [Mon, 17 Dec 2018 01:29:39 +0000 (09:29 +0800)]
ArmVirtPkg: Remove redundant library instances in ArmVirtQemuKernel.dsc
Commit 9a67ba261fe9 ("ArmVirtPkg: Replace obsoleted network drivers
from platform DSC/FDF") incorrectly added the BaseCryptLib, OpensslLib
and IntrinsicLib to "ArmVirtPkg/ArmVirtQemuKernel.dsc", it's redundant
and the library instances from "ArmVirt.dsc.inc" is already sufficient.
This patch also adjust the order of network drivers in "ArmVirtPkg/
ArmVirtQemuFvMain.fdf.inc" to make it same as the DSC file.
When there is no PCI option ROM exists, today's logic still creates
virtual BAR for option ROM using Length = 0, Alignment = (-1).
It causes the final MEM32 alignment requirement is as big as
0xFFFFFFFF_FFFFFFFF.
The patch fixes this issue by only creating virtual BAR for option
ROM when there is PCI option ROM.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
UEFI SCT crashed and failed in NonDiscoverablePciDeviceDxe becase
required checks were not performed. Perform parameters validation in
NonDiscoverablePciDeviceDxe.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
Our default is already armv7-a, so no need to rewrite the PLATFORM_FLAGS
for that. Also, setting -mfpu=neon is not entirely inappropriate, since
NEON is not mandatory under v7.
Feng, Bob C [Sun, 9 Dec 2018 13:44:32 +0000 (21:44 +0800)]
BaseTools: Fixed the build fail issue for cases
https://bugzilla.tianocore.org/show_bug.cgi?id=1386
This patch is going to fix the regression issue that is
introduced by commit 72a1d77694d51914c0dd6aa97dbfa58634b0a4a5
The issue will happen in the following cases:
1. There is no Pcd value assignment in Dsc file
2. There are duplicate Pcd filed assignment
PcdNvStoreDefaultValueBuffer value is update to Vpd Info File,
but it is not update into a internal cache. This patch will
fix this incorrect value in that internal cache.
Commit 9a67ba261fe9 ("ArmVirtPkg: Replace obsoleted network drivers
from platform DSC/FDF") failed to take into account that the now
unconditionally included IScsiDxe.inf from NetworkPkg requires a
resolution for TcpIoLib. Since specifying such a resolution is harmless
for platforms that have no networking enabled, let's just fix things
by dropping the conditionals around it.
Fu Siyuan [Tue, 30 Oct 2018 06:53:39 +0000 (14:53 +0800)]
ArmVirtPkg: Replace obsoleted network drivers from platform DSC/FDF.
This patch replaces the MdeModulePkg TCP, PXE and iSCSI driver with those
ones in NetworkPkg. These 3 drivers in MdeModulePkg are not being actively
maintained and will be removed from edk2 master soon.
Ard Biesheuvel [Wed, 12 Dec 2018 10:10:20 +0000 (11:10 +0100)]
BaseTools/tools_def ARM CLANG35: work around -mno-movt option name change
PE/COFF only has a very limited id space for runtime relocations, and
so it defines only a single relocation for movw/movt instruction pairs,
which can be combined to load a 32-bit symbol reference into a register.
For this to work as expected, these instructions must always appear in
the same order and adjacently, and this is something few compilers take
into account, unless they target PE/COFF explicitly (and this is not the
case for our ELF based toolchains)
For Clang 3.6 and later, we can pass the -mno-movt option to suppress
movw/movt pairs entirely, which works around the issue. Unfortunately,
for Clang 3.5, the option is called differently (-mllvm -arm-use-movt=0)
and mutually incompatible between 3.5 and 3.6.
Since it is desirable for the CLANG35 toolchain to be usable on newer
versions of Clang as well (given that it is the only non-LTO alternative
to CLANG38), let's work around this issue in a way that permits versions
3.5 and newer of Clang to be used with the CLANG35 profile.
So pass the -mkernel flag instead (and add -Qunused-argument so Clang
does not complain about the -mno-unaligned-access in ARM_CC_XIPFLAGS).
This also inhibits movw/movt generation, along with some other changes
(e.g., long calls) which do affect code generation but not in an
undesirable manner.
Ard Biesheuvel [Wed, 12 Dec 2018 10:04:44 +0000 (11:04 +0100)]
MdePkg/BaseMemoryLibOptDxe ARM: add missing function annotations
ARM uses the low order bit of a branch target address to decide in
which execution mode (ARM or Thumb) a function needs to be called.
In order for this to work across object files, ELF function symbols
will have the low bit set if they were emitted in Thumb mode and
cleared otherwise. This annotation is only emitted if the ELF symbols
are annotated as function, since taking the address of some data
symbol (e.g., a literal) should not produce a value with the low bit
set, even if it appears in an object file containing Thumb code.
This means that all functions coded in assembler must have this
function annotation, or they may end up getting called in the
wrong mode, crashing the program.
We currently permit R_ARM_GOT_PREL relocations in the ELF32 conversion
routines, under the assumption that relative relocations are fine as
long as the section layout is the same between ELF and PE/COFF.
However, as is the case with any proxy generating relocation, it is
up to the linker to emit an entry in the GOT table and populate it
with the correct absolute address, which should also be fixed up at
PE/COFF load time. Unfortunately, the relocations covering the GOT
section are not emitted into the static relocation sections processed
by GenFw, but only in the dynamic relocation section as a R_ARM_RELATIVE
relocation, and so GenFw fails to emit the correct PE/COFF relocation
data for GOT entries.
Since GOT indirection is pointless anyway for PE/COFF modules running
in UEFI context, let's just drop the references to R_ARM_GOT_PREL from
GenFw, resulting in a build time failure rather than a runtime failure
if such relocations do occur.
Ard Biesheuvel [Tue, 11 Dec 2018 12:01:10 +0000 (13:01 +0100)]
ArmVirtPkg/PrePiUniCoreRelocatable CLANG38: work around build issues
The self-relocating PrePi module that is used by the ArmVirtQemuKernel
and ArmVirtXen targets runs the linker in PIE mode so that it emits
dynamic relocations into the final image in a way that permits the
module to relocate itself into place before calling into the C code.
When building these targets using the CLANG38 toolchain, we switch
from the BFD to the GOLD linker, which behaves a bit differently when
building PIE executables, and insists on emitting GOT indirected symbol
references throughout, which means a) that we end up with absolute
addresses (which need to be fixed up at load time) for no good reason,
and b) we have to add support for handling GOT entries to GenFw if we
want to convert them into PE/COFF.
So instead, let's emit a shared library. Since the ELF image only serves
as the input to GenFw, this does not lead to any loss of functionality,
although it does require the -Bsymbolic linker option to be added to
ensure that no symbol based dynamic relocations are emitted (which
would, e.g., permit lazy binding for shared libraries). So for all
other toolchains, the linker option changes are a no-op.
Then, we have to convince CLANG38/GOLD that there is no need to refer
to symbols via a GOT entry. This is done by forcing hidden visibility
for all symbols in all components that make up the PrePi SEC module:
this informs the linker that a symbol is never exported or preempted,
making it safe to refer to it directly from anywhere in the code,
rather than indirectly via a GOT entry.
Ard Biesheuvel [Tue, 11 Dec 2018 09:21:25 +0000 (10:21 +0100)]
ArmVirtPkg/ArmVirtQemuKernel ARM: make some PCD settings apply to ARM
Move some PCD settings outs of the [PcdsFixedAtBuild.AARCH64] block,
so that they apply to 32-bit ARM as well. Without this change, the
ARM build doesn't work.
Ard Biesheuvel [Mon, 10 Dec 2018 14:13:39 +0000 (15:13 +0100)]
BaseTools/tools_def AARCH64 RELEASE: move GCC49/GGC5 to 4 KB alignment
Since 4 KB section alignment is required when mapping PE/COFF images
with strict permissions, update the default section alignment when
using GCC49 and GCC5 in RELEASE mode. Note that XIP modules such as
SEC, PEIMs or PEI core are not affected by this change, since the
override to 32 byte aligment remains in effect.
Ard Biesheuvel [Sat, 8 Dec 2018 10:24:31 +0000 (11:24 +0100)]
MdeModulePkg/FileExplorerLib: avoid packed struct for program data
Struct packing is only necessary for data structures whose in-memory
representation is covered by the PI or UEFI specs, and may deviate
from the ordinary C rules for alignment.
So in case of FileExplorerLib, this applies to the device path struct
only, and other structures used to carry program data should not be
packed, or we may end up with alignment faults on architectures such
as ARM, which don't permit load/store double or multiple instructions
to access memory locations that are not 32-bit aligned.
E.g., the following call in FileExplorerLibConstructor()
will perform a double-word store on the first argument, passed in
register r0, assuming that the pointer type of the argument is
enough to guarantee that the value is suitably aligned.
Eric Dong [Mon, 10 Dec 2018 07:32:14 +0000 (15:32 +0800)]
UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM.
Update CPUID definition to follow SDM 2018'11 version, changes Include:
1. Add new fields to the existed data structure, impact CPUIDs include:
1. CPUID_THERMAL_POWER_MANAGEMENT 0x06
CPUID_THERMAL_POWER_MANAGEMENT_EAX
2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
4. CPUID_EXTENDED_STATE 0x0D
CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
CPUID_EXTENDED_STATE_SUB_LEAF_ECX
5. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
6. CPUID_INTEL_SGX 0x12
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
2. Add new data structures which not existed before, impact CPUID includes:
1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
3. Remove fields which defined before, impact CPUID includes:
1. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
4. Add new sub leaf which not existed before, impact CPUID includes:
1. CPUID_INTEL_RDT_ALLOCATION 0x10
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
5. Add new CPUIDs which not exist before, new CPUIDs include:
1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F
Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
BaseLib interfaces are used in this library but not declared in module's
inf file. This patch fix this situation to keep inf and its code in
consistency. No functionality or interface change are involved.
Cc: Qin Long <qin.long@intel.com> Cc: Ting Ye <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
Today's implementation reuses the 32bit MMIO resource requested by
all PCI devices MMIO BARs when shadowing the option ROM.
Take a simple example, a system has only one PCI device. It requires
8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation
only requests 8MB (max of 4M and 8M) 32bit MMIO from
PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range
[3GB, 3GB+8MB) is allocated. The 3GB base address is firstly
programmed to the option ROM BAR for option ROM shadow. Then the
option ROM decoding is turned off and 3GB base address is programmed
to the 32bit MMIO BAR.
It doesn't cause issues when the device doesn't request too much
MMIO.
But when the device contains a 64bit MMIO BAR which requests 4GB MMIO
and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is
allocated for the option ROM. When the option ROM is being shadowed,
64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is
given to the 64bit BAR.
The range overlaps with the option ROM range which may cause the
device malfunction (e.g.: option ROM cannot be read out) when the
device has two separate decoders: one for MMIO BAR, the other for
option ROM.
The patch requests dedicated MEM32 resource for Option ROMs and
moves the Option ROM shadow logic after all MMIO BARs are programmed.
The MMIO BAR setting to 0 when shadowing Option ROM is also skipped
because the MMIO BAR already contains the correct value.
Sughosh Ganu [Mon, 3 Dec 2018 07:19:02 +0000 (12:49 +0530)]
StandaloneMM: Update permissions for Standalone MM drivers memory area
The StandaloneMM image executes in S-EL0 on reference Arm platforms
and is deployed by the trusted firmware as BL32 image. Memory for the
Standalone MM drivers is marked as RW+XN initially, allowing the
drivers to be loaded into the memory. Once loaded, the memory
attributes need to be changed to RO+XN for rodata sections and RO+X
for code sections.
Achieve this through the extra action 'UpdatePeCoffPermissions' to
request the privileged firmware in EL3 to update the permissions.
Sughosh Ganu [Mon, 3 Dec 2018 07:19:01 +0000 (12:49 +0530)]
StandaloneMM: Include the newly added library class for MMU functions
The MMU functions needed for StandaloneMM image are now exported
through a separate library class. Make the corresponding change in the
core's entry point inf file so that it references the correct library
class for modifying the MMU attributes.
Achin Gupta [Mon, 3 Dec 2018 07:20:54 +0000 (12:50 +0530)]
StandaloneMmPkg: Zero data structure explicitly
Introduction of the -mstrict-align flag results in GCC attempting
to use memset to zero out the InitMmFoundationSvcArgs structure.
In the absence of this C library function, this patch explicitly
zeroes this data structure prior to use.
Achin Gupta [Mon, 3 Dec 2018 07:20:53 +0000 (12:50 +0530)]
StandaloneMmPkg: Enforce alignment check for AArch64
On AArch64, Standalone MM during the SEC phase runs in S-EL0 with
SCTLR_EL1.A=1. This patch adds the -mstrict-align compiler flag to
ensure that the generated code is compliant with the runtime
alignment checks.
On AArch64, we can only use 48 address bits while running in UEFI,
while the GCD and UEFI memory maps may describe up to 52 bits of
physical address space. For this reason, MAX_ADDRESS was reduced
to 48 bits, to ensure that the firmware does not inadvertently
attempt to allocate memory that we cannot access.
However, MAX_ADDRESS is used in runtime drivers as well, and
runtime drivers may deal with kernel virtual addresses, which have
bits [63:48] set. In fact, the OS may be running with 64 KB pages
and pass addresses into the runtime services that use up to 52
bits of address space, either with the top bits set or cleared,
even if the physical address space does not extend beyond 48 bits.
In summary, changing MAX_ADDRESS is a mistake, and needs to be
reverted.
This patch is one of build tool performance improvement
series patches.
This patch is going to use join function instead of
string += string2 statement.
Current code use string += string2 in a loop to combine
a string. while creating a string list in a loop and using
"".join(stringlist) after the loop will be much faster.
[V2]
Optimize this patch so that it can be easy to review.
This patch is just apply the change to original files while
not create new similar files.
[V1]
This patch is one of build tool performance improvement
series patches.
This patch is going to use python list to store the parser data
instead of using sqlite database.
The replacement solution is as below:
SQL insert: list.append()
SQL select: list comprehension. for example:
Select * from table where field = “something”
->
[ item for item in table if item[3] == “something”]
SQL update: python map function. for example:
Update table set field1=newvalue where filed2 = “something”.
-> map(lambda x: x[1] = newvalue,
[item for item in table if item[2] == “something”])
SQL delete: list comprehension.
With this change, We can save the time of interpreting SQL statement
and the time of write database to file system
Currently, AutoGen and GenFds run in different python interpreters. The
parser are duplicated. This patch is going to create new API for GenFds
and have the build to call that API instead of executing GenFds.py. As
such, the GenFds and build can share the parser data.
This patch is expected to save the time of GenFds about 2~3 seconds.
More details will be logged in BZ.
This is the summary measure data generated from python cProfile for
building Ovmf.
Currently: 8379147 function calls (8135450 primitive calls) in 12.580 seconds
After applying this patch: 3428712 function calls (3418881 primitive calls) in 8.944 seconds
projects / mirror_edk2.git / log