From 647517279d97297302780598122b80c8f4f855f1 Mon Sep 17 00:00:00 2001
From: Olivier Martin <olivier.martin@arm.com>
Date: Mon, 24 Mar 2014 15:26:22 +0000
Subject: [PATCH] ArmPkg/ArmLib: Renamed Cp15CacheInfo into ArmCacheInfo

CTR (Cache Type Register) has the same format on ARMv7 and AArch64.
Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function
architecture independent.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524
---
 ArmPkg/Include/Library/ArmLib.h               |  4 ++--
 .../ArmLib/Arm9/Arm9CacheInformation.c        | 23 ++++++++++---------
 .../Library/ArmLib/Common/Arm/ArmLibSupport.S |  4 ++--
 .../ArmLib/Common/Arm/ArmLibSupport.asm       |  4 ++--
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 7a0467130d..b0ce6c7cc6 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -212,9 +212,9 @@ ArmReadIdPfr1 (
   VOID
   );
 
-UINT32
+UINTN
 EFIAPI
-Cp15CacheInfo (
+ArmCacheInfo (
   VOID
   );
 
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
index 6180a47de7..19da4db258 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
@@ -1,7 +1,8 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  
+  Copyright (c) 2014, ARM Limited. All rights reserved.
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -21,7 +22,7 @@ ArmCacheType (
   VOID
   )
 {
-  switch (CACHE_TYPE(Cp15CacheInfo()))
+  switch (CACHE_TYPE (ArmCacheInfo ()))
   {
     case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;
     default:                    return ARM_CACHE_TYPE_UNKNOWN;
@@ -34,7 +35,7 @@ ArmCacheArchitecture (
   VOID
   )
 {
-  switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))
+  switch (CACHE_ARCHITECTURE (ArmCacheInfo ()))
   {
     case CACHE_ARCHITECTURE_UNIFIED:  return ARM_CACHE_ARCHITECTURE_UNIFIED;
     case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;
@@ -48,7 +49,7 @@ ArmDataCachePresent (
   VOID
   )
 {
-  switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))
+  switch (DATA_CACHE_PRESENT (ArmCacheInfo ()))
   {
     case CACHE_PRESENT:     return TRUE;
     case CACHE_NOT_PRESENT: return FALSE;
@@ -62,7 +63,7 @@ ArmDataCacheSize (
   VOID
   )
 {
-  switch (DATA_CACHE_SIZE(Cp15CacheInfo()))
+  switch (DATA_CACHE_SIZE (ArmCacheInfo ()))
   {
     case CACHE_SIZE_4_KB:   return   4 * 1024;      
     case CACHE_SIZE_8_KB:   return   8 * 1024;
@@ -80,7 +81,7 @@ ArmDataCacheAssociativity (
   VOID
   )
 {
-  switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
+  switch (DATA_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))
   {
     case CACHE_ASSOCIATIVITY_4_WAY:   return 4;
     case CACHE_ASSOCIATIVITY_DIRECT:  return 1;
@@ -94,7 +95,7 @@ ArmDataCacheLineLength (
   VOID
   )
 {
-  switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))
+  switch (DATA_CACHE_LINE_LENGTH (ArmCacheInfo ()))
   {
     case CACHE_LINE_LENGTH_32_BYTES: return 32;
     default:                         return  0;
@@ -107,7 +108,7 @@ ArmInstructionCachePresent (
   VOID
   )
 {
-  switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))
+  switch (INSTRUCTION_CACHE_PRESENT (ArmCacheInfo ()))
   {
     case CACHE_PRESENT:     return TRUE;
     case CACHE_NOT_PRESENT: return FALSE;
@@ -121,7 +122,7 @@ ArmInstructionCacheSize (
   VOID
   )
 {
-  switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))
+  switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))
   {
     case CACHE_SIZE_4_KB:   return   4 * 1024;      
     case CACHE_SIZE_8_KB:   return   8 * 1024;
@@ -139,7 +140,7 @@ ArmInstructionCacheAssociativity (
   VOID
   )
 {
-  switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
+  switch (INSTRUCTION_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))
   {
     case CACHE_ASSOCIATIVITY_8_WAY:   return 8;
     case CACHE_ASSOCIATIVITY_4_WAY:   return 4;
@@ -154,7 +155,7 @@ ArmInstructionCacheLineLength (
   VOID
   )
 {
-  switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))
+  switch (INSTRUCTION_CACHE_LINE_LENGTH (ArmCacheInfo ()))
   {
     case CACHE_LINE_LENGTH_32_BYTES: return 32;
     default:                         return  0;
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index a3de902cc6..f3b949565f 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -24,7 +24,7 @@
 .text
 .align 2
 GCC_ASM_EXPORT(ArmReadMidr)
-GCC_ASM_EXPORT(Cp15CacheInfo)
+GCC_ASM_EXPORT(ArmCacheInfo)
 GCC_ASM_EXPORT(ArmGetInterruptState)
 GCC_ASM_EXPORT(ArmGetFiqState)
 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
@@ -54,7 +54,7 @@ ASM_PFX(ArmReadMidr):
   mrc     p15,0,R0,c0,c0,0
   bx      LR
 
-ASM_PFX(Cp15CacheInfo):
+ASM_PFX(ArmCacheInfo):
   mrc     p15,0,R0,c0,c0,1
   bx      LR
 
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index cb69f71bc7..2e26ff35cf 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -24,7 +24,7 @@
 #endif
 
     EXPORT ArmReadMidr
-    EXPORT Cp15CacheInfo
+    EXPORT ArmCacheInfo
     EXPORT ArmGetInterruptState
     EXPORT ArmGetFiqState
     EXPORT ArmGetTTBR0BaseAddress
@@ -54,7 +54,7 @@ ArmReadMidr
   mrc     p15,0,R0,c0,c0,0
   bx      LR
 
-Cp15CacheInfo
+ArmCacheInfo
   mrc     p15,0,R0,c0,c0,1
   bx      LR
 
-- 
2.39.2