From 4e48c72c4cbbd24be3ec9835a7a428dce8064567 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Fri, 14 Nov 2014 00:37:16 +0000 Subject: [PATCH] OvmfPkg: Factor out platform detection (q35 vs. piix4) Introduce macros to detect the underlying platform and access its ACPI power management registers, based on querying the host bridge device ID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gabriel Somlo Reviewed-by: Paolo Bonzini Reviewed-by: Jordan Justen Reviewed-by: Gerd Hoffmann Reviewed-by: Laszlo Ersek git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16372 6f19259b-4bc3-4df7-8a09-765794883524 --- OvmfPkg/Include/OvmfPlatforms.h | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 OvmfPkg/Include/OvmfPlatforms.h diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatforms.h new file mode 100644 index 0000000000..cf6e62435c --- /dev/null +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -0,0 +1,49 @@ +/** @file + OVMF Platform definitions + + Copyright (c) 2014, Gabriel L. Somlo + + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may + be found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __OVMF_PLATFORMS_H__ +#define __OVMF_PLATFORMS_H__ + +#include +#include + +// +// Host Bridge Device ID (DID) values for PIIX4 and Q35/MCH +// +#define INTEL_82441_DEVICE_ID 0x1237 // PIIX4 +#define INTEL_Q35_MCH_DEVICE_ID 0x29C0 // Q35 + +// +// OVMF Host Bridge DID Address +// +#define OVMF_HOSTBRIDGE_DID \ + PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET) + +// +// Power Management Device and Function numbers for PIIX4 and Q35/MCH +// +#define OVMF_PM_DEVICE_PIIX4 0x01 +#define OVMF_PM_FUNC_PIIX4 0x03 +#define OVMF_PM_DEVICE_Q35 0x1f +#define OVMF_PM_FUNC_Q35 0x00 + +// +// Power Management Register access for PIIX4 and Q35/MCH +// +#define POWER_MGMT_REGISTER_PIIX4(Offset) \ + PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_PIIX4, OVMF_PM_FUNC_PIIX4, (Offset)) +#define POWER_MGMT_REGISTER_Q35(Offset) \ + PCI_LIB_ADDRESS (0, OVMF_PM_DEVICE_Q35, OVMF_PM_FUNC_Q35, (Offset)) + +#endif -- 2.39.2