From c1589a2c24abbc026120e3b045f9045448f64b2d Mon Sep 17 00:00:00 2001 From: Liming Gao Date: Mon, 1 Dec 2014 08:17:51 +0000 Subject: [PATCH] PerformancePkg: Update comments on TscTimerLib TscTimerLib is a sample implementation that depends on chipset ACPI timer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao Reviewed-by: Star Zeng git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16457 6f19259b-4bc3-4df7-8a09-765794883524 --- PerformancePkg/Library/TscTimerLib/BaseTscTimerLib.inf | 6 +++++- PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf | 6 +++++- PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/PerformancePkg/Library/TscTimerLib/BaseTscTimerLib.inf b/PerformancePkg/Library/TscTimerLib/BaseTscTimerLib.inf index 3d53b21db7..daae8a2580 100644 --- a/PerformancePkg/Library/TscTimerLib/BaseTscTimerLib.inf +++ b/PerformancePkg/Library/TscTimerLib/BaseTscTimerLib.inf @@ -4,6 +4,10 @@ # Note: There will be 1ms penalty to get TSC frequency every time # by waiting for 3579 clocks of the ACPI timer, or 1ms. # +# Note: This library is a sample implementation that depends on chipset ACPI timer. +# It may not work on new generation chipset. PcAtChipsetPkg AcpiTimerLib is +# the generic timer library that can replace this one. +# # A version of the Timer Library using the processor's TSC. # The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. # The invariant TSC runs at a constant rate in all ACPI P-, C-. and T-states. @@ -11,7 +15,7 @@ # TSC reads are much more efficient and do not incur the overhead associated with a ring transition or # access to a platform resource. # -# Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at diff --git a/PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf b/PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf index 1de9904017..e58aeac2eb 100644 --- a/PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf +++ b/PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf @@ -1,6 +1,10 @@ ## @file # Dxe Timer Library which uses the Time Stamp Counter in the processor. # +# Note: This library is a sample implementation that depends on chipset ACPI timer. +# It may not work on new generation chipset. PcAtChipsetPkg AcpiTimerLib is +# the generic timer library that can replace this one. +# # A version of the Timer Library using the processor's TSC. # The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. # The invariant TSC runs at a constant rate in all ACPI P-, C-. and T-states. @@ -8,7 +12,7 @@ # TSC reads are much more efficient and do not incur the overhead associated with a ring transition or # access to a platform resource. # -# Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at diff --git a/PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf b/PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf index c921272585..3f39d84e07 100644 --- a/PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf +++ b/PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf @@ -1,6 +1,10 @@ ## @file # Pei Timer Library which uses the Time Stamp Counter in the processor. # +# Note: This library is a sample implementation that depends on chipset ACPI timer. +# It may not work on new generation chipset. PcAtChipsetPkg AcpiTimerLib is +# the generic timer library that can replace this one. +# # A version of the Timer Library using the processor's TSC. # The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. # The invariant TSC runs at a constant rate in all ACPI P-, C-. and T-states. @@ -8,7 +12,7 @@ # TSC reads are much more efficient and do not incur the overhead associated with a ring transition or # access to a platform resource. # -# Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at -- 2.39.2