From 0d4c1db81aab86963536deb8253f35546c4398ea Mon Sep 17 00:00:00 2001 From: Michael Kinney Date: Fri, 30 Oct 2015 17:32:27 +0000 Subject: [PATCH] UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim The PiSmmCpuDxeSmm module makes some assumptions about GDT selectors that are based on the GDT layout from the DxeIplPeim. For example, the protected mode entry code and (where appropriate) the long mode entry code in the UefiCpuPkg/PiSmmCpuDxeSmm/*/MpFuncs.* assembly files, which are used during S3 resume, open-code segment selector values that depend on DxeIplPeim's GDT layout. This updates the CpuDxe module to use the same GDT layout as the DxeIplPeim. This enables modules that are dispatched after CpuDxe to find, and potentially save and restore, a GDT layout that matches that of DxeIplPeim. The DxeIplPeim has a 2 GDT entries for data selectors that are identical. These are LINEAR_SEL (GDT Offset 0x08)and LINEAR_DATA64_SEL (GDT offset 0x30). LINEAL_SEL is used for for IA32 DXE and the LINEAR_DATA64_SEL is used for X64 DXE. This duplicate data selector was added to the CpuDxe module to keep the GDT and all selectors consistent. Using a consistent GDT also improves debug experience. Reported-by: Laszlo Ersek Analyzed-by: Laszlo Ersek Link: http://article.gmane.org/gmane.comp.bios.edk2.devel/3568 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney Reviewed-by: Laszlo Ersek Tested-by: Laszlo Ersek git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18710 6f19259b-4bc3-4df7-8a09-765794883524 --- UefiCpuPkg/CpuDxe/CpuGdt.c | 83 +++++++++++++++++++++----------------- UefiCpuPkg/CpuDxe/CpuGdt.h | 10 +++-- 2 files changed, 53 insertions(+), 40 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 35a87a6e45..9ef2fdfefb 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -2,7 +2,7 @@ C based implemention of IA32 interrupt handling only requiring a minimal assembly interrupt entry point. - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -35,10 +35,10 @@ STATIC GDT_ENTRIES GdtTemplate = { // LINEAR_SEL // { - 0x0FFFF, // limit 0xFFFFF - 0x0, // base 0 - 0x0, - 0x092, // present, ring 0, data, expand-up, writable + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x092, // present, ring 0, data, read/write 0x0CF, // page-granular, 32-bit 0x0, }, @@ -46,10 +46,10 @@ STATIC GDT_ENTRIES GdtTemplate = { // LINEAR_CODE_SEL // { - 0x0FFFF, // limit 0xFFFFF - 0x0, // base 0 - 0x0, - 0x09A, // present, ring 0, data, expand-up, writable + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x09F, // present, ring 0, code, execute/read, conforming, accessed 0x0CF, // page-granular, 32-bit 0x0, }, @@ -57,10 +57,10 @@ STATIC GDT_ENTRIES GdtTemplate = { // SYS_DATA_SEL // { - 0x0FFFF, // limit 0xFFFFF - 0x0, // base 0 - 0x0, - 0x092, // present, ring 0, data, expand-up, writable + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x093, // present, ring 0, data, read/write, accessed 0x0CF, // page-granular, 32-bit 0x0, }, @@ -68,45 +68,56 @@ STATIC GDT_ENTRIES GdtTemplate = { // SYS_CODE_SEL // { - 0x0FFFF, // limit 0xFFFFF - 0x0, // base 0 - 0x0, - 0x09A, // present, ring 0, data, expand-up, writable + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x09A, // present, ring 0, code, execute/read 0x0CF, // page-granular, 32-bit 0x0, }, // - // LINEAR_CODE64_SEL + // SPARE4_SEL // { - 0x0FFFF, // limit 0xFFFFF - 0x0, // base 0 - 0x0, - 0x09B, // present, ring 0, code, expand-up, writable - 0x0AF, // LimitHigh (CS.L=1, CS.D=0) - 0x0, // base (high) + 0x0, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x0, // type + 0x0, // limit 19:16, flags + 0x0, // base 31:24 }, // - // SPARE4_SEL + // LINEAR_DATA64_SEL // { - 0x0, // limit 0 - 0x0, // base 0 - 0x0, - 0x0, // present, ring 0, data, expand-up, writable - 0x0, // page-granular, 32-bit + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x092, // present, ring 0, data, read/write + 0x0CF, // page-granular, 32-bit 0x0, }, // + // LINEAR_CODE64_SEL + // + { + 0x0FFFF, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x09A, // present, ring 0, code, execute/read + 0x0AF, // page-granular, 64-bit code + 0x0, // base (high) + }, + // // SPARE5_SEL // { - 0x0, // limit 0 - 0x0, // base 0 - 0x0, - 0x0, // present, ring 0, data, expand-up, writable - 0x0, // page-granular, 32-bit - 0x0, + 0x0, // limit 15:0 + 0x0, // base 15:0 + 0x0, // base 23:16 + 0x0, // type + 0x0, // limit 19:16, flags + 0x0, // base 31:24 }, }; diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 7ecec5d5d9..2a00751602 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -2,7 +2,7 @@ C based implemention of IA32 interrupt handling only requiring a minimal assembly interrupt entry point. - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -42,8 +42,9 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY LinearCode64; GDT_ENTRY Spare4; + GDT_ENTRY LinearData64; + GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; } GDT_ENTRIES; @@ -54,8 +55,9 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) +#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) #if defined (MDE_CPU_IA32) @@ -63,7 +65,7 @@ struct _GDT_ENTRIES { #define CPU_DATA_SEL LINEAR_SEL #elif defined (MDE_CPU_X64) #define CPU_CODE_SEL LINEAR_CODE64_SEL -#define CPU_DATA_SEL LINEAR_SEL +#define CPU_DATA_SEL LINEAR_DATA64_SEL #else #error CPU type not supported for CPU GDT initialization! #endif -- 2.39.2