From 053e878bfb5c9d5eca779789b62891add30b14ba Mon Sep 17 00:00:00 2001 From: Michael Kubacki Date: Sun, 5 Dec 2021 14:54:17 -0800 Subject: [PATCH] UefiCpuPkg: Apply uncrustify changes REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Signed-off-by: Michael Kubacki Reviewed-by: Ray Ni --- UefiCpuPkg/Application/Cpuid/Cpuid.c | 527 +- UefiCpuPkg/CpuDxe/CpuDxe.c | 428 +- UefiCpuPkg/CpuDxe/CpuDxe.h | 59 +- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 +- UefiCpuPkg/CpuDxe/CpuGdt.h | 61 +- UefiCpuPkg/CpuDxe/CpuMp.c | 95 +- UefiCpuPkg/CpuDxe/CpuMp.h | 1 - UefiCpuPkg/CpuDxe/CpuPageTable.c | 553 +- UefiCpuPkg/CpuDxe/CpuPageTable.h | 45 +- UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c | 9 +- UefiCpuPkg/CpuDxe/X64/PagingAttribute.c | 9 +- UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c | 18 +- UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c | 14 +- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c | 106 +- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h | 2 +- UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c | 7 +- UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h | 2 +- UefiCpuPkg/CpuIoPei/CpuIoPei.c | 111 +- UefiCpuPkg/CpuIoPei/CpuIoPei.h | 114 +- UefiCpuPkg/CpuMpPei/CpuBist.c | 91 +- UefiCpuPkg/CpuMpPei/CpuMp2Pei.c | 51 +- UefiCpuPkg/CpuMpPei/CpuMpPei.c | 149 +- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 54 +- UefiCpuPkg/CpuMpPei/CpuPaging.c | 256 +- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 77 +- UefiCpuPkg/Include/AcpiCpuData.h | 60 +- UefiCpuPkg/Include/CpuHotPlugData.h | 2 +- UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 2 +- UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 2 +- UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 2 +- UefiCpuPkg/Include/Guid/MsegSmram.h | 2 +- UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 24 +- UefiCpuPkg/Include/Library/LocalApicLib.h | 28 +- UefiCpuPkg/Include/Library/MicrocodeLib.h | 16 +- UefiCpuPkg/Include/Library/MpInitLib.h | 46 +- UefiCpuPkg/Include/Library/MtrrLib.h | 63 +- UefiCpuPkg/Include/Library/PlatformSecLib.h | 8 +- .../Include/Library/RegisterCpuFeaturesLib.h | 186 +- .../Include/Library/SmmCpuFeaturesLib.h | 2 +- .../Include/Library/SmmCpuPlatformHookLib.h | 18 +- UefiCpuPkg/Include/Library/UefiCpuLib.h | 2 - UefiCpuPkg/Include/Library/VmgExitLib.h | 25 +- UefiCpuPkg/Include/Ppi/MpServices2.h | 37 +- UefiCpuPkg/Include/Ppi/RepublishSecPpi.h | 4 +- UefiCpuPkg/Include/Ppi/ShadowMicrocode.h | 13 +- UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 26 +- UefiCpuPkg/Include/Protocol/SmmCpuService.h | 26 +- UefiCpuPkg/Include/Register/LocalApic.h | 1 - .../Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 2 +- .../Library/BaseXApicLib/BaseXApicLib.c | 284 +- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 280 +- .../Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 195 +- .../CpuCacheInfoLib/DxeCpuCacheInfoLib.c | 35 +- .../CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 64 +- .../CpuCacheInfoLib/PeiCpuCacheInfoLib.c | 34 +- .../Library/CpuCommonFeaturesLib/Aesni.c | 12 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 2 +- .../CpuCommonFeaturesLib/ClockModulation.c | 19 +- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 2 +- .../CpuCommonFeaturesLib.c | 22 +- .../Library/CpuCommonFeaturesLib/Eist.c | 3 +- .../CpuCommonFeaturesLib/FastStrings.c | 3 +- .../CpuCommonFeaturesLib/FeatureControl.c | 15 +- .../CpuCommonFeaturesLib/LimitCpuIdMaxval.c | 3 +- .../CpuCommonFeaturesLib/MachineCheck.c | 21 +- .../CpuCommonFeaturesLib/MonitorMwait.c | 3 +- .../CpuCommonFeaturesLib/PendingBreak.c | 4 +- .../Library/CpuCommonFeaturesLib/Ppin.c | 21 +- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 181 +- .../Library/CpuCommonFeaturesLib/X2Apic.c | 11 +- .../CpuExceptionCommon.c | 41 +- .../CpuExceptionCommon.h | 101 +- .../CpuExceptionHandlerLib/DxeException.c | 110 +- .../Ia32/ArchExceptionHandler.c | 142 +- .../Ia32/ArchInterruptDefs.h | 28 +- .../CpuExceptionHandlerLib/PeiCpuException.c | 51 +- .../PeiDxeSmmCpuException.c | 225 +- .../SecPeiCpuException.c | 44 +- .../CpuExceptionHandlerLib/SmmException.c | 27 +- .../X64/ArchExceptionHandler.c | 131 +- .../X64/ArchInterruptDefs.h | 32 +- .../Library/CpuTimerLib/BaseCpuTimerLib.c | 1 - UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c | 42 +- .../Library/MicrocodeLib/MicrocodeLib.c | 81 +- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 246 +- UefiCpuPkg/Library/MpInitLib/Microcode.c | 134 +- UefiCpuPkg/Library/MpInitLib/MpLib.c | 761 +- UefiCpuPkg/Library/MpInitLib/MpLib.h | 353 +- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 166 +- UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c | 60 +- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 1245 ++- .../MtrrLib/UnitTest/MtrrLibUnitTest.c | 459 +- .../MtrrLib/UnitTest/MtrrLibUnitTest.h | 75 +- .../Library/MtrrLib/UnitTest/RandomNumber.c | 9600 ++++++++--------- UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 428 +- .../PlatformSecLibNull/PlatformSecLibNull.c | 8 +- .../CpuFeaturesInitialize.c | 864 +- .../DxeRegisterCpuFeaturesLib.c | 114 +- .../PeiRegisterCpuFeaturesLib.c | 141 +- .../RegisterCpuFeatures.h | 110 +- .../RegisterCpuFeaturesLib.c | 421 +- .../SecPeiDxeTimerLibUefiCpu/X86TimerLib.c | 38 +- .../SmmCpuFeaturesLib/Ia32/SmmStmSupport.c | 18 +- .../SmmCpuFeaturesLibCommon.c | 43 +- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 384 +- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 23 +- .../SmmCpuFeaturesLib/X64/SmmStmSupport.c | 28 +- .../SmmCpuPlatformHookLibNull.c | 10 +- .../Library/VmgExitLibNull/VmgExitLibNull.c | 26 +- .../PiSmmCommunicationPei.c | 122 +- .../PiSmmCommunicationPrivate.h | 8 +- .../PiSmmCommunicationSmm.c | 60 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 694 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 61 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h | 14 +- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 110 +- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 76 +- .../PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 14 +- .../PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h | 62 +- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 499 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 264 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 432 +- .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 547 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c | 71 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h | 40 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 450 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 +- .../PiSmmCpuDxeSmm/SmmProfileInternal.h | 100 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 245 +- UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c | 15 +- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 601 +- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 8 +- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 86 +- .../PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 106 +- .../PiSmmCpuDxeSmm/X64/SmmProfileArch.h | 78 +- UefiCpuPkg/SecCore/FindPeiCore.c | 63 +- UefiCpuPkg/SecCore/SecBist.c | 95 +- UefiCpuPkg/SecCore/SecMain.c | 126 +- UefiCpuPkg/SecCore/SecMain.h | 28 +- UefiCpuPkg/SecMigrationPei/SecMigrationPei.c | 116 +- UefiCpuPkg/SecMigrationPei/SecMigrationPei.h | 34 +- .../Universal/Acpi/S3Resume2Pei/S3Resume.c | 494 +- 143 files changed, 14150 insertions(+), 13055 deletions(-) diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c b/UefiCpuPkg/Application/Cpuid/Cpuid.c index cee64f2fb5..372c6ef87d 100644 --- a/UefiCpuPkg/Application/Cpuid/Cpuid.c +++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c @@ -27,134 +27,134 @@ /// Structure for cache description lookup table /// typedef struct { - UINT8 CacheDescriptor; - CHAR8 *Type; - CHAR8 *Description; + UINT8 CacheDescriptor; + CHAR8 *Type; + CHAR8 *Description; } CPUID_CACHE_INFO_DESCRIPTION; /// /// Cache description lookup table /// CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = { - { 0x00 , "General" , "Null descriptor, this byte contains no information" }, - { 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" }, - { 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" }, - { 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" }, - { 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" }, - { 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" }, - { 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" }, - { 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" }, - { 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" }, - { 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" }, - { 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" }, - { 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" }, - { 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" }, - { 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" }, - { 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" }, - { 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" }, - { 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" }, - { 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" }, - { 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" }, - { 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" }, - { 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" }, - { 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" }, - { 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" }, - { 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" }, - { 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" }, - { 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" }, - { 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" }, - { 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" }, - { 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, - { 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" }, - { 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" }, - { 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" }, - { 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" }, - { 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" }, - { 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" }, - { 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" }, - { 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" }, - { 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" }, - { 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" }, - { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" }, - { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" }, - { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" }, - { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" }, - { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" }, - { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" }, - { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" }, - { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" }, - { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" }, - { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" }, - { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" }, - { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" }, - { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" }, - { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" }, - { 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" }, - { 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" }, - { 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" }, - { 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" }, - { 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" }, - { 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" }, - { 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" }, - { 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" }, - { 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" }, - { 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, - { 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" }, - { 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" }, - { 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" }, - { 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" }, - { 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" }, - { 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" }, - { 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" }, - { 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, - { 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, - { 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" }, - { 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" }, - { 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" }, - { 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" }, - { 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" }, - { 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" }, - { 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" }, - { 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" }, - { 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" }, - { 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" }, - { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" }, - { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" }, - { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." }, - { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" }, - { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" }, - { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, - { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" }, - { 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" }, - { 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, - { 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" }, - { 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" }, - { 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" }, - { 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" }, - { 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" }, - { 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" }, - { 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, - { 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" }, - { 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" }, - { 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" }, - { 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" }, - { 0xF0 , "Prefetch" , "64-Byte prefetching" }, - { 0xF1 , "Prefetch" , "128-Byte prefetching" }, - { 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." }, - { 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" } + { 0x00, "General", "Null descriptor, this byte contains no information" }, + { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" }, + { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" }, + { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" }, + { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" }, + { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" }, + { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" }, + { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" }, + { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" }, + { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" }, + { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" }, + { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" }, + { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" }, + { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" }, + { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" }, + { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" }, + { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" }, + { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" }, + { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" }, + { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" }, + { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" }, + { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" }, + { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" }, + { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" }, + { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" }, + { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" }, + { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" }, + { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" }, + { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, + { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" }, + { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" }, + { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" }, + { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" }, + { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" }, + { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" }, + { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" }, + { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" }, + { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" }, + { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" }, + { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" }, + { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" }, + { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" }, + { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" }, + { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" }, + { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" }, + { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" }, + { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" }, + { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" }, + { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" }, + { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" }, + { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" }, + { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" }, + { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" }, + { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" }, + { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" }, + { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" }, + { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" }, + { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" }, + { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" }, + { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" }, + { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" }, + { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" }, + { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, + { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" }, + { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" }, + { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" }, + { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" }, + { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" }, + { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" }, + { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" }, + { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, + { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, + { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" }, + { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" }, + { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" }, + { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" }, + { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" }, + { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" }, + { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" }, + { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" }, + { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" }, + { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" }, + { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" }, + { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" }, + { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." }, + { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" }, + { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" }, + { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, + { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" }, + { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" }, + { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, + { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" }, + { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" }, + { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" }, + { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" }, + { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" }, + { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" }, + { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, + { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" }, + { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" }, + { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" }, + { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" }, + { 0xF0, "Prefetch", "64-Byte prefetching" }, + { 0xF1, "Prefetch", "128-Byte prefetching" }, + { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." }, + { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" } }; /// /// The maximum supported CPUID leaf index starting from leaf 0x00000000. /// -UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; +UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; /// /// The maximum supported CPUID leaf index starting from leaf 0x80000000. @@ -170,11 +170,11 @@ CpuidSignature ( VOID ) { - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; - CHAR8 Signature[13]; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + CHAR8 Signature[13]; AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); @@ -184,7 +184,7 @@ CpuidSignature ( *(UINT32 *)(Signature + 0) = Ebx; *(UINT32 *)(Signature + 4) = Edx; *(UINT32 *)(Signature + 8) = Ecx; - Signature [12] = 0; + Signature[12] = 0; Print (L" Signature = %a\n", Signature); gMaximumBasicFunction = Eax; @@ -221,7 +221,7 @@ CpuidVersionInfo ( } DisplayModel = Eax.Bits.Model; - if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) { + if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) { DisplayModel |= (Eax.Bits.ExtendedModelId << 4); } @@ -314,12 +314,14 @@ LookupCacheDescription ( if (CacheDescriptor == 0x00) { return NULL; } + NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]); for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) { if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) { return &mCpuidCacheInfoDescription[Descriptor]; } } + return NULL; } @@ -354,13 +356,15 @@ CpuidCacheInfo ( for (Index = 1; Index < 4; Index++) { CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]); if (CacheDescription != NULL) { - Print (L" %-8a %a\n", + Print ( + L" %-8a %a\n", CacheDescription->Type, CacheDescription->Description ); } } } + if (Ebx.Bits.NotValid == 0) { // // Process Ebx.CacheDescriptor[0..3] @@ -368,13 +372,15 @@ CpuidCacheInfo ( for (Index = 0; Index < 4; Index++) { CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]); if (CacheDescription != NULL) { - Print (L" %-8a %a\n", + Print ( + L" %-8a %a\n", CacheDescription->Type, CacheDescription->Description ); } } } + if (Ecx.Bits.NotValid == 0) { // // Process Ecx.CacheDescriptor[0..3] @@ -382,13 +388,15 @@ CpuidCacheInfo ( for (Index = 0; Index < 4; Index++) { CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]); if (CacheDescription != NULL) { - Print (L" %-8a %a\n", + Print ( + L" %-8a %a\n", CacheDescription->Type, CacheDescription->Description ); } } } + if (Edx.Bits.NotValid == 0) { // // Process Edx.CacheDescriptor[0..3] @@ -396,7 +404,8 @@ CpuidCacheInfo ( for (Index = 0; Index < 4; Index++) { CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]); if (CacheDescription != NULL) { - Print (L" %-8a %a\n", + Print ( + L" %-8a %a\n", CacheDescription->Type, CacheDescription->Description ); @@ -457,8 +466,12 @@ CpuidCacheParams ( CacheLevel = 0; do { AsmCpuidEx ( - CPUID_CACHE_PARAMS, CacheLevel, - &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 + CPUID_CACHE_PARAMS, + CacheLevel, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx, + &Edx.Uint32 ); if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) { Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel); @@ -472,11 +485,12 @@ CpuidCacheParams ( PRINT_BIT_FIELD (Ebx, LineSize); PRINT_BIT_FIELD (Ebx, LinePartitions); PRINT_BIT_FIELD (Ebx, Ways); - PRINT_VALUE (Ecx, NumberOfSets); + PRINT_VALUE (Ecx, NumberOfSets); PRINT_BIT_FIELD (Edx, Invalidate); PRINT_BIT_FIELD (Edx, CacheInclusiveness); PRINT_BIT_FIELD (Edx, ComplexCacheIndexing); } + CacheLevel++; } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); } @@ -585,15 +599,21 @@ CpuidStructuredExtendedFeatureFlags ( AsmCpuidEx ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - &Eax, NULL, NULL, NULL + &Eax, + NULL, + NULL, + NULL ); for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { AsmCpuidEx ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf, - NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + NULL, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx.Uint32 ); - if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) { + if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) { Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); PRINT_BIT_FIELD (Ebx, FSGSBASE); @@ -713,7 +733,7 @@ CpuidArchitecturalPerformanceMonitoring ( **/ VOID CpuidExtendedTopology ( - UINT32 LeafFunction + UINT32 LeafFunction ) { CPUID_EXTENDED_TOPOLOGY_EAX Eax; @@ -725,6 +745,7 @@ CpuidExtendedTopology ( if (LeafFunction > gMaximumBasicFunction) { return; } + if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) { return; } @@ -732,23 +753,29 @@ CpuidExtendedTopology ( LevelNumber = 0; for (LevelNumber = 0; ; LevelNumber++) { AsmCpuidEx ( - LeafFunction, LevelNumber, - &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx + LeafFunction, + LevelNumber, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx ); if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { break; } + Print ( L"%a (Leaf %08x, Sub-Leaf %08x)\n", LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY", - LeafFunction, LevelNumber + LeafFunction, + LevelNumber ); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx); PRINT_BIT_FIELD (Eax, ApicIdShift); PRINT_BIT_FIELD (Ebx, LogicalProcessors); PRINT_BIT_FIELD (Ecx, LevelNumber); PRINT_BIT_FIELD (Ecx, LevelType); - PRINT_VALUE (Edx, x2APIC_ID); + PRINT_VALUE (Edx, x2APIC_ID); } } @@ -767,8 +794,12 @@ CpuidExtendedStateSubLeaf ( UINT32 Edx; AsmCpuidEx ( - CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, - &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx + CPUID_EXTENDED_STATE, + CPUID_EXTENDED_STATE_SUB_LEAF, + &Eax.Uint32, + &Ebx, + &Ecx.Uint32, + &Edx ); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx); @@ -776,12 +807,12 @@ CpuidExtendedStateSubLeaf ( PRINT_BIT_FIELD (Eax, XSAVEC); PRINT_BIT_FIELD (Eax, XGETBV); PRINT_BIT_FIELD (Eax, XSAVES); - PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS); + PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS); PRINT_BIT_FIELD (Ecx, XCR0); PRINT_BIT_FIELD (Ecx, HWPState); PRINT_BIT_FIELD (Ecx, PT); PRINT_BIT_FIELD (Ecx, XCR0_1); - PRINT_VALUE (Edx, IA32_XSS_Supported_32_63); + PRINT_VALUE (Edx, IA32_XSS_Supported_32_63); } /** @@ -801,14 +832,18 @@ CpuidExtendedStateSizeOffset ( for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { AsmCpuidEx ( - CPUID_EXTENDED_STATE, SubLeaf, - &Eax, &Ebx, &Ecx.Uint32, &Edx + CPUID_EXTENDED_STATE, + SubLeaf, + &Eax, + &Ebx, + &Ecx.Uint32, + &Edx ); if (Edx != 0) { Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx); - PRINT_VALUE (Eax, FeatureSaveStateSize); - PRINT_VALUE (Ebx, FeatureSaveStateOffset); + PRINT_VALUE (Eax, FeatureSaveStateSize); + PRINT_VALUE (Ebx, FeatureSaveStateOffset); PRINT_BIT_FIELD (Ecx, XSS); PRINT_BIT_FIELD (Ecx, Compacted); } @@ -834,8 +869,12 @@ CpuidExtendedStateMainLeaf ( } AsmCpuidEx ( - CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, - &Eax.Uint32, &Ebx, &Ecx, &Edx + CPUID_EXTENDED_STATE, + CPUID_EXTENDED_STATE_MAIN_LEAF, + &Eax.Uint32, + &Ebx, + &Ecx, + &Edx ); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx); @@ -847,9 +886,9 @@ CpuidExtendedStateMainLeaf ( PRINT_BIT_FIELD (Eax, IA32_XSS); PRINT_BIT_FIELD (Eax, PKRU); PRINT_BIT_FIELD (Eax, IA32_XSS_2); - PRINT_VALUE (Ebx, EnabledSaveStateSize); - PRINT_VALUE (Ecx, SupportedSaveStateSize); - PRINT_VALUE (Edx, XCR0_Supported_32_63); + PRINT_VALUE (Ebx, EnabledSaveStateSize); + PRINT_VALUE (Ecx, SupportedSaveStateSize); + PRINT_VALUE (Edx, XCR0_Supported_32_63); CpuidExtendedStateSubLeaf (); CpuidExtendedStateSizeOffset (); @@ -864,20 +903,24 @@ CpuidIntelRdtMonitoringEnumerationSubLeaf ( VOID ) { - UINT32 Ebx; - CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; + UINT32 Ebx; + CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { return; } AsmCpuidEx ( - CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, - NULL, &Ebx, NULL, &Edx.Uint32 + CPUID_INTEL_RDT_MONITORING, + CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, + NULL, + &Ebx, + NULL, + &Edx.Uint32 ); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32); - PRINT_VALUE (Ebx, Maximum_RMID_Range); + PRINT_VALUE (Ebx, Maximum_RMID_Range); PRINT_BIT_FIELD (Edx, L3CacheRDT_M); } @@ -890,22 +933,26 @@ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ( VOID ) { - UINT32 Ebx; - UINT32 Ecx; - CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; + UINT32 Ebx; + UINT32 Ecx; + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { return; } AsmCpuidEx ( - CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, - NULL, &Ebx, &Ecx, &Edx.Uint32 + CPUID_INTEL_RDT_MONITORING, + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, + NULL, + &Ebx, + &Ecx, + &Edx.Uint32 ); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32); - PRINT_VALUE (Ebx, OccupancyConversionFactor); - PRINT_VALUE (Ecx, Maximum_RMID_Range); + PRINT_VALUE (Ebx, OccupancyConversionFactor); + PRINT_VALUE (Ecx, Maximum_RMID_Range); PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring); PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring); PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring); @@ -927,13 +974,17 @@ CpuidIntelRdtAllocationMemoryBandwidthSubLeaf ( CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, - &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 + CPUID_INTEL_RDT_ALLOCATION, + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, + &Eax.Uint32, + &Ebx, + &Ecx.Uint32, + &Edx.Uint32 ); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); PRINT_BIT_FIELD (Eax, MaximumMBAThrottling); - PRINT_VALUE (Ebx, AllocationUnitBitMap); + PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_BIT_FIELD (Ecx, Liner); PRINT_BIT_FIELD (Edx, HighestCosNumber); } @@ -954,13 +1005,17 @@ CpuidIntelRdtAllocationL3CacheSubLeaf ( CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, - &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 + CPUID_INTEL_RDT_ALLOCATION, + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, + &Eax.Uint32, + &Ebx, + &Ecx.Uint32, + &Edx.Uint32 ); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); PRINT_BIT_FIELD (Eax, CapacityLength); - PRINT_VALUE (Ebx, AllocationUnitBitMap); + PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_BIT_FIELD (Ecx, CodeDataPrioritization); PRINT_BIT_FIELD (Edx, HighestCosNumber); } @@ -980,13 +1035,17 @@ CpuidIntelRdtAllocationL2CacheSubLeaf ( CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, - &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + CPUID_INTEL_RDT_ALLOCATION, + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, + &Eax.Uint32, + &Ebx, + NULL, + &Edx.Uint32 ); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); PRINT_BIT_FIELD (Eax, CapacityLength); - PRINT_VALUE (Ebx, AllocationUnitBitMap); + PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_BIT_FIELD (Edx, HighestCosNumber); } @@ -1006,8 +1065,12 @@ CpuidIntelRdtAllocationMainLeaf ( } AsmCpuidEx ( - CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, - NULL, &Ebx.Uint32, NULL, NULL + CPUID_INTEL_RDT_ALLOCATION, + CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, + NULL, + &Ebx.Uint32, + NULL, + NULL ); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0); @@ -1033,8 +1096,12 @@ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ( CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, - &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + CPUID_INTEL_SGX, + CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, + &Eax.Uint32, + &Ebx, + NULL, + &Edx.Uint32 ); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); @@ -1055,14 +1122,18 @@ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ( VOID ) { - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; AsmCpuidEx ( - CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, - &Eax, &Ebx, &Ecx, &Edx + CPUID_INTEL_SGX, + CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, + &Eax, + &Ebx, + &Ecx, + &Edx ); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx); @@ -1086,8 +1157,12 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf ( SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF; do { AsmCpuidEx ( - CPUID_INTEL_SGX, SubLeaf, - &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + CPUID_INTEL_SGX, + SubLeaf, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx.Uint32 ); if (Eax.Bits.SubLeafType == 0x1) { Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf); @@ -1099,6 +1174,7 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf ( PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection); PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection); } + SubLeaf++; } while (Eax.Bits.SubLeafType == 0x1); } @@ -1121,7 +1197,10 @@ CpuidEnumerationOfIntelSgx ( AsmCpuidEx ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, &Ebx.Uint32, NULL, NULL + NULL, + &Ebx.Uint32, + NULL, + NULL ); if (Ebx.Bits.SGX != 1) { // @@ -1153,8 +1232,12 @@ CpuidIntelProcessorTraceSubLeaf ( for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { AsmCpuidEx ( - CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, - &Eax.Uint32, &Ebx.Uint32, NULL, NULL + CPUID_INTEL_PROCESSOR_TRACE, + SubLeaf, + &Eax.Uint32, + &Ebx.Uint32, + NULL, + NULL ); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0); @@ -1183,12 +1266,16 @@ CpuidIntelProcessorTraceMainLeaf ( } AsmCpuidEx ( - CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, - &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL + CPUID_INTEL_PROCESSOR_TRACE, + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, + &Eax, + &Ebx.Uint32, + &Ecx.Uint32, + NULL ); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0); - PRINT_VALUE (Eax, MaximumSubLeaf); + PRINT_VALUE (Eax, MaximumSubLeaf); PRINT_BIT_FIELD (Ebx, Cr3Filter); PRINT_BIT_FIELD (Ebx, ConfigurablePsb); PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering); @@ -1270,11 +1357,15 @@ CpuidSocVendorBrandString ( // 4 32-bit brand string values per leaf and an extra value to // null terminate the string. // - UINT32 BrandString[3 * 4 + 1]; + UINT32 BrandString[3 * 4 + 1]; AsmCpuidEx ( - CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, - &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + CPUID_SOC_VENDOR, + CPUID_SOC_VENDOR_BRAND_STRING1, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx.Uint32 ); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); @@ -1284,8 +1375,12 @@ CpuidSocVendorBrandString ( BrandString[3] = Edx.Uint32; AsmCpuidEx ( - CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, - &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + CPUID_SOC_VENDOR, + CPUID_SOC_VENDOR_BRAND_STRING2, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx.Uint32 ); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); @@ -1295,8 +1390,12 @@ CpuidSocVendorBrandString ( BrandString[7] = Edx.Uint32; AsmCpuidEx ( - CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, - &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + CPUID_SOC_VENDOR, + CPUID_SOC_VENDOR_BRAND_STRING3, + &Eax.Uint32, + &Ebx.Uint32, + &Ecx.Uint32, + &Edx.Uint32 ); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); @@ -1329,8 +1428,12 @@ CpuidSocVendor ( } AsmCpuidEx ( - CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, - &Eax, &Ebx.Uint32, &Ecx, &Edx + CPUID_SOC_VENDOR, + CPUID_SOC_VENDOR_MAIN_LEAF, + &Eax, + &Ebx.Uint32, + &Ecx, + &Edx ); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx); @@ -1338,11 +1441,12 @@ CpuidSocVendor ( Print (L" Not Supported\n"); return; } - PRINT_VALUE (Eax, MaxSOCID_Index); + + PRINT_VALUE (Eax, MaxSOCID_Index); PRINT_BIT_FIELD (Ebx, SocVendorId); PRINT_BIT_FIELD (Ebx, IsVendorScheme); - PRINT_VALUE (Ecx, ProjectID); - PRINT_VALUE (Edx, SteppingID); + PRINT_VALUE (Ecx, ProjectID); + PRINT_VALUE (Edx, SteppingID); CpuidSocVendorBrandString (); } @@ -1367,12 +1471,15 @@ CpuidDeterministicAddressTranslationParameters ( AsmCpuidEx ( CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, - &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 + &Eax, + &Ebx.Uint32, + &Ecx, + &Edx.Uint32 ); Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32); - PRINT_VALUE (Eax, MaxID_Index); + PRINT_VALUE (Eax, MaxID_Index); PRINT_BIT_FIELD (Ebx, Page4K); PRINT_BIT_FIELD (Ebx, Page2M); PRINT_BIT_FIELD (Ebx, Page4M); @@ -1380,7 +1487,7 @@ CpuidDeterministicAddressTranslationParameters ( PRINT_BIT_FIELD (Ebx, Partitioning); PRINT_BIT_FIELD (Ebx, Way); - PRINT_VALUE (Ecx, NumberOfSets); + PRINT_VALUE (Ecx, NumberOfSets); PRINT_BIT_FIELD (Edx, TranslationCacheType); PRINT_BIT_FIELD (Edx, TranslationCacheLevel); @@ -1402,7 +1509,7 @@ CpuidExtendedFunction ( AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0); - PRINT_VALUE (Eax, MaximumExtendedFunction); + PRINT_VALUE (Eax, MaximumExtendedFunction); gMaximumExtendedFunction = Eax; } @@ -1456,7 +1563,7 @@ CpuidProcessorBrandString ( // 4 32-bit brand string values per leaf and an extra value to // null terminate the string. // - UINT32 BrandString[3 * 4 + 1]; + UINT32 BrandString[3 * 4 + 1]; if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) { AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); @@ -1583,11 +1690,11 @@ UefiMain ( CpuidVersionInfo (); CpuidCacheInfo (); CpuidSerialNumber (); - CpuidCacheParams(); + CpuidCacheParams (); CpuidMonitorMwait (); CpuidThermalPowerManagement (); CpuidStructuredExtendedFeatureFlags (); - CpuidDirectCacheAccessInfo(); + CpuidDirectCacheAccessInfo (); CpuidArchitecturalPerformanceMonitoring (); CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY); CpuidExtendedStateMainLeaf (); diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index efa0bc3308..00f3cb0957 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -13,15 +13,15 @@ // // Global Variables // -BOOLEAN InterruptState = FALSE; -EFI_HANDLE mCpuHandle = NULL; -BOOLEAN mIsFlushingGCD; -BOOLEAN mIsAllocatingPageTable = FALSE; -UINT64 mValidMtrrAddressMask; -UINT64 mValidMtrrBitsMask; -UINT64 mTimerPeriod = 0; - -FIXED_MTRR mFixedMtrrTable[] = { +BOOLEAN InterruptState = FALSE; +EFI_HANDLE mCpuHandle = NULL; +BOOLEAN mIsFlushingGCD; +BOOLEAN mIsAllocatingPageTable = FALSE; +UINT64 mValidMtrrAddressMask; +UINT64 mValidMtrrBitsMask; +UINT64 mTimerPeriod = 0; + +FIXED_MTRR mFixedMtrrTable[] = { { MSR_IA32_MTRR_FIX64K_00000, 0, @@ -79,7 +79,6 @@ FIXED_MTRR mFixedMtrrTable[] = { }, }; - EFI_CPU_ARCH_PROTOCOL gCpu = { CpuFlushCpuDataCache, CpuEnableInterrupt, @@ -115,10 +114,10 @@ EFI_CPU_ARCH_PROTOCOL gCpu = { EFI_STATUS EFIAPI CpuFlushCpuDataCache ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS Start, - IN UINT64 Length, - IN EFI_CPU_FLUSH_TYPE FlushType + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType ) { if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) { @@ -132,7 +131,6 @@ CpuFlushCpuDataCache ( } } - /** Enables CPU interrupts. @@ -145,7 +143,7 @@ CpuFlushCpuDataCache ( EFI_STATUS EFIAPI CpuEnableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This + IN EFI_CPU_ARCH_PROTOCOL *This ) { EnableInterrupts (); @@ -154,7 +152,6 @@ CpuEnableInterrupt ( return EFI_SUCCESS; } - /** Disables CPU interrupts. @@ -167,7 +164,7 @@ CpuEnableInterrupt ( EFI_STATUS EFIAPI CpuDisableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This + IN EFI_CPU_ARCH_PROTOCOL *This ) { DisableInterrupts (); @@ -176,7 +173,6 @@ CpuDisableInterrupt ( return EFI_SUCCESS; } - /** Return the state of interrupts. @@ -190,8 +186,8 @@ CpuDisableInterrupt ( EFI_STATUS EFIAPI CpuGetInterruptState ( - IN EFI_CPU_ARCH_PROTOCOL *This, - OUT BOOLEAN *State + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State ) { if (State == NULL) { @@ -202,7 +198,6 @@ CpuGetInterruptState ( return EFI_SUCCESS; } - /** Generates an INIT to the CPU. @@ -218,14 +213,13 @@ CpuGetInterruptState ( EFI_STATUS EFIAPI CpuInit ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_CPU_INIT_TYPE InitType + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType ) { return EFI_UNSUPPORTED; } - /** Registers a function to be called from the CPU interrupt handler. @@ -249,15 +243,14 @@ CpuInit ( EFI_STATUS EFIAPI CpuRegisterInterruptHandler ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ) { return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); } - /** Returns a timer value from one of the CPU's internal timers. There is no inherent time interval between ticks but is a function of the CPU frequency. @@ -284,14 +277,14 @@ CpuRegisterInterruptHandler ( EFI_STATUS EFIAPI CpuGetTimerValue ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN UINT32 TimerIndex, - OUT UINT64 *TimerValue, - OUT UINT64 *TimerPeriod OPTIONAL + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL ) { - UINT64 BeginValue; - UINT64 EndValue; + UINT64 BeginValue; + UINT64 EndValue; if (TimerValue == NULL) { return EFI_INVALID_PARAMETER; @@ -310,7 +303,7 @@ CpuGetTimerValue ( // BeginValue = AsmReadTsc (); MicroSecondDelay (100); - EndValue = AsmReadTsc (); + EndValue = AsmReadTsc (); // // Calculate the actual frequency // @@ -323,6 +316,7 @@ CpuGetTimerValue ( NULL ); } + *TimerPeriod = mTimerPeriod; } @@ -339,7 +333,7 @@ CpuGetTimerValue ( VOID EFIAPI SetMtrrsFromBuffer ( - IN VOID *Buffer + IN VOID *Buffer ) { MtrrSetAllMtrrs (Buffer); @@ -373,10 +367,10 @@ SetMtrrsFromBuffer ( EFI_STATUS EFIAPI CpuSetMemoryAttributes ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { RETURN_STATUS Status; @@ -395,7 +389,7 @@ CpuSetMemoryAttributes ( // to avoid unnecessary computing. // if (mIsFlushingGCD) { - DEBUG((DEBUG_VERBOSE, " Flushing GCD\n")); + DEBUG ((DEBUG_VERBOSE, " Flushing GCD\n")); return EFI_SUCCESS; } @@ -410,11 +404,11 @@ CpuSetMemoryAttributes ( // by page table memory allocation. // if (mIsAllocatingPageTable) { - DEBUG((DEBUG_VERBOSE, " Allocating page table memory\n")); + DEBUG ((DEBUG_VERBOSE, " Allocating page table memory\n")); return EFI_SUCCESS; } - CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK; + CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK; MemoryAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK; if (Attributes != (CacheAttributes | MemoryAttributes)) { @@ -427,30 +421,31 @@ CpuSetMemoryAttributes ( } switch (CacheAttributes) { - case EFI_MEMORY_UC: - CacheType = CacheUncacheable; - break; + case EFI_MEMORY_UC: + CacheType = CacheUncacheable; + break; - case EFI_MEMORY_WC: - CacheType = CacheWriteCombining; - break; + case EFI_MEMORY_WC: + CacheType = CacheWriteCombining; + break; - case EFI_MEMORY_WT: - CacheType = CacheWriteThrough; - break; + case EFI_MEMORY_WT: + CacheType = CacheWriteThrough; + break; - case EFI_MEMORY_WP: - CacheType = CacheWriteProtected; - break; + case EFI_MEMORY_WP: + CacheType = CacheWriteProtected; + break; - case EFI_MEMORY_WB: - CacheType = CacheWriteBack; - break; + case EFI_MEMORY_WB: + CacheType = CacheWriteBack; + break; - default: - return EFI_INVALID_PARAMETER; + default: + return EFI_INVALID_PARAMETER; } - CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress); + + CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress); if (CurrentCacheType != CacheType) { // // call MTRR library function @@ -484,7 +479,8 @@ CpuSetMemoryAttributes ( ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED); } } - if (EFI_ERROR(Status)) { + + if (EFI_ERROR (Status)) { return Status; } } @@ -507,15 +503,15 @@ InitializeMtrrMask ( VOID ) { - UINT32 RegEax; - UINT8 PhysicalAddressBits; + UINT32 RegEax; + UINT8 PhysicalAddressBits; AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000008) { AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits = (UINT8) RegEax; + PhysicalAddressBits = (UINT8)RegEax; } else { PhysicalAddressBits = 36; } @@ -536,22 +532,22 @@ InitializeMtrrMask ( **/ UINT64 GetMemorySpaceAttributeFromMtrrType ( - IN UINT8 MtrrAttributes + IN UINT8 MtrrAttributes ) { switch (MtrrAttributes) { - case MTRR_CACHE_UNCACHEABLE: - return EFI_MEMORY_UC; - case MTRR_CACHE_WRITE_COMBINING: - return EFI_MEMORY_WC; - case MTRR_CACHE_WRITE_THROUGH: - return EFI_MEMORY_WT; - case MTRR_CACHE_WRITE_PROTECTED: - return EFI_MEMORY_WP; - case MTRR_CACHE_WRITE_BACK: - return EFI_MEMORY_WB; - default: - return 0; + case MTRR_CACHE_UNCACHEABLE: + return EFI_MEMORY_UC; + case MTRR_CACHE_WRITE_COMBINING: + return EFI_MEMORY_WC; + case MTRR_CACHE_WRITE_THROUGH: + return EFI_MEMORY_WT; + case MTRR_CACHE_WRITE_PROTECTED: + return EFI_MEMORY_WP; + case MTRR_CACHE_WRITE_BACK: + return EFI_MEMORY_WB; + default: + return 0; } } @@ -575,29 +571,33 @@ GetMemorySpaceAttributeFromMtrrType ( **/ EFI_STATUS SearchGcdMemorySpaces ( - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN UINTN NumberOfDescriptors, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - OUT UINTN *StartIndex, - OUT UINTN *EndIndex + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN UINTN NumberOfDescriptors, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + OUT UINTN *StartIndex, + OUT UINTN *EndIndex ) { - UINTN Index; + UINTN Index; *StartIndex = 0; *EndIndex = 0; for (Index = 0; Index < NumberOfDescriptors; Index++) { - if (BaseAddress >= MemorySpaceMap[Index].BaseAddress && - BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { + if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) && + (BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) + { *StartIndex = Index; } - if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress && - BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { + + if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) && + (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) + { *EndIndex = Index; return EFI_SUCCESS; } } + return EFI_NOT_FOUND; } @@ -619,11 +619,11 @@ SearchGcdMemorySpaces ( **/ EFI_STATUS SetGcdMemorySpaceAttributes ( - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN UINTN NumberOfDescriptors, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, + IN UINTN NumberOfDescriptors, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { EFI_STATUS Status; @@ -655,6 +655,7 @@ SetGcdMemorySpaceAttributes ( if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { continue; } + // // Calculate the start and end address of the overlapping range // @@ -663,11 +664,13 @@ SetGcdMemorySpaceAttributes ( } else { RegionStart = MemorySpaceMap[Index].BaseAddress; } + if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { RegionLength = BaseAddress + Length - RegionStart; } else { RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; } + // // Set memory attributes according to MTRR attribute and the original attribute of descriptor // @@ -681,7 +684,6 @@ SetGcdMemorySpaceAttributes ( return EFI_SUCCESS; } - /** Refreshes the GCD Memory Space attributes according to MTRRs. @@ -693,22 +695,22 @@ RefreshMemoryAttributesFromMtrr ( VOID ) { - EFI_STATUS Status; - UINTN Index; - UINTN SubIndex; - UINT64 RegValue; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; - UINT64 Attributes; - UINT64 CurrentAttributes; - UINT8 MtrrType; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; - UINT64 DefaultAttributes; - VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; - MTRR_FIXED_SETTINGS MtrrFixedSettings; - UINT32 FirmwareVariableMtrrCount; - UINT8 DefaultMemoryType; + EFI_STATUS Status; + UINTN Index; + UINTN SubIndex; + UINT64 RegValue; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 Length; + UINT64 Attributes; + UINT64 CurrentAttributes; + UINT8 MtrrType; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + UINT64 DefaultAttributes; + VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; + MTRR_FIXED_SETTINGS MtrrFixedSettings; + UINT32 FirmwareVariableMtrrCount; + UINT8 DefaultMemoryType; FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount (); ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR); @@ -738,7 +740,7 @@ RefreshMemoryAttributesFromMtrr ( ); ASSERT_EFI_ERROR (Status); - DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType (); + DefaultMemoryType = (UINT8)MtrrGetDefaultMemoryType (); DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType); // @@ -748,6 +750,7 @@ RefreshMemoryAttributesFromMtrr ( if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { continue; } + gDS->SetMemorySpaceAttributes ( MemorySpaceMap[Index].BaseAddress, MemorySpaceMap[Index].Length, @@ -761,7 +764,8 @@ RefreshMemoryAttributesFromMtrr ( // for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { if (VariableMtrr[Index].Valid && - VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) { + (VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK)) + { SetGcdMemorySpaceAttributes ( MemorySpaceMap, NumberOfDescriptors, @@ -777,9 +781,10 @@ RefreshMemoryAttributesFromMtrr ( // for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { if (VariableMtrr[Index].Valid && - VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK && - VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) { - Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type); + (VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) && + (VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE)) + { + Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type); SetGcdMemorySpaceAttributes ( MemorySpaceMap, NumberOfDescriptors, @@ -795,7 +800,8 @@ RefreshMemoryAttributesFromMtrr ( // for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { if (VariableMtrr[Index].Valid && - VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) { + (VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE)) + { SetGcdMemorySpaceAttributes ( MemorySpaceMap, NumberOfDescriptors, @@ -819,7 +825,7 @@ RefreshMemoryAttributesFromMtrr ( // Check for continuous fixed MTRR sections // for (SubIndex = 0; SubIndex < 8; SubIndex++) { - MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8); + MtrrType = (UINT8)RShiftU64 (RegValue, SubIndex * 8); CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType); if (Length == 0) { // @@ -839,13 +845,15 @@ RefreshMemoryAttributesFromMtrr ( Attributes ); BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex; - Length = 0; - Attributes = CurrentAttributes; + Length = 0; + Attributes = CurrentAttributes; } } + Length += mFixedMtrrTable[Index].Length; } } + // // Handle the last fixed MTRR region // @@ -916,20 +924,20 @@ InitInterruptDescriptorTable ( VOID ) { - EFI_STATUS Status; - EFI_VECTOR_HANDOFF_INFO *VectorInfoList; - EFI_VECTOR_HANDOFF_INFO *VectorInfo; + EFI_STATUS Status; + EFI_VECTOR_HANDOFF_INFO *VectorInfoList; + EFI_VECTOR_HANDOFF_INFO *VectorInfo; VectorInfo = NULL; - Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList); - if (Status == EFI_SUCCESS && VectorInfoList != NULL) { + Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList); + if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) { VectorInfo = VectorInfoList; } + Status = InitializeCpuInterruptHandlers (VectorInfo); ASSERT_EFI_ERROR (Status); } - /** Callback function for idle events. @@ -941,8 +949,8 @@ InitInterruptDescriptorTable ( VOID EFIAPI IdleLoopEventCallback ( - IN EFI_EVENT Event, - IN VOID *Context + IN EFI_EVENT Event, + IN VOID *Context ) { CpuSleep (); @@ -989,24 +997,27 @@ IdleLoopEventCallback ( **/ EFI_STATUS IntersectMemoryDescriptor ( - IN UINT64 Base, - IN UINT64 Length, - IN UINT64 Capabilities, - IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor + IN UINT64 Base, + IN UINT64 Length, + IN UINT64 Capabilities, + IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor ) { - UINT64 IntersectionBase; - UINT64 IntersectionEnd; - EFI_STATUS Status; + UINT64 IntersectionBase; + UINT64 IntersectionEnd; + EFI_STATUS Status; - if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo && - (Descriptor->Capabilities & Capabilities) == Capabilities) { + if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) && + ((Descriptor->Capabilities & Capabilities) == Capabilities)) + { return EFI_SUCCESS; } IntersectionBase = MAX (Base, Descriptor->BaseAddress); - IntersectionEnd = MIN (Base + Length, - Descriptor->BaseAddress + Descriptor->Length); + IntersectionEnd = MIN ( + Base + Length, + Descriptor->BaseAddress + Descriptor->Length + ); if (IntersectionBase >= IntersectionEnd) { // // The descriptor and the aperture don't overlap. @@ -1015,21 +1026,39 @@ IntersectMemoryDescriptor ( } if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) { - Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, - IntersectionBase, IntersectionEnd - IntersectionBase, - Capabilities); - - DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, - "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__, - IntersectionBase, IntersectionEnd, Status)); + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + IntersectionBase, + IntersectionEnd - IntersectionBase, + Capabilities + ); + + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: %a: add [%Lx, %Lx): %r\n", + gEfiCallerBaseName, + __FUNCTION__, + IntersectionBase, + IntersectionEnd, + Status + )); return Status; } - DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts " - "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__, - Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length, - (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities, - Base, Base + Length, Capabilities)); + DEBUG (( + DEBUG_ERROR, + "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts " + "with aperture [%Lx, %Lx) cap %Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + Descriptor->BaseAddress, + Descriptor->BaseAddress + Descriptor->Length, + (UINT32)Descriptor->GcdMemoryType, + Descriptor->Capabilities, + Base, + Base + Length, + Capabilities + )); return EFI_INVALID_PARAMETER; } @@ -1046,49 +1075,60 @@ IntersectMemoryDescriptor ( **/ EFI_STATUS AddMemoryMappedIoSpace ( - IN UINT64 Base, - IN UINT64 Length, - IN UINT64 Capabilities + IN UINT64 Base, + IN UINT64 Length, + IN UINT64 Capabilities ) { - EFI_STATUS Status; - UINTN Index; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + EFI_STATUS Status; + UINTN Index; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n", - gEfiCallerBaseName, __FUNCTION__, Status)); + DEBUG (( + DEBUG_ERROR, + "%a: %a: GetMemorySpaceMap(): %r\n", + gEfiCallerBaseName, + __FUNCTION__, + Status + )); return Status; } for (Index = 0; Index < NumberOfDescriptors; Index++) { - Status = IntersectMemoryDescriptor (Base, Length, Capabilities, - &MemorySpaceMap[Index]); + Status = IntersectMemoryDescriptor ( + Base, + Length, + Capabilities, + &MemorySpaceMap[Index] + ); if (EFI_ERROR (Status)) { goto FreeMemorySpaceMap; } } DEBUG_CODE_BEGIN (); - // - // Make sure there are adjacent descriptors covering [Base, Base + Length). - // It is possible that they have not been merged; merging can be prevented - // by allocation and different capabilities. - // - UINT64 CheckBase; - EFI_STATUS CheckStatus; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; - - for (CheckBase = Base; - CheckBase < Base + Length; - CheckBase = Descriptor.BaseAddress + Descriptor.Length) { - CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor); - ASSERT_EFI_ERROR (CheckStatus); - ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo); - ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities); - } + // + // Make sure there are adjacent descriptors covering [Base, Base + Length). + // It is possible that they have not been merged; merging can be prevented + // by allocation and different capabilities. + // + UINT64 CheckBase; + EFI_STATUS CheckStatus; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; + + for (CheckBase = Base; + CheckBase < Base + Length; + CheckBase = Descriptor.BaseAddress + Descriptor.Length) + { + CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor); + ASSERT_EFI_ERROR (CheckStatus); + ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo); + ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities); + } + DEBUG_CODE_END (); FreeMemorySpaceMap: @@ -1105,14 +1145,14 @@ FreeMemorySpaceMap: **/ VOID AddLocalApicMemorySpace ( - IN EFI_HANDLE ImageHandle + IN EFI_HANDLE ImageHandle ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS BaseAddress; - BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress(); - Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC); + BaseAddress = (EFI_PHYSICAL_ADDRESS)GetLocalApicBaseAddress (); + Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC); ASSERT_EFI_ERROR (Status); // @@ -1130,8 +1170,13 @@ AddLocalApicMemorySpace ( NULL ); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n", - gEfiCallerBaseName, __FUNCTION__, Status)); + DEBUG (( + DEBUG_INFO, + "%a: %a: AllocateMemorySpace() Status - %r\n", + gEfiCallerBaseName, + __FUNCTION__, + Status + )); } } @@ -1149,14 +1194,14 @@ AddLocalApicMemorySpace ( EFI_STATUS EFIAPI InitializeCpu ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; EFI_EVENT IdleLoopEvent; - InitializePageTableLib(); + InitializePageTableLib (); InitializeFloatingPointUnits (); @@ -1180,7 +1225,8 @@ InitializeCpu ( // Status = gBS->InstallMultipleProtocolInterfaces ( &mCpuHandle, - &gEfiCpuArchProtocolGuid, &gCpu, + &gEfiCpuArchProtocolGuid, + &gCpu, NULL ); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h index 9771ec8336..2208671cb9 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.h +++ b/UefiCpuPkg/CpuDxe/CpuDxe.h @@ -63,10 +63,10 @@ EFI_STATUS EFIAPI CpuFlushCpuDataCache ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS Start, - IN UINT64 Length, - IN EFI_CPU_FLUSH_TYPE FlushType + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType ); /** @@ -81,7 +81,7 @@ CpuFlushCpuDataCache ( EFI_STATUS EFIAPI CpuEnableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This + IN EFI_CPU_ARCH_PROTOCOL *This ); /** @@ -96,7 +96,7 @@ CpuEnableInterrupt ( EFI_STATUS EFIAPI CpuDisableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This + IN EFI_CPU_ARCH_PROTOCOL *This ); /** @@ -112,8 +112,8 @@ CpuDisableInterrupt ( EFI_STATUS EFIAPI CpuGetInterruptState ( - IN EFI_CPU_ARCH_PROTOCOL *This, - OUT BOOLEAN *State + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State ); /** @@ -131,8 +131,8 @@ CpuGetInterruptState ( EFI_STATUS EFIAPI CpuInit ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_CPU_INIT_TYPE InitType + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType ); /** @@ -158,9 +158,9 @@ CpuInit ( EFI_STATUS EFIAPI CpuRegisterInterruptHandler ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ); /** @@ -189,10 +189,10 @@ CpuRegisterInterruptHandler ( EFI_STATUS EFIAPI CpuGetTimerValue ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN UINT32 TimerIndex, - OUT UINT64 *TimerValue, - OUT UINT64 *TimerPeriod OPTIONAL + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL ); /** @@ -214,10 +214,10 @@ CpuGetTimerValue ( EFI_STATUS EFIAPI CpuSetMemoryAttributes ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); /** @@ -238,7 +238,7 @@ InitGlobalDescriptorTable ( VOID EFIAPI SetCodeSelector ( - UINT16 Selector + UINT16 Selector ); /** @@ -250,7 +250,7 @@ SetCodeSelector ( VOID EFIAPI SetDataSelectors ( - UINT16 Selector + UINT16 Selector ); /** @@ -273,8 +273,8 @@ RefreshGcdMemoryAttributesFromPaging ( VOID EFIAPI DebugExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ); /** @@ -289,12 +289,11 @@ DebugExceptionHandler ( VOID EFIAPI PageFaultExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ); -extern BOOLEAN mIsAllocatingPageTable; -extern UINTN mNumberOfProcessors; +extern BOOLEAN mIsAllocatingPageTable; +extern UINTN mNumberOfProcessors; #endif - diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 692402c55d..cf571138e5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -13,7 +13,7 @@ // // Global descriptor table (GDT) Template // -STATIC GDT_ENTRIES mGdtTemplate = { +STATIC GDT_ENTRIES mGdtTemplate = { // // NULL_SEL // @@ -143,7 +143,7 @@ InitGlobalDescriptorTable ( ); ASSERT_EFI_ERROR (Status); ASSERT ((Memory != 0) && (Memory < SIZE_4GB)); - Gdt = (GDT_ENTRIES *) (UINTN) Memory; + Gdt = (GDT_ENTRIES *)(UINTN)Memory; // // Initialize all GDT entries @@ -153,8 +153,8 @@ InitGlobalDescriptorTable ( // // Write GDT register // - Gdtr.Base = (UINT32) (UINTN) Gdt; - Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1); + Gdtr.Base = (UINT32)(UINTN)Gdt; + Gdtr.Limit = (UINT16)(sizeof (mGdtTemplate) - 1); AsmWriteGdtr (&Gdtr); // diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 1c94487cbe..b09f15725a 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -21,48 +21,47 @@ // typedef struct _GDT_ENTRY { - UINT16 Limit15_0; - UINT16 Base15_0; - UINT8 Base23_16; - UINT8 Type; - UINT8 Limit19_16_and_flags; - UINT8 Base31_24; + UINT16 Limit15_0; + UINT16 Base15_0; + UINT8 Base23_16; + UINT8 Type; + UINT8 Limit19_16_and_flags; + UINT8 Base31_24; } GDT_ENTRY; typedef -struct _GDT_ENTRIES { - GDT_ENTRY Null; - GDT_ENTRY Linear; - GDT_ENTRY LinearCode; - GDT_ENTRY SysData; - GDT_ENTRY SysCode; - GDT_ENTRY SysCode16; - GDT_ENTRY LinearData64; - GDT_ENTRY LinearCode64; - GDT_ENTRY Spare5; + struct _GDT_ENTRIES { + GDT_ENTRY Null; + GDT_ENTRY Linear; + GDT_ENTRY LinearCode; + GDT_ENTRY SysData; + GDT_ENTRY SysCode; + GDT_ENTRY SysCode16; + GDT_ENTRY LinearData64; + GDT_ENTRY LinearCode64; + GDT_ENTRY Spare5; } GDT_ENTRIES; #pragma pack () -#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null) -#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear) -#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) -#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) -#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) -#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) -#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) -#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) +#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null) +#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear) +#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) +#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) +#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) +#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) +#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) +#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) #if defined (MDE_CPU_IA32) -#define CPU_CODE_SEL LINEAR_CODE_SEL -#define CPU_DATA_SEL LINEAR_SEL +#define CPU_CODE_SEL LINEAR_CODE_SEL +#define CPU_DATA_SEL LINEAR_SEL #elif defined (MDE_CPU_X64) -#define CPU_CODE_SEL LINEAR_CODE64_SEL -#define CPU_DATA_SEL LINEAR_DATA64_SEL +#define CPU_CODE_SEL LINEAR_CODE64_SEL +#define CPU_DATA_SEL LINEAR_DATA64_SEL #else -#error CPU type not supported for CPU GDT initialization! + #error CPU type not supported for CPU GDT initialization! #endif #endif // _CPU_GDT_H_ - diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c index 60ede38df4..1f218367b3 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.c +++ b/UefiCpuPkg/CpuDxe/CpuMp.c @@ -9,8 +9,8 @@ #include "CpuDxe.h" #include "CpuMp.h" -EFI_HANDLE mMpServiceHandle = NULL; -UINTN mNumberOfProcessors = 1; +EFI_HANDLE mMpServiceHandle = NULL; +UINTN mNumberOfProcessors = 1; EFI_MP_SERVICES_PROTOCOL mMpServicesTemplate = { GetNumberOfProcessors, @@ -509,7 +509,7 @@ WhoAmI ( OUT UINTN *ProcessorNumber ) { - return MpInitLibWhoAmI (ProcessorNumber);; + return MpInitLibWhoAmI (ProcessorNumber); } /** @@ -547,8 +547,8 @@ CollectBistDataFromHob ( // Sec Platform Information2 PPI includes BSP/APs' BIST information // SecPlatformInformation2 = GET_GUID_HOB_DATA (GuidHob); - NumberOfData = SecPlatformInformation2->NumberOfCpus; - CpuInstance = SecPlatformInformation2->CpuInstance; + NumberOfData = SecPlatformInformation2->NumberOfCpus; + CpuInstance = SecPlatformInformation2->CpuInstance; } else { // // Otherwise, get gEfiSecPlatformInformationPpiGuid Guided HOB @@ -556,14 +556,14 @@ CollectBistDataFromHob ( GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); if (GuidHob != NULL) { SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob); - NumberOfData = 1; + NumberOfData = 1; // // SEC Platform Information only includes BSP's BIST information // does not have BSP's APIC ID // - BspCpuInstance.CpuLocation = GetApicId (); - BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; - CpuInstance = &BspCpuInstance; + BspCpuInstance.CpuLocation = GetApicId (); + BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; + CpuInstance = &BspCpuInstance; } else { DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n")); // @@ -583,6 +583,7 @@ CollectBistDataFromHob ( BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags; } } + if (BistData.Uint32 != 0) { // // Report Status Code that self test is failed @@ -607,7 +608,7 @@ CollectBistDataFromHob ( VOID EFIAPI GetGdtr ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); @@ -625,12 +626,12 @@ GetGdtr ( VOID EFIAPI InitializeExceptionStackSwitchHandlers ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + CPU_EXCEPTION_INIT_DATA *EssData; + IA32_DESCRIPTOR Idtr; + EFI_STATUS Status; EssData = Buffer; // @@ -638,9 +639,9 @@ InitializeExceptionStackSwitchHandlers ( // the AP's IDT is the same as BSP's IDT either. // AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable = (VOID *)Idtr.Base; + EssData->Ia32.IdtTable = (VOID *)Idtr.Base; EssData->Ia32.IdtTableSize = Idtr.Limit + 1; - Status = InitializeCpuExceptionHandlersEx (NULL, EssData); + Status = InitializeCpuExceptionHandlersEx (NULL, EssData); ASSERT_EFI_ERROR (Status); } @@ -656,19 +657,19 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; + UINTN Index; + UINTN Bsp; + UINTN ExceptionNumber; + UINTN OldGdtSize; + UINTN NewGdtSize; + UINTN NewStackSize; + IA32_DESCRIPTOR Gdtr; + CPU_EXCEPTION_INIT_DATA EssData; + UINT8 *GdtBuffer; + UINT8 *StackTop; ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; StackTop = AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors); ASSERT (StackTop != NULL); @@ -678,17 +679,17 @@ InitializeMpExceptionStackSwitchHandlers ( // The default exception handlers must have been initialized. Let's just skip // it in this method. // - EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; + EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.InitDefaultHandlers = FALSE; - EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); + EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; - EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); + EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize); // // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // - Gdtr.Base = 0; + Gdtr.Base = 0; Gdtr.Limit = 0; MpInitLibWhoAmI (&Bsp); for (Index = 0; Index < mNumberOfProcessors; ++Index) { @@ -733,7 +734,7 @@ InitializeMpExceptionStackSwitchHandlers ( // | | // -------------------------------- // - OldGdtSize = Gdtr.Limit + 1; + OldGdtSize = Gdtr.Limit + 1; EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1); EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) * @@ -749,19 +750,21 @@ InitializeMpExceptionStackSwitchHandlers ( // // Make sure GDT table alignment // - EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); - NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); + EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); + NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize); - EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + - EssData.Ia32.ExceptionTssDescSize); + EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + + EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; - DEBUG ((DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", - (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop)); + DEBUG (( + DEBUG_INFO, + "Exception stack top[cpu%lu]: 0x%lX\n", + (UINT64)(UINTN)Index, + (UINT64)(UINTN)StackTop + )); if (Index == Bsp) { InitializeExceptionStackSwitchHandlers (&EssData); @@ -776,7 +779,7 @@ InitializeMpExceptionStackSwitchHandlers ( ); } - StackTop -= NewStackSize; + StackTop -= NewStackSize; } } @@ -815,9 +818,9 @@ InitializeMpSupport ( VOID ) { - EFI_STATUS Status; - UINTN NumberOfProcessors; - UINTN NumberOfEnabledProcessors; + EFI_STATUS Status; + UINTN NumberOfProcessors; + UINTN NumberOfEnabledProcessors; // // Wakeup APs to do initialization @@ -841,9 +844,9 @@ InitializeMpSupport ( Status = gBS->InstallMultipleProtocolInterfaces ( &mMpServiceHandle, - &gEfiMpServiceProtocolGuid, &mMpServicesTemplate, + &gEfiMpServiceProtocolGuid, + &mMpServicesTemplate, NULL ); ASSERT_EFI_ERROR (Status); } - diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h index 4ee171d8c4..b461753510 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.h +++ b/UefiCpuPkg/CpuDxe/CpuMp.h @@ -467,4 +467,3 @@ WhoAmI ( ); #endif // _CPU_MP_H_ - diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c index c34059f87f..d9e65ab4b2 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -24,27 +24,27 @@ /// /// Page Table Entry /// -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_U BIT2 -#define IA32_PG_WT BIT3 -#define IA32_PG_CD BIT4 -#define IA32_PG_A BIT5 -#define IA32_PG_D BIT6 -#define IA32_PG_PS BIT7 -#define IA32_PG_PAT_2M BIT12 -#define IA32_PG_PAT_4K IA32_PG_PS -#define IA32_PG_PMNT BIT62 -#define IA32_PG_NX BIT63 - -#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P) +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_U BIT2 +#define IA32_PG_WT BIT3 +#define IA32_PG_CD BIT4 +#define IA32_PG_A BIT5 +#define IA32_PG_D BIT6 +#define IA32_PG_PS BIT7 +#define IA32_PG_PAT_2M BIT12 +#define IA32_PG_PAT_4K IA32_PG_PS +#define IA32_PG_PMNT BIT62 +#define IA32_PG_NX BIT63 + +#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P) // // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE // X64 PAE PDPTE does not have such restriction // -#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P) +#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P) -#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS) +#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS) #define PAGING_4K_MASK 0xFFF #define PAGING_2M_MASK 0x1FFFFF @@ -52,9 +52,9 @@ #define PAGING_PAE_INDEX_MASK 0x1FF -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull #define MAX_PF_ENTRY_COUNT 10 #define MAX_DEBUG_MESSAGE_LENGTH 0x100 @@ -68,9 +68,9 @@ typedef enum { } PAGE_ATTRIBUTE; typedef struct { - PAGE_ATTRIBUTE Attribute; - UINT64 Length; - UINT64 AddressMask; + PAGE_ATTRIBUTE Attribute; + UINT64 Length; + UINT64 AddressMask; } PAGE_ATTRIBUTE_TABLE; typedef enum { @@ -79,21 +79,21 @@ typedef enum { PageActionClear, } PAGE_ACTION; -PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { - {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, - {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, - {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, +PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { + { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 }, + { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 }, + { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, }; -PAGE_TABLE_POOL *mPageTablePool = NULL; -BOOLEAN mPageTablePoolLock = FALSE; -PAGE_TABLE_LIB_PAGING_CONTEXT mPagingContext; -EFI_SMM_BASE2_PROTOCOL *mSmmBase2 = NULL; +PAGE_TABLE_POOL *mPageTablePool = NULL; +BOOLEAN mPageTablePoolLock = FALSE; +PAGE_TABLE_LIB_PAGING_CONTEXT mPagingContext; +EFI_SMM_BASE2_PROTOCOL *mSmmBase2 = NULL; // // Record the page fault exception count for one instruction execution. // -UINTN *mPFEntryCount; +UINTN *mPFEntryCount; UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT]; /** @@ -119,7 +119,7 @@ IsInSmm ( VOID ) { - BOOLEAN InSmm; + BOOLEAN InSmm; InSmm = FALSE; if (mSmmBase2 == NULL) { @@ -137,7 +137,7 @@ IsInSmm ( // load its own page table. // return (InSmm && - mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3()); + mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3 ()); } /** @@ -147,23 +147,23 @@ IsInSmm ( **/ VOID GetCurrentPagingContext ( - IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext + IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext ) { - UINT32 RegEax; - CPUID_EXTENDED_CPU_SIG_EDX RegEdx; - MSR_IA32_EFER_REGISTER MsrEfer; - IA32_CR4 Cr4; - IA32_CR0 Cr0; - UINT32 *Attributes; - UINTN *PageTableBase; + UINT32 RegEax; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + MSR_IA32_EFER_REGISTER MsrEfer; + IA32_CR4 Cr4; + IA32_CR0 Cr0; + UINT32 *Attributes; + UINTN *PageTableBase; // // Don't retrieve current paging context from processor if in SMM mode. // if (!IsInSmm ()) { - ZeroMem (&mPagingContext, sizeof(mPagingContext)); - if (sizeof(UINTN) == sizeof(UINT64)) { + ZeroMem (&mPagingContext, sizeof (mPagingContext)); + if (sizeof (UINTN) == sizeof (UINT64)) { mPagingContext.MachineType = IMAGE_FILE_MACHINE_X64; } else { mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386; @@ -179,15 +179,19 @@ GetCurrentPagingContext ( } else { *PageTableBase = 0; } + if (Cr0.Bits.WP != 0) { *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; } + if (Cr4.Bits.PSE != 0) { *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE; } + if (Cr4.Bits.PAE != 0) { *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE; } + if (Cr4.Bits.LA57 != 0) { *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL; } @@ -198,7 +202,7 @@ GetCurrentPagingContext ( if (RegEdx.Bits.NX != 0) { // XD supported - MsrEfer.Uint64 = AsmReadMsr64(MSR_CORE_IA32_EFER); + MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER); if (MsrEfer.Bits.NXE != 0) { // XD activated *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; @@ -231,11 +235,13 @@ PageAttributeToLength ( ) { UINTN Index; - for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) { + + for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) { if (PageAttribute == mPageAttributeTable[Index].Attribute) { return (UINTN)mPageAttributeTable[Index].Length; } } + return 0; } @@ -252,11 +258,13 @@ PageAttributeToMask ( ) { UINTN Index; - for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) { + + for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) { if (PageAttribute == mPageAttributeTable[Index].Attribute) { return (UINTN)mPageAttributeTable[Index].AddressMask; } } + return 0; } @@ -271,22 +279,22 @@ PageAttributeToMask ( **/ VOID * GetPageTableEntry ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, - IN PHYSICAL_ADDRESS Address, - OUT PAGE_ATTRIBUTE *PageAttribute + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, + IN PHYSICAL_ADDRESS Address, + OUT PAGE_ATTRIBUTE *PageAttribute ) { - UINTN Index1; - UINTN Index2; - UINTN Index3; - UINTN Index4; - UINTN Index5; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINT64 *L4PageTable; - UINT64 *L5PageTable; - UINT64 AddressEncMask; + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINTN Index5; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + UINT64 *L5PageTable; + UINT64 AddressEncMask; ASSERT (PagingContext != NULL); @@ -312,6 +320,7 @@ GetPageTableEntry ( } else { L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase; } + if (L4PageTable[Index4] == 0) { *PageAttribute = PageNone; return NULL; @@ -319,13 +328,15 @@ GetPageTableEntry ( L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64); } else { - ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0); + ASSERT ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0); L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase; } + if (L3PageTable[Index3] == 0) { *PageAttribute = PageNone; return NULL; } + if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { // 1G *PageAttribute = Page1G; @@ -337,6 +348,7 @@ GetPageTableEntry ( *PageAttribute = PageNone; return NULL; } + if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { // 2M *PageAttribute = Page2M; @@ -349,6 +361,7 @@ GetPageTableEntry ( *PageAttribute = PageNone; return NULL; } + *PageAttribute = Page4K; return &L1PageTable[Index1]; } @@ -362,20 +375,24 @@ GetPageTableEntry ( **/ UINT64 GetAttributesFromPageEntry ( - IN UINT64 *PageEntry + IN UINT64 *PageEntry ) { UINT64 Attributes; + Attributes = 0; if ((*PageEntry & IA32_PG_P) == 0) { Attributes |= EFI_MEMORY_RP; } + if ((*PageEntry & IA32_PG_RW) == 0) { Attributes |= EFI_MEMORY_RO; } + if ((*PageEntry & IA32_PG_NX) != 0) { Attributes |= EFI_MEMORY_XP; } + return Attributes; } @@ -390,11 +407,11 @@ GetAttributesFromPageEntry ( **/ VOID ConvertPageEntryAttribute ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, - IN UINT64 *PageEntry, - IN UINT64 Attributes, - IN PAGE_ACTION PageAction, - OUT BOOLEAN *IsModified + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, + IN UINT64 *PageEntry, + IN UINT64 Attributes, + IN PAGE_ACTION PageAction, + OUT BOOLEAN *IsModified ) { UINT64 CurrentPageEntry; @@ -402,45 +419,46 @@ ConvertPageEntryAttribute ( UINT32 *PageAttributes; CurrentPageEntry = *PageEntry; - NewPageEntry = CurrentPageEntry; + NewPageEntry = CurrentPageEntry; if ((Attributes & EFI_MEMORY_RP) != 0) { switch (PageAction) { - case PageActionAssign: - case PageActionSet: - NewPageEntry &= ~(UINT64)IA32_PG_P; - break; - case PageActionClear: - NewPageEntry |= IA32_PG_P; - break; + case PageActionAssign: + case PageActionSet: + NewPageEntry &= ~(UINT64)IA32_PG_P; + break; + case PageActionClear: + NewPageEntry |= IA32_PG_P; + break; } } else { switch (PageAction) { - case PageActionAssign: - NewPageEntry |= IA32_PG_P; - break; - case PageActionSet: - case PageActionClear: - break; + case PageActionAssign: + NewPageEntry |= IA32_PG_P; + break; + case PageActionSet: + case PageActionClear: + break; } } + if ((Attributes & EFI_MEMORY_RO) != 0) { switch (PageAction) { - case PageActionAssign: - case PageActionSet: - NewPageEntry &= ~(UINT64)IA32_PG_RW; - break; - case PageActionClear: - NewPageEntry |= IA32_PG_RW; - break; + case PageActionAssign: + case PageActionSet: + NewPageEntry &= ~(UINT64)IA32_PG_RW; + break; + case PageActionClear: + NewPageEntry |= IA32_PG_RW; + break; } } else { switch (PageAction) { - case PageActionAssign: - NewPageEntry |= IA32_PG_RW; - break; - case PageActionSet: - case PageActionClear: - break; + case PageActionAssign: + NewPageEntry |= IA32_PG_RW; + break; + case PageActionSet: + case PageActionClear: + break; } } @@ -449,25 +467,26 @@ ConvertPageEntryAttribute ( if ((*PageAttributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) != 0) { if ((Attributes & EFI_MEMORY_XP) != 0) { switch (PageAction) { - case PageActionAssign: - case PageActionSet: - NewPageEntry |= IA32_PG_NX; - break; - case PageActionClear: - NewPageEntry &= ~IA32_PG_NX; - break; + case PageActionAssign: + case PageActionSet: + NewPageEntry |= IA32_PG_NX; + break; + case PageActionClear: + NewPageEntry &= ~IA32_PG_NX; + break; } } else { switch (PageAction) { - case PageActionAssign: - NewPageEntry &= ~IA32_PG_NX; - break; - case PageActionSet: - case PageActionClear: - break; + case PageActionAssign: + NewPageEntry &= ~IA32_PG_NX; + break; + case PageActionSet: + case PageActionClear: + break; } } } + *PageEntry = NewPageEntry; if (CurrentPageEntry != NewPageEntry) { *IsModified = TRUE; @@ -490,13 +509,13 @@ ConvertPageEntryAttribute ( **/ PAGE_ATTRIBUTE NeedSplitPage ( - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute ) { - UINT64 PageEntryLength; + UINT64 PageEntryLength; PageEntryLength = PageAttributeToLength (PageAttribute); @@ -525,16 +544,16 @@ NeedSplitPage ( **/ RETURN_STATUS SplitPage ( - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute, - IN PAGE_ATTRIBUTE SplitAttribute, - IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute, + IN PAGE_ATTRIBUTE SplitAttribute, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc ) { - UINT64 BaseAddress; - UINT64 *NewPageEntry; - UINTN Index; - UINT64 AddressEncMask; + UINT64 BaseAddress; + UINT64 *NewPageEntry; + UINTN Index; + UINT64 AddressEncMask; ASSERT (PageAttribute == Page2M || PageAttribute == Page1G); @@ -555,10 +574,12 @@ SplitPage ( if (NewPageEntry == NULL) { return RETURN_OUT_OF_RESOURCES; } + BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64; - for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); return RETURN_SUCCESS; } else { @@ -570,16 +591,18 @@ SplitPage ( // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table. // ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K); - if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) { + if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) { NewPageEntry = AllocatePagesFunc (1); DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); if (NewPageEntry == NULL) { return RETURN_OUT_OF_RESOURCES; } + BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64; - for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); return RETURN_SUCCESS; } else { @@ -603,14 +626,16 @@ IsReadOnlyPageWriteProtected ( ) { IA32_CR0 Cr0; + // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { Cr0.UintN = AsmReadCr0 (); - return (BOOLEAN) (Cr0.Bits.WP != 0); + return (BOOLEAN)(Cr0.Bits.WP != 0); } + return FALSE; } @@ -623,12 +648,13 @@ DisableReadOnlyPageWriteProtect ( ) { IA32_CR0 Cr0; + // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { - Cr0.UintN = AsmReadCr0 (); + Cr0.UintN = AsmReadCr0 (); Cr0.Bits.WP = 0; AsmWriteCr0 (Cr0.UintN); } @@ -643,12 +669,13 @@ EnableReadOnlyPageWriteProtect ( ) { IA32_CR0 Cr0; + // // To avoid unforseen consequences, don't touch paging settings in SMM mode // in this driver. // if (!IsInSmm ()) { - Cr0.UintN = AsmReadCr0 (); + Cr0.UintN = AsmReadCr0 (); Cr0.Bits.WP = 1; AsmWriteCr0 (Cr0.UintN); } @@ -685,33 +712,35 @@ EnableReadOnlyPageWriteProtect ( **/ RETURN_STATUS ConvertMemoryPageAttributes ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN PAGE_ACTION PageAction, - IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL, - OUT BOOLEAN *IsSplitted OPTIONAL, - OUT BOOLEAN *IsModified OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_ACTION PageAction, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL, + OUT BOOLEAN *IsSplitted OPTIONAL, + OUT BOOLEAN *IsModified OPTIONAL ) { - PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; - UINT64 *PageEntry; - PAGE_ATTRIBUTE PageAttribute; - UINTN PageEntryLength; - PAGE_ATTRIBUTE SplitAttribute; - RETURN_STATUS Status; - BOOLEAN IsEntryModified; - BOOLEAN IsWpEnabled; + PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; + UINT64 *PageEntry; + PAGE_ATTRIBUTE PageAttribute; + UINTN PageEntryLength; + PAGE_ATTRIBUTE SplitAttribute; + RETURN_STATUS Status; + BOOLEAN IsEntryModified; + BOOLEAN IsWpEnabled; if ((BaseAddress & (SIZE_4KB - 1)) != 0) { DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress)); return EFI_UNSUPPORTED; } + if ((Length & (SIZE_4KB - 1)) != 0) { DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length)); return EFI_UNSUPPORTED; } + if (Length == 0) { DEBUG ((DEBUG_ERROR, "Length is 0!\n")); return RETURN_INVALID_PARAMETER; @@ -725,44 +754,50 @@ ConvertMemoryPageAttributes ( if (PagingContext == NULL) { GetCurrentPagingContext (&CurrentPagingContext); } else { - CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingContext)); + CopyMem (&CurrentPagingContext, PagingContext, sizeof (CurrentPagingContext)); } - switch(CurrentPagingContext.MachineType) { - case IMAGE_FILE_MACHINE_I386: - if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) { - if (Attributes == 0) { - return EFI_SUCCESS; - } else { - DEBUG ((DEBUG_ERROR, "PageTable is 0!\n")); + + switch (CurrentPagingContext.MachineType) { + case IMAGE_FILE_MACHINE_I386: + if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) { + if (Attributes == 0) { + return EFI_SUCCESS; + } else { + DEBUG ((DEBUG_ERROR, "PageTable is 0!\n")); + return EFI_UNSUPPORTED; + } + } + + if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) { + DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n")); return EFI_UNSUPPORTED; } - } - if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) { - DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n")); - return EFI_UNSUPPORTED; - } - if ((BaseAddress + Length) > BASE_4GB) { - DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n")); + + if ((BaseAddress + Length) > BASE_4GB) { + DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n")); + return EFI_UNSUPPORTED; + } + + break; + case IMAGE_FILE_MACHINE_X64: + ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0); + break; + default: + ASSERT (FALSE); return EFI_UNSUPPORTED; - } - break; - case IMAGE_FILE_MACHINE_X64: - ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0); - break; - default: - ASSERT(FALSE); - return EFI_UNSUPPORTED; - break; + break; } -// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); + // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); if (IsSplitted != NULL) { *IsSplitted = FALSE; } + if (IsModified != NULL) { *IsModified = FALSE; } + if (AllocatePagesFunc == NULL) { AllocatePagesFunc = AllocatePageTableMemory; } @@ -785,8 +820,9 @@ ConvertMemoryPageAttributes ( Status = RETURN_UNSUPPORTED; goto Done; } + PageEntryLength = PageAttributeToLength (PageAttribute); - SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); + SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); if (SplitAttribute == PageNone) { ConvertPageEntryAttribute (&CurrentPagingContext, PageEntry, Attributes, PageAction, &IsEntryModified); if (IsEntryModified) { @@ -794,27 +830,32 @@ ConvertMemoryPageAttributes ( *IsModified = TRUE; } } + // // Convert success, move to next // BaseAddress += PageEntryLength; - Length -= PageEntryLength; + Length -= PageEntryLength; } else { if (AllocatePagesFunc == NULL) { Status = RETURN_UNSUPPORTED; goto Done; } + Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc); if (RETURN_ERROR (Status)) { Status = RETURN_UNSUPPORTED; goto Done; } + if (IsSplitted != NULL) { *IsSplitted = TRUE; } + if (IsModified != NULL) { *IsModified = TRUE; } + // // Just split current page // Convert success in next around @@ -829,6 +870,7 @@ Done: if (IsWpEnabled) { EnableReadOnlyPageWriteProtect (); } + return Status; } @@ -863,20 +905,20 @@ Done: RETURN_STATUS EFIAPI AssignMemoryPageAttributes ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL ) { RETURN_STATUS Status; BOOLEAN IsModified; BOOLEAN IsSplitted; -// DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes)); + // DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes)); Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { if ((PagingContext == NULL) && IsModified) { // // Flush TLB as last step. @@ -885,7 +927,7 @@ AssignMemoryPageAttributes ( // TLB flush in MWAIT loop mode, there's no need to flush TLB for them // here. // - CpuFlushTlb(); + CpuFlushTlb (); } } @@ -900,7 +942,7 @@ IsExecuteDisableEnabled ( VOID ) { - MSR_CORE_IA32_EFER_REGISTER MsrEfer; + MSR_CORE_IA32_EFER_REGISTER MsrEfer; MsrEfer.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); return (MsrEfer.Bits.NXE == 1); @@ -914,21 +956,21 @@ RefreshGcdMemoryAttributesFromPaging ( VOID ) { - EFI_STATUS Status; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; - PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext; - PAGE_ATTRIBUTE PageAttribute; - UINT64 *PageEntry; - UINT64 PageLength; - UINT64 MemorySpaceLength; - UINT64 Length; - UINT64 BaseAddress; - UINT64 PageStartAddress; - UINT64 Attributes; - UINT64 Capabilities; - UINT64 NewAttributes; - UINTN Index; + EFI_STATUS Status; + UINTN NumberOfDescriptors; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext; + PAGE_ATTRIBUTE PageAttribute; + UINT64 *PageEntry; + UINT64 PageLength; + UINT64 MemorySpaceLength; + UINT64 Length; + UINT64 BaseAddress; + UINT64 PageStartAddress; + UINT64 Attributes; + UINT64 Capabilities; + UINT64 NewAttributes; + UINTN Index; // // Assuming that memory space map returned is sorted already; otherwise sort @@ -939,10 +981,10 @@ RefreshGcdMemoryAttributesFromPaging ( GetCurrentPagingContext (&PagingContext); - Attributes = 0; - NewAttributes = 0; - BaseAddress = 0; - PageLength = 0; + Attributes = 0; + NewAttributes = 0; + BaseAddress = 0; + PageLength = 0; if (IsExecuteDisableEnabled ()) { Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP; @@ -975,7 +1017,8 @@ RefreshGcdMemoryAttributesFromPaging ( DEBUG (( DEBUG_WARN, "Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n", - (UINT64)Index, MemorySpaceMap[Index].BaseAddress, + (UINT64)Index, + MemorySpaceMap[Index].BaseAddress, MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1, MemorySpaceMap[Index].Capabilities, MemorySpaceMap[Index].Capabilities | Capabilities @@ -1011,14 +1054,15 @@ RefreshGcdMemoryAttributesFromPaging ( // // Note current memory space might start in the middle of a page // - PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask(PageAttribute); - PageLength = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress); - Attributes = GetAttributesFromPageEntry (PageEntry); + PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask (PageAttribute); + PageLength = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress); + Attributes = GetAttributesFromPageEntry (PageEntry); } Length = MIN (PageLength, MemorySpaceLength); if (Attributes != (MemorySpaceMap[Index].Attributes & - EFI_MEMORY_ATTRIBUTE_MASK)) { + EFI_MEMORY_ATTRIBUTE_MASK)) + { NewAttributes = (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_ATTRIBUTE_MASK) | Attributes; Status = gDS->SetMemorySpaceAttributes ( @@ -1030,7 +1074,9 @@ RefreshGcdMemoryAttributesFromPaging ( DEBUG (( DEBUG_VERBOSE, "Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n", - (UINT64)Index, BaseAddress, BaseAddress + Length - 1, + (UINT64)Index, + BaseAddress, + BaseAddress + Length - 1, MemorySpaceMap[Index].Attributes, NewAttributes )); @@ -1064,11 +1110,11 @@ RefreshGcdMemoryAttributesFromPaging ( **/ BOOLEAN InitializePageTablePool ( - IN UINTN PoolPages + IN UINTN PoolPages ) { - VOID *Buffer; - BOOLEAN IsModified; + VOID *Buffer; + BOOLEAN IsModified; // // Do not allow re-entrance. @@ -1078,15 +1124,15 @@ InitializePageTablePool ( } mPageTablePoolLock = TRUE; - IsModified = FALSE; + IsModified = FALSE; // // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for // header. // PoolPages += 1; // Add one page for header. - PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) * - PAGE_TABLE_POOL_UNIT_PAGES; + PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) * + PAGE_TABLE_POOL_UNIT_PAGES; Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT); if (Buffer == NULL) { DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n")); @@ -1103,19 +1149,19 @@ InitializePageTablePool ( // Link all pools into a list for easier track later. // if (mPageTablePool == NULL) { - mPageTablePool = Buffer; + mPageTablePool = Buffer; mPageTablePool->NextPool = mPageTablePool; } else { ((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool; - mPageTablePool->NextPool = Buffer; - mPageTablePool = Buffer; + mPageTablePool->NextPool = Buffer; + mPageTablePool = Buffer; } // // Reserve one page for pool header. // - mPageTablePool->FreePages = PoolPages - 1; - mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1); + mPageTablePool->FreePages = PoolPages - 1; + mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1); // // Mark the whole pool pages as read-only. @@ -1157,10 +1203,10 @@ Done: VOID * EFIAPI AllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ) { - VOID *Buffer; + VOID *Buffer; if (Pages == 0) { return NULL; @@ -1169,8 +1215,9 @@ AllocatePageTableMemory ( // // Renew the pool if necessary. // - if (mPageTablePool == NULL || - Pages > mPageTablePool->FreePages) { + if ((mPageTablePool == NULL) || + (Pages > mPageTablePool->FreePages)) + { if (!InitializePageTablePool (Pages)) { return NULL; } @@ -1178,8 +1225,8 @@ AllocatePageTableMemory ( Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset; - mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages); - mPageTablePool->FreePages -= Pages; + mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages); + mPageTablePool->FreePages -= Pages; return Buffer; } @@ -1196,13 +1243,13 @@ AllocatePageTableMemory ( VOID EFIAPI DebugExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { - UINTN CpuIndex; - UINTN PFEntry; - BOOLEAN IsWpEnabled; + UINTN CpuIndex; + UINTN PFEntry; + BOOLEAN IsWpEnabled; MpInitLibWhoAmI (&CpuIndex); @@ -1238,9 +1285,9 @@ DebugExceptionHandler ( // Clear TF in EFLAGS // if (mPagingContext.MachineType == IMAGE_FILE_MACHINE_I386) { - SystemContext.SystemContextIa32->Eflags &= (UINT32)~BIT8; + SystemContext.SystemContextIa32->Eflags &= (UINT32) ~BIT8; } else { - SystemContext.SystemContextX64->Rflags &= (UINT64)~BIT8; + SystemContext.SystemContextX64->Rflags &= (UINT64) ~BIT8; } } @@ -1256,20 +1303,20 @@ DebugExceptionHandler ( VOID EFIAPI PageFaultExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { - EFI_STATUS Status; - UINT64 PFAddress; - PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext; - PAGE_ATTRIBUTE PageAttribute; - UINT64 Attributes; - UINT64 *PageEntry; - UINTN Index; - UINTN CpuIndex; - UINTN PageNumber; - BOOLEAN NonStopMode; + EFI_STATUS Status; + UINT64 PFAddress; + PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext; + PAGE_ATTRIBUTE PageAttribute; + UINT64 Attributes; + UINT64 *PageEntry; + UINTN Index; + UINTN CpuIndex; + UINTN PageNumber; + BOOLEAN NonStopMode; PFAddress = AsmReadCr2 () & ~EFI_PAGE_MASK; if (PFAddress < BASE_4KB) { @@ -1289,23 +1336,28 @@ PageFaultExceptionHandler ( PageNumber = 2; while (PageNumber > 0) { PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute); - ASSERT(PageEntry != NULL); + ASSERT (PageEntry != NULL); if (PageEntry != NULL) { Attributes = GetAttributesFromPageEntry (PageEntry); if ((Attributes & EFI_MEMORY_RP) != 0) { Attributes &= ~EFI_MEMORY_RP; - Status = AssignMemoryPageAttributes (&PagingContext, PFAddress, - EFI_PAGE_SIZE, Attributes, NULL); - if (!EFI_ERROR(Status)) { + Status = AssignMemoryPageAttributes ( + &PagingContext, + PFAddress, + EFI_PAGE_SIZE, + Attributes, + NULL + ); + if (!EFI_ERROR (Status)) { Index = mPFEntryCount[CpuIndex]; // // Re-retrieve page entry because above calling might update page // table due to table split. // - PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute); + PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute); mLastPFEntryPointer[CpuIndex][Index++] = PageEntry; - mPFEntryCount[CpuIndex] = Index; + mPFEntryCount[CpuIndex] = Index; } } } @@ -1345,9 +1397,9 @@ InitializePageTableLib ( VOID ) { - PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; - UINT32 *Attributes; - UINTN *PageTableBase; + PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; + UINT32 *Attributes; + UINTN *PageTableBase; GetCurrentPagingContext (&CurrentPagingContext); @@ -1357,7 +1409,8 @@ InitializePageTableLib ( // Reserve memory of page tables for future uses, if paging is enabled. // if ((*PageTableBase != 0) && - (*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) { + ((*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0)) + { DisableReadOnlyPageWriteProtect (); InitializePageTablePool (1); EnableReadOnlyPageWriteProtect (); @@ -1377,5 +1430,5 @@ InitializePageTableLib ( DEBUG ((DEBUG_INFO, " PageTableBase - 0x%Lx\n", (UINT64)*PageTableBase)); DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", *Attributes)); - return ; + return; } diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTable.h index 0b2a02a2be..607e936b8a 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.h +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h @@ -19,19 +19,19 @@ #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED BIT31 // Other bits are reserved for future use typedef struct { - UINT32 PageTableBase; - UINT32 Reserved; - UINT32 Attributes; + UINT32 PageTableBase; + UINT32 Reserved; + UINT32 Attributes; } PAGE_TABLE_LIB_PAGING_CONTEXT_IA32; typedef struct { - UINT64 PageTableBase; - UINT32 Attributes; + UINT64 PageTableBase; + UINT32 Attributes; } PAGE_TABLE_LIB_PAGING_CONTEXT_X64; typedef union { - PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Ia32; - PAGE_TABLE_LIB_PAGING_CONTEXT_X64 X64; + PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Ia32; + PAGE_TABLE_LIB_PAGING_CONTEXT_X64 X64; } PAGE_TABLE_LIB_PAGING_CONTEXT_DATA; typedef struct { @@ -41,8 +41,8 @@ typedef struct { // #define IMAGE_FILE_MACHINE_I386 0x014c // #define IMAGE_FILE_MACHINE_X64 0x8664 // - UINT16 MachineType; - PAGE_TABLE_LIB_PAGING_CONTEXT_DATA ContextData; + UINT16 MachineType; + PAGE_TABLE_LIB_PAGING_CONTEXT_DATA ContextData; } PAGE_TABLE_LIB_PAGING_CONTEXT; #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB @@ -52,12 +52,11 @@ typedef struct { (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1)) typedef struct { - VOID *NextPool; - UINTN Offset; - UINTN FreePages; + VOID *NextPool; + UINTN Offset; + UINTN FreePages; } PAGE_TABLE_POOL; - /** Allocates one or more 4KB pages for page table. @@ -68,7 +67,7 @@ typedef struct { **/ typedef VOID * -(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES) ( +(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES)( IN UINTN Pages ); @@ -103,11 +102,11 @@ VOID * RETURN_STATUS EFIAPI AssignMemoryPageAttributes ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL ); /** @@ -136,7 +135,7 @@ InitializePageTableLib ( VOID * EFIAPI AllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ); /** @@ -149,9 +148,9 @@ AllocatePageTableMemory ( **/ VOID GetPagingDetails ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, - OUT UINTN **PageTableBase OPTIONAL, - OUT UINT32 **Attributes OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL ); #endif diff --git a/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c b/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c index 3325a42dd2..9145c17ad2 100644 --- a/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c +++ b/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c @@ -8,7 +8,6 @@ #include "CpuPageTable.h" - /** Get paging details. @@ -19,16 +18,16 @@ **/ VOID GetPagingDetails ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, - OUT UINTN **PageTableBase OPTIONAL, - OUT UINT32 **Attributes OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL ) { if (PageTableBase != NULL) { *PageTableBase = &PagingContextData->Ia32.PageTableBase; } + if (Attributes != NULL) { *Attributes = &PagingContextData->Ia32.Attributes; } } - diff --git a/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c b/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c index 7967935612..31ec0caff8 100644 --- a/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c +++ b/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c @@ -8,7 +8,6 @@ #include "CpuPageTable.h" - /** Get paging details. @@ -19,16 +18,16 @@ **/ VOID GetPagingDetails ( - IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, - OUT UINTN **PageTableBase OPTIONAL, - OUT UINT32 **Attributes OPTIONAL + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL ) { if (PageTableBase != NULL) { *PageTableBase = &PagingContextData->X64.PageTableBase; } + if (Attributes != NULL) { *Attributes = &PagingContextData->X64.Attributes; } } - diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c index 230b9fad7e..0a0e14a134 100644 --- a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c +++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c @@ -18,7 +18,6 @@ #include #include - /** Worker function to perform CPU feature initialization. @@ -28,8 +27,8 @@ CpuFeaturesInitializeWorker ( VOID ) { - EFI_STATUS Status; - EFI_HANDLE Handle; + EFI_STATUS Status; + EFI_HANDLE Handle; CpuFeaturesDetect (); @@ -57,12 +56,12 @@ CpuFeaturesInitializeWorker ( VOID EFIAPI SmmConfigurationEventNotify ( - IN EFI_EVENT Event, - IN VOID *Context + IN EFI_EVENT Event, + IN VOID *Context ) { - EFI_STATUS Status; - EFI_SMM_CONFIGURATION_PROTOCOL *SmmConfiguration; + EFI_STATUS Status; + EFI_SMM_CONFIGURATION_PROTOCOL *SmmConfiguration; // // Make sure this notification is for this handler @@ -91,8 +90,8 @@ SmmConfigurationEventNotify ( EFI_STATUS EFIAPI CpuFeaturesDxeInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) { VOID *Registration; @@ -133,4 +132,3 @@ CpuFeaturesDxeInitialize ( return EFI_SUCCESS; } - diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c index be559a9595..8448668e5a 100644 --- a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c +++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c @@ -16,7 +16,7 @@ #include -EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc = { +EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEdkiiCpuFeaturesInitDoneGuid, NULL @@ -40,14 +40,15 @@ CpuFeaturesPeimInitialize ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; Status = PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR (Status); - if (BootMode == BOOT_ON_S3_RESUME && - !PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) { + if ((BootMode == BOOT_ON_S3_RESUME) && + !PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) + { // // Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE // on S3 boot mode @@ -62,7 +63,7 @@ CpuFeaturesPeimInitialize ( // // Install CPU Features Init Done PPI // - Status = PeiServicesInstallPpi(&mPeiCpuFeaturesInitDonePpiDesc); + Status = PeiServicesInstallPpi (&mPeiCpuFeaturesInitDonePpiDesc); ASSERT_EFI_ERROR (Status); // @@ -72,4 +73,3 @@ CpuFeaturesPeimInitialize ( return EFI_SUCCESS; } - diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c index ade8207288..87f4f805ca 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c @@ -18,7 +18,7 @@ EFI_HANDLE mHandle = NULL; // // CPU I/O 2 Protocol instance // -EFI_CPU_IO2_PROTOCOL mCpuIo2 = { +EFI_CPU_IO2_PROTOCOL mCpuIo2 = { { CpuMemoryServiceRead, CpuMemoryServiceWrite @@ -32,7 +32,7 @@ EFI_CPU_IO2_PROTOCOL mCpuIo2 = { // // Lookup table for increment values based on transfer widths // -UINT8 mInStride[] = { +UINT8 mInStride[] = { 1, // EfiCpuIoWidthUint8 2, // EfiCpuIoWidthUint16 4, // EfiCpuIoWidthUint32 @@ -50,7 +50,7 @@ UINT8 mInStride[] = { // // Lookup table for increment values based on transfer widths // -UINT8 mOutStride[] = { +UINT8 mOutStride[] = { 1, // EfiCpuIoWidthUint8 2, // EfiCpuIoWidthUint16 4, // EfiCpuIoWidthUint32 @@ -120,14 +120,14 @@ CpuIoCheckParameter ( // For FIFO type, the target address won't increase during the access, // so treat Count as 1 // - if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { + if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) { Count = 1; } // // Check to see if Width is in the valid range for I/O Port operations // - Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { return EFI_INVALID_PARAMETER; } @@ -164,6 +164,7 @@ CpuIoCheckParameter ( if (MaxCount < (Count - 1)) { return EFI_UNSUPPORTED; } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { return EFI_UNSUPPORTED; } @@ -243,9 +244,9 @@ CpuMemoryServiceRead ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiCpuIoWidthUint8) { *Uint8Buffer = MmioRead8 ((UINTN)Address); @@ -257,6 +258,7 @@ CpuMemoryServiceRead ( *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); } } + return EFI_SUCCESS; } @@ -323,9 +325,9 @@ CpuMemoryServiceWrite ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiCpuIoWidthUint8) { MmioWrite8 ((UINTN)Address, *Uint8Buffer); @@ -337,6 +339,7 @@ CpuMemoryServiceWrite ( MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); } } + return EFI_SUCCESS; } @@ -403,31 +406,31 @@ CpuIoServiceRead ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); // // Fifo operations supported for (mInStride[Width] == 0) // if (InStride == 0) { switch (OperationWidth) { - case EfiCpuIoWidthUint8: - IoReadFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint16: - IoReadFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint32: - IoReadFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + case EfiCpuIoWidthUint8: + IoReadFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint16: + IoReadFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint32: + IoReadFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; } } @@ -510,31 +513,31 @@ CpuIoServiceWrite ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); // // Fifo operations supported for (mInStride[Width] == 0) // if (InStride == 0) { switch (OperationWidth) { - case EfiCpuIoWidthUint8: - IoWriteFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint16: - IoWriteFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint32: - IoWriteFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + case EfiCpuIoWidthUint8: + IoWriteFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint16: + IoWriteFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint32: + IoWriteFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; } } @@ -568,12 +571,13 @@ CpuIo2Initialize ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); Status = gBS->InstallMultipleProtocolInterfaces ( &mHandle, - &gEfiCpuIo2ProtocolGuid, &mCpuIo2, + &gEfiCpuIo2ProtocolGuid, + &mCpuIo2, NULL ); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h index 3b16b205f6..7ebde0759b 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h @@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include -#define MAX_IO_PORT_ADDRESS 0xFFFF +#define MAX_IO_PORT_ADDRESS 0xFFFF /** Reads memory-mapped registers. diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c index 7e314eaa15..44e52562a8 100644 --- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c +++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c @@ -16,7 +16,7 @@ EFI_HANDLE mHandle = NULL; // // SMM CPU I/O Protocol instance // -EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = { +EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = { { CpuMemoryServiceRead, CpuMemoryServiceWrite @@ -30,7 +30,7 @@ EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = { // // Lookup table for increment values based on transfer widths // -UINT8 mStride[] = { +UINT8 mStride[] = { 1, // SMM_IO_UINT8 2, // SMM_IO_UINT16 4, // SMM_IO_UINT32 @@ -112,6 +112,7 @@ CpuIoCheckParameter ( if (MaxCount < (Count - 1)) { return EFI_UNSUPPORTED; } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { return EFI_UNSUPPORTED; } @@ -184,6 +185,7 @@ CpuMemoryServiceRead ( *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); } } + return EFI_SUCCESS; } @@ -244,6 +246,7 @@ CpuMemoryServiceWrite ( MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); } } + return EFI_SUCCESS; } diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h index eda9fbb090..8404513554 100644 --- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h +++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h @@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include -#define MAX_IO_PORT_ADDRESS 0xFFFF +#define MAX_IO_PORT_ADDRESS 0xFFFF /** Reads memory-mapped registers. diff --git a/UefiCpuPkg/CpuIoPei/CpuIoPei.c b/UefiCpuPkg/CpuIoPei/CpuIoPei.c index 98bae46e29..0d0fe3d4bc 100644 --- a/UefiCpuPkg/CpuIoPei/CpuIoPei.c +++ b/UefiCpuPkg/CpuIoPei/CpuIoPei.c @@ -43,7 +43,7 @@ EFI_PEI_CPU_IO_PPI gCpuIoPpi = { // // PPI Descriptor used to install the CPU I/O PPI // -EFI_PEI_PPI_DESCRIPTOR gPpiList = { +EFI_PEI_PPI_DESCRIPTOR gPpiList = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiPeiCpuIoPpiInstalledGuid, NULL @@ -52,7 +52,7 @@ EFI_PEI_PPI_DESCRIPTOR gPpiList = { // // Lookup table for increment values based on transfer widths // -UINT8 mInStride[] = { +UINT8 mInStride[] = { 1, // EfiPeiCpuIoWidthUint8 2, // EfiPeiCpuIoWidthUint16 4, // EfiPeiCpuIoWidthUint32 @@ -70,7 +70,7 @@ UINT8 mInStride[] = { // // Lookup table for increment values based on transfer widths // -UINT8 mOutStride[] = { +UINT8 mOutStride[] = { 1, // EfiPeiCpuIoWidthUint8 2, // EfiPeiCpuIoWidthUint16 4, // EfiPeiCpuIoWidthUint32 @@ -131,14 +131,14 @@ CpuIoCheckParameter ( // For FIFO type, the target address won't increase during the access, // so treat Count as 1 // - if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) { + if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) { Count = 1; } // // Check to see if Width is in the valid range for I/O Port operations // - Width = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); + Width = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03); if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) { return EFI_INVALID_PARAMETER; } @@ -168,6 +168,7 @@ CpuIoCheckParameter ( if (MaxCount < (Count - 1)) { return EFI_UNSUPPORTED; } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { return EFI_UNSUPPORTED; } @@ -220,10 +221,10 @@ CpuMemoryServiceRead ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); - Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03); + Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiPeiCpuIoWidthUint8) { *Uint8Buffer = MmioRead8 ((UINTN)Address); @@ -247,6 +248,7 @@ CpuMemoryServiceRead ( } } } + return EFI_SUCCESS; } @@ -294,10 +296,10 @@ CpuMemoryServiceWrite ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); - Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03); + Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiPeiCpuIoWidthUint8) { MmioWrite8 ((UINTN)Address, *Uint8Buffer); @@ -321,6 +323,7 @@ CpuMemoryServiceWrite ( } } } + return EFI_SUCCESS; } @@ -368,31 +371,31 @@ CpuIoServiceRead ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03); // // Fifo operations supported for (mInStride[Width] == 0) // if (InStride == 0) { switch (OperationWidth) { - case EfiPeiCpuIoWidthUint8: - IoReadFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiPeiCpuIoWidthUint16: - IoReadFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiPeiCpuIoWidthUint32: - IoReadFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + case EfiPeiCpuIoWidthUint8: + IoReadFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint16: + IoReadFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint32: + IoReadFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; } } @@ -465,31 +468,31 @@ CpuIoServiceWrite ( // // Select loop based on the width of the transfer // - InStride = mInStride[Width]; - OutStride = mOutStride[Width]; - OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03); // // Fifo operations supported for (mInStride[Width] == 0) // if (InStride == 0) { switch (OperationWidth) { - case EfiPeiCpuIoWidthUint8: - IoWriteFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiPeiCpuIoWidthUint16: - IoWriteFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiPeiCpuIoWidthUint32: - IoWriteFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + case EfiPeiCpuIoWidthUint8: + IoWriteFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint16: + IoWriteFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint32: + IoWriteFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; } } @@ -572,9 +575,9 @@ CpuIoRead16 ( UINT32 EFIAPI CpuIoRead32 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ) { return IoRead32 ((UINTN)Address); diff --git a/UefiCpuPkg/CpuIoPei/CpuIoPei.h b/UefiCpuPkg/CpuIoPei/CpuIoPei.h index e8676df906..eb1982f947 100644 --- a/UefiCpuPkg/CpuIoPei/CpuIoPei.h +++ b/UefiCpuPkg/CpuIoPei/CpuIoPei.h @@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include -#define MAX_IO_PORT_ADDRESS 0xFFFF +#define MAX_IO_PORT_ADDRESS 0xFFFF /** Reads memory-mapped registers. @@ -149,9 +149,9 @@ CpuIoServiceWrite ( UINT8 EFIAPI CpuIoRead8 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -168,9 +168,9 @@ CpuIoRead8 ( UINT16 EFIAPI CpuIoRead16 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -187,9 +187,9 @@ CpuIoRead16 ( UINT32 EFIAPI CpuIoRead32 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -206,9 +206,9 @@ CpuIoRead32 ( UINT64 EFIAPI CpuIoRead64 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -224,10 +224,10 @@ CpuIoRead64 ( VOID EFIAPI CpuIoWrite8 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT8 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT8 Data ); /** @@ -243,10 +243,10 @@ CpuIoWrite8 ( VOID EFIAPI CpuIoWrite16 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT16 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT16 Data ); /** @@ -262,10 +262,10 @@ CpuIoWrite16 ( VOID EFIAPI CpuIoWrite32 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT32 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT32 Data ); /** @@ -281,10 +281,10 @@ CpuIoWrite32 ( VOID EFIAPI CpuIoWrite64 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT64 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT64 Data ); /** @@ -301,9 +301,9 @@ CpuIoWrite64 ( UINT8 EFIAPI CpuMemRead8 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -320,9 +320,9 @@ CpuMemRead8 ( UINT16 EFIAPI CpuMemRead16 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -339,9 +339,9 @@ CpuMemRead16 ( UINT32 EFIAPI CpuMemRead32 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -358,9 +358,9 @@ CpuMemRead32 ( UINT64 EFIAPI CpuMemRead64 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address ); /** @@ -376,10 +376,10 @@ CpuMemRead64 ( VOID EFIAPI CpuMemWrite8 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT8 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT8 Data ); /** @@ -395,10 +395,10 @@ CpuMemWrite8 ( VOID EFIAPI CpuMemWrite16 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT16 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT16 Data ); /** @@ -414,10 +414,10 @@ CpuMemWrite16 ( VOID EFIAPI CpuMemWrite32 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT32 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT32 Data ); /** @@ -433,10 +433,10 @@ CpuMemWrite32 ( VOID EFIAPI CpuMemWrite64 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_PEI_CPU_IO_PPI *This, - IN UINT64 Address, - IN UINT64 Data + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT64 Data ); #endif diff --git a/UefiCpuPkg/CpuMpPei/CpuBist.c b/UefiCpuPkg/CpuMpPei/CpuBist.c index bb35bb4347..7dc93cd784 100644 --- a/UefiCpuPkg/CpuMpPei/CpuBist.c +++ b/UefiCpuPkg/CpuMpPei/CpuBist.c @@ -8,11 +8,11 @@ #include "CpuMpPei.h" -EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi = { +EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi = { SecPlatformInformation2 }; -EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = { +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiSecPlatformInformation2PpiGuid, &mSecPlatformInformation2Ppi @@ -33,14 +33,14 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = { EFI_STATUS EFIAPI SecPlatformInformation2 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 ) { - EFI_HOB_GUID_TYPE *GuidHob; - VOID *DataInHob; - UINTN DataSize; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *DataInHob; + UINTN DataSize; GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformation2PpiGuid); if (GuidHob == NULL) { @@ -54,12 +54,12 @@ SecPlatformInformation2 ( // // return the information from BistHob // - if ((*StructureSize) < (UINT64) DataSize) { - *StructureSize = (UINT64) DataSize; + if ((*StructureSize) < (UINT64)DataSize) { + *StructureSize = (UINT64)DataSize; return EFI_BUFFER_TOO_SMALL; } - *StructureSize = (UINT64) DataSize; + *StructureSize = (UINT64)DataSize; CopyMem (PlatformInformationRecord2, DataInHob, DataSize); return EFI_SUCCESS; } @@ -82,11 +82,11 @@ SecPlatformInformation2 ( **/ EFI_STATUS GetBistInfoFromPpi ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_GUID *Guid, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, - OUT VOID **BistInformationData, - OUT UINT64 *BistInformationSize OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_GUID *Guid, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, + OUT VOID **BistInformationData, + OUT UINT64 *BistInformationSize OPTIONAL ) { EFI_STATUS Status; @@ -110,15 +110,15 @@ GetBistInfoFromPpi ( // InformationSize = 0; SecPlatformInformation2 = NULL; - Status = SecPlatformInformation2Ppi->PlatformInformation2 ( - PeiServices, - &InformationSize, - SecPlatformInformation2 - ); + Status = SecPlatformInformation2Ppi->PlatformInformation2 ( + PeiServices, + &InformationSize, + SecPlatformInformation2 + ); if (Status == EFI_BUFFER_TOO_SMALL) { Status = PeiServicesAllocatePool ( - (UINTN) InformationSize, - (VOID **) &SecPlatformInformation2 + (UINTN)InformationSize, + (VOID **)&SecPlatformInformation2 ); if (Status == EFI_SUCCESS) { // @@ -134,6 +134,7 @@ GetBistInfoFromPpi ( if (BistInformationSize != NULL) { *BistInformationSize = InformationSize; } + return EFI_SUCCESS; } } @@ -154,7 +155,7 @@ GetBistInfoFromPpi ( **/ VOID CollectBistDataFromPpi ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN CONST EFI_PEI_SERVICES **PeiServices ) { EFI_STATUS Status; @@ -174,14 +175,13 @@ CollectBistDataFromPpi ( EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2; EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob; - - MpInitLibGetNumberOfProcessors(&NumberOfProcessors, &NumberOfEnabledProcessors); + MpInitLibGetNumberOfProcessors (&NumberOfProcessors, &NumberOfEnabledProcessors); BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) + sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors; Status = PeiServicesAllocatePool ( - (UINTN) BistInformationSize, - (VOID **) &PlatformInformationRecord2 + (UINTN)BistInformationSize, + (VOID **)&PlatformInformationRecord2 ); ASSERT_EFI_ERROR (Status); PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors; @@ -197,7 +197,7 @@ CollectBistDataFromPpi ( PeiServices, &gEfiSecPlatformInformation2PpiGuid, &SecInformationDescriptor, - (VOID *) &SecPlatformInformation2, + (VOID *)&SecPlatformInformation2, NULL ); if (Status == EFI_SUCCESS) { @@ -214,7 +214,7 @@ CollectBistDataFromPpi ( PeiServices, &gEfiSecPlatformInformationPpiGuid, &SecInformationDescriptor, - (VOID *) &SecPlatformInformation, + (VOID *)&SecPlatformInformation, NULL ); if (Status == EFI_SUCCESS) { @@ -223,16 +223,17 @@ CollectBistDataFromPpi ( // SEC Platform Information only includes BSP's BIST information // and does not have BSP's APIC ID // - BspCpuInstance.CpuLocation = GetInitialApicId (); - BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; - CpuInstance = &BspCpuInstance; + BspCpuInstance.CpuLocation = GetInitialApicId (); + BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; + CpuInstance = &BspCpuInstance; } else { DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n")); } } - for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber ++) { + + for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber++) { MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData); - for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex ++) { + for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex++) { ASSERT (CpuInstance != NULL); if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) { // @@ -241,6 +242,7 @@ CollectBistDataFromPpi ( BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags; } } + if (BistData.Uint32 != 0) { // // Report Status Code that self test is failed @@ -250,12 +252,15 @@ CollectBistDataFromPpi ( (EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST) ); } - DEBUG ((DEBUG_INFO, " APICID - 0x%08x, BIST - 0x%08x\n", - (UINT32) ProcessorInfo.ProcessorId, - BistData - )); - CpuInstanceInHob = PlatformInformationRecord2->CpuInstance; - CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32) ProcessorInfo.ProcessorId; + + DEBUG (( + DEBUG_INFO, + " APICID - 0x%08x, BIST - 0x%08x\n", + (UINT32)ProcessorInfo.ProcessorId, + BistData + )); + CpuInstanceInHob = PlatformInformationRecord2->CpuInstance; + CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32)ProcessorInfo.ProcessorId; CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData; } @@ -266,7 +271,7 @@ CollectBistDataFromPpi ( BuildGuidDataHob ( &gEfiSecPlatformInformation2PpiGuid, PlatformInformationRecord2, - (UINTN) BistInformationSize + (UINTN)BistInformationSize ); if (SecPlatformInformation2 != NULL) { @@ -285,6 +290,6 @@ CollectBistDataFromPpi ( // Install SecPlatformInformation2 PPI // Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi); - ASSERT_EFI_ERROR(Status); + ASSERT_EFI_ERROR (Status); } } diff --git a/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c b/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c index c1116a5b77..9c55eadb18 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c +++ b/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c @@ -43,9 +43,9 @@ EFI_STATUS EFIAPI EdkiiPeiGetNumberOfProcessors ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - OUT UINTN *NumberOfProcessors, - OUT UINTN *NumberOfEnabledProcessors + IN EDKII_PEI_MP_SERVICES2_PPI *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors ) { if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) { @@ -85,9 +85,9 @@ EdkiiPeiGetNumberOfProcessors ( EFI_STATUS EFIAPI EdkiiPeiGetProcessorInfo ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ) { return MpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuffer, NULL); @@ -157,11 +157,11 @@ EdkiiPeiGetProcessorInfo ( EFI_STATUS EFIAPI EdkiiPeiStartupAllAPs ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN UINTN TimeoutInMicroSeconds, - IN VOID *ProcedureArgument OPTIONAL + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL ) { return MpInitLibStartupAllAPs ( @@ -221,11 +221,11 @@ EdkiiPeiStartupAllAPs ( EFI_STATUS EFIAPI EdkiiPeiStartupThisAP ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ) { return MpInitLibStartupThisAP ( @@ -321,10 +321,10 @@ EdkiiPeiSwitchBSP ( EFI_STATUS EFIAPI EdkiiPeiEnableDisableAP ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag); @@ -388,10 +388,10 @@ EdkiiPeiWhoAmI ( EFI_STATUS EFIAPI EdkiiPeiStartupAllCPUs ( - IN EDKII_PEI_MP_SERVICES2_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN UINTN TimeoutInMicroSeconds, - IN VOID *ProcedureArgument OPTIONAL + IN EDKII_PEI_MP_SERVICES2_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL ) { return MpInitLibStartupAllCPUs ( @@ -404,7 +404,7 @@ EdkiiPeiStartupAllCPUs ( // // CPU MP2 PPI to be installed // -EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = { +EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = { EdkiiPeiGetNumberOfProcessors, EdkiiPeiGetProcessorInfo, EdkiiPeiStartupAllAPs, @@ -414,4 +414,3 @@ EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = { EdkiiPeiWhoAmI, EdkiiPeiStartupAllCPUs }; - diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c index 3c1bad6470..1e68c91d95 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c @@ -8,12 +8,12 @@ #include "CpuMpPei.h" -extern EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi; +extern EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi; // // CPU MP PPI to be installed // -EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = { +EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = { PeiGetNumberOfProcessors, PeiGetProcessorInfo, PeiStartupAllAPs, @@ -23,7 +23,7 @@ EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = { PeiWhoAmI, }; -EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = { +EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = { { EFI_PEI_PPI_DESCRIPTOR_PPI, &gEdkiiPeiMpServices2PpiGuid, @@ -73,10 +73,10 @@ EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = { EFI_STATUS EFIAPI PeiGetNumberOfProcessors ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - OUT UINTN *NumberOfProcessors, - OUT UINTN *NumberOfEnabledProcessors + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors ) { if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) { @@ -193,12 +193,12 @@ PeiGetProcessorInfo ( EFI_STATUS EFIAPI PeiStartupAllAPs ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN UINTN TimeoutInMicroSeconds, - IN VOID *ProcedureArgument OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL ) { return MpInitLibStartupAllAPs ( @@ -260,12 +260,12 @@ PeiStartupAllAPs ( EFI_STATUS EFIAPI PeiStartupThisAP ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ) { return MpInitLibStartupThisAP ( @@ -366,11 +366,11 @@ PeiSwitchBSP ( EFI_STATUS EFIAPI PeiEnableDisableAP ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag); @@ -423,7 +423,7 @@ PeiWhoAmI ( VOID EFIAPI GetGdtr ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); @@ -441,12 +441,12 @@ GetGdtr ( VOID EFIAPI InitializeExceptionStackSwitchHandlers ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - CPU_EXCEPTION_INIT_DATA *EssData; - IA32_DESCRIPTOR Idtr; - EFI_STATUS Status; + CPU_EXCEPTION_INIT_DATA *EssData; + IA32_DESCRIPTOR Idtr; + EFI_STATUS Status; EssData = Buffer; // @@ -454,9 +454,9 @@ InitializeExceptionStackSwitchHandlers ( // the AP's IDT is the same as BSP's IDT either. // AsmReadIdtr (&Idtr); - EssData->Ia32.IdtTable = (VOID *)Idtr.Base; + EssData->Ia32.IdtTable = (VOID *)Idtr.Base; EssData->Ia32.IdtTableSize = Idtr.Limit + 1; - Status = InitializeCpuExceptionHandlersEx (NULL, EssData); + Status = InitializeCpuExceptionHandlersEx (NULL, EssData); ASSERT_EFI_ERROR (Status); } @@ -472,58 +472,59 @@ InitializeMpExceptionStackSwitchHandlers ( VOID ) { - EFI_STATUS Status; - UINTN Index; - UINTN Bsp; - UINTN ExceptionNumber; - UINTN OldGdtSize; - UINTN NewGdtSize; - UINTN NewStackSize; - IA32_DESCRIPTOR Gdtr; - CPU_EXCEPTION_INIT_DATA EssData; - UINT8 *GdtBuffer; - UINT8 *StackTop; - UINTN NumberOfProcessors; + EFI_STATUS Status; + UINTN Index; + UINTN Bsp; + UINTN ExceptionNumber; + UINTN OldGdtSize; + UINTN NewGdtSize; + UINTN NewStackSize; + IA32_DESCRIPTOR Gdtr; + CPU_EXCEPTION_INIT_DATA EssData; + UINT8 *GdtBuffer; + UINT8 *StackTop; + UINTN NumberOfProcessors; if (!PcdGetBool (PcdCpuStackGuard)) { return; } - MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); + MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL); MpInitLibWhoAmI (&Bsp); ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList); - NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors)); - ASSERT(StackTop != NULL); + ASSERT (StackTop != NULL); if (StackTop == NULL) { return; } + StackTop += NewStackSize * NumberOfProcessors; // // The default exception handlers must have been initialized. Let's just skip // it in this method. // - EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; + EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.InitDefaultHandlers = FALSE; - EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); + EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; - EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); + EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize); // // Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // - Gdtr.Base = 0; + Gdtr.Base = 0; Gdtr.Limit = 0; for (Index = 0; Index < NumberOfProcessors; ++Index) { // // To support stack switch, we need to re-construct GDT but not IDT. // if (Index == Bsp) { - GetGdtr(&Gdtr); + GetGdtr (&Gdtr); } else { // // AP might have different size of GDT from BSP. @@ -560,7 +561,7 @@ InitializeMpExceptionStackSwitchHandlers ( // | | // -------------------------------- // - OldGdtSize = Gdtr.Limit + 1; + OldGdtSize = Gdtr.Limit + 1; EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1); EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) * @@ -583,19 +584,21 @@ InitializeMpExceptionStackSwitchHandlers ( // // Make sure GDT table alignment // - EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); - NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); + EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); + NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize); - EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + - EssData.Ia32.ExceptionTssDescSize); + EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + + EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; - DEBUG ((DEBUG_INFO, - "Exception stack top[cpu%lu]: 0x%lX\n", - (UINT64)(UINTN)Index, - (UINT64)(UINTN)StackTop)); + DEBUG (( + DEBUG_INFO, + "Exception stack top[cpu%lu]: 0x%lX\n", + (UINT64)(UINTN)Index, + (UINT64)(UINTN)StackTop + )); if (Index == Bsp) { InitializeExceptionStackSwitchHandlers (&EssData); @@ -610,7 +613,7 @@ InitializeMpExceptionStackSwitchHandlers ( ); } - StackTop -= NewStackSize; + StackTop -= NewStackSize; } } @@ -625,23 +628,23 @@ InitializeMpExceptionStackSwitchHandlers ( **/ EFI_STATUS InitializeCpuMpWorker ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; - EFI_VECTOR_HANDOFF_INFO *VectorInfo; - EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi; + EFI_STATUS Status; + EFI_VECTOR_HANDOFF_INFO *VectorInfo; + EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi; // // Get Vector Hand-off Info PPI // VectorInfo = NULL; - Status = PeiServicesLocatePpi ( - &gEfiVectorHandoffInfoPpiGuid, - 0, - NULL, - (VOID **)&VectorHandoffInfoPpi - ); + Status = PeiServicesLocatePpi ( + &gEfiVectorHandoffInfoPpiGuid, + 0, + NULL, + (VOID **)&VectorHandoffInfoPpi + ); if (Status == EFI_SUCCESS) { VectorInfo = VectorHandoffInfoPpi->Info; } @@ -672,7 +675,7 @@ InitializeCpuMpWorker ( // // Install CPU MP PPI // - Status = PeiServicesInstallPpi(mPeiCpuMpPpiList); + Status = PeiServicesInstallPpi (mPeiCpuMpPpiList); ASSERT_EFI_ERROR (Status); return Status; @@ -697,7 +700,7 @@ CpuMpPeimInit ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; + EFI_STATUS Status; // // For the sake of special initialization needing to be done right after diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h index c6870656ca..0649c48d14 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h @@ -29,7 +29,7 @@ #include #include -extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; +extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; /** This service retrieves the number of logical processor in the platform @@ -68,10 +68,10 @@ extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; EFI_STATUS EFIAPI PeiGetNumberOfProcessors ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - OUT UINTN *NumberOfProcessors, - OUT UINTN *NumberOfEnabledProcessors + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors ); /** @@ -175,12 +175,12 @@ PeiGetProcessorInfo ( EFI_STATUS EFIAPI PeiStartupAllAPs ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN UINTN TimeoutInMicroSeconds, - IN VOID *ProcedureArgument OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL ); /** @@ -232,12 +232,12 @@ PeiStartupAllAPs ( EFI_STATUS EFIAPI PeiStartupThisAP ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ); /** @@ -325,11 +325,11 @@ PeiSwitchBSP ( EFI_STATUS EFIAPI PeiEnableDisableAP ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_MP_SERVICES_PPI *This, - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ); /** @@ -375,7 +375,7 @@ PeiWhoAmI ( **/ VOID CollectBistDataFromPpi ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN CONST EFI_PEI_SERVICES **PeiServices ); /** @@ -393,9 +393,9 @@ CollectBistDataFromPpi ( EFI_STATUS EFIAPI SecPlatformInformation2 ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 ); /** @@ -421,7 +421,7 @@ MigrateGdt ( **/ EFI_STATUS InitializeCpuMpWorker ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN CONST EFI_PEI_SERVICES **PeiServices ); /** diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c b/UefiCpuPkg/CpuMpPei/CpuPaging.c index 3e261d6657..1354222253 100644 --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c @@ -16,23 +16,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "CpuMpPei.h" -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_U BIT2 -#define IA32_PG_A BIT5 -#define IA32_PG_D BIT6 -#define IA32_PG_PS BIT7 -#define IA32_PG_NX BIT63 - -#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P) -#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U |\ +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_U BIT2 +#define IA32_PG_A BIT5 +#define IA32_PG_D BIT6 +#define IA32_PG_PS BIT7 +#define IA32_PG_NX BIT63 + +#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P) +#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \ PAGE_ATTRIBUTE_BITS) -#define PAGING_PAE_INDEX_MASK 0x1FF -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull -#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull +#define PAGING_PAE_INDEX_MASK 0x1FF +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull +#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull typedef enum { PageNone = 0, @@ -45,19 +45,19 @@ typedef enum { } PAGE_ATTRIBUTE; typedef struct { - PAGE_ATTRIBUTE Attribute; - UINT64 Length; - UINT64 AddressMask; - UINTN AddressBitOffset; - UINTN AddressBitLength; + PAGE_ATTRIBUTE Attribute; + UINT64 Length; + UINT64 AddressMask; + UINTN AddressBitOffset; + UINTN AddressBitLength; } PAGE_ATTRIBUTE_TABLE; -PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { - {PageNone, 0, 0, 0, 0}, - {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9}, - {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9}, - {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9}, - {Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9}, +PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { + { PageNone, 0, 0, 0, 0 }, + { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 }, + { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 }, + { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 }, + { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 }, }; EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = { @@ -80,8 +80,8 @@ IsIa32PaeSupported ( VOID ) { - UINT32 RegEax; - CPUID_VERSION_INFO_EDX RegEdx; + UINT32 RegEax; + CPUID_VERSION_INFO_EDX RegEdx; AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL); if (RegEax >= CPUID_VERSION_INFO) { @@ -104,14 +104,14 @@ IsIa32PaeSupported ( **/ VOID * AllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ) { - VOID *Address; + VOID *Address; - Address = AllocatePages(Pages); + Address = AllocatePages (Pages); if (Address != NULL) { - ZeroMem(Address, EFI_PAGES_TO_SIZE (Pages)); + ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages)); } return Address; @@ -129,13 +129,13 @@ GetPhysicalAddressWidth ( VOID ) { - UINT32 RegEax; + UINT32 RegEax; - if (sizeof(UINTN) == 4) { + if (sizeof (UINTN) == 4) { return 32; } - AsmCpuid(CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL); RegEax &= 0xFF; @@ -161,7 +161,7 @@ GetPageTableTopLevelType ( VOID ) { - MSR_IA32_EFER_REGISTER MsrEfer; + MSR_IA32_EFER_REGISTER MsrEfer; MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER); @@ -178,19 +178,19 @@ GetPageTableTopLevelType ( **/ VOID * GetPageTableEntry ( - IN PHYSICAL_ADDRESS Address, - OUT PAGE_ATTRIBUTE *PageAttribute + IN PHYSICAL_ADDRESS Address, + OUT PAGE_ATTRIBUTE *PageAttribute ) { - INTN Level; - UINTN Index; - UINT64 *PageTable; - UINT64 AddressEncMask; + INTN Level; + UINTN Index; + UINT64 *PageTable; + UINT64 AddressEncMask; AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); - PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); + PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) { - Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset); + Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset); Index &= PAGING_PAE_INDEX_MASK; // @@ -204,7 +204,7 @@ GetPageTableEntry ( // // Page memory? // - if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) { + if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) { *PageAttribute = (PAGE_ATTRIBUTE)Level; return &PageTable[Index]; } @@ -235,19 +235,19 @@ GetPageTableEntry ( **/ RETURN_STATUS SplitPage ( - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute, - IN PAGE_ATTRIBUTE SplitAttribute, - IN BOOLEAN Recursively + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute, + IN PAGE_ATTRIBUTE SplitAttribute, + IN BOOLEAN Recursively ) { - UINT64 BaseAddress; - UINT64 *NewPageEntry; - UINTN Index; - UINT64 AddressEncMask; - PAGE_ATTRIBUTE SplitTo; + UINT64 BaseAddress; + UINT64 *NewPageEntry; + UINTN Index; + UINT64 AddressEncMask; + PAGE_ATTRIBUTE SplitTo; - if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) { + if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) { ASSERT (SplitAttribute != PageNone); ASSERT (SplitAttribute < PageAttribute); return RETURN_INVALID_PARAMETER; @@ -262,13 +262,13 @@ SplitPage ( // // One level down each step to achieve more compact page table. // - SplitTo = PageAttribute - 1; + SplitTo = PageAttribute - 1; AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & mPageAttributeTable[SplitTo].AddressMask; - BaseAddress = *PageEntry & - ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & - mPageAttributeTable[PageAttribute].AddressMask; - for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + BaseAddress = *PageEntry & + ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & + mPageAttributeTable[PageAttribute].AddressMask; + for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { NewPageEntry[Index] = BaseAddress | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); @@ -276,7 +276,7 @@ SplitPage ( NewPageEntry[Index] |= IA32_PG_PS; } - if (Recursively && SplitTo > SplitAttribute) { + if (Recursively && (SplitTo > SplitAttribute)) { SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively); } @@ -313,20 +313,20 @@ SplitPage ( RETURN_STATUS EFIAPI ConvertMemoryPageAttributes ( - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { - UINT64 *PageEntry; - PAGE_ATTRIBUTE PageAttribute; - RETURN_STATUS Status; - EFI_PHYSICAL_ADDRESS MaximumAddress; - - if (Length == 0 || - (BaseAddress & (SIZE_4KB - 1)) != 0 || - (Length & (SIZE_4KB - 1)) != 0) { - + UINT64 *PageEntry; + PAGE_ATTRIBUTE PageAttribute; + RETURN_STATUS Status; + EFI_PHYSICAL_ADDRESS MaximumAddress; + + if ((Length == 0) || + ((BaseAddress & (SIZE_4KB - 1)) != 0) || + ((Length & (SIZE_4KB - 1)) != 0)) + { ASSERT (Length > 0); ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0); ASSERT ((Length & (SIZE_4KB - 1)) == 0); @@ -335,9 +335,10 @@ ConvertMemoryPageAttributes ( } MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32; - if (BaseAddress > MaximumAddress || - Length > MaximumAddress || - (BaseAddress > MaximumAddress - (Length - 1))) { + if ((BaseAddress > MaximumAddress) || + (Length > MaximumAddress) || + (BaseAddress > MaximumAddress - (Length - 1))) + { return RETURN_UNSUPPORTED; } @@ -355,6 +356,7 @@ ConvertMemoryPageAttributes ( if (RETURN_ERROR (Status)) { return Status; } + // // Do it again until the page is 4K. // @@ -374,7 +376,7 @@ ConvertMemoryPageAttributes ( // Convert success, move to next // BaseAddress += SIZE_4KB; - Length -= SIZE_4KB; + Length -= SIZE_4KB; } return RETURN_SUCCESS; @@ -394,8 +396,8 @@ GetMaxMemoryPage ( IN PAGE_ATTRIBUTE TopLevelType ) { - UINT32 RegEax; - UINT32 RegEdx; + UINT32 RegEax; + UINT32 RegEdx; if (TopLevelType == Page512G) { AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); @@ -421,31 +423,31 @@ CreatePageTable ( VOID ) { - RETURN_STATUS Status; - UINTN PhysicalAddressBits; - UINTN NumberOfEntries; - PAGE_ATTRIBUTE TopLevelPageAttr; - UINTN PageTable; - PAGE_ATTRIBUTE MaxMemoryPage; - UINTN Index; - UINT64 AddressEncMask; - UINT64 *PageEntry; - EFI_PHYSICAL_ADDRESS PhysicalAddress; - - TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType (); + RETURN_STATUS Status; + UINTN PhysicalAddressBits; + UINTN NumberOfEntries; + PAGE_ATTRIBUTE TopLevelPageAttr; + UINTN PageTable; + PAGE_ATTRIBUTE MaxMemoryPage; + UINTN Index; + UINT64 AddressEncMask; + UINT64 *PageEntry; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + + TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType (); PhysicalAddressBits = GetPhysicalAddressWidth (); - NumberOfEntries = (UINTN)1 << (PhysicalAddressBits - - mPageAttributeTable[TopLevelPageAttr].AddressBitOffset); + NumberOfEntries = (UINTN)1 << (PhysicalAddressBits - + mPageAttributeTable[TopLevelPageAttr].AddressBitOffset); - PageTable = (UINTN) AllocatePageTableMemory (1); + PageTable = (UINTN)AllocatePageTableMemory (1); if (PageTable == 0) { return 0; } - AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); + AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask; - MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr); - PageEntry = (UINT64 *)PageTable; + MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr); + PageEntry = (UINT64 *)PageTable; PhysicalAddress = 0; for (Index = 0; Index < NumberOfEntries; ++Index) { @@ -455,7 +457,7 @@ CreatePageTable ( // Split the top page table down to the maximum page size supported // if (MaxMemoryPage < TopLevelPageAttr) { - Status = SplitPage(PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE); + Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE); ASSERT_EFI_ERROR (Status); } @@ -466,11 +468,10 @@ CreatePageTable ( *PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U); } - PageEntry += 1; + PageEntry += 1; PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length; } - return PageTable; } @@ -483,12 +484,12 @@ EnablePaging ( VOID ) { - UINTN PageTable; + UINTN PageTable; PageTable = CreatePageTable (); ASSERT (PageTable != 0); if (PageTable != 0) { - AsmWriteCr3(PageTable); + AsmWriteCr3 (PageTable); AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG } @@ -509,15 +510,15 @@ EnablePaging ( VOID EFIAPI GetStackBase ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - EFI_PHYSICAL_ADDRESS StackBase; + EFI_PHYSICAL_ADDRESS StackBase; - StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase; + StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase; StackBase += BASE_4KB; StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1); - StackBase -= PcdGet32(PcdCpuApStackSize); + StackBase -= PcdGet32 (PcdCpuApStackSize); *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase; } @@ -532,21 +533,21 @@ SetupStackGuardPage ( VOID ) { - EFI_PEI_HOB_POINTERS Hob; - EFI_PHYSICAL_ADDRESS StackBase; - UINTN NumberOfProcessors; - UINTN Bsp; - UINTN Index; + EFI_PEI_HOB_POINTERS Hob; + EFI_PHYSICAL_ADDRESS StackBase; + UINTN NumberOfProcessors; + UINTN Bsp; + UINTN Index; // // One extra page at the bottom of the stack is needed for Guard page. // - if (PcdGet32(PcdCpuApStackSize) <= EFI_PAGE_SIZE) { + if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) { DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n")); ASSERT (FALSE); } - MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); + MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL); MpInitLibWhoAmI (&Bsp); for (Index = 0; Index < NumberOfProcessors; ++Index) { StackBase = 0; @@ -554,26 +555,35 @@ SetupStackGuardPage ( if (Index == Bsp) { Hob.Raw = GetHobList (); while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) { - if (CompareGuid (&gEfiHobMemoryAllocStackGuid, - &(Hob.MemoryAllocationStack->AllocDescriptor.Name))) { + if (CompareGuid ( + &gEfiHobMemoryAllocStackGuid, + &(Hob.MemoryAllocationStack->AllocDescriptor.Name) + )) + { StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress; break; } + Hob.Raw = GET_NEXT_HOB (Hob); } } else { // // Ask AP to return is stack base address. // - MpInitLibStartupThisAP(GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL); + MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL); } + ASSERT (StackBase != 0); // // Set Guard page at stack base address. // - ConvertMemoryPageAttributes(StackBase, EFI_PAGE_SIZE, 0); - DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", - (UINT64)StackBase, (UINT64)Index)); + ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0); + DEBUG (( + DEBUG_INFO, + "Stack Guard set at %lx [cpu%lu]!\n", + (UINT64)StackBase, + (UINT64)Index + )); } // @@ -614,13 +624,13 @@ MemoryDiscoveredPpiNotifyCallback ( // the task switch (for the sake of stack switch). // InitStackGuard = FALSE; - Hob.Raw = NULL; + Hob.Raw = NULL; if (IsIa32PaeSupported ()) { - Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); + Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); InitStackGuard = PcdGetBool (PcdCpuStackGuard); } - if (InitStackGuard || Hob.Raw != NULL) { + if (InitStackGuard || (Hob.Raw != NULL)) { EnablePaging (); } @@ -643,8 +653,8 @@ MemoryDiscoveredPpiNotifyCallback ( Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw); } + CpuFlushTlb (); return Status; } - diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c index 6100799a79..59a5d932ee 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -34,10 +34,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Data structure used to allocate ACPI_CPU_DATA and its supporting structures // typedef struct { - ACPI_CPU_DATA AcpiCpuData; - MTRR_SETTINGS MtrrTable; - IA32_DESCRIPTOR GdtrProfile; - IA32_DESCRIPTOR IdtrProfile; + ACPI_CPU_DATA AcpiCpuData; + MTRR_SETTINGS MtrrTable; + IA32_DESCRIPTOR GdtrProfile; + IA32_DESCRIPTOR IdtrProfile; } ACPI_CPU_DATA_EX; /** @@ -57,12 +57,12 @@ AllocateAcpiNvsMemory ( EFI_STATUS Status; VOID *Buffer; - Status = gBS->AllocatePages ( - AllocateAnyPages, - EfiACPIMemoryNVS, - EFI_SIZE_TO_PAGES (Size), - &Address - ); + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIMemoryNVS, + EFI_SIZE_TO_PAGES (Size), + &Address + ); if (EFI_ERROR (Status)) { return NULL; } @@ -86,7 +86,7 @@ AllocateZeroPages ( IN UINTN Size ) { - VOID *Buffer; + VOID *Buffer; Buffer = AllocatePages (EFI_SIZE_TO_PAGES (Size)); if (Buffer != NULL) { @@ -95,6 +95,7 @@ AllocateZeroPages ( return Buffer; } + /** Callback function executed when the EndOfDxe event group is signaled. @@ -110,20 +111,20 @@ CpuS3DataOnEndOfDxe ( OUT VOID *Context ) { - EFI_STATUS Status; - ACPI_CPU_DATA_EX *AcpiCpuDataEx; + EFI_STATUS Status; + ACPI_CPU_DATA_EX *AcpiCpuDataEx; - AcpiCpuDataEx = (ACPI_CPU_DATA_EX *) Context; + AcpiCpuDataEx = (ACPI_CPU_DATA_EX *)Context; // // Allocate a 4KB reserved page below 1MB // AcpiCpuDataEx->AcpiCpuData.StartupVector = BASE_1MB - 1; - Status = gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - 1, - &AcpiCpuDataEx->AcpiCpuData.StartupVector - ); + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + 1, + &AcpiCpuDataEx->AcpiCpuData.StartupVector + ); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_VERBOSE, "%a\n", __FUNCTION__)); @@ -158,19 +159,19 @@ CpuS3DataInitialize ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - ACPI_CPU_DATA_EX *AcpiCpuDataEx; - ACPI_CPU_DATA *AcpiCpuData; - EFI_MP_SERVICES_PROTOCOL *MpServices; - UINTN NumberOfCpus; - UINTN NumberOfEnabledProcessors; - VOID *Stack; - UINTN GdtSize; - UINTN IdtSize; - VOID *Gdt; - VOID *Idt; - EFI_EVENT Event; - ACPI_CPU_DATA *OldAcpiCpuData; + EFI_STATUS Status; + ACPI_CPU_DATA_EX *AcpiCpuDataEx; + ACPI_CPU_DATA *AcpiCpuData; + EFI_MP_SERVICES_PROTOCOL *MpServices; + UINTN NumberOfCpus; + UINTN NumberOfEnabledProcessors; + VOID *Stack; + UINTN GdtSize; + UINTN IdtSize; + VOID *Gdt; + VOID *Idt; + EFI_EVENT Event; + ACPI_CPU_DATA *OldAcpiCpuData; if (!PcdGetBool (PcdAcpiS3Enable)) { return EFI_UNSUPPORTED; @@ -179,7 +180,7 @@ CpuS3DataInitialize ( // // Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure // - OldAcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress); + OldAcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress); AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX)); ASSERT (AcpiCpuDataEx != NULL); @@ -212,9 +213,9 @@ CpuS3DataInitialize ( AcpiCpuData->StackSize = PcdGet32 (PcdCpuApStackSize); AcpiCpuData->ApMachineCheckHandlerBase = 0; AcpiCpuData->ApMachineCheckHandlerSize = 0; - AcpiCpuData->GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile; - AcpiCpuData->IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile; - AcpiCpuData->MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable; + AcpiCpuData->GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile; + AcpiCpuData->IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile; + AcpiCpuData->MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable; // // Allocate stack space for all CPUs. @@ -238,7 +239,7 @@ CpuS3DataInitialize ( // GdtSize = AcpiCpuDataEx->GdtrProfile.Limit + 1; IdtSize = AcpiCpuDataEx->IdtrProfile.Limit + 1; - Gdt = AllocateZeroPages (GdtSize + IdtSize); + Gdt = AllocateZeroPages (GdtSize + IdtSize); ASSERT (Gdt != NULL); Idt = (VOID *)((UINTN)Gdt + GdtSize); CopyMem (Gdt, (VOID *)AcpiCpuDataEx->GdtrProfile.Base, GdtSize); diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h index 659821072d..161a43c278 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -52,19 +52,19 @@ typedef struct { // // Record the package count in this CPU. // - UINT32 PackageCount; + UINT32 PackageCount; // // Record the max core count in this CPU. // Different packages may have different core count, this value // save the max core count in all the packages. // - UINT32 MaxCoreCount; + UINT32 MaxCoreCount; // // Record the max thread count in this CPU. // Different cores may have different thread count, this value // save the max thread count in all the cores. // - UINT32 MaxThreadCount; + UINT32 MaxThreadCount; // // This field points to an array. // This array saves thread count (type UINT32) of each package. @@ -74,7 +74,7 @@ typedef struct { // therefore it doesn't need the dependency semaphores, it should set // this field to 0. // - EFI_PHYSICAL_ADDRESS ThreadCountPerPackage; + EFI_PHYSICAL_ADDRESS ThreadCountPerPackage; // // This field points to an array. // This array saves thread count (type UINT8) of each core. @@ -84,21 +84,21 @@ typedef struct { // therefore it doesn't need the dependency semaphores, it should set // this field to 0. // - EFI_PHYSICAL_ADDRESS ThreadCountPerCore; + EFI_PHYSICAL_ADDRESS ThreadCountPerCore; } CPU_STATUS_INFORMATION; // // Element of register table entry // typedef struct { - REGISTER_TYPE RegisterType; // offset 0 - 3 - UINT32 Index; // offset 4 - 7 - UINT8 ValidBitStart; // offset 8 - UINT8 ValidBitLength; // offset 9 - BOOLEAN TestThenWrite; // offset 10 - UINT8 Reserved1; // offset 11 - UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped - UINT64 Value; // offset 16-23 + REGISTER_TYPE RegisterType; // offset 0 - 3 + UINT32 Index; // offset 4 - 7 + UINT8 ValidBitStart; // offset 8 + UINT8 ValidBitLength; // offset 9 + BOOLEAN TestThenWrite; // offset 10 + UINT8 Reserved1; // offset 11 + UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped + UINT64 Value; // offset 16-23 } CPU_REGISTER_TABLE_ENTRY; // @@ -109,20 +109,20 @@ typedef struct { // // The number of valid entries in the RegisterTableEntry buffer // - UINT32 TableLength; - UINT32 NumberBeforeReset; + UINT32 TableLength; + UINT32 NumberBeforeReset; // // The size, in bytes, of the RegisterTableEntry buffer // - UINT32 AllocatedSize; + UINT32 AllocatedSize; // // The initial APIC ID of the CPU this register table applies to // - UINT32 InitialApicId; + UINT32 InitialApicId; // // Physical address of CPU_REGISTER_TABLE_ENTRY structures. // - EFI_PHYSICAL_ADDRESS RegisterTableEntry; + EFI_PHYSICAL_ADDRESS RegisterTableEntry; } CPU_REGISTER_TABLE; // @@ -151,11 +151,11 @@ typedef struct { // If a register table is not required for any one of the CPUs, then // RegisterTable may be set to 0. // - EFI_PHYSICAL_ADDRESS RegisterTable; + EFI_PHYSICAL_ADDRESS RegisterTable; // // CPU information which is required when set the register table. // - CPU_STATUS_INFORMATION CpuStatus; + CPU_STATUS_INFORMATION CpuStatus; // // Location info for each AP. // It points to an array which saves all APs location info. @@ -180,7 +180,7 @@ typedef struct { // it is recommended that the buffer be zero-filled. This buffer is used to // wake APs during an ACPI S3 resume. // - EFI_PHYSICAL_ADDRESS StartupVector; + EFI_PHYSICAL_ADDRESS StartupVector; // // Physical address of structure of type IA32_DESCRIPTOR. The // IA32_DESCRIPTOR structure provides the base address and length of a GDT @@ -188,7 +188,7 @@ typedef struct { // used during an ACPI S3 resume. This is typically the contents of the GDT // used by the boot processor when the platform is booted. // - EFI_PHYSICAL_ADDRESS GdtrProfile; + EFI_PHYSICAL_ADDRESS GdtrProfile; // // Physical address of structure of type IA32_DESCRIPTOR. The // IA32_DESCRIPTOR structure provides the base address and length of an IDT. @@ -196,31 +196,31 @@ typedef struct { // used during an ACPI S3 resume. This is typically the contents of the IDT // used by the boot processor when the platform is booted. // - EFI_PHYSICAL_ADDRESS IdtrProfile; + EFI_PHYSICAL_ADDRESS IdtrProfile; // // Physical address of a buffer that is used as stacks during ACPI S3 resume. // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This // structure must be allocated from memory of type EfiACPIMemoryNVS. // - EFI_PHYSICAL_ADDRESS StackAddress; + EFI_PHYSICAL_ADDRESS StackAddress; // // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume. // - UINT32 StackSize; + UINT32 StackSize; // // The number of CPUs. If a platform does not support hot plug CPUs, then // this is the number of CPUs detected when the platform is booted, regardless // of being enabled or disabled. If a platform does support hot plug CPUs, // then this is the maximum number of CPUs that the platform supports. // - UINT32 NumberOfCpus; + UINT32 NumberOfCpus; // // Physical address of structure of type MTRR_SETTINGS that contains a copy // of the MTRR settings that are compatible with the MTRR settings used by // the boot processor when the platform was booted. These MTRR settings are // used during an ACPI S3 resume. // - EFI_PHYSICAL_ADDRESS MtrrTable; + EFI_PHYSICAL_ADDRESS MtrrTable; // // Physical address of a buffer that contains the machine check handler that // is used during an ACPI S3 Resume. In order for this machine check @@ -228,18 +228,18 @@ typedef struct { // vector in the IDT provided by IdtrProfile must be initialized to transfer // control to this physical address. // - EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase; + EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase; // // The size, in bytes, of the machine check handler that is used during an // ACPI S3 Resume. If this field is 0, then a machine check handler is not // provided. // - UINT32 ApMachineCheckHandlerSize; + UINT32 ApMachineCheckHandlerSize; // // Data structure that is used for CPU feature initialization during ACPI S3 // resume. // - CPU_FEATURE_INIT_DATA CpuFeatureInitData; + CPU_FEATURE_INIT_DATA CpuFeatureInitData; } ACPI_CPU_DATA; #endif diff --git a/UefiCpuPkg/Include/CpuHotPlugData.h b/UefiCpuPkg/Include/CpuHotPlugData.h index 6321a149fa..dd0d7b9f3e 100644 --- a/UefiCpuPkg/Include/CpuHotPlugData.h +++ b/UefiCpuPkg/Include/CpuHotPlugData.h @@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _CPU_HOT_PLUG_DATA_H_ #define _CPU_HOT_PLUG_DATA_H_ -#define CPU_HOT_PLUG_DATA_REVISION_1 0x00000001 +#define CPU_HOT_PLUG_DATA_REVISION_1 0x00000001 typedef struct { UINT32 Revision; // Used for version identification for this structure diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h index 81c8ff63d4..b23580f1da 100644 --- a/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h +++ b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h @@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 } \ } -extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid; +extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid; #endif diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h index a005a51fd6..28eb5c7076 100644 --- a/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h +++ b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h @@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 } \ } -extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid; +extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid; #endif diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h index 2d307fbffb..2772c41a16 100644 --- a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h @@ -11,7 +11,7 @@ #ifndef _MICROCODE_PATCH_HOB_H_ #define _MICROCODE_PATCH_HOB_H_ -extern EFI_GUID gEdkiiMicrocodePatchHobGuid; +extern EFI_GUID gEdkiiMicrocodePatchHobGuid; // // The EDKII microcode patch HOB will be produced by MpInitLib and it can be diff --git a/UefiCpuPkg/Include/Guid/MsegSmram.h b/UefiCpuPkg/Include/Guid/MsegSmram.h index 01001c4730..77dd3eda05 100644 --- a/UefiCpuPkg/Include/Guid/MsegSmram.h +++ b/UefiCpuPkg/Include/Guid/MsegSmram.h @@ -15,7 +15,7 @@ 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 } \ } -extern EFI_GUID gMsegSmramGuid; +extern EFI_GUID gMsegSmramGuid; // // The data portion of this HOB is type EFI_SMRAM_DESCRIPTOR diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h index 3422997f54..022d9f2ca8 100644 --- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h +++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h @@ -13,49 +13,49 @@ typedef struct { // // Package number. // - UINT32 Package; + UINT32 Package; // // Core type of logical processor. // Value = CPUID.1Ah:EAX[31:24] // - UINT8 CoreType; + UINT8 CoreType; // // Level of the cache that this package's this type of logical processor corresponds to. // Value = CPUID.04h:EAX[07:05] // - UINT8 CacheLevel : 3; + UINT8 CacheLevel : 3; // // Type of the cache that this package's this type of logical processor corresponds to. // Value = CPUID.04h:EAX[04:00] // - UINT8 CacheType : 5; + UINT8 CacheType : 5; // // Ways of associativity. // Value = CPUID.04h:EBX[31:22] // - UINT16 CacheWays : 10; + UINT16 CacheWays : 10; // // Fully associative cache. // Value = CPUID.04h:EAX[09] // - UINT16 FullyAssociativeCache : 1; + UINT16 FullyAssociativeCache : 1; // // Direct mapped cache. // Value = CPUID.04h:EDX[02] // - UINT16 DirectMappedCache : 1; - UINT16 Reserved : 4; + UINT16 DirectMappedCache : 1; + UINT16 Reserved : 4; // // Size of single cache that this package's this type of logical processor corresponds to. // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1) // - UINT32 CacheSizeinKB; + UINT32 CacheSizeinKB; // // Number of the cache that this package's this type of logical processor corresponds to. // Have subtracted the number of caches that are shared. // - UINT16 CacheCount; + UINT16 CacheCount; } CPU_CACHE_INFO; /** @@ -78,8 +78,8 @@ typedef struct { EFI_STATUS EFIAPI GetCpuCacheInfo ( - IN OUT CPU_CACHE_INFO *CpuCacheInfo, - IN OUT UINTN *CpuCacheInfoCount + IN OUT CPU_CACHE_INFO *CpuCacheInfo, + IN OUT UINTN *CpuCacheInfoCount ); #endif diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h index 96b93aa347..b55d88b0f5 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -38,7 +38,7 @@ GetLocalApicBaseAddress ( VOID EFIAPI SetLocalApicBaseAddress ( - IN UINTN BaseAddress + IN UINTN BaseAddress ); /** @@ -120,8 +120,8 @@ GetApicVersion ( VOID EFIAPI SendFixedIpi ( - IN UINT32 ApicId, - IN UINT8 Vector + IN UINT32 ApicId, + IN UINT8 Vector ); /** @@ -134,7 +134,7 @@ SendFixedIpi ( VOID EFIAPI SendFixedIpiAllExcludingSelf ( - IN UINT8 Vector + IN UINT8 Vector ); /** @@ -147,7 +147,7 @@ SendFixedIpiAllExcludingSelf ( VOID EFIAPI SendSmiIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ); /** @@ -171,7 +171,7 @@ SendSmiIpiAllExcludingSelf ( VOID EFIAPI SendInitIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ); /** @@ -200,8 +200,8 @@ SendInitIpiAllExcludingSelf ( VOID EFIAPI SendInitSipiSipi ( - IN UINT32 ApicId, - IN UINT32 StartupRoutine + IN UINT32 ApicId, + IN UINT32 StartupRoutine ); /** @@ -218,7 +218,7 @@ SendInitSipiSipi ( VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( - IN UINT32 StartupRoutine + IN UINT32 StartupRoutine ); /** @@ -296,10 +296,10 @@ GetApicTimerCurrentCount ( VOID EFIAPI InitializeApicTimer ( - IN UINTN DivideValue, - IN UINT32 InitCount, - IN BOOLEAN PeriodicMode, - IN UINT8 Vector + IN UINTN DivideValue, + IN UINT32 InitCount, + IN BOOLEAN PeriodicMode, + IN UINT8 Vector ); /** @@ -453,5 +453,5 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Core OPTIONAL, OUT UINT32 *Thread OPTIONAL ); -#endif +#endif diff --git a/UefiCpuPkg/Include/Library/MicrocodeLib.h b/UefiCpuPkg/Include/Library/MicrocodeLib.h index f14d56ba5f..1890b50840 100644 --- a/UefiCpuPkg/Include/Library/MicrocodeLib.h +++ b/UefiCpuPkg/Include/Library/MicrocodeLib.h @@ -52,7 +52,7 @@ GetProcessorMicrocodeCpuId ( UINT32 EFIAPI GetMicrocodeLength ( - IN CPU_MICROCODE_HEADER *Microcode + IN CPU_MICROCODE_HEADER *Microcode ); /** @@ -65,7 +65,7 @@ GetMicrocodeLength ( VOID EFIAPI LoadMicrocode ( - IN CPU_MICROCODE_HEADER *Microcode + IN CPU_MICROCODE_HEADER *Microcode ); /** @@ -109,12 +109,12 @@ LoadMicrocode ( BOOLEAN EFIAPI IsValidMicrocode ( - IN CPU_MICROCODE_HEADER *Microcode, - IN UINTN MicrocodeLength, - IN UINT32 MinimumRevision, - IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, - IN UINTN MicrocodeCpuIdCount, - IN BOOLEAN VerifyChecksum + IN CPU_MICROCODE_HEADER *Microcode, + IN UINTN MicrocodeLength, + IN UINT32 MinimumRevision, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, + IN UINTN MicrocodeCpuIdCount, + IN BOOLEAN VerifyChecksum ); #endif diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h b/UefiCpuPkg/Include/Library/MpInitLib.h index d6a1e6c067..1853c46415 100644 --- a/UefiCpuPkg/Include/Library/MpInitLib.h +++ b/UefiCpuPkg/Include/Library/MpInitLib.h @@ -54,8 +54,8 @@ MpInitLibInitialize ( EFI_STATUS EFIAPI MpInitLibGetNumberOfProcessors ( - OUT UINTN *NumberOfProcessors OPTIONAL, - OUT UINTN *NumberOfEnabledProcessors OPTIONAL + OUT UINTN *NumberOfProcessors OPTIONAL, + OUT UINTN *NumberOfEnabledProcessors OPTIONAL ); /** @@ -161,12 +161,12 @@ MpInitLibGetProcessorInfo ( EFI_STATUS EFIAPI MpInitLibStartupAllAPs ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ); /** @@ -243,12 +243,12 @@ MpInitLibStartupAllAPs ( EFI_STATUS EFIAPI MpInitLibStartupThisAP ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ); /** @@ -280,8 +280,8 @@ MpInitLibStartupThisAP ( EFI_STATUS EFIAPI MpInitLibSwitchBSP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ); /** @@ -317,9 +317,9 @@ MpInitLibSwitchBSP ( EFI_STATUS EFIAPI MpInitLibEnableDisableAP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ); /** @@ -341,7 +341,7 @@ MpInitLibEnableDisableAP ( EFI_STATUS EFIAPI MpInitLibWhoAmI ( - OUT UINTN *ProcessorNumber + OUT UINTN *ProcessorNumber ); /** @@ -373,9 +373,9 @@ MpInitLibWhoAmI ( EFI_STATUS EFIAPI MpInitLibStartupAllCPUs ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ); #endif diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h index 9110787067..683d9f2c14 100644 --- a/UefiCpuPkg/Include/Library/MtrrLib.h +++ b/UefiCpuPkg/Include/Library/MtrrLib.h @@ -24,27 +24,27 @@ // #define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2 -#define MTRR_NUMBER_OF_FIXED_MTRR 11 +#define MTRR_NUMBER_OF_FIXED_MTRR 11 // // Structure to describe a fixed MTRR // typedef struct { - UINT32 Msr; - UINT32 BaseAddress; - UINT32 Length; + UINT32 Msr; + UINT32 BaseAddress; + UINT32 Length; } FIXED_MTRR; // // Structure to describe a variable MTRR // typedef struct { - UINT64 BaseAddress; - UINT64 Length; - UINT64 Type; - UINT32 Msr; - BOOLEAN Valid; - BOOLEAN Used; + UINT64 BaseAddress; + UINT64 Length; + UINT64 Type; + UINT32 Msr; + BOOLEAN Valid; + BOOLEAN Used; } VARIABLE_MTRR; // @@ -59,14 +59,14 @@ typedef struct _MTRR_VARIABLE_SETTING_ { // Array for variable MTRRs // typedef struct _MTRR_VARIABLE_SETTINGS_ { - MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; + MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; } MTRR_VARIABLE_SETTINGS; // // Array for fixed MTRRs // typedef struct _MTRR_FIXED_SETTINGS_ { - UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR]; + UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR]; } MTRR_FIXED_SETTINGS; // @@ -98,9 +98,9 @@ typedef enum { #define MTRR_CACHE_INVALID_TYPE 7 typedef struct { - UINT64 BaseAddress; - UINT64 Length; - MTRR_MEMORY_CACHE_TYPE Type; + UINT64 BaseAddress; + UINT64 Length; + MTRR_MEMORY_CACHE_TYPE Type; } MTRR_MEMORY_RANGE; /** @@ -168,7 +168,6 @@ MtrrSetMemoryAttribute ( IN MTRR_MEMORY_CACHE_TYPE Attribute ); - /** This function will get the memory cache type of the specific address. This function is mainly for debugging purposes. @@ -181,10 +180,9 @@ MtrrSetMemoryAttribute ( MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetMemoryAttribute ( - IN PHYSICAL_ADDRESS Address + IN PHYSICAL_ADDRESS Address ); - /** This function gets the content in fixed MTRRs @@ -193,13 +191,12 @@ MtrrGetMemoryAttribute ( @return The pointer of FixedSettings **/ -MTRR_FIXED_SETTINGS* +MTRR_FIXED_SETTINGS * EFIAPI MtrrGetFixedMtrr ( - OUT MTRR_FIXED_SETTINGS *FixedSettings + OUT MTRR_FIXED_SETTINGS *FixedSettings ); - /** This function gets the content in all MTRRs (variable and fixed) @@ -211,10 +208,9 @@ MtrrGetFixedMtrr ( MTRR_SETTINGS * EFIAPI MtrrGetAllMtrrs ( - OUT MTRR_SETTINGS *MtrrSetting + OUT MTRR_SETTINGS *MtrrSetting ); - /** This function sets all MTRRs (variable and fixed) @@ -226,10 +222,9 @@ MtrrGetAllMtrrs ( MTRR_SETTINGS * EFIAPI MtrrSetAllMtrrs ( - IN MTRR_SETTINGS *MtrrSetting + IN MTRR_SETTINGS *MtrrSetting ); - /** Get the attribute of variable MTRRs. @@ -248,12 +243,11 @@ MtrrSetAllMtrrs ( UINT32 EFIAPI MtrrGetMemoryAttributeInVariableMtrr ( - IN UINT64 MtrrValidBitsMask, - IN UINT64 MtrrValidAddressMask, - OUT VARIABLE_MTRR *VariableMtrr + IN UINT64 MtrrValidBitsMask, + IN UINT64 MtrrValidAddressMask, + OUT VARIABLE_MTRR *VariableMtrr ); - /** This function prints all MTRRs for debugging. **/ @@ -355,10 +349,11 @@ MtrrSetMemoryAttributeInMtrrSettings ( RETURN_STATUS EFIAPI MtrrSetMemoryAttributesInMtrrSettings ( - IN OUT MTRR_SETTINGS *MtrrSetting, - IN VOID *Scratch, - IN OUT UINTN *ScratchSize, - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount + IN OUT MTRR_SETTINGS *MtrrSetting, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount ); + #endif // _MTRR_LIB_H_ diff --git a/UefiCpuPkg/Include/Library/PlatformSecLib.h b/UefiCpuPkg/Include/Library/PlatformSecLib.h index c27ecfaf94..564fc31542 100644 --- a/UefiCpuPkg/Include/Library/PlatformSecLib.h +++ b/UefiCpuPkg/Include/Library/PlatformSecLib.h @@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_PEI_PPI_DESCRIPTOR * EFIAPI SecPlatformMain ( - IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData ); /** @@ -47,9 +47,9 @@ SecPlatformMain ( EFI_STATUS EFIAPI SecPlatformInformation ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ); /** diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 60caf313bf..36459afc5e 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -20,62 +20,62 @@ /// modifiers of a CPU feature. When used in a list, the define value /// CPU_FEATURE_END is used to terminate a list of CPU feature values. /// @{ -#define CPU_FEATURE_AESNI 0 -#define CPU_FEATURE_TURBO_MODE 1 -#define CPU_FEATURE_MWAIT 2 -#define CPU_FEATURE_ACPI 3 -#define CPU_FEATURE_EIST 4 -#define CPU_FEATURE_RESERVED_5 5 -#define CPU_FEATURE_FASTSTRINGS 6 -#define CPU_FEATURE_VMX 7 -#define CPU_FEATURE_SMX 8 -#define CPU_FEATURE_LMCE 9 -#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10 -#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11 -#define CPU_FEATURE_MCE 12 -#define CPU_FEATURE_MCA 13 -#define CPU_FEATURE_MCG_CTL 14 -#define CPU_FEATURE_PENDING_BREAK 15 -#define CPU_FEATURE_C1E 16 -#define CPU_FEATURE_C1_AUTO_DEMOTION 17 -#define CPU_FEATURE_C3_AUTO_DEMOTION 18 -#define CPU_FEATURE_C1_UNDEMOTION 19 -#define CPU_FEATURE_C3_UNDEMOTION 20 -#define CPU_FEATURE_C_STATE 21 -#define CPU_FEATURE_TM 22 -#define CPU_FEATURE_TM2 23 -#define CPU_FEATURE_X2APIC 24 -#define CPU_FEATURE_RESERVED_25 25 -#define CPU_FEATURE_RESERVED_26 26 -#define CPU_FEATURE_RESERVED_27 27 -#define CPU_FEATURE_RESERVED_28 28 -#define CPU_FEATURE_RESERVED_29 29 -#define CPU_FEATURE_RESERVED_30 30 -#define CPU_FEATURE_RESERVED_31 31 - -#define CPU_FEATURE_L2_PREFETCHER (32+0) -#define CPU_FEATURE_L1_DATA_PREFETCHER (32+1) -#define CPU_FEATURE_HARDWARE_PREFETCHER (32+2) -#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH (32+3) -#define CPU_FEATURE_DCU_PREFETCHER (32+4) -#define CPU_FEATURE_IP_PREFETCHER (32+5) -#define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6) -#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7) -#define CPU_FEATURE_THREE_STRIKE_COUNTER (32+8) -#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9) -#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10) -#define CPU_FEATURE_PPIN (32+11) -#define CPU_FEATURE_PROC_TRACE (32+12) - -#define CPU_FEATURE_BEFORE_ALL BIT23 -#define CPU_FEATURE_AFTER_ALL BIT24 -#define CPU_FEATURE_THREAD_BEFORE BIT25 -#define CPU_FEATURE_THREAD_AFTER BIT26 -#define CPU_FEATURE_CORE_BEFORE BIT27 -#define CPU_FEATURE_CORE_AFTER BIT28 -#define CPU_FEATURE_PACKAGE_BEFORE BIT29 -#define CPU_FEATURE_PACKAGE_AFTER BIT30 -#define CPU_FEATURE_END MAX_UINT32 +#define CPU_FEATURE_AESNI 0 +#define CPU_FEATURE_TURBO_MODE 1 +#define CPU_FEATURE_MWAIT 2 +#define CPU_FEATURE_ACPI 3 +#define CPU_FEATURE_EIST 4 +#define CPU_FEATURE_RESERVED_5 5 +#define CPU_FEATURE_FASTSTRINGS 6 +#define CPU_FEATURE_VMX 7 +#define CPU_FEATURE_SMX 8 +#define CPU_FEATURE_LMCE 9 +#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10 +#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11 +#define CPU_FEATURE_MCE 12 +#define CPU_FEATURE_MCA 13 +#define CPU_FEATURE_MCG_CTL 14 +#define CPU_FEATURE_PENDING_BREAK 15 +#define CPU_FEATURE_C1E 16 +#define CPU_FEATURE_C1_AUTO_DEMOTION 17 +#define CPU_FEATURE_C3_AUTO_DEMOTION 18 +#define CPU_FEATURE_C1_UNDEMOTION 19 +#define CPU_FEATURE_C3_UNDEMOTION 20 +#define CPU_FEATURE_C_STATE 21 +#define CPU_FEATURE_TM 22 +#define CPU_FEATURE_TM2 23 +#define CPU_FEATURE_X2APIC 24 +#define CPU_FEATURE_RESERVED_25 25 +#define CPU_FEATURE_RESERVED_26 26 +#define CPU_FEATURE_RESERVED_27 27 +#define CPU_FEATURE_RESERVED_28 28 +#define CPU_FEATURE_RESERVED_29 29 +#define CPU_FEATURE_RESERVED_30 30 +#define CPU_FEATURE_RESERVED_31 31 + +#define CPU_FEATURE_L2_PREFETCHER (32+0) +#define CPU_FEATURE_L1_DATA_PREFETCHER (32+1) +#define CPU_FEATURE_HARDWARE_PREFETCHER (32+2) +#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH (32+3) +#define CPU_FEATURE_DCU_PREFETCHER (32+4) +#define CPU_FEATURE_IP_PREFETCHER (32+5) +#define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6) +#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7) +#define CPU_FEATURE_THREE_STRIKE_COUNTER (32+8) +#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9) +#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10) +#define CPU_FEATURE_PPIN (32+11) +#define CPU_FEATURE_PROC_TRACE (32+12) + +#define CPU_FEATURE_BEFORE_ALL BIT23 +#define CPU_FEATURE_AFTER_ALL BIT24 +#define CPU_FEATURE_THREAD_BEFORE BIT25 +#define CPU_FEATURE_THREAD_AFTER BIT26 +#define CPU_FEATURE_CORE_BEFORE BIT27 +#define CPU_FEATURE_CORE_AFTER BIT28 +#define CPU_FEATURE_PACKAGE_BEFORE BIT29 +#define CPU_FEATURE_PACKAGE_AFTER BIT30 +#define CPU_FEATURE_END MAX_UINT32 /// @} /// @@ -85,28 +85,28 @@ typedef struct { // // Set to 1 when current processor is the first thread in the core it resides in. // - UINT32 Thread : 1; + UINT32 Thread : 1; // // Set to 1 when current processor is a thread of the first core in the module it resides in. // - UINT32 Core : 1; + UINT32 Core : 1; // // Set to 1 when current processor is a thread of the first module in the tile it resides in. // - UINT32 Module : 1; + UINT32 Module : 1; // // Set to 1 when current processor is a thread of the first tile in the die it resides in. // - UINT32 Tile : 1; + UINT32 Tile : 1; // // Set to 1 when current processor is a thread of the first die in the package it resides in. // - UINT32 Die : 1; + UINT32 Die : 1; // // Set to 1 when current processor is a thread of the first package in the system. // - UINT32 Package : 1; - UINT32 Reserved : 26; + UINT32 Package : 1; + UINT32 Reserved : 26; } REGISTER_CPU_FEATURE_FIRST_PROCESSOR; /// @@ -118,36 +118,36 @@ typedef struct { /// /// The package that the CPU resides /// - EFI_PROCESSOR_INFORMATION ProcessorInfo; + EFI_PROCESSOR_INFORMATION ProcessorInfo; /// /// The bit flag indicating whether the CPU is the first Thread/Core/Module/Tile/Die/Package in its parent scope. /// - REGISTER_CPU_FEATURE_FIRST_PROCESSOR First; + REGISTER_CPU_FEATURE_FIRST_PROCESSOR First; /// /// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// - UINT32 DisplayFamily; + UINT32 DisplayFamily; /// /// The Display Model of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// - UINT32 DisplayModel; + UINT32 DisplayModel; /// /// The Stepping ID of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// - UINT32 SteppingId; + UINT32 SteppingId; /// /// The Processor Type of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// - UINT32 ProcessorType; + UINT32 ProcessorType; /// /// Bit field structured returned in ECX from CPUID leaf CPUID_VERSION_INFO /// - CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx; + CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx; /// /// Bit field structured returned in EDX from CPUID leaf CPUID_VERSION_INFO /// - CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx; + CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx; } REGISTER_CPU_FEATURE_INFORMATION; /** @@ -167,7 +167,7 @@ typedef struct { BOOLEAN EFIAPI IsCpuFeatureSupported ( - IN UINT32 Feature + IN UINT32 Feature ); /** @@ -184,7 +184,7 @@ IsCpuFeatureSupported ( BOOLEAN EFIAPI IsCpuFeatureInSetting ( - IN UINT32 Feature + IN UINT32 Feature ); /** @@ -303,10 +303,10 @@ RETURN_STATUS RETURN_STATUS EFIAPI RegisterCpuFeature ( - IN CHAR8 *FeatureName OPTIONAL, - IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL, - IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL, - IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL, + IN CHAR8 *FeatureName OPTIONAL, + IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL, + IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL, + IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL, ... ); @@ -348,7 +348,7 @@ CpuFeaturesInitialize ( VOID EFIAPI SwitchBspAfterFeaturesInitialize ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ); /** @@ -368,11 +368,11 @@ SwitchBspAfterFeaturesInitialize ( VOID EFIAPI CpuRegisterTableWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ); /** @@ -394,11 +394,11 @@ CpuRegisterTableWrite ( VOID EFIAPI CpuRegisterTableTestThenWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ); /** @@ -418,11 +418,11 @@ CpuRegisterTableTestThenWrite ( VOID EFIAPI PreSmmCpuRegisterTableWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ); /** diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h index dbcd57e0ad..54cae865a2 100644 --- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h @@ -408,7 +408,7 @@ SmmCpuFeaturesCompleteSmmReadyToLock ( VOID * EFIAPI SmmCpuFeaturesAllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ); #endif diff --git a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h b/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h index fdb756de9d..f9cc3f7249 100644 --- a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h +++ b/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h @@ -13,10 +13,10 @@ /// SMM Page Size Type /// typedef enum { - SmmPageSize4K, - SmmPageSize2M, - SmmPageSize1G, - MaxSmmPageSizeType + SmmPageSize4K, + SmmPageSize2M, + SmmPageSize1G, + MaxSmmPageSizeType } SMM_PAGE_SIZE_TYPE; /** @@ -74,7 +74,7 @@ ClearTopLevelSmiStatus ( EFI_STATUS EFIAPI PlatformSmmBspElection ( - OUT BOOLEAN *IsBsp + OUT BOOLEAN *IsBsp ); /** @@ -94,10 +94,10 @@ PlatformSmmBspElection ( EFI_STATUS EFIAPI GetPlatformPageTableAttribute ( - IN UINT64 Address, - OUT SMM_PAGE_SIZE_TYPE *PageSize, - OUT UINTN *NumOfPages, - OUT UINTN *PageAttribute + IN UINT64 Address, + OUT SMM_PAGE_SIZE_TYPE *PageSize, + OUT UINTN *NumOfPages, + OUT UINTN *PageAttribute ); #endif diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h index 092c1d2116..0ff4a35774 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -13,8 +13,6 @@ #ifndef __UEFI_CPU_LIB_H__ #define __UEFI_CPU_LIB_H__ - - /** Initializes floating point units for requirement of UEFI specification. diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/Library/VmgExitLib.h index 061948cf84..ebda1c3d90 100644 --- a/UefiCpuPkg/Include/Library/VmgExitLib.h +++ b/UefiCpuPkg/Include/Library/VmgExitLib.h @@ -15,7 +15,6 @@ #include #include - /** Perform VMGEXIT. @@ -38,10 +37,10 @@ UINT64 EFIAPI VmgExit ( - IN OUT GHCB *Ghcb, - IN UINT64 ExitCode, - IN UINT64 ExitInfo1, - IN UINT64 ExitInfo2 + IN OUT GHCB *Ghcb, + IN UINT64 ExitCode, + IN UINT64 ExitInfo1, + IN UINT64 ExitInfo2 ); /** @@ -58,8 +57,8 @@ VmgExit ( VOID EFIAPI VmgInit ( - IN OUT GHCB *Ghcb, - IN OUT BOOLEAN *InterruptState + IN OUT GHCB *Ghcb, + IN OUT BOOLEAN *InterruptState ); /** @@ -76,8 +75,8 @@ VmgInit ( VOID EFIAPI VmgDone ( - IN OUT GHCB *Ghcb, - IN BOOLEAN InterruptState + IN OUT GHCB *Ghcb, + IN BOOLEAN InterruptState ); /** @@ -93,8 +92,8 @@ VmgDone ( VOID EFIAPI VmgSetOffsetValid ( - IN OUT GHCB *Ghcb, - IN GHCB_REGISTER Offset + IN OUT GHCB *Ghcb, + IN GHCB_REGISTER Offset ); /** @@ -113,8 +112,8 @@ VmgSetOffsetValid ( BOOLEAN EFIAPI VmgIsOffsetValid ( - IN GHCB *Ghcb, - IN GHCB_REGISTER Offset + IN GHCB *Ghcb, + IN GHCB_REGISTER Offset ); /** diff --git a/UefiCpuPkg/Include/Ppi/MpServices2.h b/UefiCpuPkg/Include/Ppi/MpServices2.h index 3e224ed995..36feac5237 100644 --- a/UefiCpuPkg/Include/Ppi/MpServices2.h +++ b/UefiCpuPkg/Include/Ppi/MpServices2.h @@ -16,7 +16,7 @@ 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba} \ } -typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI; +typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI; /** Get the number of CPU's. @@ -35,7 +35,7 @@ typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI; **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)( IN EDKII_PEI_MP_SERVICES2_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors @@ -57,7 +57,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer @@ -97,7 +97,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, @@ -139,7 +139,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, @@ -171,7 +171,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP @@ -205,7 +205,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, @@ -227,12 +227,11 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI)( IN EDKII_PEI_MP_SERVICES2_PPI *This, OUT UINTN *ProcessorNumber ); - /** Activate all of the application proessors. @@ -256,7 +255,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS) ( +(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS)( IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN TimeoutInMicroSeconds, @@ -264,16 +263,16 @@ EFI_STATUS ); struct _EDKII_PEI_MP_SERVICES2_PPI { - EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; - EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; - EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; - EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; - EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP; - EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; - EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI; - EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs; + EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; + EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; + EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; + EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; + EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP; + EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; + EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI; + EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs; }; -extern EFI_GUID gEdkiiPeiMpServices2PpiGuid; +extern EFI_GUID gEdkiiPeiMpServices2PpiGuid; #endif diff --git a/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h b/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h index ea865acbb5..2ea99394a9 100644 --- a/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h +++ b/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h @@ -46,9 +46,9 @@ EFI_STATUS /// Republish SEC PPIs /// struct _REPUBLISH_SEC_PPI_PPI { - REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS RepublishSecPpis; + REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS RepublishSecPpis; }; -extern EFI_GUID gRepublishSecPpiPpiGuid; +extern EFI_GUID gRepublishSecPpiPpiGuid; #endif diff --git a/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h b/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h index be48965422..ee20e30414 100644 --- a/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h +++ b/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h @@ -14,11 +14,11 @@ 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 } \ } -typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE_PPI; +typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE_PPI; typedef struct { - UINT32 ProcessorSignature; - UINT8 PlatformId; + UINT32 ProcessorSignature; + UINT8 PlatformId; } EDKII_PEI_MICROCODE_CPU_ID; /** @@ -44,7 +44,7 @@ typedef struct { **/ typedef EFI_STATUS -(EFIAPI *EDKII_PEI_SHADOW_MICROCODE) ( +(EFIAPI *EDKII_PEI_SHADOW_MICROCODE)( IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, IN UINTN CpuIdCount, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, @@ -57,10 +57,9 @@ EFI_STATUS /// abstracts handling microcode shadow support. /// struct _EDKII_PEI_SHADOW_MICROCODE_PPI { - EDKII_PEI_SHADOW_MICROCODE ShadowMicrocode; + EDKII_PEI_SHADOW_MICROCODE ShadowMicrocode; }; -extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid; +extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid; #endif - diff --git a/UefiCpuPkg/Include/Protocol/SmMonitorInit.h b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h index db2ce11f1e..0f77897e03 100644 --- a/UefiCpuPkg/Include/Protocol/SmMonitorInit.h +++ b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h @@ -34,7 +34,7 @@ **/ typedef EFI_STATUS -(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR) ( +(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR)( IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize ); @@ -54,7 +54,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE) ( +(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE)( IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL ); @@ -74,7 +74,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE) ( +(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE)( IN STM_RSC *ResourceList OPTIONAL, IN UINT32 NumEntries OPTIONAL ); @@ -94,14 +94,14 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE) ( +(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE)( OUT STM_RSC *ResourceList, IN OUT UINT32 *ResourceSize ); typedef UINT32 EFI_SM_MONITOR_STATE; -#define EFI_SM_MONITOR_STATE_ENABLED 0x1 -#define EFI_SM_MONITOR_STATE_ACTIVATED 0x2 +#define EFI_SM_MONITOR_STATE_ENABLED 0x1 +#define EFI_SM_MONITOR_STATE_ACTIVATED 0x2 /** @@ -112,7 +112,7 @@ typedef UINT32 EFI_SM_MONITOR_STATE; **/ typedef EFI_SM_MONITOR_STATE -(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE) ( +(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE)( VOID ); @@ -120,16 +120,16 @@ typedef struct _EFI_SM_MONITOR_INIT_PROTOCOL { // // Valid at boot-time only // - EFI_SM_MONITOR_LOAD_MONITOR LoadMonitor; - EFI_SM_MONITOR_ADD_PI_RESOURCE AddPiResource; - EFI_SM_MONITOR_DELETE_PI_RESOURCE DeletePiResource; - EFI_SM_MONITOR_GET_PI_RESOURCE GetPiResource; + EFI_SM_MONITOR_LOAD_MONITOR LoadMonitor; + EFI_SM_MONITOR_ADD_PI_RESOURCE AddPiResource; + EFI_SM_MONITOR_DELETE_PI_RESOURCE DeletePiResource; + EFI_SM_MONITOR_GET_PI_RESOURCE GetPiResource; // // Valid at runtime // - EFI_SM_MONITOR_GET_MONITOR_STATE GetMonitorState; + EFI_SM_MONITOR_GET_MONITOR_STATE GetMonitorState; } EFI_SM_MONITOR_INIT_PROTOCOL; -extern EFI_GUID gEfiSmMonitorInitProtocolGuid; +extern EFI_GUID gEfiSmMonitorInitProtocolGuid; #endif diff --git a/UefiCpuPkg/Include/Protocol/SmmCpuService.h b/UefiCpuPkg/Include/Protocol/SmmCpuService.h index 13ba1feeba..952767afce 100644 --- a/UefiCpuPkg/Include/Protocol/SmmCpuService.h +++ b/UefiCpuPkg/Include/Protocol/SmmCpuService.h @@ -44,7 +44,7 @@ typedef struct _EFI_SMM_CPU_SERVICE_PROTOCOL EFI_SMM_CPU_SERVICE_PROTOCOL; **/ typedef EFI_STATUS -(EFIAPI * EFI_SMM_GET_PROCESSOR_INFO) ( +(EFIAPI *EFI_SMM_GET_PROCESSOR_INFO)( IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer @@ -82,7 +82,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI * EFI_SMM_SWITCH_BSP) ( +(EFIAPI *EFI_SMM_SWITCH_BSP)( IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber ); @@ -106,7 +106,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SMM_ADD_PROCESSOR) ( +(EFIAPI *EFI_SMM_ADD_PROCESSOR)( IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINT64 ProcessorId, OUT UINTN *ProcessorNumber @@ -128,7 +128,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SMM_REMOVE_PROCESSOR) ( +(EFIAPI *EFI_SMM_REMOVE_PROCESSOR)( IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber ); @@ -156,7 +156,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI * EFI_SMM_WHOAMI) ( +(EFIAPI *EFI_SMM_WHOAMI)( IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, OUT UINTN *ProcessorNumber ); @@ -180,7 +180,7 @@ EFI_STATUS **/ typedef EFI_STATUS -(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER) ( +(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER)( IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler @@ -190,14 +190,14 @@ EFI_STATUS // This protocol provides CPU services from SMM. // struct _EFI_SMM_CPU_SERVICE_PROTOCOL { - EFI_SMM_GET_PROCESSOR_INFO GetProcessorInfo; - EFI_SMM_SWITCH_BSP SwitchBsp; - EFI_SMM_ADD_PROCESSOR AddProcessor; - EFI_SMM_REMOVE_PROCESSOR RemoveProcessor; - EFI_SMM_WHOAMI WhoAmI; - EFI_SMM_REGISTER_EXCEPTION_HANDLER RegisterExceptionHandler; + EFI_SMM_GET_PROCESSOR_INFO GetProcessorInfo; + EFI_SMM_SWITCH_BSP SwitchBsp; + EFI_SMM_ADD_PROCESSOR AddProcessor; + EFI_SMM_REMOVE_PROCESSOR RemoveProcessor; + EFI_SMM_WHOAMI WhoAmI; + EFI_SMM_REGISTER_EXCEPTION_HANDLER RegisterExceptionHandler; }; -extern EFI_GUID gEfiSmmCpuServiceProtocolGuid; +extern EFI_GUID gEfiSmmCpuServiceProtocolGuid; #endif diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h index 689c825777..55498ce3ea 100644 --- a/UefiCpuPkg/Include/Register/LocalApic.h +++ b/UefiCpuPkg/Include/Register/LocalApic.h @@ -11,4 +11,3 @@ #include #endif - diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c index 50891618c4..5d925bc273 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -77,5 +77,5 @@ GetCpuSteppingId ( AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); - return (UINT8) Eax.Bits.SteppingId; + return (UINT8)Eax.Bits.SteppingId; } diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index 7b4e730f98..f9e06b2fca 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported ( AsmCpuid (1, &RegEax, NULL, NULL, NULL); FamilyId = BitFieldRead32 (RegEax, 8, 11); - if (FamilyId == 0x04 || FamilyId == 0x05) { + if ((FamilyId == 0x04) || (FamilyId == 0x05)) { // // CPUs with a FamilyId of 0x04 or 0x05 do not support the // Local APIC Base Address MSR // return FALSE; } + return TRUE; } @@ -78,8 +79,8 @@ GetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + - (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) + + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); } /** @@ -93,7 +94,7 @@ GetLocalApicBaseAddress ( VOID EFIAPI SetLocalApicBaseAddress ( - IN UINTN BaseAddress + IN UINTN BaseAddress ) { MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; @@ -109,8 +110,8 @@ SetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); - ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); + ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12); + ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32)); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } @@ -137,7 +138,7 @@ ReadLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); - return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); + return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset); } /** @@ -157,14 +158,14 @@ ReadLocalApicReg ( VOID EFIAPI WriteLocalApicReg ( - IN UINTN MmioOffset, - IN UINT32 Value + IN UINTN MmioOffset, + IN UINT32 Value ) { ASSERT ((MmioOffset & 0xf) == 0); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); - MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); + MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value); } /** @@ -177,13 +178,13 @@ WriteLocalApicReg ( **/ VOID SendIpi ( - IN UINT32 IcrLow, - IN UINT32 ApicId + IN UINT32 IcrLow, + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLowReg; - UINT32 IcrHigh; - BOOLEAN InterruptState; + LOCAL_APIC_ICR_LOW IcrLowReg; + UINT32 IcrHigh; + BOOLEAN InterruptState; ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (ApicId <= 0xff); @@ -222,7 +223,6 @@ SendIpi ( WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh); SetInterruptState (InterruptState); - } // @@ -244,21 +244,21 @@ GetApicMode ( ) { DEBUG_CODE_BEGIN (); - { - MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; + { + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; + // + // Check to see if the CPU supports the APIC Base Address MSR + // + if (LocalApicBaseAddressMsrSupported ()) { + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); // - // Check to see if the CPU supports the APIC Base Address MSR + // Local APIC should have been enabled // - if (LocalApicBaseAddressMsrSupported ()) { - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - // - // Local APIC should have been enabled - // - ASSERT (ApicBaseMsr.Bits.EN != 0); - ASSERT (ApicBaseMsr.Bits.EXTD == 0); - } + ASSERT (ApicBaseMsr.Bits.EN != 0); + ASSERT (ApicBaseMsr.Bits.EXTD == 0); } + } DEBUG_CODE_END (); return LOCAL_APIC_MODE_XAPIC; } @@ -299,9 +299,9 @@ GetInitialApicId ( VOID ) { - UINT32 ApicId; - UINT32 MaxCpuIdIndex; - UINT32 RegEbx; + UINT32 ApicId; + UINT32 MaxCpuIdIndex; + UINT32 RegEbx; ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); @@ -338,7 +338,7 @@ GetApicId ( VOID ) { - UINT32 ApicId; + UINT32 ApicId; ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); @@ -347,9 +347,10 @@ GetApicId ( // If the initial local APIC ID is less 0x100, read APIC ID from // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID. // - ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); + ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); ApicId >>= 24; } + return ApicId; } @@ -378,16 +379,16 @@ GetApicVersion ( VOID EFIAPI SendFixedIpi ( - IN UINT32 ApicId, - IN UINT8 Vector + IN UINT32 ApicId, + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Level = 1; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, ApicId); } @@ -401,16 +402,16 @@ SendFixedIpi ( VOID EFIAPI SendFixedIpiAllExcludingSelf ( - IN UINT8 Vector + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, 0); } @@ -424,14 +425,14 @@ SendFixedIpiAllExcludingSelf ( VOID EFIAPI SendSmiIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -446,11 +447,11 @@ SendSmiIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -465,14 +466,14 @@ SendSmiIpiAllExcludingSelf ( VOID EFIAPI SendInitIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -487,11 +488,11 @@ SendInitIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -511,21 +512,21 @@ SendInitIpiAllExcludingSelf ( VOID EFIAPI SendInitSipiSipi ( - IN UINT32 ApicId, - IN UINT32 StartupRoutine + IN UINT32 ApicId, + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpi (ApicId); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); if (!StandardSignatureIsAuthenticAMD ()) { MicroSecondDelay (200); @@ -547,20 +548,20 @@ SendInitSipiSipi ( VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( - IN UINT32 StartupRoutine + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpiAllExcludingSelf (); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); if (!StandardSignatureIsAuthenticAMD ()) { @@ -616,13 +617,13 @@ ProgramVirtualWireMode ( VOID ) { - LOCAL_APIC_SVR Svr; - LOCAL_APIC_LVT_LINT Lint; + LOCAL_APIC_SVR Svr; + LOCAL_APIC_LVT_LINT Lint; // // Enable the APIC via SVR and set the spurious interrupt to use Int 00F. // - Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); + Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); Svr.Bits.SpuriousVector = 0xf; Svr.Bits.SoftwareEnable = 1; WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32); @@ -630,21 +631,21 @@ ProgramVirtualWireMode ( // // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32); // // Program the LINT0 vector entry as NMI. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32); } @@ -659,13 +660,13 @@ DisableLvtInterrupts ( VOID ) { - LOCAL_APIC_LVT_LINT LvtLint; + LOCAL_APIC_LVT_LINT LvtLint; - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32); - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32); } @@ -712,15 +713,15 @@ GetApicTimerCurrentCount ( VOID EFIAPI InitializeApicTimer ( - IN UINTN DivideValue, - IN UINT32 InitCount, - IN BOOLEAN PeriodicMode, - IN UINT8 Vector + IN UINTN DivideValue, + IN UINT32 InitCount, + IN BOOLEAN PeriodicMode, + IN UINT8 Vector ) { - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; - UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; // // Ensure local APIC is in software-enabled state. @@ -734,10 +735,10 @@ InitializeApicTimer ( if (DivideValue != 0) { ASSERT (DivideValue <= 128); - ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); + ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue)); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Bits.DivideValue1 = (Divisor & 0x3); Dcr.Bits.DivideValue2 = (Divisor >> 2); WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); @@ -752,7 +753,8 @@ InitializeApicTimer ( } else { LvtTimer.Bits.TimerMode = 0; } - LvtTimer.Bits.Mask = 0; + + LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -774,25 +776,25 @@ GetApicTimerState ( OUT UINT8 *Vector OPTIONAL ) { - UINT32 Divisor; - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; // // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt // Vector Register. // This bit will be 1, if local APIC is software enabled. // - ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); + ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); if (DivideValue != NULL) { - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); - Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); - Divisor = (Divisor + 1) & 0x7; + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); + Divisor = (Divisor + 1) & 0x7; *DivideValue = ((UINTN)1) << Divisor; } - if (PeriodicMode != NULL || Vector != NULL) { + if ((PeriodicMode != NULL) || (Vector != NULL)) { LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); if (PeriodicMode != NULL) { if (LvtTimer.Bits.TimerMode == 1) { @@ -801,8 +803,9 @@ GetApicTimerState ( *PeriodicMode = FALSE; } } + if (Vector != NULL) { - *Vector = (UINT8) LvtTimer.Bits.Vector; + *Vector = (UINT8)LvtTimer.Bits.Vector; } } } @@ -816,9 +819,9 @@ EnableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -832,9 +835,9 @@ DisableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -851,7 +854,7 @@ GetApicTimerInterruptState ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); return (BOOLEAN)(LvtTimer.Bits.Mask == 0); @@ -944,6 +947,7 @@ GetApicMsiValue ( MsiData.Bits.Level = 1; } } + return MsiData.Uint64; } @@ -995,12 +999,15 @@ GetProcessorLocationByApicId ( if (Thread != NULL) { *Thread = 0; } + if (Core != NULL) { *Core = 0; } + if (Package != NULL) { *Package = 0; } + return; } @@ -1008,7 +1015,7 @@ GetProcessorLocationByApicId ( // Assume three-level mapping of APIC ID: Package|Core|Thread. // ThreadBits = 0; - CoreBits = 0; + CoreBits = 0; // // Get max index of CPUID @@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported = FALSE; if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId ( CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; break; } + SubIndex++; } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } @@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { @@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId ( MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); } } - } - else { + } else { // // Extract core count based on CACHE information // @@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId ( } } - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); + CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1); } if (Thread != NULL) { *Thread = InitialApicId & ((1 << ThreadBits) - 1); } + if (Core != NULL) { *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } + if (Package != NULL) { *Package = (InitialApicId >> (ThreadBits + CoreBits)); } @@ -1158,13 +1167,13 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Thread OPTIONAL ) { - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxStandardCpuIdIndex; - UINT32 Index; - UINTN LevelType; - UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; - UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxStandardCpuIdIndex; + UINT32 Index; + UINTN LevelType; + UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] = 0; @@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId ( if (Die != NULL) { *Die = 0; } + if (Tile != NULL) { *Tile = 0; } + if (Module != NULL) { *Module = 0; } + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); return; } @@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId ( // is the preferred mechanism for enumerating topology. // for (Index = 0; ; Index++) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_V2_EXTENDED_TOPOLOGY, Index, &ExtendedTopologyEax.Uint32, @@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId ( if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { break; } + ASSERT (LevelType < ARRAY_SIZE (Bits)); Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; } @@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId ( } Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT - ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 - ; LevelType ++ - ) { + ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 + ; LevelType++ + ) + { if (Location[LevelType] != NULL) { // // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index cdcbca0461..aaa42ff845 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported ( AsmCpuid (1, &RegEax, NULL, NULL, NULL); FamilyId = BitFieldRead32 (RegEax, 8, 11); - if (FamilyId == 0x04 || FamilyId == 0x05) { + if ((FamilyId == 0x04) || (FamilyId == 0x05)) { // // CPUs with a FamilyId of 0x04 or 0x05 do not support the // Local APIC Base Address MSR // return FALSE; } + return TRUE; } @@ -79,8 +80,8 @@ GetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + - (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) + + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); } /** @@ -94,7 +95,7 @@ GetLocalApicBaseAddress ( VOID EFIAPI SetLocalApicBaseAddress ( - IN UINTN BaseAddress + IN UINTN BaseAddress ) { MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; @@ -110,8 +111,8 @@ SetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); - ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); + ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12); + ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32)); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } @@ -135,12 +136,12 @@ ReadLocalApicReg ( IN UINTN MmioOffset ) { - UINT32 MsrIndex; + UINT32 MsrIndex; ASSERT ((MmioOffset & 0xf) == 0); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { - return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); + return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset); } else { // // DFR is not supported in x2APIC mode. @@ -174,16 +175,16 @@ ReadLocalApicReg ( VOID EFIAPI WriteLocalApicReg ( - IN UINTN MmioOffset, - IN UINT32 Value + IN UINTN MmioOffset, + IN UINT32 Value ) { - UINT32 MsrIndex; + UINT32 MsrIndex; ASSERT ((MmioOffset & 0xf) == 0); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { - MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); + MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value); } else { // // DFR is not supported in x2APIC mode. @@ -216,15 +217,15 @@ WriteLocalApicReg ( **/ VOID SendIpi ( - IN UINT32 IcrLow, - IN UINT32 ApicId + IN UINT32 IcrLow, + IN UINT32 ApicId ) { - UINT64 MsrValue; - LOCAL_APIC_ICR_LOW IcrLowReg; - UINTN LocalApciBaseAddress; - UINT32 IcrHigh; - BOOLEAN InterruptState; + UINT64 MsrValue; + LOCAL_APIC_ICR_LOW IcrLowReg; + UINTN LocalApciBaseAddress; + UINT32 IcrHigh; + BOOLEAN InterruptState; // // Legacy APIC or X2APIC? @@ -237,7 +238,7 @@ SendIpi ( // // Get base address of this LAPIC // - LocalApciBaseAddress = GetLocalApicBaseAddress(); + LocalApciBaseAddress = GetLocalApicBaseAddress (); // // Save existing contents of ICR high 32 bits @@ -271,13 +272,12 @@ SendIpi ( MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh); SetInterruptState (InterruptState); - } else { // // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an // interrupt in x2APIC mode. // - MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow; + MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow; AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue); } } @@ -354,7 +354,7 @@ SetApicMode ( case LOCAL_APIC_MODE_XAPIC: break; case LOCAL_APIC_MODE_X2APIC: - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.EXTD = 1; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); break; @@ -368,9 +368,9 @@ SetApicMode ( // Transition from x2APIC mode to xAPIC mode is a two-step process: // x2APIC -> Local APIC disabled -> xAPIC // - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.EXTD = 0; - ApicBaseMsr.Bits.EN = 0; + ApicBaseMsr.Bits.EN = 0; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); ApicBaseMsr.Bits.EN = 1; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); @@ -398,9 +398,9 @@ GetInitialApicId ( VOID ) { - UINT32 ApicId; - UINT32 MaxCpuIdIndex; - UINT32 RegEbx; + UINT32 ApicId; + UINT32 MaxCpuIdIndex; + UINT32 RegEbx; if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { // @@ -419,6 +419,7 @@ GetInitialApicId ( return ApicId; } } + AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); return RegEbx >> 24; } else { @@ -437,8 +438,8 @@ GetApicId ( VOID ) { - UINT32 ApicId; - UINT32 InitApicId; + UINT32 ApicId; + UINT32 InitApicId; ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { @@ -473,16 +474,16 @@ GetApicVersion ( VOID EFIAPI SendFixedIpi ( - IN UINT32 ApicId, - IN UINT8 Vector + IN UINT32 ApicId, + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Level = 1; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, ApicId); } @@ -496,16 +497,16 @@ SendFixedIpi ( VOID EFIAPI SendFixedIpiAllExcludingSelf ( - IN UINT8 Vector + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, 0); } @@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf ( VOID EFIAPI SendSmiIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf ( VOID EFIAPI SendInitIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf ( VOID EFIAPI SendInitSipiSipi ( - IN UINT32 ApicId, - IN UINT32 StartupRoutine + IN UINT32 ApicId, + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpi (ApicId); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); if (!StandardSignatureIsAuthenticAMD ()) { MicroSecondDelay (200); @@ -642,20 +643,20 @@ SendInitSipiSipi ( VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( - IN UINT32 StartupRoutine + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpiAllExcludingSelf (); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); if (!StandardSignatureIsAuthenticAMD ()) { @@ -711,13 +712,13 @@ ProgramVirtualWireMode ( VOID ) { - LOCAL_APIC_SVR Svr; - LOCAL_APIC_LVT_LINT Lint; + LOCAL_APIC_SVR Svr; + LOCAL_APIC_LVT_LINT Lint; // // Enable the APIC via SVR and set the spurious interrupt to use Int 00F. // - Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); + Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); Svr.Bits.SpuriousVector = 0xf; Svr.Bits.SoftwareEnable = 1; WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32); @@ -725,21 +726,21 @@ ProgramVirtualWireMode ( // // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32); // // Program the LINT0 vector entry as NMI. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32); } @@ -754,13 +755,13 @@ DisableLvtInterrupts ( VOID ) { - LOCAL_APIC_LVT_LINT LvtLint; + LOCAL_APIC_LVT_LINT LvtLint; - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32); - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32); } @@ -807,15 +808,15 @@ GetApicTimerCurrentCount ( VOID EFIAPI InitializeApicTimer ( - IN UINTN DivideValue, - IN UINT32 InitCount, - IN BOOLEAN PeriodicMode, - IN UINT8 Vector + IN UINTN DivideValue, + IN UINT32 InitCount, + IN BOOLEAN PeriodicMode, + IN UINT8 Vector ) { - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; - UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; // // Ensure local APIC is in software-enabled state. @@ -829,10 +830,10 @@ InitializeApicTimer ( if (DivideValue != 0) { ASSERT (DivideValue <= 128); - ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); + ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue)); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Bits.DivideValue1 = (Divisor & 0x3); Dcr.Bits.DivideValue2 = (Divisor >> 2); WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); @@ -847,7 +848,8 @@ InitializeApicTimer ( } else { LvtTimer.Bits.TimerMode = 0; } - LvtTimer.Bits.Mask = 0; + + LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -869,25 +871,25 @@ GetApicTimerState ( OUT UINT8 *Vector OPTIONAL ) { - UINT32 Divisor; - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; // // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt // Vector Register. // This bit will be 1, if local APIC is software enabled. // - ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); + ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); if (DivideValue != NULL) { - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); - Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); - Divisor = (Divisor + 1) & 0x7; + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); + Divisor = (Divisor + 1) & 0x7; *DivideValue = ((UINTN)1) << Divisor; } - if (PeriodicMode != NULL || Vector != NULL) { + if ((PeriodicMode != NULL) || (Vector != NULL)) { LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); if (PeriodicMode != NULL) { if (LvtTimer.Bits.TimerMode == 1) { @@ -896,8 +898,9 @@ GetApicTimerState ( *PeriodicMode = FALSE; } } + if (Vector != NULL) { - *Vector = (UINT8) LvtTimer.Bits.Vector; + *Vector = (UINT8)LvtTimer.Bits.Vector; } } } @@ -911,9 +914,9 @@ EnableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -927,9 +930,9 @@ DisableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -946,7 +949,7 @@ GetApicTimerInterruptState ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); return (BOOLEAN)(LvtTimer.Bits.Mask == 0); @@ -1039,6 +1042,7 @@ GetApicMsiValue ( MsiData.Bits.Level = 1; } } + return MsiData.Uint64; } @@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId ( if (Thread != NULL) { *Thread = 0; } + if (Core != NULL) { *Core = 0; } + if (Package != NULL) { *Package = 0; } + return; } @@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId ( // Assume three-level mapping of APIC ID: Package|Core|Thread. // ThreadBits = 0; - CoreBits = 0; + CoreBits = 0; // // Get max index of CPUID @@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported = FALSE; if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId ( CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; break; } + SubIndex++; } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } @@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { @@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId ( MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); } } - } - else { + } else { // // Extract core count based on CACHE information // @@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId ( } } - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); + CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1); } if (Thread != NULL) { *Thread = InitialApicId & ((1 << ThreadBits) - 1); } + if (Core != NULL) { *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } + if (Package != NULL) { *Package = (InitialApicId >> (ThreadBits + CoreBits)); } @@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Thread OPTIONAL ) { - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxStandardCpuIdIndex; - UINT32 Index; - UINTN LevelType; - UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; - UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxStandardCpuIdIndex; + UINT32 Index; + UINTN LevelType; + UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] = 0; @@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId ( if (Die != NULL) { *Die = 0; } + if (Tile != NULL) { *Tile = 0; } + if (Module != NULL) { *Module = 0; } + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); return; } @@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId ( // is the preferred mechanism for enumerating topology. // for (Index = 0; ; Index++) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_V2_EXTENDED_TOPOLOGY, Index, &ExtendedTopologyEax.Uint32, @@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId ( if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { break; } + ASSERT (LevelType < ARRAY_SIZE (Bits)); Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; } @@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId ( } Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT - ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 - ; LevelType ++ - ) { + ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 + ; LevelType++ + ) + { if (Location[LevelType] != NULL) { // // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c index f4fcee39e9..c7973735e1 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c @@ -17,21 +17,31 @@ **/ VOID CpuCacheInfoPrintCpuCacheInfoTable ( - IN CPU_CACHE_INFO *CpuCacheInfo, - IN UINTN CpuCacheInfoCount + IN CPU_CACHE_INFO *CpuCacheInfo, + IN UINTN CpuCacheInfoCount ) { - UINTN Index; + UINTN Index; DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); for (Index = 0; Index < CpuCacheInfoCount; Index++) { - DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n", - Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel, - CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache, - CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount)); + DEBUG (( + DEBUG_INFO, + "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n", + Index, + CpuCacheInfo[Index].Package, + CpuCacheInfo[Index].CoreType, + CpuCacheInfo[Index].CacheLevel, + CpuCacheInfo[Index].CacheType, + CpuCacheInfo[Index].CacheWays, + CpuCacheInfo[Index].FullyAssociativeCache, + CpuCacheInfo[Index].DirectMappedCache, + CpuCacheInfo[Index].CacheSizeinKB, + CpuCacheInfo[Index].CacheCount + )); } DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); @@ -50,24 +60,24 @@ CpuCacheInfoPrintCpuCacheInfoTable ( INTN EFIAPI CpuCacheInfoCompare ( - IN CONST VOID *Buffer1, - IN CONST VOID *Buffer2 + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 ) { - CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2; + CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2; ZeroMem (&Comparator1, sizeof (Comparator1)); ZeroMem (&Comparator2, sizeof (Comparator2)); - Comparator1.Bits.Package = ((CPU_CACHE_INFO*)Buffer1)->Package; - Comparator1.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer1)->CoreType; - Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel; - Comparator1.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer1)->CacheType; + Comparator1.Bits.Package = ((CPU_CACHE_INFO *)Buffer1)->Package; + Comparator1.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer1)->CoreType; + Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer1)->CacheLevel; + Comparator1.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer1)->CacheType; - Comparator2.Bits.Package = ((CPU_CACHE_INFO*)Buffer2)->Package; - Comparator2.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer2)->CoreType; - Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel; - Comparator2.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer2)->CacheType; + Comparator2.Bits.Package = ((CPU_CACHE_INFO *)Buffer2)->Package; + Comparator2.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer2)->CoreType; + Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer2)->CacheLevel; + Comparator2.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer2)->CacheType; if (Comparator1.Uint64 == Comparator2.Uint64) { return 0; @@ -89,15 +99,15 @@ CpuCacheInfoCompare ( **/ UINT32 CpuCacheInfoGetNumberOfPackages ( - IN CPUID_PROCESSOR_INFO *ProcessorInfo, - IN UINTN NumberOfProcessors, - IN OUT UINT32 *Package + IN CPUID_PROCESSOR_INFO *ProcessorInfo, + IN UINTN NumberOfProcessors, + IN OUT UINT32 *Package ) { - UINTN ProcessorIndex; - UINT32 PackageIndex; - UINT32 PackageCount; - UINT32 CurrentPackage; + UINTN ProcessorIndex; + UINT32 PackageIndex; + UINT32 PackageCount; + UINT32 CurrentPackage; PackageCount = 0; @@ -135,21 +145,21 @@ CpuCacheInfoGetNumberOfPackages ( @retval Return the number of CoreType of requested package. **/ UINTN -CpuCacheInfoGetNumberOfCoreTypePerPackage( - IN CPUID_PROCESSOR_INFO *ProcessorInfo, - IN UINTN NumberOfProcessors, - IN UINTN Package +CpuCacheInfoGetNumberOfCoreTypePerPackage ( + IN CPUID_PROCESSOR_INFO *ProcessorInfo, + IN UINTN NumberOfProcessors, + IN UINTN Package ) { - UINTN ProcessorIndex; + UINTN ProcessorIndex; // // Core Type value comes from CPUID.1Ah.EAX[31:24]. // So max number of core types should be MAX_UINT8. // - UINT8 CoreType[MAX_UINT8]; - UINTN CoreTypeIndex; - UINTN CoreTypeCount; - UINT8 CurrentCoreType; + UINT8 CoreType[MAX_UINT8]; + UINTN CoreTypeIndex; + UINTN CoreTypeCount; + UINT8 CurrentCoreType; // // CoreType array is empty. @@ -192,23 +202,23 @@ CpuCacheInfoGetNumberOfCoreTypePerPackage( VOID EFIAPI CpuCacheInfoCollectCoreAndCacheData ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - UINTN ProcessorIndex; - UINT32 CpuidMaxInput; - UINT8 CacheParamLeafIndex; - CPUID_CACHE_PARAMS_EAX CacheParamEax; - CPUID_CACHE_PARAMS_EBX CacheParamEbx; - UINT32 CacheParamEcx; - CPUID_CACHE_PARAMS_EDX CacheParamEdx; - CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax; - COLLECT_CPUID_CACHE_DATA_CONTEXT *Context; - CPUID_CACHE_DATA *CacheData; - - Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer; + UINTN ProcessorIndex; + UINT32 CpuidMaxInput; + UINT8 CacheParamLeafIndex; + CPUID_CACHE_PARAMS_EAX CacheParamEax; + CPUID_CACHE_PARAMS_EBX CacheParamEbx; + UINT32 CacheParamEcx; + CPUID_CACHE_PARAMS_EDX CacheParamEdx; + CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax; + COLLECT_CPUID_CACHE_DATA_CONTEXT *Context; + CPUID_CACHE_DATA *CacheData; + + Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer; ProcessorIndex = CpuCacheInfoWhoAmI (Context->MpServices); - CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex]; + CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex]; AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL); @@ -218,7 +228,7 @@ CpuCacheInfoCollectCoreAndCacheData ( Context->ProcessorInfo[ProcessorIndex].CoreType = 0; if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) { AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL); - Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType; + Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType; } // @@ -240,7 +250,7 @@ CpuCacheInfoCollectCoreAndCacheData ( CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0); CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors; CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) * - (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB; + (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB; CacheParamLeafIndex++; } @@ -264,25 +274,25 @@ CpuCacheInfoCollectCoreAndCacheData ( **/ EFI_STATUS CpuCacheInfoCollectCpuCacheInfoData ( - IN CPUID_CACHE_DATA *CacheData, - IN CPUID_PROCESSOR_INFO *ProcessorInfo, - IN UINTN NumberOfProcessors, - IN OUT CPU_CACHE_INFO *CacheInfo, - IN OUT UINTN *CacheInfoCount + IN CPUID_CACHE_DATA *CacheData, + IN CPUID_PROCESSOR_INFO *ProcessorInfo, + IN UINTN NumberOfProcessors, + IN OUT CPU_CACHE_INFO *CacheInfo, + IN OUT UINTN *CacheInfoCount ) { - EFI_STATUS Status; - UINT32 NumberOfPackage; - UINT32 Package[MAX_NUM_OF_PACKAGE]; - UINTN PackageIndex; - UINTN TotalNumberOfCoreType; - UINTN MaxCacheInfoCount; - CPU_CACHE_INFO *LocalCacheInfo; - UINTN CacheInfoIndex; - UINTN LocalCacheInfoCount; - UINTN Index; - UINTN NextIndex; - CPU_CACHE_INFO SortBuffer; + EFI_STATUS Status; + UINT32 NumberOfPackage; + UINT32 Package[MAX_NUM_OF_PACKAGE]; + UINTN PackageIndex; + UINTN TotalNumberOfCoreType; + UINTN MaxCacheInfoCount; + CPU_CACHE_INFO *LocalCacheInfo; + UINTN CacheInfoIndex; + UINTN LocalCacheInfoCount; + UINTN Index; + UINTN NextIndex; + CPU_CACHE_INFO SortBuffer; // // Get number of Packages and Package ID. @@ -299,7 +309,7 @@ CpuCacheInfoCollectCpuCacheInfoData ( } MaxCacheInfoCount = TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_LEAF; - LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo))); + LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo))); ASSERT (LocalCacheInfo != NULL); if (LocalCacheInfo == NULL) { return EFI_OUT_OF_RESOURCES; @@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData ( continue; } - if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel && - CacheData[Index].CacheType == CacheData[NextIndex].CacheType && - ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && - ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && - (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) == - (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) { + if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) && + (CacheData[Index].CacheType == CacheData[NextIndex].CacheType) && + (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) && + (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) && + ((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) == + (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits))) + { CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache } } @@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData ( // For the cache that already exists in LocalCacheInfo, increase its CacheCount. // for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) { - if (LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && - LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && - LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel && - LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType) { + if ((LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) && + (LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) && + (LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) && + (LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType)) + { LocalCacheInfo[CacheInfoIndex].CacheCount++; break; } @@ -370,11 +382,11 @@ CpuCacheInfoCollectCpuCacheInfoData ( // // Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type. // - QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID*) &SortBuffer); + QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID *)&SortBuffer); CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount); DEBUG_CODE ( CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount); - ); + ); Status = EFI_SUCCESS; } @@ -405,23 +417,23 @@ CpuCacheInfoCollectCpuCacheInfoData ( EFI_STATUS EFIAPI GetCpuCacheInfo ( - IN OUT CPU_CACHE_INFO *CpuCacheInfo, - IN OUT UINTN *CpuCacheInfoCount + IN OUT CPU_CACHE_INFO *CpuCacheInfo, + IN OUT UINTN *CpuCacheInfoCount ) { - EFI_STATUS Status; - UINT32 CpuidMaxInput; - UINT32 NumberOfProcessors; - UINTN CacheDataCount; - UINTN ProcessorIndex; - EFI_PROCESSOR_INFORMATION ProcessorInfo; + EFI_STATUS Status; + UINT32 CpuidMaxInput; + UINT32 NumberOfProcessors; + UINTN CacheDataCount; + UINTN ProcessorIndex; + EFI_PROCESSOR_INFORMATION ProcessorInfo; COLLECT_CPUID_CACHE_DATA_CONTEXT Context; if (CpuCacheInfoCount == NULL) { return EFI_INVALID_PARAMETER; } - if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) { + if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) { return EFI_INVALID_PARAMETER; } @@ -445,13 +457,14 @@ GetCpuCacheInfo ( if (Context.ProcessorInfo == NULL) { return EFI_OUT_OF_RESOURCES; } + // // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData. // CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf // per logical processor. The array begin with data of each Cache Parameter Leaf of processor 0, followed // by data of each Cache Parameter Leaf of processor 1 ... // - CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF; + CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF; Context.CacheData = AllocatePages (EFI_SIZE_TO_PAGES (CacheDataCount * sizeof (*Context.CacheData))); ASSERT (Context.CacheData != NULL); if (Context.CacheData == NULL) { @@ -467,7 +480,7 @@ GetCpuCacheInfo ( for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) { CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo); Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package; - Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32) ProcessorInfo.ProcessorId; + Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32)ProcessorInfo.ProcessorId; } // diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c index d810294e21..ebf2db86ba 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c @@ -23,10 +23,10 @@ **/ EFI_STATUS CpuCacheInfoGetMpServices ( - OUT MP_SERVICES *MpServices + OUT MP_SERVICES *MpServices ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices->Protocol); ASSERT_EFI_ERROR (Status); @@ -43,12 +43,12 @@ CpuCacheInfoGetMpServices ( **/ VOID CpuCacheInfoStartupAllCPUs ( - IN MP_SERVICES MpServices, - IN EFI_AP_PROCEDURE Procedure, - IN VOID *ProcedureArgument + IN MP_SERVICES MpServices, + IN EFI_AP_PROCEDURE Procedure, + IN VOID *ProcedureArgument ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Procedure, FALSE, NULL, 0, ProcedureArgument, NULL); if (Status == EFI_NOT_STARTED) { @@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs ( // Status = EFI_SUCCESS; } + ASSERT_EFI_ERROR (Status); Procedure (ProcedureArgument); @@ -72,12 +73,12 @@ CpuCacheInfoStartupAllCPUs ( **/ VOID CpuCacheInfoGetProcessorInfo ( - IN MP_SERVICES MpServices, - IN UINTN ProcessorNum, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo + IN MP_SERVICES MpServices, + IN UINTN ProcessorNum, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, ProcessorNum, ProcessorInfo); ASSERT_EFI_ERROR (Status); @@ -92,11 +93,11 @@ CpuCacheInfoGetProcessorInfo ( **/ UINT32 CpuCacheInfoWhoAmI ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ) { - EFI_STATUS Status; - UINTN ProcessorNum; + EFI_STATUS Status; + UINTN ProcessorNum; Status = MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorNum); ASSERT_EFI_ERROR (Status); @@ -113,12 +114,12 @@ CpuCacheInfoWhoAmI ( **/ UINT32 CpuCacheInfoGetNumberOfProcessors ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ) { - EFI_STATUS Status; - UINTN NumberOfProcessor; - UINTN NumberOfEnabledProcessor; + EFI_STATUS Status; + UINTN NumberOfProcessor; + UINTN NumberOfEnabledProcessor; Status = MpServices.Protocol->GetNumberOfProcessors (MpServices.Protocol, &NumberOfProcessor, &NumberOfEnabledProcessor); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h index 829a9f43ce..953b3d66b1 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h @@ -25,24 +25,24 @@ typedef union { // Type of the cache that this package's this type of logical processor corresponds to. // Value = CPUID.04h:EAX[04:00] // - UINT32 CacheType : 5; + UINT32 CacheType : 5; // // Level of the cache that this package's this type of logical processor corresponds to. // Value = CPUID.04h:EAX[07:05] // - UINT32 CacheLevel : 3; + UINT32 CacheLevel : 3; // // Core type of logical processor. // Value = CPUID.1Ah:EAX[31:24] // - UINT32 CoreType : 8; - UINT32 Reserved : 16; + UINT32 CoreType : 8; + UINT32 Reserved : 16; // // Package number. // - UINT32 Package; + UINT32 Package; } Bits; - UINT64 Uint64; + UINT64 Uint64; } CPU_CACHE_INFO_COMPARATOR; typedef struct { @@ -50,17 +50,17 @@ typedef struct { // Package ID, the information comes from // EFI_CPU_PHYSICAL_LOCATION.Package // - UINT32 Package; + UINT32 Package; // // APIC ID, the information comes from // EFI_PROCESSOR_INFORMATION.ProcessorId // - UINT32 ApicId; + UINT32 ApicId; // // Core type of logical processor. // Value = CPUID.1Ah:EAX[31:24] // - UINT8 CoreType; + UINT8 CoreType; } CPUID_PROCESSOR_INFO; typedef struct { @@ -68,39 +68,39 @@ typedef struct { // Level of the cache. // Value = CPUID.04h:EAX[07:05] // - UINT8 CacheLevel : 3; + UINT8 CacheLevel : 3; // // Type of the cache. // Value = CPUID.04h:EAX[04:00] // - UINT8 CacheType : 5; + UINT8 CacheType : 5; // // Ways of associativity. // Value = CPUID.04h:EBX[31:22] // - UINT16 CacheWays : 10; + UINT16 CacheWays : 10; // // Fully associative cache. // Value = CPUID.04h:EAX[09] // - UINT16 FullyAssociativeCache : 1; + UINT16 FullyAssociativeCache : 1; // // Direct mapped cache. // Value = CPUID.04h:EDX[02] // - UINT16 DirectMappedCache : 1; - UINT16 Reserved : 4; + UINT16 DirectMappedCache : 1; + UINT16 Reserved : 4; // // Cache share bits. // Value = CPUID.04h:EAX[25:14] // - UINT16 CacheShareBits; + UINT16 CacheShareBits; // // Size of single cache. // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1) // - UINT32 CacheSizeinKB; + UINT32 CacheSizeinKB; } CPUID_CACHE_DATA; typedef union { @@ -109,24 +109,23 @@ typedef union { } MP_SERVICES; typedef struct { - MP_SERVICES MpServices; - CPUID_PROCESSOR_INFO *ProcessorInfo; - CPUID_CACHE_DATA *CacheData; + MP_SERVICES MpServices; + CPUID_PROCESSOR_INFO *ProcessorInfo; + CPUID_CACHE_DATA *CacheData; } COLLECT_CPUID_CACHE_DATA_CONTEXT; - /* Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP. To save boot time, skip starting up all APs to calculate each AP's count of Deterministic Cache Parameters Leaf, so use a definition instead. Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCacheData function. */ -#define MAX_NUM_OF_CACHE_PARAMS_LEAF 6 +#define MAX_NUM_OF_CACHE_PARAMS_LEAF 6 /* Defines the maximum count of packages. */ -#define MAX_NUM_OF_PACKAGE 100 +#define MAX_NUM_OF_PACKAGE 100 /** Get EDKII_PEI_MP_SERVICES2_PPI or EFI_MP_SERVICES_PROTOCOL pointer. @@ -139,7 +138,7 @@ typedef struct { **/ EFI_STATUS CpuCacheInfoGetMpServices ( - OUT MP_SERVICES *MpServices + OUT MP_SERVICES *MpServices ); /** @@ -151,9 +150,9 @@ CpuCacheInfoGetMpServices ( **/ VOID CpuCacheInfoStartupAllCPUs ( - IN MP_SERVICES MpServices, - IN EFI_AP_PROCEDURE Procedure, - IN VOID *ProcedureArgument + IN MP_SERVICES MpServices, + IN EFI_AP_PROCEDURE Procedure, + IN VOID *ProcedureArgument ); /** @@ -165,9 +164,9 @@ CpuCacheInfoStartupAllCPUs ( **/ VOID CpuCacheInfoGetProcessorInfo ( - IN MP_SERVICES MpServices, - IN UINTN ProcessorNum, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo + IN MP_SERVICES MpServices, + IN UINTN ProcessorNum, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo ); /** @@ -179,7 +178,7 @@ CpuCacheInfoGetProcessorInfo ( **/ UINT32 CpuCacheInfoWhoAmI ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ); /** @@ -191,6 +190,7 @@ CpuCacheInfoWhoAmI ( **/ UINT32 CpuCacheInfoGetNumberOfProcessors ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ); + #endif diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c index 06c160421b..ea262d8f02 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c @@ -24,10 +24,10 @@ **/ EFI_STATUS CpuCacheInfoGetMpServices ( - OUT MP_SERVICES *MpServices + OUT MP_SERVICES *MpServices ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, (VOID **)&MpServices->Ppi); ASSERT_EFI_ERROR (Status); @@ -44,12 +44,12 @@ CpuCacheInfoGetMpServices ( **/ VOID CpuCacheInfoStartupAllCPUs ( - IN MP_SERVICES MpServices, - IN EFI_AP_PROCEDURE Procedure, - IN VOID *ProcedureArgument + IN MP_SERVICES MpServices, + IN EFI_AP_PROCEDURE Procedure, + IN VOID *ProcedureArgument ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0, ProcedureArgument); ASSERT_EFI_ERROR (Status); @@ -64,12 +64,12 @@ CpuCacheInfoStartupAllCPUs ( **/ VOID CpuCacheInfoGetProcessorInfo ( - IN MP_SERVICES MpServices, - IN UINTN ProcessorNum, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo + IN MP_SERVICES MpServices, + IN UINTN ProcessorNum, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNum, ProcessorInfo); ASSERT_EFI_ERROR (Status); @@ -84,11 +84,11 @@ CpuCacheInfoGetProcessorInfo ( **/ UINT32 CpuCacheInfoWhoAmI ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ) { - EFI_STATUS Status; - UINTN ProcessorNum; + EFI_STATUS Status; + UINTN ProcessorNum; Status = MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum); ASSERT_EFI_ERROR (Status); @@ -105,12 +105,12 @@ CpuCacheInfoWhoAmI ( **/ UINT32 CpuCacheInfoGetNumberOfProcessors ( - IN MP_SERVICES MpServices + IN MP_SERVICES MpServices ) { - EFI_STATUS Status; - UINTN NumberOfProcessor; - UINTN NumberOfEnabledProcessor; + EFI_STATUS Status; + UINTN NumberOfProcessor; + UINTN NumberOfEnabledProcessor; Status = MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &NumberOfProcessor, &NumberOfEnabledProcessor); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c index 80a7df2957..beda97e238 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -23,7 +23,7 @@ AesniGetConfigData ( IN UINTN NumberOfProcessors ) { - UINT64 *ConfigData; + UINT64 *ConfigData; ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors); ASSERT (ConfigData != NULL); @@ -54,14 +54,15 @@ AesniSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; + MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) { - MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; + MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData; ASSERT (MsrFeatureConfig != NULL); MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); return TRUE; } + return FALSE; } @@ -91,7 +92,7 @@ AesniInitialize ( IN BOOLEAN State ) { - MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; + MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; // // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index, @@ -102,7 +103,7 @@ AesniInitialize ( // programming it. // if (CpuInfo->ProcessorInfo.Location.Thread == 0) { - MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; + MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData; ASSERT (MsrFeatureConfig != NULL); if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( @@ -115,5 +116,6 @@ AesniInitialize ( ); } } + return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c index 98a3408370..bc09f8bc62 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c @@ -66,7 +66,7 @@ C1eInitialize ( // MSR_NEHALEM_POWER_CTL once for each package. // if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { - return RETURN_SUCCESS; + return RETURN_SUCCESS; } CPU_REGISTER_TABLE_WRITE_FIELD ( diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c index 94d596605b..5874a99570 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c @@ -9,8 +9,8 @@ #include "CpuCommonFeatures.h" typedef struct { - CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax; - MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation; + CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax; + MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation; } CLOCK_MODULATION_CONFIG_DATA; /** @@ -28,7 +28,7 @@ ClockModulationGetConfigData ( IN UINTN NumberOfProcessors ) { - UINT32 *ConfigData; + UINT32 *ConfigData; ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors); ASSERT (ConfigData != NULL); @@ -59,10 +59,10 @@ ClockModulationSupport ( IN VOID *ConfigData OPTIONAL ) { - CLOCK_MODULATION_CONFIG_DATA *CmConfigData; + CLOCK_MODULATION_CONFIG_DATA *CmConfigData; if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) { - CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; + CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData; ASSERT (CmConfigData != NULL); AsmCpuid ( CPUID_THERMAL_POWER_MANAGEMENT, @@ -74,6 +74,7 @@ ClockModulationSupport ( CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); return TRUE; } + return FALSE; } @@ -103,15 +104,15 @@ ClockModulationInitialize ( IN BOOLEAN State ) { - CLOCK_MODULATION_CONFIG_DATA *CmConfigData; - MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation; + CLOCK_MODULATION_CONFIG_DATA *CmConfigData; + MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation; - CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; + CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData; ASSERT (CmConfigData != NULL); ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation; if (State) { - ClockModulation->Bits.OnDemandClockModulationEnable = 1; + ClockModulation->Bits.OnDemandClockModulationEnable = 1; ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1; if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) { ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0; diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 74f27dcc44..5434a45f6a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -860,7 +860,7 @@ X2ApicInitialize ( VOID * EFIAPI PpinGetConfigData ( - IN UINTN NumberOfProcessors + IN UINTN NumberOfProcessors ); /** diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 725ef7bd43..7f0e1004b9 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -20,7 +20,7 @@ CpuCommonFeaturesLibConstructor ( VOID ) { - RETURN_STATUS Status; + RETURN_STATUS Status; if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) { Status = RegisterCpuFeature ( @@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) { Status = RegisterCpuFeature ( "MWAIT", @@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) { Status = RegisterCpuFeature ( "ACPI", @@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) { Status = RegisterCpuFeature ( "EIST", @@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) { Status = RegisterCpuFeature ( "FastStrings", @@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { Status = RegisterCpuFeature ( "Lock Feature Control Register", @@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { Status = RegisterCpuFeature ( "SMX", @@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { Status = RegisterCpuFeature ( "VMX", @@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) { Status = RegisterCpuFeature ( "Limit CpuId Maximum Value", @@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) { Status = RegisterCpuFeature ( "Machine Check Enable", @@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) { Status = RegisterCpuFeature ( "Machine Check Architect", @@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) { Status = RegisterCpuFeature ( "MCG_CTL", @@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) { Status = RegisterCpuFeature ( "Pending Break", @@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) { Status = RegisterCpuFeature ( "C1E", @@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) { Status = RegisterCpuFeature ( "X2Apic", @@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { Status = RegisterCpuFeature ( "PPIN", @@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { Status = RegisterCpuFeature ( "LMCE", @@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) { Status = RegisterCpuFeature ( "Proc Trace", @@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor ( return RETURN_SUCCESS; } - - - diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c index ed42afe289..aedf3e6f2c 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c @@ -69,7 +69,8 @@ EistInitialize ( // if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c index 9ae5216555..63c3bf9d10 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c @@ -40,7 +40,8 @@ FastStringsInitialize ( // if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 8ad81a6e87..63ec27a1a6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -68,7 +68,8 @@ VmxInitialize ( // if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } @@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize ( // if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } @@ -218,7 +220,7 @@ SmxInitialize ( IN BOOLEAN State ) { - RETURN_STATUS Status; + RETURN_STATUS Status; // // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for @@ -226,7 +228,8 @@ SmxInitialize ( // core. // if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } @@ -236,7 +239,7 @@ SmxInitialize ( if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) { DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n")); - State = FALSE; + State = FALSE; Status = RETURN_UNSUPPORTED; } @@ -247,7 +250,7 @@ SmxInitialize ( IA32_CR4, Bits.SMXE, (State) ? 1 : 0 - ) + ) CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( ProcessorNumber, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c index 71d82eab8d..bf495f96bb 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c @@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize ( IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 0e78a0ce26..d8b070d9f1 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -102,6 +102,7 @@ McaSupport ( if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) { return FALSE; } + return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1); } @@ -144,7 +145,8 @@ McaInitialize ( IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } @@ -162,7 +164,7 @@ McaInitialize ( if (State) { McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); - for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) { + for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) { CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -172,7 +174,7 @@ McaInitialize ( } if (PcdGetBool (PcdIsPowerOnReset)) { - for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) { + for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) { CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -215,6 +217,7 @@ McgCtlSupport ( if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) { return FALSE; } + McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); return (McgCap.Bits.MCG_CTL_P == 1); } @@ -249,7 +252,7 @@ McgCtlInitialize ( ProcessorNumber, Msr, MSR_IA32_MCG_CTL, - (State)? MAX_UINT64 : 0 + (State) ? MAX_UINT64 : 0 ); return RETURN_SUCCESS; } @@ -279,7 +282,7 @@ LmceSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_MCG_CAP_REGISTER McgCap; + MSR_IA32_MCG_CAP_REGISTER McgCap; if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) { return FALSE; @@ -287,9 +290,10 @@ LmceSupport ( McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); if (ProcessorNumber == 0) { - DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0))); + DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0))); } - return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0); + + return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0); } /** @@ -325,7 +329,8 @@ LmceInitialize ( // if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c index 9fcbaf8d5d..d55cf6c6f2 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c @@ -70,7 +70,8 @@ MonitorMwaitInitialize ( IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c index 3d7030d609..6095dbde05 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c @@ -36,9 +36,11 @@ PendingBreakSupport ( IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1); } + return FALSE; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c index 468e425a0b..a7c2c12a51 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -20,10 +20,10 @@ VOID * EFIAPI PpinGetConfigData ( - IN UINTN NumberOfProcessors + IN UINTN NumberOfProcessors ) { - VOID *ConfigData; + VOID *ConfigData; ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors); ASSERT (ConfigData != NULL); @@ -55,8 +55,8 @@ PpinSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; + MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; if ((CpuInfo->DisplayFamily == 0x06) && ((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2 @@ -65,13 +65,14 @@ PpinSupport ( (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series. (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor - )) { + )) + { // // Check whether platform support this feature. // PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); if (PlatformInfo.Bits.PPIN_CAP != 0) { - MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; + MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData; ASSERT (MsrPpinCtrl != NULL); MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); return TRUE; @@ -112,9 +113,9 @@ PpinInitialize ( IN BOOLEAN State ) { - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; - MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; + MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData; ASSERT (MsrPpinCtrl != NULL); // @@ -143,14 +144,14 @@ PpinInitialize ( // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP. // MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1; - MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0; + MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0; } else { // // Disable and Lock. // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear. // MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0; - MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1; + MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1; } CPU_REGISTER_TABLE_WRITE64 ( diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c index e567ed54e7..04e6a60728 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -17,8 +17,7 @@ /// be terminated by an entry with the END bit set to 1, so 2 /// entries are required to use a single valid entry. /// -#define MAX_TOPA_ENTRY_COUNT 2 - +#define MAX_TOPA_ENTRY_COUNT 2 /// /// Processor trace output scheme selection. @@ -29,25 +28,25 @@ typedef enum { } RTIT_OUTPUT_SCHEME; typedef struct { - BOOLEAN TopaSupported; - BOOLEAN SingleRangeSupported; - MSR_IA32_RTIT_CTL_REGISTER RtitCtrl; - MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase; - MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs; + BOOLEAN TopaSupported; + BOOLEAN SingleRangeSupported; + MSR_IA32_RTIT_CTL_REGISTER RtitCtrl; + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase; + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs; } PROC_TRACE_PROCESSOR_DATA; typedef struct { - UINT32 NumberOfProcessors; + UINT32 NumberOfProcessors; - UINT8 ProcTraceOutputScheme; - UINT32 ProcTraceMemSize; + UINT8 ProcTraceOutputScheme; + UINT32 ProcTraceMemSize; - UINTN *ThreadMemRegionTable; - UINTN AllocatedThreads; + UINTN *ThreadMemRegionTable; + UINTN AllocatedThreads; - UINTN *TopaMemArray; + UINTN *TopaMemArray; - PROC_TRACE_PROCESSOR_DATA *ProcessorData; + PROC_TRACE_PROCESSOR_DATA *ProcessorData; } PROC_TRACE_DATA; typedef struct { @@ -73,10 +72,10 @@ ProcTraceGetConfigData ( ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors); ASSERT (ConfigData != NULL); - ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA)); + ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA)); - ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors; - ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize); + ConfigData->NumberOfProcessors = (UINT32)NumberOfProcessors; + ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize); ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme); return ConfigData; @@ -107,17 +106,18 @@ ProcTraceSupport ( IN VOID *ConfigData OPTIONAL ) { - PROC_TRACE_DATA *ProcTraceData; - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; - CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; + PROC_TRACE_DATA *ProcTraceData; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; // // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user) // - ProcTraceData = (PROC_TRACE_DATA *) ConfigData; + ProcTraceData = (PROC_TRACE_DATA *)ConfigData; ASSERT (ProcTraceData != NULL); if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || - (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) { + (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) + { return FALSE; } @@ -130,12 +130,13 @@ ProcTraceSupport ( } AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL); - ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1); - ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1); + ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1); + ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1); if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) || - (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) { - ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); - ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); + (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) + { + ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); + ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); return TRUE; } @@ -170,36 +171,37 @@ ProcTraceInitialize ( IN BOOLEAN State ) { - UINT32 MemRegionSize; - UINTN Pages; - UINTN Alignment; - UINTN MemRegionBaseAddr; - UINTN *ThreadMemRegionTable; - UINTN Index; - UINTN TopaTableBaseAddr; - UINTN AlignedAddress; - UINTN *TopaMemArray; - PROC_TRACE_TOPA_TABLE *TopaTable; - PROC_TRACE_DATA *ProcTraceData; - BOOLEAN FirstIn; - MSR_IA32_RTIT_CTL_REGISTER CtrlReg; - MSR_IA32_RTIT_STATUS_REGISTER StatusReg; - MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; + UINT32 MemRegionSize; + UINTN Pages; + UINTN Alignment; + UINTN MemRegionBaseAddr; + UINTN *ThreadMemRegionTable; + UINTN Index; + UINTN TopaTableBaseAddr; + UINTN AlignedAddress; + UINTN *TopaMemArray; + PROC_TRACE_TOPA_TABLE *TopaTable; + PROC_TRACE_DATA *ProcTraceData; + BOOLEAN FirstIn; + MSR_IA32_RTIT_CTL_REGISTER CtrlReg; + MSR_IA32_RTIT_STATUS_REGISTER StatusReg; + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg; - RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; // // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program // MSR_IA32_RTIT_* for thread 0 in each core. // if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || - IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) + { if (CpuInfo->ProcessorInfo.Location.Thread != 0) { return RETURN_SUCCESS; } } - ProcTraceData = (PROC_TRACE_DATA *) ConfigData; + ProcTraceData = (PROC_TRACE_DATA *)ConfigData; ASSERT (ProcTraceData != NULL); // @@ -235,7 +237,7 @@ ProcTraceInitialize ( } MemRegionBaseAddr = 0; - FirstIn = FALSE; + FirstIn = FALSE; if (ProcTraceData->ThreadMemRegionTable == NULL) { FirstIn = TRUE; @@ -245,7 +247,7 @@ ProcTraceInitialize ( /// /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding /// - MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12)); + MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12)); if (FirstIn) { DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize)); } @@ -258,32 +260,34 @@ ProcTraceInitialize ( // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be // aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared. // - ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *)); + ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *)); if (ThreadMemRegionTable == NULL) { DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n")); return RETURN_OUT_OF_RESOURCES; } + ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable; for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) { - Pages = EFI_SIZE_TO_PAGES (MemRegionSize); - Alignment = MemRegionSize; - AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); + Pages = EFI_SIZE_TO_PAGES (MemRegionSize); + Alignment = MemRegionSize; + AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment); if (AlignedAddress == 0) { DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads)); if (Index == 0) { // // Could not allocate for BSP even // - FreePool ((VOID *) ThreadMemRegionTable); + FreePool ((VOID *)ThreadMemRegionTable); ThreadMemRegionTable = NULL; return RETURN_OUT_OF_RESOURCES; } + break; } ThreadMemRegionTable[Index] = AlignedAddress; - DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index])); + DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index])); } DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads)); @@ -303,7 +307,8 @@ ProcTraceInitialize ( // Single Range output scheme // if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && - (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) { + (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) + { if (FirstIn) { DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n")); } @@ -322,9 +327,9 @@ ProcTraceInitialize ( // // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region // - OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; - OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF; - OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; + OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; + OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -335,9 +340,9 @@ ProcTraceInitialize ( // // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h) // - OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; + OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF; - OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF; + OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -350,7 +355,8 @@ ProcTraceInitialize ( // ToPA(Table of physical address) scheme // if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && - (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) { + (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) + { // // Create ToPA structure aligned at 4KB for each logical thread // with at least 2 entries by 8 bytes size each. The first entry @@ -364,35 +370,38 @@ ProcTraceInitialize ( // // Let BSP allocate ToPA table mem for all threads // - TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *)); + TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *)); if (TopaMemArray == NULL) { DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n")); return RETURN_OUT_OF_RESOURCES; } + ProcTraceData->TopaMemArray = TopaMemArray; for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) { - Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); - Alignment = 0x1000; - AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); + Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); + Alignment = 0x1000; + AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment); if (AlignedAddress == 0) { if (Index < ProcTraceData->AllocatedThreads) { ProcTraceData->AllocatedThreads = Index; } + DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads)); if (Index == 0) { // // Could not allocate for BSP even // - FreePool ((VOID *) TopaMemArray); + FreePool ((VOID *)TopaMemArray); TopaMemArray = NULL; return RETURN_OUT_OF_RESOURCES; } + break; } TopaMemArray[Index] = AlignedAddress; - DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index])); + DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index])); } DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads)); @@ -404,26 +413,26 @@ ProcTraceInitialize ( return RETURN_SUCCESS; } - TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; - TopaEntryPtr = &TopaTable->TopaEntry[0]; - TopaEntryPtr->Uint64 = 0; - TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF; - TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; - TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize; - TopaEntryPtr->Bits.END = 0; + TopaTable = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr; + TopaEntryPtr = &TopaTable->TopaEntry[0]; + TopaEntryPtr->Uint64 = 0; + TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF; + TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize; + TopaEntryPtr->Bits.END = 0; - TopaEntryPtr = &TopaTable->TopaEntry[1]; - TopaEntryPtr->Uint64 = 0; - TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF; - TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; - TopaEntryPtr->Bits.END = 1; + TopaEntryPtr = &TopaTable->TopaEntry[1]; + TopaEntryPtr->Uint64 = 0; + TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF; + TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF; + TopaEntryPtr->Bits.END = 1; // // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base // - OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; - OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF; - OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; + OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; + OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF; + OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -434,9 +443,9 @@ ProcTraceInitialize ( // // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 // - OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; + OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0; - OutputMaskPtrsReg.Bits.OutputOffset = 0; + OutputMaskPtrsReg.Bits.OutputOffset = 0; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, @@ -458,10 +467,10 @@ ProcTraceInitialize ( /// /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) /// - CtrlReg.Bits.OS = 1; - CtrlReg.Bits.User = 1; + CtrlReg.Bits.OS = 1; + CtrlReg.Bits.User = 1; CtrlReg.Bits.BranchEn = 1; - CtrlReg.Bits.TraceEn = 1; + CtrlReg.Bits.TraceEn = 1; CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c index 181dcae21c..220f307e5a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c @@ -23,7 +23,7 @@ X2ApicGetConfigData ( IN UINTN NumberOfProcessors ) { - BOOLEAN *ConfigData; + BOOLEAN *ConfigData; ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors); ASSERT (ConfigData != NULL); @@ -56,10 +56,10 @@ X2ApicSupport ( IN VOID *ConfigData OPTIONAL ) { - BOOLEAN *X2ApicEnabled; + BOOLEAN *X2ApicEnabled; ASSERT (ConfigData != NULL); - X2ApicEnabled = (BOOLEAN *) ConfigData; + X2ApicEnabled = (BOOLEAN *)ConfigData; // // *ConfigData indicates if X2APIC enabled on current processor // @@ -94,7 +94,7 @@ X2ApicInitialize ( IN BOOLEAN State ) { - BOOLEAN *X2ApicEnabled; + BOOLEAN *X2ApicEnabled; // // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program @@ -107,7 +107,7 @@ X2ApicInitialize ( } ASSERT (ConfigData != NULL); - X2ApicEnabled = (BOOLEAN *) ConfigData; + X2ApicEnabled = (BOOLEAN *)ConfigData; if (X2ApicEnabled[ProcessorNumber]) { PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, @@ -133,5 +133,6 @@ X2ApicInitialize ( ); } } + return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 49d0041e2f..903fac927e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -14,15 +14,15 @@ // // 1 means an error code will be pushed, otherwise 0 // -CONST UINT32 mErrorCodeFlag = 0x20227d00; +CONST UINT32 mErrorCodeFlag = 0x20227d00; // // Define the maximum message length // #define MAX_DEBUG_MESSAGE_LENGTH 0x100 -CONST CHAR8 mExceptionReservedStr[] = "Reserved"; -CONST CHAR8 *mExceptionNameStr[] = { +CONST CHAR8 mExceptionReservedStr[] = "Reserved"; +CONST CHAR8 *mExceptionNameStr[] = { "#DE - Divide Error", "#DB - Debug", "NMI Interrupt", @@ -66,10 +66,10 @@ CONST CHAR8 *mExceptionNameStr[] = { **/ CONST CHAR8 * GetExceptionNameStr ( - IN EFI_EXCEPTION_TYPE ExceptionType + IN EFI_EXCEPTION_TYPE ExceptionType ) { - if ((UINTN) ExceptionType < EXCEPTION_KNOWN_NAME_NUM) { + if ((UINTN)ExceptionType < EXCEPTION_KNOWN_NAME_NUM) { return mExceptionNameStr[ExceptionType]; } else { return mExceptionReservedStr; @@ -115,13 +115,13 @@ InternalPrintMessage ( **/ VOID DumpModuleImageInfo ( - IN UINTN CurrentEip + IN UINTN CurrentEip ) { - EFI_STATUS Status; - UINTN Pe32Data; - VOID *PdbPointer; - VOID *EntryPoint; + EFI_STATUS Status; + UINTN Pe32Data; + VOID *PdbPointer; + VOID *EntryPoint; Pe32Data = PeCoffSearchImageBase (CurrentEip); if (Pe32Data == 0) { @@ -130,20 +130,22 @@ DumpModuleImageInfo ( // // Find Image Base entry point // - Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, &EntryPoint); + Status = PeCoffLoaderGetEntryPoint ((VOID *)Pe32Data, &EntryPoint); if (EFI_ERROR (Status)) { EntryPoint = NULL; } + InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip); - PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); + PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data); if (PdbPointer != NULL) { InternalPrintMessage ("%a", PdbPointer); } else { - InternalPrintMessage ("(No PDB) " ); + InternalPrintMessage ("(No PDB) "); } + InternalPrintMessage ( " (ImageBase=%016lp, EntryPoint=%016p) !!!!\n", - (VOID *) Pe32Data, + (VOID *)Pe32Data, EntryPoint ); } @@ -162,9 +164,9 @@ DumpModuleImageInfo ( **/ EFI_STATUS ReadAndVerifyVectorInfo ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, - OUT RESERVED_VECTORS_DATA *ReservedVector, - IN UINTN VectorCount + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, + OUT RESERVED_VECTORS_DATA *ReservedVector, + IN UINTN VectorCount ) { while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) { @@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo ( // return EFI_INVALID_PARAMETER; } + if (VectorInfo->VectorNumber < VectorCount) { ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute; } - VectorInfo ++; + + VectorInfo++; } + return EFI_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 0544d6dba6..0f012bccde 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -20,21 +20,21 @@ #include #include -#define CPU_EXCEPTION_NUM 32 -#define CPU_INTERRUPT_NUM 256 -#define HOOKAFTER_STUB_SIZE 16 +#define CPU_EXCEPTION_NUM 32 +#define CPU_INTERRUPT_NUM 256 +#define HOOKAFTER_STUB_SIZE 16 // // Exception Error Code of Page-Fault Exception // -#define IA32_PF_EC_P BIT0 -#define IA32_PF_EC_WR BIT1 -#define IA32_PF_EC_US BIT2 -#define IA32_PF_EC_RSVD BIT3 -#define IA32_PF_EC_ID BIT4 -#define IA32_PF_EC_PK BIT5 -#define IA32_PF_EC_SS BIT6 -#define IA32_PF_EC_SGX BIT15 +#define IA32_PF_EC_P BIT0 +#define IA32_PF_EC_WR BIT1 +#define IA32_PF_EC_US BIT2 +#define IA32_PF_EC_RSVD BIT3 +#define IA32_PF_EC_ID BIT4 +#define IA32_PF_EC_PK BIT5 +#define IA32_PF_EC_SS BIT6 +#define IA32_PF_EC_SGX BIT15 #include "ArchInterruptDefs.h" @@ -47,26 +47,26 @@ #define CPU_KNOWN_GOOD_STACK_SIZE \ FixedPcdGet32 (PcdCpuKnownGoodStackSize) -#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) // // Record exception handler information // typedef struct { - UINTN ExceptionStart; - UINTN ExceptionStubHeaderSize; - UINTN HookAfterStubHeaderStart; + UINTN ExceptionStart; + UINTN ExceptionStubHeaderSize; + UINTN HookAfterStubHeaderStart; } EXCEPTION_HANDLER_TEMPLATE_MAP; typedef struct { - UINTN IdtEntryCount; - SPIN_LOCK DisplayMessageSpinLock; - RESERVED_VECTORS_DATA *ReservedVectors; - EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; + UINTN IdtEntryCount; + SPIN_LOCK DisplayMessageSpinLock; + RESERVED_VECTORS_DATA *ReservedVectors; + EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; } EXCEPTION_HANDLER_DATA; -extern CONST UINT32 mErrorCodeFlag; -extern CONST UINTN mDoFarReturnFlag; +extern CONST UINT32 mErrorCodeFlag; +extern CONST UINTN mDoFarReturnFlag; /** Return address map of exception handler template so that C code can generate @@ -77,7 +77,7 @@ extern CONST UINTN mDoFarReturnFlag; VOID EFIAPI AsmGetTemplateAddressMap ( - OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap ); /** @@ -90,8 +90,8 @@ AsmGetTemplateAddressMap ( **/ VOID ArchUpdateIdtEntry ( - OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, - IN UINTN InterruptHandler + OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, + IN UINTN InterruptHandler ); /** @@ -102,7 +102,7 @@ ArchUpdateIdtEntry ( **/ UINTN ArchGetIdtHandler ( - IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry + IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry ); /** @@ -128,7 +128,7 @@ InternalPrintMessage ( **/ VOID DumpModuleImageInfo ( - IN UINTN CurrentEip + IN UINTN CurrentEip ); /** @@ -139,8 +139,8 @@ DumpModuleImageInfo ( **/ VOID DumpImageAndCpuContent ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ); /** @@ -157,8 +157,8 @@ DumpImageAndCpuContent ( **/ EFI_STATUS InitializeCpuExceptionHandlersWorker ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); /** @@ -180,9 +180,9 @@ InitializeCpuExceptionHandlersWorker ( **/ EFI_STATUS RegisterCpuInterruptHandlerWorker ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); /** @@ -210,9 +210,9 @@ UpdateIdtTable ( **/ VOID ArchSaveExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); /** @@ -224,9 +224,9 @@ ArchSaveExceptionContext ( **/ VOID ArchRestoreExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); /** @@ -240,9 +240,9 @@ ArchRestoreExceptionContext ( VOID EFIAPI AsmVectorNumFixup ( - IN VOID *NewVectorAddr, - IN UINT8 VectorNum, - IN VOID *OldVectorAddr + IN VOID *NewVectorAddr, + IN UINT8 VectorNum, + IN VOID *OldVectorAddr ); /** @@ -258,9 +258,9 @@ AsmVectorNumFixup ( **/ EFI_STATUS ReadAndVerifyVectorInfo ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, - OUT RESERVED_VECTORS_DATA *ReservedVector, - IN UINTN VectorCount + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, + OUT RESERVED_VECTORS_DATA *ReservedVector, + IN UINTN VectorCount ); /** @@ -272,7 +272,7 @@ ReadAndVerifyVectorInfo ( **/ CONST CHAR8 * GetExceptionNameStr ( - IN EFI_EXCEPTION_TYPE ExceptionType + IN EFI_EXCEPTION_TYPE ExceptionType ); /** @@ -284,9 +284,9 @@ GetExceptionNameStr ( **/ VOID CommonExceptionHandlerWorker ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); /** @@ -301,7 +301,7 @@ CommonExceptionHandlerWorker ( **/ EFI_STATUS ArchSetupExceptionStack ( - IN CPU_EXCEPTION_INIT_DATA *StackSwitchData + IN CPU_EXCEPTION_INIT_DATA *StackSwitchData ); /** @@ -318,4 +318,3 @@ AsmGetTssTemplateMap ( ); #endif - diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index fd59f09ecd..61f11e98f8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -12,17 +12,17 @@ #include #include -CONST UINTN mDoFarReturnFlag = 0; +CONST UINTN mDoFarReturnFlag = 0; -RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; -EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; -UINTN mEnabledInterruptNum = 0; +RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; +EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; +UINTN mEnabledInterruptNum = 0; -EXCEPTION_HANDLER_DATA mExceptionHandlerData; +EXCEPTION_HANDLER_DATA mExceptionHandlerData; -UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER * - CPU_KNOWN_GOOD_STACK_SIZE]; -UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; +UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER * + CPU_KNOWN_GOOD_STACK_SIZE]; +UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; /** Common exception handler. @@ -33,8 +33,8 @@ UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; VOID EFIAPI CommonExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData); @@ -59,7 +59,7 @@ CommonExceptionHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { mExceptionHandlerData.ReservedVectors = mReservedVectorsData; @@ -87,19 +87,19 @@ InitializeCpuExceptionHandlers ( EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { - EFI_STATUS Status; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - IA32_DESCRIPTOR IdtDescriptor; - UINTN IdtEntryCount; - EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; - UINTN Index; - UINTN InterruptEntry; - UINT8 *InterruptEntryCode; - RESERVED_VECTORS_DATA *ReservedVectors; - EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; + EFI_STATUS Status; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_DESCRIPTOR IdtDescriptor; + UINTN IdtEntryCount; + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; + UINTN Index; + UINTN InterruptEntry; + UINT8 *InterruptEntryCode; + RESERVED_VECTORS_DATA *ReservedVectors; + EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; Status = gBS->AllocatePool ( EfiBootServicesCode, @@ -107,7 +107,7 @@ InitializeCpuInterruptHandlers ( (VOID **)&ReservedVectors ); ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL); - SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff); + SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff); if (VectorInfo != NULL) { Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM); if (EFI_ERROR (Status)) { @@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers ( if (IdtEntryCount > CPU_INTERRUPT_NUM) { IdtEntryCount = CPU_INTERRUPT_NUM; } + // // Create Interrupt Descriptor Table and Copy the old IDT table in // @@ -144,18 +145,18 @@ InitializeCpuInterruptHandlers ( ); ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL); - InterruptEntry = (UINTN) InterruptEntryCode; - for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) { + InterruptEntry = (UINTN)InterruptEntryCode; + for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) { CopyMem ( - (VOID *) InterruptEntry, - (VOID *) TemplateMap.ExceptionStart, + (VOID *)InterruptEntry, + (VOID *)TemplateMap.ExceptionStart, TemplateMap.ExceptionStubHeaderSize ); - AsmVectorNumFixup ((VOID *) InterruptEntry, (UINT8) Index, (VOID *) TemplateMap.ExceptionStart); + AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID *)TemplateMap.ExceptionStart); InterruptEntry += TemplateMap.ExceptionStubHeaderSize; } - TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode; + TemplateMap.ExceptionStart = (UINTN)InterruptEntryCode; mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM; mExceptionHandlerData.ReservedVectors = ReservedVectors; mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler; @@ -166,9 +167,9 @@ InitializeCpuInterruptHandlers ( // // Load Interrupt Descriptor Table // - IdtDescriptor.Base = (UINTN) IdtTable; - IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1); - AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor); + IdtDescriptor.Base = (UINTN)IdtTable; + IdtDescriptor.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1); + AsmWriteIdtr ((IA32_DESCRIPTOR *)&IdtDescriptor); return EFI_SUCCESS; } @@ -199,8 +200,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS EFIAPI RegisterCpuInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ) { return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData); @@ -230,14 +231,14 @@ RegisterCpuInterruptHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ) { - EFI_STATUS Status; - CPU_EXCEPTION_INIT_DATA EssData; - IA32_DESCRIPTOR Idtr; - IA32_DESCRIPTOR Gdtr; + EFI_STATUS Status; + CPU_EXCEPTION_INIT_DATA EssData; + IA32_DESCRIPTOR Idtr; + IA32_DESCRIPTOR Gdtr; // // To avoid repeat initialization of default handlers, the caller should pass @@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx ( // version instead; or this method must be implemented as a simple wrapper of // non-ex version of it, if this version has to be called. // - if (InitData == NULL || InitData->X64.InitDefaultHandlers) { + if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) { Status = InitializeCpuExceptionHandlers (VectorInfo); } else { Status = EFI_SUCCESS; @@ -263,25 +264,26 @@ InitializeCpuExceptionHandlersEx ( AsmReadIdtr (&Idtr); AsmReadGdtr (&Gdtr); - EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV; - EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack); - EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV; + EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack); + EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; + EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; - EssData.X64.IdtTable = (VOID *)Idtr.Base; - EssData.X64.IdtTableSize = Idtr.Limit + 1; - EssData.X64.GdtTable = mNewGdt; - EssData.X64.GdtTableSize = sizeof (mNewGdt); - EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; + EssData.X64.IdtTable = (VOID *)Idtr.Base; + EssData.X64.IdtTableSize = Idtr.Limit + 1; + EssData.X64.GdtTable = mNewGdt; + EssData.X64.GdtTableSize = sizeof (mNewGdt); + EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1; + EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; + EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; InitData = &EssData; } + Status = ArchSetupExceptionStack (InitData); } } - return Status; + return Status; } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 903449e0da..f13e8e7020 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -18,13 +18,13 @@ **/ VOID ArchUpdateIdtEntry ( - OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, - IN UINTN InterruptHandler + OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, + IN UINTN InterruptHandler ) { - IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler; - IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16); - IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; + IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler; + IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16); + IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; } /** @@ -35,7 +35,7 @@ ArchUpdateIdtEntry ( **/ UINTN ArchGetIdtHandler ( - IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry + IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry ) { return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16); @@ -50,13 +50,13 @@ ArchGetIdtHandler ( **/ VOID ArchSaveExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - IA32_EFLAGS32 Eflags; - RESERVED_VECTORS_DATA *ReservedVectors; + IA32_EFLAGS32 Eflags; + RESERVED_VECTORS_DATA *ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors; // @@ -71,13 +71,13 @@ ArchSaveExceptionContext ( // // Clear IF flag to avoid old IDT handler enable interrupt by IRET // - Eflags.UintN = SystemContext.SystemContextIa32->Eflags; - Eflags.Bits.IF = 0; + Eflags.UintN = SystemContext.SystemContextIa32->Eflags; + Eflags.Bits.IF = 0; SystemContext.SystemContextIa32->Eflags = Eflags.UintN; // // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // - SystemContext.SystemContextIa32->Eip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; + SystemContext.SystemContextIa32->Eip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode; } /** @@ -89,14 +89,14 @@ ArchSaveExceptionContext ( **/ VOID ArchRestoreExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - RESERVED_VECTORS_DATA *ReservedVectors; + RESERVED_VECTORS_DATA *ReservedVectors; - ReservedVectors = ExceptionHandlerData->ReservedVectors; + ReservedVectors = ExceptionHandlerData->ReservedVectors; SystemContext.SystemContextIa32->Eflags = ReservedVectors[ExceptionType].OldFlags; SystemContext.SystemContextIa32->Cs = ReservedVectors[ExceptionType].OldCs; SystemContext.SystemContextIa32->Eip = ReservedVectors[ExceptionType].OldIp; @@ -116,32 +116,33 @@ ArchRestoreExceptionContext ( **/ EFI_STATUS ArchSetupExceptionStack ( - IN CPU_EXCEPTION_INIT_DATA *StackSwitchData + IN CPU_EXCEPTION_INIT_DATA *StackSwitchData ) { - IA32_DESCRIPTOR Gdtr; - IA32_DESCRIPTOR Idtr; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - IA32_TSS_DESCRIPTOR *TssDesc; - IA32_TASK_STATE_SEGMENT *Tss; - UINTN StackTop; - UINTN Index; - UINTN Vector; - UINTN TssBase; - UINTN GdtSize; - EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; - - if (StackSwitchData == NULL || - StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || - StackSwitchData->Ia32.KnownGoodStackTop == 0 || - StackSwitchData->Ia32.KnownGoodStackSize == 0 || - StackSwitchData->Ia32.StackSwitchExceptions == NULL || - StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 || - StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || - StackSwitchData->Ia32.GdtTable == NULL || - StackSwitchData->Ia32.IdtTable == NULL || - StackSwitchData->Ia32.ExceptionTssDesc == NULL || - StackSwitchData->Ia32.ExceptionTss == NULL) { + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; + UINTN StackTop; + UINTN Index; + UINTN Vector; + UINTN TssBase; + UINTN GdtSize; + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; + + if ((StackSwitchData == NULL) || + (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) || + (StackSwitchData->Ia32.KnownGoodStackTop == 0) || + (StackSwitchData->Ia32.KnownGoodStackSize == 0) || + (StackSwitchData->Ia32.StackSwitchExceptions == NULL) || + (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) || + (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->Ia32.GdtTable == NULL) || + (StackSwitchData->Ia32.IdtTable == NULL) || + (StackSwitchData->Ia32.ExceptionTssDesc == NULL) || + (StackSwitchData->Ia32.ExceptionTss == NULL)) + { return EFI_INVALID_PARAMETER; } @@ -159,7 +160,8 @@ ArchSetupExceptionStack ( } if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize > - ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) { + ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) + { return EFI_INVALID_PARAMETER; } @@ -168,11 +170,14 @@ ArchSetupExceptionStack ( // specified. // if (StackSwitchData->Ia32.ExceptionTssDescSize < - sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { + sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) + { return EFI_INVALID_PARAMETER; } + if (StackSwitchData->Ia32.ExceptionTssSize < - sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { + sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) + { return EFI_INVALID_PARAMETER; } @@ -191,13 +196,14 @@ ArchSetupExceptionStack ( (UINTN)(StackSwitchData->Ia32.GdtTable); if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) { CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); - Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable; + Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable; Gdtr.Limit = (UINT16)GdtSize - 1; } if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) { Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable; } + if (StackSwitchData->Ia32.IdtTableSize > 0) { Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); } @@ -208,14 +214,14 @@ ArchSetupExceptionStack ( // TssBase = (UINTN)Tss; - TssDesc->Uint64 = 0; - TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; - TssDesc->Bits.BaseLow = (UINT16)TssBase; - TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); - TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; - TssDesc->Bits.P = 1; - TssDesc->Bits.LimitHigh = 0; - TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); + TssDesc->Uint64 = 0; + TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.BaseLow = (UINT16)TssBase; + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; + TssDesc->Bits.P = 1; + TssDesc->Bits.LimitHigh = 0; + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); // // Fixup exception task descriptor and task-state segment @@ -234,7 +240,7 @@ ArchSetupExceptionStack ( TssBase = (UINTN)Tss; TssDesc->Uint64 = 0; - TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; @@ -246,14 +252,15 @@ ArchSetupExceptionStack ( // Fixup TSS // Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index]; - if (Vector >= CPU_EXCEPTION_NUM || - Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { + if ((Vector >= CPU_EXCEPTION_NUM) || + (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) + { continue; } ZeroMem (Tss, sizeof (*Tss)); - Tss->EIP = (UINT32)(TemplateMap.ExceptionStart - + Vector * TemplateMap.ExceptionStubHeaderSize); + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart + + Vector * TemplateMap.ExceptionStubHeaderSize); Tss->EFLAGS = 0x2; Tss->ESP = StackTop; Tss->CR3 = AsmReadCr3 (); @@ -264,7 +271,7 @@ ArchSetupExceptionStack ( Tss->FS = AsmReadFs (); Tss->GS = AsmReadGs (); - StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; + StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; // // Update IDT to use Task Gate for given exception @@ -303,8 +310,8 @@ ArchSetupExceptionStack ( VOID EFIAPI DumpCpuContext ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { InternalPrintMessage ( @@ -331,8 +338,10 @@ DumpCpuContext ( (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0 ); } + InternalPrintMessage ("\n"); } + InternalPrintMessage ( "EIP - %08x, CS - %08x, EFLAGS - %08x\n", SystemContext.SystemContextIa32->Eip, @@ -406,8 +415,8 @@ DumpCpuContext ( **/ VOID DumpImageAndCpuContent ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { DumpCpuContext (ExceptionType, SystemContext); @@ -415,7 +424,8 @@ DumpImageAndCpuContent ( // Dump module image base and module entry point by EIP // if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && - ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) { + ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) + { // // The EIP in SystemContext could not be used // if it is page fault with I/D set. diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h index fc37fbe582..211d2abe48 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h @@ -10,29 +10,29 @@ #define _ARCH_CPU_INTERRUPT_DEFS_H_ typedef struct { - EFI_SYSTEM_CONTEXT_IA32 SystemContext; - BOOLEAN ExceptionDataFlag; - UINTN OldIdtHandler; + EFI_SYSTEM_CONTEXT_IA32 SystemContext; + BOOLEAN ExceptionDataFlag; + UINTN OldIdtHandler; } EXCEPTION_HANDLER_CONTEXT; // // Register Structure Definitions // typedef struct { - EFI_STATUS_CODE_DATA Header; - EFI_SYSTEM_CONTEXT_IA32 SystemContext; + EFI_STATUS_CODE_DATA Header; + EFI_SYSTEM_CONTEXT_IA32 SystemContext; } CPU_STATUS_CODE_TEMPLATE; typedef struct { - SPIN_LOCK SpinLock; - UINT32 ApicId; - UINT32 Attribute; - UINTN ExceptonHandler; - UINTN OldFlags; - UINTN OldCs; - UINTN OldIp; - UINTN ExceptionData; - UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; + SPIN_LOCK SpinLock; + UINT32 ApicId; + UINT32 Attribute; + UINTN ExceptonHandler; + UINTN OldFlags; + UINTN OldCs; + UINTN OldIp; + UINTN ExceptionData; + UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; } RESERVED_VECTORS_DATA; #define CPU_TSS_DESC_SIZE \ diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index d256643435..687fc4177f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -13,11 +13,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include -CONST UINTN mDoFarReturnFlag = 0; +CONST UINTN mDoFarReturnFlag = 0; typedef struct { - UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE]; - EXCEPTION_HANDLER_DATA *ExceptionHandlerData; + UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE]; + EXCEPTION_HANDLER_DATA *ExceptionHandlerData; } EXCEPTION0_STUB_HEADER; /** @@ -34,9 +34,9 @@ GetExceptionHandlerData ( VOID ) { - IA32_DESCRIPTOR IdtDescriptor; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - EXCEPTION0_STUB_HEADER *Exception0StubHeader; + IA32_DESCRIPTOR IdtDescriptor; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + EXCEPTION0_STUB_HEADER *Exception0StubHeader; AsmReadIdtr (&IdtDescriptor); IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; @@ -56,12 +56,13 @@ GetExceptionHandlerData ( **/ VOID SetExceptionHandlerData ( - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - EXCEPTION0_STUB_HEADER *Exception0StubHeader; - IA32_DESCRIPTOR IdtDescriptor; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; + EXCEPTION0_STUB_HEADER *Exception0StubHeader; + IA32_DESCRIPTOR IdtDescriptor; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + // // Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header. // So AP can get the ExceptionHandlerData by reading the IDT[0]. @@ -89,8 +90,8 @@ SetExceptionHandlerData ( VOID EFIAPI CommonExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { EXCEPTION_HANDLER_DATA *ExceptionHandlerData; @@ -120,12 +121,12 @@ CommonExceptionHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { - EFI_STATUS Status; - EXCEPTION_HANDLER_DATA *ExceptionHandlerData; - RESERVED_VECTORS_DATA *ReservedVectors; + EFI_STATUS Status; + EXCEPTION_HANDLER_DATA *ExceptionHandlerData; + RESERVED_VECTORS_DATA *ReservedVectors; ReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM); ASSERT (ReservedVectors != NULL); @@ -166,7 +167,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { return EFI_UNSUPPORTED; @@ -198,8 +199,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS EFIAPI RegisterCpuInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ) { return EFI_UNSUPPORTED; @@ -230,11 +231,11 @@ RegisterCpuInterruptHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ) { - EFI_STATUS Status; + EFI_STATUS Status; // // To avoid repeat initialization of default handlers, the caller should pass @@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx ( // version instead; or this method must be implemented as a simple wrapper of // non-ex version of it, if this version has to be called. // - if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) { + if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) { Status = InitializeCpuExceptionHandlers (VectorInfo); } else { Status = EFI_SUCCESS; @@ -253,10 +254,10 @@ InitializeCpuExceptionHandlersEx ( // // Initializing stack switch is only necessary for Stack Guard functionality. // - if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) { + if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) { Status = ArchSetupExceptionStack (InitData); } } - return Status; + return Status; } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 892d349d4b..762ea2460f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -19,14 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ VOID CommonExceptionHandlerWorker ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext; - RESERVED_VECTORS_DATA *ReservedVectors; - EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; + EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext; + RESERVED_VECTORS_DATA *ReservedVectors; + EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; if (ExceptionType == VC_EXCEPTION) { EFI_STATUS Status; @@ -45,68 +45,72 @@ CommonExceptionHandlerWorker ( } } - ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32); + ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(SystemContext.SystemContextIa32); ReservedVectors = ExceptionHandlerData->ReservedVectors; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; switch (ReservedVectors[ExceptionType].Attribute) { - case EFI_VECTOR_HANDOFF_HOOK_BEFORE: - // - // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler. - // Save the original handler to stack so the assembly code can jump to it instead of returning from handler. - // - ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE; - ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; - break; - case EFI_VECTOR_HANDOFF_HOOK_AFTER: - while (TRUE) { - // - // If spin-lock can be acquired, it's the first time entering here. - // - if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) { - // - // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler. - // Save the original handler to stack but skip running the new handler so the original handler is executed - // firstly. - // - ReservedVectors[ExceptionType].ApicId = GetApicId (); - ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData); - ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE; - ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; - return; - } + case EFI_VECTOR_HANDOFF_HOOK_BEFORE: // - // If spin-lock cannot be acquired, it's the second time entering here. - // 'break' instead of 'return' is used so the new exception handler can be executed. + // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler. + // Save the original handler to stack so the assembly code can jump to it instead of returning from handler. // - if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) { + ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE; + ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; + break; + case EFI_VECTOR_HANDOFF_HOOK_AFTER: + while (TRUE) { // - // Old IDT handler has been executed, then restore CPU exception content to - // run new exception handler. + // If spin-lock can be acquired, it's the first time entering here. // - ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData); + if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) { + // + // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler. + // Save the original handler to stack but skip running the new handler so the original handler is executed + // firstly. + // + ReservedVectors[ExceptionType].ApicId = GetApicId (); + ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData); + ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE; + ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; + return; + } + // - // Release spin lock for ApicId + // If spin-lock cannot be acquired, it's the second time entering here. + // 'break' instead of 'return' is used so the new exception handler can be executed. // - ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock); - break; + if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) { + // + // Old IDT handler has been executed, then restore CPU exception content to + // run new exception handler. + // + ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData); + // + // Release spin lock for ApicId + // + ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock); + break; + } + + CpuPause (); } - CpuPause (); - } - break; - case 0xffffffff: - break; - default: - // - // It should never reach here - // - CpuDeadLoop (); - break; + + break; + case 0xffffffff: + break; + default: + // + // It should never reach here + // + CpuDeadLoop (); + break; } - if (ExternalInterruptHandler != NULL && - ExternalInterruptHandler[ExceptionType] != NULL) { - (ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext); + if ((ExternalInterruptHandler != NULL) && + (ExternalInterruptHandler[ExceptionType] != NULL)) + { + (ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext); } else if (ExceptionType < CPU_EXCEPTION_NUM) { // // Get Spinlock to display CPU information @@ -114,6 +118,7 @@ CommonExceptionHandlerWorker ( while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) { CpuPause (); } + // // Initialize the serial port before dumping. // @@ -151,10 +156,10 @@ UpdateIdtTable ( IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - UINT16 CodeSegment; - UINTN Index; - UINTN InterruptHandler; - RESERVED_VECTORS_DATA *ReservedVectors; + UINT16 CodeSegment; + UINTN Index; + UINTN InterruptHandler; + RESERVED_VECTORS_DATA *ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors; // @@ -162,47 +167,47 @@ UpdateIdtTable ( // CodeSegment = AsmReadCs (); - for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index ++) { + for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index++) { IdtTable[Index].Bits.Selector = CodeSegment; // // Check reserved vectors attributes // switch (ReservedVectors[Index].Attribute) { - case EFI_VECTOR_HANDOFF_DO_NOT_HOOK: - // - // Keep original IDT entry - // - continue; - case EFI_VECTOR_HANDOFF_HOOK_AFTER: - InitializeSpinLock (&ReservedVectors[Index].SpinLock); - CopyMem ( - (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, - (VOID *) TemplateMap->HookAfterStubHeaderStart, - TemplateMap->ExceptionStubHeaderSize - ); - AsmVectorNumFixup ( - (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, - (UINT8) Index, - (VOID *) TemplateMap->HookAfterStubHeaderStart - ); + case EFI_VECTOR_HANDOFF_DO_NOT_HOOK: + // + // Keep original IDT entry + // + continue; + case EFI_VECTOR_HANDOFF_HOOK_AFTER: + InitializeSpinLock (&ReservedVectors[Index].SpinLock); + CopyMem ( + (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode, + (VOID *)TemplateMap->HookAfterStubHeaderStart, + TemplateMap->ExceptionStubHeaderSize + ); + AsmVectorNumFixup ( + (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode, + (UINT8)Index, + (VOID *)TemplateMap->HookAfterStubHeaderStart + ); // // Go on the following code // - case EFI_VECTOR_HANDOFF_HOOK_BEFORE: - // - // Save original IDT handler address - // - ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]); + case EFI_VECTOR_HANDOFF_HOOK_BEFORE: + // + // Save original IDT handler address + // + ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]); // // Go on the following code // - default: - // - // Update new IDT entry - // - InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize; - ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); - break; + default: + // + // Update new IDT entry + // + InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize; + ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); + break; } } } @@ -221,19 +226,19 @@ UpdateIdtTable ( **/ EFI_STATUS InitializeCpuExceptionHandlersWorker ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - EFI_STATUS Status; - IA32_DESCRIPTOR IdtDescriptor; - UINTN IdtEntryCount; - EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - RESERVED_VECTORS_DATA *ReservedVectors; + EFI_STATUS Status; + IA32_DESCRIPTOR IdtDescriptor; + UINTN IdtEntryCount; + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + RESERVED_VECTORS_DATA *ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors; - SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); + SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); if (VectorInfo != NULL) { Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM); if (EFI_ERROR (Status)) { @@ -253,7 +258,7 @@ InitializeCpuExceptionHandlersWorker ( IdtEntryCount = CPU_EXCEPTION_NUM; } - IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base; + IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; AsmGetTemplateAddressMap (&TemplateMap); ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE); @@ -282,33 +287,33 @@ InitializeCpuExceptionHandlersWorker ( **/ EFI_STATUS RegisterCpuInterruptHandlerWorker ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - UINTN EnabledInterruptNum; - RESERVED_VECTORS_DATA *ReservedVectors; - EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; + UINTN EnabledInterruptNum; + RESERVED_VECTORS_DATA *ReservedVectors; + EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; EnabledInterruptNum = ExceptionHandlerData->IdtEntryCount; ReservedVectors = ExceptionHandlerData->ReservedVectors; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; - if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum || - ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) { + if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) || + (ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK)) + { return EFI_UNSUPPORTED; } - if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) { + if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) { return EFI_INVALID_PARAMETER; } - if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) { + if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) { return EFI_ALREADY_STARTED; } ExternalInterruptHandler[InterruptType] = InterruptHandler; return EFI_SUCCESS; } - diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 01b5a2f1f4..c614d5b0b6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include "CpuExceptionCommon.h" -CONST UINTN mDoFarReturnFlag = 0; +CONST UINTN mDoFarReturnFlag = 0; /** Common exception handler. @@ -21,8 +21,8 @@ CONST UINTN mDoFarReturnFlag = 0; VOID EFIAPI CommonExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { if (ExceptionType == VC_EXCEPTION) { @@ -79,26 +79,27 @@ CommonExceptionHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { - EFI_STATUS Status; - RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM]; - IA32_DESCRIPTOR IdtDescriptor; - UINTN IdtEntryCount; - UINT16 CodeSegment; - EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - UINTN Index; - UINTN InterruptHandler; + EFI_STATUS Status; + RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM]; + IA32_DESCRIPTOR IdtDescriptor; + UINTN IdtEntryCount; + UINT16 CodeSegment; + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + UINTN Index; + UINTN InterruptHandler; if (VectorInfo != NULL) { - SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); + SetMem ((VOID *)ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM); if (EFI_ERROR (Status)) { return EFI_INVALID_PARAMETER; } } + // // Read IDT descriptor and calculate IDT size // @@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers ( // IdtEntryCount = CPU_EXCEPTION_NUM; } + // // Use current CS as the segment selector of interrupt gate in IDT // @@ -117,7 +119,7 @@ InitializeCpuExceptionHandlers ( AsmGetTemplateAddressMap (&TemplateMap); IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; - for (Index = 0; Index < IdtEntryCount; Index ++) { + for (Index = 0; Index < IdtEntryCount; Index++) { IdtTable[Index].Bits.Selector = CodeSegment; // // Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK @@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers ( continue; } } + // // Update IDT entry // InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize; ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); } + return EFI_SUCCESS; } @@ -156,7 +160,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { return EFI_UNSUPPORTED; @@ -188,8 +192,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS EFIAPI RegisterCpuInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ) { return EFI_UNSUPPORTED; @@ -220,8 +224,8 @@ RegisterCpuInterruptHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ) { return InitializeCpuExceptionHandlers (VectorInfo); diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c index e7977d49b7..77ee74579f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c @@ -9,16 +9,17 @@ #include #include "CpuExceptionCommon.h" -CONST UINTN mDoFarReturnFlag = 1; +CONST UINTN mDoFarReturnFlag = 1; // // Spin lock for CPU information display // -SPIN_LOCK mDisplayMessageSpinLock; +SPIN_LOCK mDisplayMessageSpinLock; + +RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; +EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; +EXCEPTION_HANDLER_DATA mExceptionHandlerData; -RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; -EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; -EXCEPTION_HANDLER_DATA mExceptionHandlerData; /** Common exception handler. @@ -28,8 +29,8 @@ EXCEPTION_HANDLER_DATA mExceptionHandlerData; VOID EFIAPI CommonExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData); @@ -54,7 +55,7 @@ CommonExceptionHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { mExceptionHandlerData.ReservedVectors = mReservedVectorsData; @@ -82,7 +83,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { return EFI_UNSUPPORTED; @@ -114,8 +115,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS EFIAPI RegisterCpuInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ) { return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData); @@ -146,8 +147,8 @@ RegisterCpuInterruptHandler ( EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL ) { return InitializeCpuExceptionHandlers (VectorInfo); diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index d3da16e4df..cd7dccd481 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -17,8 +17,8 @@ **/ VOID ArchUpdateIdtEntry ( - OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, - IN UINTN InterruptHandler + OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, + IN UINTN InterruptHandler ) { IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler; @@ -35,11 +35,11 @@ ArchUpdateIdtEntry ( **/ UINTN ArchGetIdtHandler ( - IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry + IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry ) { - return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) + - (((UINTN) IdtEntry->Bits.OffsetUpper) << 32); + return IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16) + + (((UINTN)IdtEntry->Bits.OffsetUpper) << 32); } /** @@ -51,13 +51,13 @@ ArchGetIdtHandler ( **/ VOID ArchSaveExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - IA32_EFLAGS32 Eflags; - RESERVED_VECTORS_DATA *ReservedVectors; + IA32_EFLAGS32 Eflags; + RESERVED_VECTORS_DATA *ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors; // @@ -74,13 +74,13 @@ ArchSaveExceptionContext ( // // Clear IF flag to avoid old IDT handler enable interrupt by IRET // - Eflags.UintN = SystemContext.SystemContextX64->Rflags; - Eflags.Bits.IF = 0; + Eflags.UintN = SystemContext.SystemContextX64->Rflags; + Eflags.Bits.IF = 0; SystemContext.SystemContextX64->Rflags = Eflags.UintN; // // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // - SystemContext.SystemContextX64->Rip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; + SystemContext.SystemContextX64->Rip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode; } /** @@ -92,14 +92,14 @@ ArchSaveExceptionContext ( **/ VOID ArchRestoreExceptionContext ( - IN UINTN ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext, - IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData + IN UINTN ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext, + IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ) { - RESERVED_VECTORS_DATA *ReservedVectors; + RESERVED_VECTORS_DATA *ReservedVectors; - ReservedVectors = ExceptionHandlerData->ReservedVectors; + ReservedVectors = ExceptionHandlerData->ReservedVectors; SystemContext.SystemContextX64->Ss = ReservedVectors[ExceptionType].OldSs; SystemContext.SystemContextX64->Rsp = ReservedVectors[ExceptionType].OldSp; SystemContext.SystemContextX64->Rflags = ReservedVectors[ExceptionType].OldFlags; @@ -121,31 +121,32 @@ ArchRestoreExceptionContext ( **/ EFI_STATUS ArchSetupExceptionStack ( - IN CPU_EXCEPTION_INIT_DATA *StackSwitchData + IN CPU_EXCEPTION_INIT_DATA *StackSwitchData ) { - IA32_DESCRIPTOR Gdtr; - IA32_DESCRIPTOR Idtr; - IA32_IDT_GATE_DESCRIPTOR *IdtTable; - IA32_TSS_DESCRIPTOR *TssDesc; - IA32_TASK_STATE_SEGMENT *Tss; - UINTN StackTop; - UINTN Index; - UINTN Vector; - UINTN TssBase; - UINTN GdtSize; - - if (StackSwitchData == NULL || - StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || - StackSwitchData->X64.KnownGoodStackTop == 0 || - StackSwitchData->X64.KnownGoodStackSize == 0 || - StackSwitchData->X64.StackSwitchExceptions == NULL || - StackSwitchData->X64.StackSwitchExceptionNumber == 0 || - StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || - StackSwitchData->X64.GdtTable == NULL || - StackSwitchData->X64.IdtTable == NULL || - StackSwitchData->X64.ExceptionTssDesc == NULL || - StackSwitchData->X64.ExceptionTss == NULL) { + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; + UINTN StackTop; + UINTN Index; + UINTN Vector; + UINTN TssBase; + UINTN GdtSize; + + if ((StackSwitchData == NULL) || + (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) || + (StackSwitchData->X64.KnownGoodStackTop == 0) || + (StackSwitchData->X64.KnownGoodStackSize == 0) || + (StackSwitchData->X64.StackSwitchExceptions == NULL) || + (StackSwitchData->X64.StackSwitchExceptionNumber == 0) || + (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->X64.GdtTable == NULL) || + (StackSwitchData->X64.IdtTable == NULL) || + (StackSwitchData->X64.ExceptionTssDesc == NULL) || + (StackSwitchData->X64.ExceptionTss == NULL)) + { return EFI_INVALID_PARAMETER; } @@ -163,7 +164,8 @@ ArchSetupExceptionStack ( } if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) > - ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) { + ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) + { return EFI_INVALID_PARAMETER; } @@ -173,6 +175,7 @@ ArchSetupExceptionStack ( if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) { return EFI_INVALID_PARAMETER; } + if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) { return EFI_INVALID_PARAMETER; } @@ -196,13 +199,14 @@ ArchSetupExceptionStack ( (UINTN)(StackSwitchData->X64.GdtTable); if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) { CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); - Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable; + Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable; Gdtr.Limit = (UINT16)GdtSize - 1; } if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) { Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable; } + if (StackSwitchData->X64.IdtTableSize > 0) { Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1); } @@ -213,16 +217,16 @@ ArchSetupExceptionStack ( // TssBase = (UINTN)Tss; - TssDesc->Uint128.Uint64 = 0; - TssDesc->Uint128.Uint64_1= 0; - TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; - TssDesc->Bits.BaseLow = (UINT16)TssBase; - TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); - TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; - TssDesc->Bits.P = 1; - TssDesc->Bits.LimitHigh = 0; - TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24); - TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32); + TssDesc->Uint128.Uint64 = 0; + TssDesc->Uint128.Uint64_1 = 0; + TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.BaseLow = (UINT16)TssBase; + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; + TssDesc->Bits.P = 1; + TssDesc->Bits.LimitHigh = 0; + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24); + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32); // // Fixup exception task descriptor and task-state segment @@ -236,16 +240,18 @@ ArchSetupExceptionStack ( // Fixup IST // Tss->IST[Index] = StackTop; - StackTop -= StackSwitchData->X64.KnownGoodStackSize; + StackTop -= StackSwitchData->X64.KnownGoodStackSize; // // Set the IST field to enable corresponding IST // Vector = StackSwitchData->X64.StackSwitchExceptions[Index]; - if (Vector >= CPU_EXCEPTION_NUM || - Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { + if ((Vector >= CPU_EXCEPTION_NUM) || + (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) + { continue; } + IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1); } @@ -276,8 +282,8 @@ ArchSetupExceptionStack ( VOID EFIAPI DumpCpuContext ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { InternalPrintMessage ( @@ -304,8 +310,10 @@ DumpCpuContext ( (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0 ); } + InternalPrintMessage ("\n"); } + InternalPrintMessage ( "RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n", SystemContext.SystemContextX64->Rip, @@ -406,8 +414,8 @@ DumpCpuContext ( **/ VOID DumpImageAndCpuContent ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { DumpCpuContext (ExceptionType, SystemContext); @@ -415,7 +423,8 @@ DumpImageAndCpuContent ( // Dump module image base and module entry point by RIP // if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && - ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) { + ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) + { // // The RIP in SystemContext could not be used // if it is page fault with I/D set. diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h index c3a07862ea..008670cb0d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h @@ -10,9 +10,9 @@ #define _ARCH_CPU_INTERRUPT_DEFS_H_ typedef struct { - EFI_SYSTEM_CONTEXT_X64 SystemContext; - BOOLEAN ExceptionDataFlag; - UINTN OldIdtHandler; + EFI_SYSTEM_CONTEXT_X64 SystemContext; + BOOLEAN ExceptionDataFlag; + UINTN OldIdtHandler; } EXCEPTION_HANDLER_CONTEXT; // @@ -24,20 +24,20 @@ typedef struct { } CPU_STATUS_CODE_TEMPLATE; typedef struct { - SPIN_LOCK SpinLock; - UINT32 ApicId; - UINT32 Attribute; - UINTN ExceptonHandler; - UINTN OldSs; - UINTN OldSp; - UINTN OldFlags; - UINTN OldCs; - UINTN OldIp; - UINTN ExceptionData; - UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; + SPIN_LOCK SpinLock; + UINT32 ApicId; + UINT32 Attribute; + UINTN ExceptonHandler; + UINTN OldSs; + UINTN OldSp; + UINTN OldFlags; + UINTN OldCs; + UINTN OldIp; + UINTN ExceptionData; + UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; } RESERVED_VECTORS_DATA; -#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR) -#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT) +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR) +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT) #endif diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c index 6ddf917bad..98363bd8f7 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c @@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency ( { return CpuidCoreClockCalculateTscFrequency (); } - diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c index bce02eeef9..1955b90e54 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c +++ b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c @@ -13,7 +13,9 @@ #include #include -GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } }; +GUID mCpuCrystalFrequencyHobGuid = { + 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } +}; /** Internal function to retrieves the 64-bit frequency in Hz. @@ -41,11 +43,11 @@ CpuidCoreClockCalculateTscFrequency ( VOID ) { - UINT64 TscFrequency; - UINT64 CoreXtalFrequency; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; + UINT64 TscFrequency; + UINT64 CoreXtalFrequency; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; // // Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Information @@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency ( // // If EAX or EBX returns 0, the XTAL ratio is not enumerated. // - if (RegEax == 0 || RegEbx ==0 ) { + if ((RegEax == 0) || (RegEbx == 0)) { ASSERT (RegEax != 0); ASSERT (RegEbx != 0); return 0; } + // // If ECX returns 0, the XTAL frequency is not enumerated. // And PcdCpuCoreCrystalClockFrequency defined should base on processor series. @@ -69,7 +72,7 @@ CpuidCoreClockCalculateTscFrequency ( if (RegEcx == 0) { CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency); } else { - CoreXtalFrequency = (UINT64) RegEcx; + CoreXtalFrequency = (UINT64)RegEcx; } // @@ -99,7 +102,7 @@ InternalCpuDelay ( // // The target timer count is calculated here // - Ticks = AsmReadTsc() + Delay; + Ticks = AsmReadTsc () + Delay; // // Wait until time out @@ -107,8 +110,8 @@ InternalCpuDelay ( // Thus, this function must be called within 10 years of reset since // Intel guarantees a minimum of 10 years before the TSC wraps. // - while (AsmReadTsc() <= Ticks) { - CpuPause(); + while (AsmReadTsc () <= Ticks) { + CpuPause (); } } @@ -128,7 +131,6 @@ MicroSecondDelay ( IN UINTN MicroSeconds ) { - InternalCpuDelay ( DivU64x32 ( MultU64x64 ( @@ -136,8 +138,8 @@ MicroSecondDelay ( InternalGetPerformanceCounterFrequency () ), 1000000u - ) - ); + ) + ); return MicroSeconds; } @@ -158,7 +160,6 @@ NanoSecondDelay ( IN UINTN NanoSeconds ) { - InternalCpuDelay ( DivU64x32 ( MultU64x64 ( @@ -166,8 +167,8 @@ NanoSecondDelay ( InternalGetPerformanceCounterFrequency () ), 1000000000u - ) - ); + ) + ); return NanoSeconds; } @@ -230,6 +231,7 @@ GetPerformanceCounterProperties ( if (EndValue != NULL) { *EndValue = 0xffffffffffffffffULL; } + return InternalGetPerformanceCounterFrequency (); } @@ -269,9 +271,9 @@ GetTimeInNanoSecond ( // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34, // i.e. highest bit set in Remainder should <= 33. // - Shift = MAX (0, HighBitSet64 (Remainder) - 33); - Remainder = RShiftU64 (Remainder, (UINTN) Shift); - Frequency = RShiftU64 (Frequency, (UINTN) Shift); + Shift = MAX (0, HighBitSet64 (Remainder) - 33); + Remainder = RShiftU64 (Remainder, (UINTN)Shift); + Frequency = RShiftU64 (Frequency, (UINTN)Shift); NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); return NanoSeconds; diff --git a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c index 03a43fdae7..767ec80f8a 100644 --- a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c +++ b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c @@ -25,7 +25,7 @@ GetProcessorMicrocodeSignature ( VOID ) { - MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr; + MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr; AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); @@ -44,12 +44,12 @@ GetProcessorMicrocodeCpuId ( EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId ) { - MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; ASSERT (MicrocodeCpuId != NULL); - PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); - MicrocodeCpuId->PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId; + PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + MicrocodeCpuId->PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId; AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL); } @@ -71,10 +71,10 @@ GetProcessorMicrocodeCpuId ( UINT32 EFIAPI GetMicrocodeLength ( - IN CPU_MICROCODE_HEADER *Microcode + IN CPU_MICROCODE_HEADER *Microcode ) { - UINT32 TotalSize; + UINT32 TotalSize; ASSERT (Microcode != NULL); @@ -82,6 +82,7 @@ GetMicrocodeLength ( if (Microcode->DataSize != 0) { TotalSize = Microcode->TotalSize; } + return TotalSize; } @@ -95,12 +96,12 @@ GetMicrocodeLength ( VOID EFIAPI LoadMicrocode ( - IN CPU_MICROCODE_HEADER *Microcode + IN CPU_MICROCODE_HEADER *Microcode ) { ASSERT (Microcode != NULL); - AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1)); + AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64)(UINTN)(Microcode + 1)); } /** @@ -119,13 +120,13 @@ LoadMicrocode ( **/ BOOLEAN IsProcessorMatchedMicrocode ( - IN UINT32 ProcessorSignature, - IN UINT32 ProcessorFlags, - IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, - IN UINTN MicrocodeCpuIdCount + IN UINT32 ProcessorSignature, + IN UINT32 ProcessorFlags, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + IN UINTN MicrocodeCpuIdCount ) { - UINTN Index; + UINTN Index; if (MicrocodeCpuIdCount == 0) { return TRUE; @@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode ( for (Index = 0; Index < MicrocodeCpuIdCount; Index++) { if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) && - (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) { + ((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0)) + { return TRUE; } } @@ -182,22 +184,22 @@ IsProcessorMatchedMicrocode ( BOOLEAN EFIAPI IsValidMicrocode ( - IN CPU_MICROCODE_HEADER *Microcode, - IN UINTN MicrocodeLength, - IN UINT32 MinimumRevision, - IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, - IN UINTN MicrocodeCpuIdCount, - IN BOOLEAN VerifyChecksum + IN CPU_MICROCODE_HEADER *Microcode, + IN UINTN MicrocodeLength, + IN UINT32 MinimumRevision, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, + IN UINTN MicrocodeCpuIdCount, + IN BOOLEAN VerifyChecksum ) { - UINTN Index; - UINT32 DataSize; - UINT32 TotalSize; - CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; - CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; - UINT32 ExtendedTableLength; - UINT32 Sum32; - BOOLEAN Match; + UINTN Index; + UINT32 DataSize; + UINT32 TotalSize; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + UINT32 ExtendedTableLength; + UINT32 Sum32; + BOOLEAN Match; ASSERT (Microcode != NULL); @@ -206,7 +208,7 @@ IsValidMicrocode ( // the input microcode buffer is so small that even cannot contain the header. // the input microcode buffer is so large that exceeds MAX_ADDRESS. // - if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN) Microcode))) { + if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN)Microcode))) { return FALSE; } @@ -249,7 +251,7 @@ IsValidMicrocode ( // // The summation of all DWORDs in microcode should be zero. // - if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) != 0)) { + if (VerifyChecksum && (CalculateSum32 ((UINT32 *)Microcode, TotalSize) != 0)) { return FALSE; } @@ -272,29 +274,34 @@ IsValidMicrocode ( if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) { return FALSE; } + // // Extended Table exist, check if the CPU in support list // - ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN) (Microcode + 1) + DataSize); + ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINTN)(Microcode + 1) + DataSize); if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) { return FALSE; } + if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE) - > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) { + > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) + { return FALSE; } + // // Check the extended table checksum // - if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength) != 0)) { + if (VerifyChecksum && (CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength) != 0)) { return FALSE; } - ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1); - for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index ++) { + ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1); + for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) { if (VerifyChecksum && (ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag - + ExtendedTable[Index].Checksum != Sum32)) { + + ExtendedTable[Index].Checksum != Sum32)) + { // // The extended table entry is valid when the summation of Processor Signature, Processor Flags // and Checksum equal to the coresponding summation from primary header. Because: @@ -308,6 +315,7 @@ IsValidMicrocode ( // continue; } + Match = IsProcessorMatchedMicrocode ( ExtendedTable[Index].ProcessorSignature.Uint32, ExtendedTable[Index].ProcessorFlag, @@ -318,5 +326,6 @@ IsValidMicrocode ( return TRUE; } } + return FALSE; } diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c index 93fc63bf93..9d9206d209 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -18,21 +18,21 @@ #include -#define AP_SAFE_STACK_SIZE 128 +#define AP_SAFE_STACK_SIZE 128 -CPU_MP_DATA *mCpuMpData = NULL; -EFI_EVENT mCheckAllApsEvent = NULL; -EFI_EVENT mMpInitExitBootServicesEvent = NULL; -EFI_EVENT mLegacyBootEvent = NULL; -volatile BOOLEAN mStopCheckAllApsStatus = TRUE; -VOID *mReservedApLoopFunc = NULL; -UINTN mReservedTopOfApStack; -volatile UINT32 mNumberToFinish = 0; +CPU_MP_DATA *mCpuMpData = NULL; +EFI_EVENT mCheckAllApsEvent = NULL; +EFI_EVENT mMpInitExitBootServicesEvent = NULL; +EFI_EVENT mLegacyBootEvent = NULL; +volatile BOOLEAN mStopCheckAllApsStatus = TRUE; +VOID *mReservedApLoopFunc = NULL; +UINTN mReservedTopOfApStack; +volatile UINT32 mNumberToFinish = 0; // // Begin wakeup buffer allocation below 0x88000 // -STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000; +STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000; /** Enable Debug Agent to support source debugging on AP function. @@ -70,7 +70,7 @@ GetCpuMpData ( **/ VOID SaveCpuMpData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { mCpuMpData = CpuMpData; @@ -86,12 +86,12 @@ SaveCpuMpData ( **/ UINTN GetWakeupBuffer ( - IN UINTN WakeupBufferSize + IN UINTN WakeupBufferSize ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS StartAddress; - EFI_MEMORY_TYPE MemoryType; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS StartAddress; + EFI_MEMORY_TYPE MemoryType; if (PcdGetBool (PcdSevEsIsEnabled)) { MemoryType = EfiReservedMemoryType; @@ -115,6 +115,7 @@ GetWakeupBuffer ( } else { StartAddress = 0x88000; } + Status = gBS->AllocatePages ( AllocateMaxAddress, MemoryType, @@ -123,7 +124,7 @@ GetWakeupBuffer ( ); ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - StartAddress = (EFI_PHYSICAL_ADDRESS) -1; + StartAddress = (EFI_PHYSICAL_ADDRESS)-1; } else if (PcdGetBool (PcdSevEsIsEnabled)) { // // Next SEV-ES wakeup buffer allocation must be below this allocation @@ -131,10 +132,14 @@ GetWakeupBuffer ( mSevEsDxeWakeupBuffer = StartAddress; } - DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n", - (UINTN) StartAddress, WakeupBufferSize)); + DEBUG (( + DEBUG_INFO, + "WakeupBufferStart = %x, WakeupBufferSize = %x\n", + (UINTN)StartAddress, + WakeupBufferSize + )); - return (UINTN) StartAddress; + return (UINTN)StartAddress; } /** @@ -151,19 +156,19 @@ GetWakeupBuffer ( **/ UINTN GetModeTransitionBuffer ( - IN UINTN BufferSize + IN UINTN BufferSize ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS StartAddress; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS StartAddress; StartAddress = BASE_4GB - 1; - Status = gBS->AllocatePages ( - AllocateMaxAddress, - EfiBootServicesCode, - EFI_SIZE_TO_PAGES (BufferSize), - &StartAddress - ); + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiBootServicesCode, + EFI_SIZE_TO_PAGES (BufferSize), + &StartAddress + ); if (EFI_ERROR (Status)) { StartAddress = 0; } @@ -194,27 +199,27 @@ GetSevEsAPMemory ( // Allocate 1 page for AP jump table page // StartAddress = BASE_4GB - 1; - Status = gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - 1, - &StartAddress - ); + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + 1, + &StartAddress + ); ASSERT_EFI_ERROR (Status); - DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN) StartAddress)); + DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN)StartAddress)); // // Save the SevEsAPMemory as the AP jump table. // Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB); - Ghcb = Msr.Ghcb; + Ghcb = Msr.Ghcb; VmgInit (Ghcb, &InterruptState); - VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress); + VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64)(UINTN)StartAddress); VmgDone (Ghcb, InterruptState); - return (UINTN) StartAddress; + return (UINTN)StartAddress; } /** @@ -226,9 +231,9 @@ CheckAndUpdateApsStatus ( VOID ) { - UINTN ProcessorNumber; - EFI_STATUS Status; - CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + EFI_STATUS Status; + CPU_MP_DATA *CpuMpData; CpuMpData = GetCpuMpData (); @@ -236,13 +241,12 @@ CheckAndUpdateApsStatus ( // First, check whether pending StartupAllAPs() exists. // if (CpuMpData->WaitEvent != NULL) { - Status = CheckAllAPs (); // // If all APs finish for StartupAllAPs(), signal the WaitEvent for it. // if (Status != EFI_NOT_READY) { - Status = gBS->SignalEvent (CpuMpData->WaitEvent); + Status = gBS->SignalEvent (CpuMpData->WaitEvent); CpuMpData->WaitEvent = NULL; } } @@ -251,7 +255,6 @@ CheckAndUpdateApsStatus ( // Second, check whether pending StartupThisAPs() callings exist. // for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) { - if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) { continue; } @@ -260,7 +263,7 @@ CheckAndUpdateApsStatus ( if (Status != EFI_NOT_READY) { gBS->SignalEvent (CpuMpData->CpuData[ProcessorNumber].WaitEvent); - CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL; + CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL; } } } @@ -279,8 +282,8 @@ CheckAndUpdateApsStatus ( VOID EFIAPI CheckApsStatus ( - IN EFI_EVENT Event, - IN VOID *Context + IN EFI_EVENT Event, + IN VOID *Context ) { // @@ -307,18 +310,20 @@ GetProtectedMode16CS ( UINTN GdtEntryCount; UINT16 Index; - Index = (UINT16) -1; + Index = (UINT16)-1; AsmReadGdtr (&GdtrDesc); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); - GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base; for (Index = 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L == 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) { + if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) { break; } } + GdtEntry++; } + ASSERT (Index != GdtEntryCount); return Index * 8; } @@ -340,15 +345,17 @@ GetProtectedModeCS ( AsmReadGdtr (&GdtrDesc); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); - GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base; for (Index = 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L == 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) { + if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) { break; } } + GdtEntry++; } + ASSERT (Index != GdtEntryCount); return Index * 8; } @@ -364,11 +371,11 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; + UINTN ProcessorNumber; + UINTN StackStart; MpInitLibWhoAmI (&ProcessorNumber); CpuMpData = GetCpuMpData (); @@ -378,13 +385,14 @@ RelocateApLoop ( } else { StackStart = mReservedTopOfApStack; } - AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc; + + AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc; AsmRelocateApLoopFunc ( MwaitSupport, CpuMpData->ApTargetCState, CpuMpData->PmCodeSegment, StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN) &mNumberToFinish, + (UINTN)&mNumberToFinish, CpuMpData->Pm16CodeSegment, CpuMpData->SevEsAPBuffer, CpuMpData->WakeupBuffer @@ -406,32 +414,32 @@ RelocateApLoop ( VOID EFIAPI MpInitChangeApLoopCallback ( - IN EFI_EVENT Event, - IN VOID *Context + IN EFI_EVENT Event, + IN VOID *Context ) { - CPU_MP_DATA *CpuMpData; + CPU_MP_DATA *CpuMpData; - CpuMpData = GetCpuMpData (); - CpuMpData->PmCodeSegment = GetProtectedModeCS (); + CpuMpData = GetCpuMpData (); + CpuMpData->PmCodeSegment = GetProtectedModeCS (); CpuMpData->Pm16CodeSegment = GetProtectedMode16CS (); - CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode); - mNumberToFinish = CpuMpData->CpuCount - 1; + CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode); + mNumberToFinish = CpuMpData->CpuCount - 1; WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); while (mNumberToFinish > 0) { CpuPause (); } - if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN) -1)) { + if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN)-1)) { // // There are APs present. Re-use reserved memory area below 1MB from // WakeupBuffer as the area to be used for transitioning to 16-bit mode // in support of booting of the AP by an OS. // CopyMem ( - (VOID *) CpuMpData->WakeupBuffer, - (VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress + - CpuMpData->AddressMap.SwitchToRealPM16ModeOffset), + (VOID *)CpuMpData->WakeupBuffer, + (VOID *)(CpuMpData->AddressMap.RendezvousFunnelAddress + + CpuMpData->AddressMap.SwitchToRealPM16ModeOffset), CpuMpData->AddressMap.SwitchToRealPM16ModeSize ); } @@ -446,16 +454,16 @@ MpInitChangeApLoopCallback ( **/ VOID InitMpGlobalData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Address; - UINTN ApSafeBufferSize; - UINTN Index; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc; - UINTN StackBase; - CPU_INFO_IN_HOB *CpuInfoInHob; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Address; + UINTN ApSafeBufferSize; + UINTN Index; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc; + UINTN StackBase; + CPU_INFO_IN_HOB *CpuInfoInHob; SaveCpuMpData (CpuMpData); @@ -485,7 +493,7 @@ InitMpGlobalData ( // CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; for (Index = 0; Index < CpuMpData->CpuCount; ++Index) { - if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) { + if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) { StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize; } else { StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize; @@ -501,8 +509,12 @@ InitMpGlobalData ( ); ASSERT_EFI_ERROR (Status); - DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", - (UINT64)StackBase, (UINT64)Index)); + DEBUG (( + DEBUG_INFO, + "Stack Guard set at %lx [cpu%lu]!\n", + (UINT64)StackBase, + (UINT64)Index + )); } } @@ -514,9 +526,11 @@ InitMpGlobalData ( // Allocating it in advance since memory services are not available in // Exit Boot Services callback function. // - ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( - CpuMpData->AddressMap.RelocateApLoopFuncSize - )); + ApSafeBufferSize = EFI_PAGES_TO_SIZE ( + EFI_SIZE_TO_PAGES ( + CpuMpData->AddressMap.RelocateApLoopFuncSize + ) + ); Address = BASE_4GB - 1; Status = gBS->AllocatePages ( AllocateMaxAddress, @@ -526,7 +540,7 @@ InitMpGlobalData ( ); ASSERT_EFI_ERROR (Status); - mReservedApLoopFunc = (VOID *) (UINTN) Address; + mReservedApLoopFunc = (VOID *)(UINTN)Address; ASSERT (mReservedApLoopFunc != NULL); // @@ -545,9 +559,11 @@ InitMpGlobalData ( ); } - ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( - CpuMpData->CpuCount * AP_SAFE_STACK_SIZE - )); + ApSafeBufferSize = EFI_PAGES_TO_SIZE ( + EFI_SIZE_TO_PAGES ( + CpuMpData->CpuCount * AP_SAFE_STACK_SIZE + ) + ); Address = BASE_4GB - 1; Status = gBS->AllocatePages ( AllocateMaxAddress, @@ -557,7 +573,7 @@ InitMpGlobalData ( ); ASSERT_EFI_ERROR (Status); - mReservedTopOfApStack = (UINTN) Address + ApSafeBufferSize; + mReservedTopOfApStack = (UINTN)Address + ApSafeBufferSize; ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0); CopyMem ( mReservedApLoopFunc, @@ -684,15 +700,15 @@ InitMpGlobalData ( EFI_STATUS EFIAPI MpInitLibStartupAllAPs ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ) { - EFI_STATUS Status; + EFI_STATUS Status; // // Temporarily stop checkAllApsStatus for avoid resource dead-lock. @@ -791,15 +807,15 @@ MpInitLibStartupAllAPs ( EFI_STATUS EFIAPI MpInitLibStartupThisAP ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ) { - EFI_STATUS Status; + EFI_STATUS Status; // // temporarily stop checkAllApsStatus for avoid resource dead-lock. @@ -849,19 +865,19 @@ MpInitLibStartupThisAP ( EFI_STATUS EFIAPI MpInitLibSwitchBSP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ) { - EFI_STATUS Status; - EFI_TIMER_ARCH_PROTOCOL *Timer; - UINT64 TimerPeriod; + EFI_STATUS Status; + EFI_TIMER_ARCH_PROTOCOL *Timer; + UINT64 TimerPeriod; TimerPeriod = 0; // // Locate Timer Arch Protocol // - Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **) &Timer); + Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **)&Timer); if (EFI_ERROR (Status)) { Timer = NULL; } @@ -922,13 +938,13 @@ MpInitLibSwitchBSP ( EFI_STATUS EFIAPI MpInitLibEnableDisableAP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { - EFI_STATUS Status; - BOOLEAN TempStopCheckState; + EFI_STATUS Status; + BOOLEAN TempStopCheckState; TempStopCheckState = FALSE; // @@ -961,7 +977,7 @@ MpInitLibEnableDisableAP ( **/ EFI_STATUS PlatformShadowMicrocode ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { // diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c index 105a9f84bf..f9f070fa8b 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -18,17 +18,17 @@ **/ VOID MicrocodeDetect ( - IN CPU_MP_DATA *CpuMpData, - IN UINTN ProcessorNumber + IN CPU_MP_DATA *CpuMpData, + IN UINTN ProcessorNumber ) { - CPU_MICROCODE_HEADER *Microcode; - UINTN MicrocodeEnd; - CPU_AP_DATA *BspData; - UINT32 LatestRevision; - CPU_MICROCODE_HEADER *LatestMicrocode; - UINT32 ThreadId; - EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId; + CPU_MICROCODE_HEADER *Microcode; + UINTN MicrocodeEnd; + CPU_AP_DATA *BspData; + UINT32 LatestRevision; + CPU_MICROCODE_HEADER *LatestMicrocode; + UINT32 ThreadId; + EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId; if (CpuMpData->MicrocodePatchRegionSize == 0) { // @@ -47,7 +47,7 @@ MicrocodeDetect ( GetProcessorMicrocodeCpuId (&MicrocodeCpuId); - if (ProcessorNumber != (UINTN) CpuMpData->BspNumber) { + if (ProcessorNumber != (UINTN)CpuMpData->BspNumber) { // // Direct use microcode of BSP if AP is the same as BSP. // Assume BSP calls this routine() before AP. @@ -55,8 +55,9 @@ MicrocodeDetect ( BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]); if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) && (BspData->PlatformId == MicrocodeCpuId.PlatformId) && - (BspData->MicrocodeEntryAddr != 0)) { - LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN) BspData->MicrocodeEntryAddr; + (BspData->MicrocodeEntryAddr != 0)) + { + LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr; LatestRevision = LatestMicrocode->UpdateRevision; goto LoadMicrocode; } @@ -69,11 +70,11 @@ MicrocodeDetect ( // LatestRevision = 0; LatestMicrocode = NULL; - Microcode = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; - MicrocodeEnd = (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatchRegionSize; + Microcode = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress; + MicrocodeEnd = (UINTN)Microcode + (UINTN)CpuMpData->MicrocodePatchRegionSize; do { - if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) { + if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN)Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) { // // It is the padding data between the microcode patches for microcode patches alignment. // Because the microcode patch is the multiple of 1-KByte, the padding data should not @@ -81,14 +82,15 @@ MicrocodeDetect ( // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to // find the next possible microcode patch header. // - Microcode = (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB); + Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB); continue; } + LatestMicrocode = Microcode; LatestRevision = LatestMicrocode->UpdateRevision; - Microcode = (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicrocodeLength (Microcode)); - } while ((UINTN) Microcode < MicrocodeEnd); + Microcode = (CPU_MICROCODE_HEADER *)(((UINTN)Microcode) + GetMicrocodeLength (Microcode)); + } while ((UINTN)Microcode < MicrocodeEnd); LoadMicrocode: if (LatestRevision != 0) { @@ -97,7 +99,7 @@ LoadMicrocode: // patch header) for each processor even it's the same as the loaded one. // It will be used when building the microcode patch cache HOB. // - CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN) LatestMicrocode; + CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN)LatestMicrocode; } if (LatestRevision > GetProcessorMicrocodeSignature ()) { @@ -109,6 +111,7 @@ LoadMicrocode: // LoadMicrocode (LatestMicrocode); } + // // It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading. // @@ -129,15 +132,15 @@ LoadMicrocode: **/ VOID ShadowMicrocodePatchWorker ( - IN OUT CPU_MP_DATA *CpuMpData, - IN MICROCODE_PATCH_INFO *Patches, - IN UINTN PatchCount, - IN UINTN TotalLoadSize + IN OUT CPU_MP_DATA *CpuMpData, + IN MICROCODE_PATCH_INFO *Patches, + IN UINTN PatchCount, + IN UINTN TotalLoadSize ) { - UINTN Index; - VOID *MicrocodePatchInRam; - UINT8 *Walker; + UINTN Index; + VOID *MicrocodePatchInRam; + UINT8 *Walker; ASSERT ((Patches != NULL) && (PatchCount != 0)); @@ -152,7 +155,7 @@ ShadowMicrocodePatchWorker ( for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) { CopyMem ( Walker, - (VOID *) Patches[Index].Address, + (VOID *)Patches[Index].Address, Patches[Index].Size ); Walker += Patches[Index].Size; @@ -161,13 +164,15 @@ ShadowMicrocodePatchWorker ( // // Update the microcode patch related fields in CpuMpData // - CpuMpData->MicrocodePatchAddress = (UINTN) MicrocodePatchInRam; + CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam; CpuMpData->MicrocodePatchRegionSize = TotalLoadSize; DEBUG (( DEBUG_INFO, "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", - __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize + __FUNCTION__, + CpuMpData->MicrocodePatchAddress, + CpuMpData->MicrocodePatchRegionSize )); return; @@ -181,19 +186,19 @@ ShadowMicrocodePatchWorker ( **/ VOID ShadowMicrocodePatchByPcd ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { - UINTN Index; - CPU_MICROCODE_HEADER *MicrocodeEntryPoint; - UINTN MicrocodeEnd; - UINTN TotalSize; - MICROCODE_PATCH_INFO *PatchInfoBuffer; - UINTN MaxPatchNumber; - UINTN PatchCount; - UINTN TotalLoadSize; - EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds; - BOOLEAN Valid; + UINTN Index; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN MicrocodeEnd; + UINTN TotalSize; + MICROCODE_PATCH_INFO *PatchInfoBuffer; + UINTN MaxPatchNumber; + UINTN PatchCount; + UINTN TotalLoadSize; + EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds; + BOOLEAN Valid; // // Initialize the microcode patch related fields in CpuMpData as the values @@ -203,10 +208,10 @@ ShadowMicrocodePatchByPcd ( CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress); CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize); - MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; - MicrocodeEnd = (UINTN) MicrocodeEntryPoint + - (UINTN) CpuMpData->MicrocodePatchRegionSize; - if ((MicrocodeEntryPoint == NULL) || ((UINTN) MicrocodeEntryPoint == MicrocodeEnd)) { + MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress; + MicrocodeEnd = (UINTN)MicrocodeEntryPoint + + (UINTN)CpuMpData->MicrocodePatchRegionSize; + if ((MicrocodeEntryPoint == NULL) || ((UINTN)MicrocodeEntryPoint == MicrocodeEnd)) { // // There is no microcode patches // @@ -242,7 +247,7 @@ ShadowMicrocodePatchByPcd ( do { Valid = IsValidMicrocode ( MicrocodeEntryPoint, - MicrocodeEnd - (UINTN) MicrocodeEntryPoint, + MicrocodeEnd - (UINTN)MicrocodeEntryPoint, 0, MicrocodeCpuIds, CpuMpData->CpuCount, @@ -252,7 +257,7 @@ ShadowMicrocodePatchByPcd ( // // Padding data between the microcode patches, skip 1KB to check next entry. // - MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB); + MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(((UINTN)MicrocodeEntryPoint) + SIZE_1KB); continue; } @@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd ( if (PatchInfoBuffer == NULL) { goto OnExit; } + MaxPatchNumber = MaxPatchNumber * 2; } @@ -285,21 +291,23 @@ ShadowMicrocodePatchByPcd ( // // Store the information of this microcode patch // - PatchInfoBuffer[PatchCount - 1].Address = (UINTN) MicrocodeEntryPoint; + PatchInfoBuffer[PatchCount - 1].Address = (UINTN)MicrocodeEntryPoint; PatchInfoBuffer[PatchCount - 1].Size = TotalSize; - TotalLoadSize += TotalSize; + TotalLoadSize += TotalSize; // // Process the next microcode patch // - MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEntryPoint + TotalSize); - } while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd); + MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)((UINTN)MicrocodeEntryPoint + TotalSize); + } while ((UINTN)MicrocodeEntryPoint < MicrocodeEnd); if (PatchCount != 0) { DEBUG (( DEBUG_INFO, "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n", - __FUNCTION__, PatchCount, TotalLoadSize + __FUNCTION__, + PatchCount, + TotalLoadSize )); ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize); @@ -309,6 +317,7 @@ OnExit: if (PatchInfoBuffer != NULL) { FreePool (PatchInfoBuffer); } + FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID))); } @@ -319,10 +328,10 @@ OnExit: **/ VOID ShadowMicrocodeUpdatePatch ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = PlatformShadowMicrocode (CpuMpData); if (EFI_ERROR (Status)) { @@ -347,16 +356,16 @@ ShadowMicrocodeUpdatePatch ( **/ BOOLEAN GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize + UINT64 *Address, + UINT64 *RegionSize ) { - EFI_HOB_GUID_TYPE *GuidHob; - EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob; + EFI_HOB_GUID_TYPE *GuidHob; + EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob; GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid); if (GuidHob == NULL) { - DEBUG((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__)); + DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__)); return FALSE; } @@ -365,9 +374,12 @@ GetMicrocodePatchInfoFromHob ( *Address = MicrocodePathHob->MicrocodePatchAddress; *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize; - DEBUG(( - DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", - __FUNCTION__, *Address, *RegionSize + DEBUG (( + DEBUG_INFO, + "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", + __FUNCTION__, + *Address, + *RegionSize )); return TRUE; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index b390c558d4..2d8e9512ab 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -13,8 +13,7 @@ #include #include -EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID; - +EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID; /** The function will check if BSP Execute Disable is enabled. @@ -38,7 +37,7 @@ IsBspExecuteDisableEnabled ( BOOLEAN Enabled; IA32_CR0 Cr0; - Enabled = FALSE; + Enabled = FALSE; Cr0.UintN = AsmReadCr0 (); if (Cr0.Bits.PG != 0) { // @@ -78,12 +77,12 @@ IsBspExecuteDisableEnabled ( VOID EFIAPI FutureBSPProc ( - IN VOID *Buffer + IN VOID *Buffer ) { - CPU_MP_DATA *DataInHob; + CPU_MP_DATA *DataInHob; - DataInHob = (CPU_MP_DATA *) Buffer; + DataInHob = (CPU_MP_DATA *)Buffer; AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo); } @@ -96,7 +95,7 @@ FutureBSPProc ( **/ CPU_STATE GetApState ( - IN CPU_AP_DATA *CpuData + IN CPU_AP_DATA *CpuData ) { return CpuData->State; @@ -110,8 +109,8 @@ GetApState ( **/ VOID SetApState ( - IN CPU_AP_DATA *CpuData, - IN CPU_STATE State + IN CPU_AP_DATA *CpuData, + IN CPU_STATE State ) { AcquireSpinLock (&CpuData->ApLock); @@ -126,7 +125,7 @@ SetApState ( **/ VOID SaveLocalApicTimerSetting ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { // @@ -148,7 +147,7 @@ SaveLocalApicTimerSetting ( **/ VOID SyncLocalApicTimerSetting ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { // @@ -173,10 +172,10 @@ SyncLocalApicTimerSetting ( **/ VOID SaveVolatileRegisters ( - OUT CPU_VOLATILE_REGISTERS *VolatileRegisters + OUT CPU_VOLATILE_REGISTERS *VolatileRegisters ) { - CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; VolatileRegisters->Cr0 = AsmReadCr0 (); VolatileRegisters->Cr3 = AsmReadCr3 (); @@ -210,12 +209,12 @@ SaveVolatileRegisters ( **/ VOID RestoreVolatileRegisters ( - IN CPU_VOLATILE_REGISTERS *VolatileRegisters, - IN BOOLEAN IsRestoreDr + IN CPU_VOLATILE_REGISTERS *VolatileRegisters, + IN BOOLEAN IsRestoreDr ) { - CPUID_VERSION_INFO_EDX VersionInfoEdx; - IA32_TSS_DESCRIPTOR *Tss; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + IA32_TSS_DESCRIPTOR *Tss; AsmWriteCr3 (VolatileRegisters->Cr3); AsmWriteCr4 (VolatileRegisters->Cr4); @@ -239,8 +238,9 @@ RestoreVolatileRegisters ( AsmWriteGdtr (&VolatileRegisters->Gdtr); AsmWriteIdtr (&VolatileRegisters->Idtr); - if (VolatileRegisters->Tr != 0 && - VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { + if ((VolatileRegisters->Tr != 0) && + (VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit)) + { Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + VolatileRegisters->Tr); if (Tss->Bits.P == 1) { @@ -261,7 +261,7 @@ IsMwaitSupport ( VOID ) { - CPUID_VERSION_INFO_ECX VersionInfoEcx; + CPUID_VERSION_INFO_ECX VersionInfoEcx; AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &VersionInfoEcx.Uint32, NULL); return (VersionInfoEcx.Bits.MONITOR == 1) ? TRUE : FALSE; @@ -276,11 +276,11 @@ IsMwaitSupport ( **/ UINT8 GetApLoopMode ( - OUT UINT32 *MonitorFilterSize + OUT UINT32 *MonitorFilterSize ) { - UINT8 ApLoopMode; - CPUID_MONITOR_MWAIT_EBX MonitorMwaitEbx; + UINT8 ApLoopMode; + CPUID_MONITOR_MWAIT_EBX MonitorMwaitEbx; ASSERT (MonitorFilterSize != NULL); @@ -328,20 +328,20 @@ GetApLoopMode ( **/ VOID SortApicId ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - UINTN Index1; - UINTN Index2; - UINTN Index3; - UINT32 ApicId; - CPU_INFO_IN_HOB CpuInfo; - UINT32 ApCount; - CPU_INFO_IN_HOB *CpuInfoInHob; - volatile UINT32 *StartupApSignal; - - ApCount = CpuMpData->CpuCount - 1; - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINT32 ApicId; + CPU_INFO_IN_HOB CpuInfo; + UINT32 ApCount; + CPU_INFO_IN_HOB *CpuInfoInHob; + volatile UINT32 *StartupApSignal; + + ApCount = CpuMpData->CpuCount - 1; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; if (ApCount != 0) { for (Index1 = 0; Index1 < ApCount; Index1++) { Index3 = Index1; @@ -355,6 +355,7 @@ SortApicId ( ApicId = CpuInfoInHob[Index2].ApicId; } } + if (Index3 != Index1) { CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB)); CopyMem ( @@ -367,7 +368,7 @@ SortApicId ( // // Also exchange the StartupApSignal. // - StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal; + StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal; CpuMpData->CpuData[Index3].StartupApSignal = CpuMpData->CpuData[Index1].StartupApSignal; CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal; @@ -380,7 +381,7 @@ SortApicId ( ApicId = GetInitialApicId (); for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) { if (CpuInfoInHob[Index1].ApicId == ApicId) { - CpuMpData->BspNumber = (UINT32) Index1; + CpuMpData->BspNumber = (UINT32)Index1; break; } } @@ -416,8 +417,8 @@ ApInitializeSync ( UINTN ProcessorNumber; EFI_STATUS Status; - CpuMpData = (CPU_MP_DATA *) Buffer; - Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); + CpuMpData = (CPU_MP_DATA *)Buffer; + Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); ASSERT_EFI_ERROR (Status); // // Load microcode on AP @@ -440,20 +441,20 @@ ApInitializeSync ( **/ EFI_STATUS GetProcessorNumber ( - IN CPU_MP_DATA *CpuMpData, - OUT UINTN *ProcessorNumber + IN CPU_MP_DATA *CpuMpData, + OUT UINTN *ProcessorNumber ) { - UINTN TotalProcessorNumber; - UINTN Index; - CPU_INFO_IN_HOB *CpuInfoInHob; - UINT32 CurrentApicId; + UINTN TotalProcessorNumber; + UINTN Index; + CPU_INFO_IN_HOB *CpuInfoInHob; + UINT32 CurrentApicId; - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; TotalProcessorNumber = CpuMpData->CpuCount; - CurrentApicId = GetApicId (); - for (Index = 0; Index < TotalProcessorNumber; Index ++) { + CurrentApicId = GetApicId (); + for (Index = 0; Index < TotalProcessorNumber; Index++) { if (CpuInfoInHob[Index].ApicId == CurrentApicId) { *ProcessorNumber = Index; return EFI_SUCCESS; @@ -472,12 +473,12 @@ GetProcessorNumber ( **/ UINTN CollectProcessorCount ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - UINTN Index; - CPU_INFO_IN_HOB *CpuInfoInHob; - BOOLEAN X2Apic; + UINTN Index; + CPU_INFO_IN_HOB *CpuInfoInHob; + BOOLEAN X2Apic; // // Send 1st broadcast IPI to APs to wakeup APs @@ -504,7 +505,7 @@ CollectProcessorCount ( // X2Apic = TRUE; } else { - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; for (Index = 0; Index < CpuMpData->CpuCount; Index++) { if (CpuInfoInHob[Index].InitialApicId >= 0xFF) { X2Apic = TRUE; @@ -525,6 +526,7 @@ CollectProcessorCount ( while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { CpuPause (); } + // // Enable x2APIC on BSP // @@ -536,6 +538,7 @@ CollectProcessorCount ( SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); } } + DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ())); // // Sort BSP/Aps by CPU APIC ID in ascending order @@ -558,16 +561,16 @@ CollectProcessorCount ( **/ VOID InitializeApData ( - IN OUT CPU_MP_DATA *CpuMpData, - IN UINTN ProcessorNumber, - IN UINT32 BistData, - IN UINT64 ApTopOfStack + IN OUT CPU_MP_DATA *CpuMpData, + IN UINTN ProcessorNumber, + IN UINT32 BistData, + IN UINT64 ApTopOfStack ) { - CPU_INFO_IN_HOB *CpuInfoInHob; - MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + CPU_INFO_IN_HOB *CpuInfoInHob; + MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId (); CpuInfoInHob[ProcessorNumber].ApicId = GetApicId (); CpuInfoInHob[ProcessorNumber].Health = BistData; @@ -580,7 +583,7 @@ InitializeApData ( // NOTE: PlatformId is not relevant on AMD platforms. // if (!StandardSignatureIsAuthenticAMD ()) { - PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId; } @@ -592,7 +595,7 @@ InitializeApData ( NULL ); - InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock); + InitializeSpinLock (&CpuMpData->CpuData[ProcessorNumber].ApLock); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); } @@ -613,18 +616,21 @@ GetProtectedMode16CS ( UINTN GdtEntryCount; UINT16 Index; - Index = (UINT16) -1; + Index = (UINT16)-1; AsmReadGdtr (&GdtrDesc); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); - GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base; for (Index = 0; Index < GdtEntryCount; Index++) { - if (GdtEntry->Bits.L == 0 && - GdtEntry->Bits.DB == 0 && - GdtEntry->Bits.Type > 8) { + if ((GdtEntry->Bits.L == 0) && + (GdtEntry->Bits.DB == 0) && + (GdtEntry->Bits.Type > 8)) + { break; } + GdtEntry++; } + ASSERT (Index != GdtEntryCount); return Index * 8; } @@ -646,18 +652,21 @@ GetProtectedMode32CS ( UINTN GdtEntryCount; UINT16 Index; - Index = (UINT16) -1; + Index = (UINT16)-1; AsmReadGdtr (&GdtrDesc); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); - GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base; for (Index = 0; Index < GdtEntryCount; Index++) { - if (GdtEntry->Bits.L == 0 && - GdtEntry->Bits.DB == 1 && - GdtEntry->Bits.Type > 8) { + if ((GdtEntry->Bits.L == 0) && + (GdtEntry->Bits.DB == 1) && + (GdtEntry->Bits.Type > 8)) + { break; } + GdtEntry++; } + ASSERT (Index != GdtEntryCount); return Index * 8; } @@ -674,16 +683,16 @@ GetProtectedMode32CS ( STATIC VOID MpInitLibSevEsAPReset ( - IN GHCB *Ghcb, - IN CPU_MP_DATA *CpuMpData + IN GHCB *Ghcb, + IN CPU_MP_DATA *CpuMpData ) { - EFI_STATUS Status; - UINTN ProcessorNumber; - UINT16 Code16, Code32; - AP_RESET *APResetFn; - UINTN BufferStart; - UINTN StackStart; + EFI_STATUS Status; + UINTN ProcessorNumber; + UINT16 Code16, Code32; + AP_RESET *APResetFn; + UINTN BufferStart; + UINTN StackStart; Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); ASSERT_EFI_ERROR (Status); @@ -692,14 +701,14 @@ MpInitLibSevEsAPReset ( Code32 = GetProtectedMode32CS (); if (CpuMpData->WakeupBufferHigh != 0) { - APResetFn = (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset); + APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset); } else { - APResetFn = (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset); + APResetFn = (AP_RESET *)(CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset); } BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart; - StackStart = CpuMpData->SevEsAPResetStackStart - - (AP_RESET_STACK_SIZE * ProcessorNumber); + StackStart = CpuMpData->SevEsAPResetStackStart - + (AP_RESET_STACK_SIZE * ProcessorNumber); // // This call never returns. @@ -716,19 +725,19 @@ MpInitLibSevEsAPReset ( VOID EFIAPI ApWakeupFunction ( - IN MP_CPU_EXCHANGE_INFO *ExchangeInfo, - IN UINTN ApIndex + IN MP_CPU_EXCHANGE_INFO *ExchangeInfo, + IN UINTN ApIndex ) { - CPU_MP_DATA *CpuMpData; - UINTN ProcessorNumber; - EFI_AP_PROCEDURE Procedure; - VOID *Parameter; - UINT32 BistData; - volatile UINT32 *ApStartupSignalBuffer; - CPU_INFO_IN_HOB *CpuInfoInHob; - UINT64 ApTopOfStack; - UINTN CurrentApicMode; + CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + EFI_AP_PROCEDURE Procedure; + VOID *Parameter; + UINT32 BistData; + volatile UINT32 *ApStartupSignalBuffer; + CPU_INFO_IN_HOB *CpuInfoInHob; + UINT64 ApTopOfStack; + UINTN CurrentApicMode; // // AP finished assembly code and begin to execute C code @@ -753,8 +762,8 @@ ApWakeupFunction ( // // This is first time AP wakeup, get BIST information from AP stack // - ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize; - BistData = *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN)); + ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize; + BistData = *(UINT32 *)((UINTN)ApTopOfStack - sizeof (UINTN)); // // CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment, // to initialize AP in InitConfig path. @@ -773,7 +782,7 @@ ApWakeupFunction ( // ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal; InterlockedCompareExchange32 ( - (UINT32 *) ApStartupSignalBuffer, + (UINT32 *)ApStartupSignalBuffer, WAKEUP_AP_SIGNAL, 0 ); @@ -788,7 +797,7 @@ ApWakeupFunction ( // different IDT shared by all APs. // RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE); - } else { + } else { if (CpuMpData->ApLoopMode == ApInHltLoop) { // // Restore AP's volatile registers saved before AP is halted @@ -806,7 +815,7 @@ ApWakeupFunction ( if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) { Procedure = (EFI_AP_PROCEDURE)CpuMpData->CpuData[ProcessorNumber].ApFunction; - Parameter = (VOID *) CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument; + Parameter = (VOID *)CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument; if (Procedure != NULL) { SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy); // @@ -817,19 +826,20 @@ ApWakeupFunction ( // Invoke AP function here // Procedure (Parameter); - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; if (CpuMpData->SwitchBspFlag) { // // Re-get the processor number due to BSP/AP maybe exchange in AP function // GetProcessorNumber (CpuMpData, &ProcessorNumber); - CpuMpData->CpuData[ProcessorNumber].ApFunction = 0; + CpuMpData->CpuData[ProcessorNumber].ApFunction = 0; CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument = 0; - ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal; - CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack; + ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal; + CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack; } else { - if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () || - CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) { + if ((CpuInfoInHob[ProcessorNumber].ApicId != GetApicId ()) || + (CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ())) + { if (CurrentApicMode != GetApicMode ()) { // // If APIC mode change happened during AP function execution, @@ -847,6 +857,7 @@ ApWakeupFunction ( } } } + SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished); } } @@ -861,7 +872,7 @@ ApWakeupFunction ( // // AP finished executing C code // - InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount); + InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); if (CpuMpData->InitFlag == ApInitConfig) { // @@ -870,7 +881,7 @@ ApWakeupFunction ( // performs another INIT-SIPI-SIPI sequence. // if (!CpuMpData->SevEsIsEnabled) { - InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting); + InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting); } } @@ -890,11 +901,11 @@ ApWakeupFunction ( BOOLEAN DoDecrement; BOOLEAN InterruptState; - DoDecrement = (BOOLEAN) (CpuMpData->InitFlag == ApInitConfig); + DoDecrement = (BOOLEAN)(CpuMpData->InitFlag == ApInitConfig); while (TRUE) { Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB); - Ghcb = Msr.Ghcb; + Ghcb = Msr.Ghcb; VmgInit (Ghcb, &InterruptState); @@ -905,7 +916,7 @@ ApWakeupFunction ( // Perform the delayed decrement just before issuing the first // VMGEXIT with AP_RESET_HOLD. // - InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting); + InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting); } Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0); @@ -928,16 +939,18 @@ ApWakeupFunction ( } else { CpuSleep (); } + CpuPause (); } } + while (TRUE) { DisableInterrupts (); if (CpuMpData->ApLoopMode == ApInMwaitLoop) { // // Place AP in MWAIT-loop // - AsmMonitor ((UINTN) ApStartupSignalBuffer, 0, 0); + AsmMonitor ((UINTN)ApStartupSignalBuffer, 0, 0); if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) { // // Check AP start-up signal again. @@ -973,7 +986,7 @@ ApWakeupFunction ( **/ VOID WaitApWakeup ( - IN volatile UINT32 *ApStartupSignalBuffer + IN volatile UINT32 *ApStartupSignalBuffer ) { // @@ -981,10 +994,11 @@ WaitApWakeup ( // Otherwise, write StartupApSignal again till AP waken up. // while (InterlockedCompareExchange32 ( - (UINT32 *) ApStartupSignalBuffer, - WAKEUP_AP_SIGNAL, - WAKEUP_AP_SIGNAL - ) != 0) { + (UINT32 *)ApStartupSignalBuffer, + WAKEUP_AP_SIGNAL, + WAKEUP_AP_SIGNAL + ) != 0) + { CpuPause (); } } @@ -997,30 +1011,30 @@ WaitApWakeup ( **/ VOID FillExchangeInfoData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; - UINTN Size; - IA32_SEGMENT_DESCRIPTOR *Selector; - IA32_CR4 Cr4; + volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; + UINTN Size; + IA32_SEGMENT_DESCRIPTOR *Selector; + IA32_CR4 Cr4; - ExchangeInfo = CpuMpData->MpCpuExchangeInfo; - ExchangeInfo->StackStart = CpuMpData->Buffer; - ExchangeInfo->StackSize = CpuMpData->CpuApStackSize; - ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer; - ExchangeInfo->ModeOffset = CpuMpData->AddressMap.ModeEntryOffset; + ExchangeInfo = CpuMpData->MpCpuExchangeInfo; + ExchangeInfo->StackStart = CpuMpData->Buffer; + ExchangeInfo->StackSize = CpuMpData->CpuApStackSize; + ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer; + ExchangeInfo->ModeOffset = CpuMpData->AddressMap.ModeEntryOffset; - ExchangeInfo->CodeSegment = AsmReadCs (); - ExchangeInfo->DataSegment = AsmReadDs (); + ExchangeInfo->CodeSegment = AsmReadCs (); + ExchangeInfo->DataSegment = AsmReadDs (); - ExchangeInfo->Cr3 = AsmReadCr3 (); + ExchangeInfo->Cr3 = AsmReadCr3 (); - ExchangeInfo->CFunction = (UINTN) ApWakeupFunction; + ExchangeInfo->CFunction = (UINTN)ApWakeupFunction; ExchangeInfo->ApIndex = 0; ExchangeInfo->NumApsExecuting = 0; - ExchangeInfo->InitFlag = (UINTN) CpuMpData->InitFlag; - ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + ExchangeInfo->InitFlag = (UINTN)CpuMpData->InitFlag; + ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; ExchangeInfo->CpuMpData = CpuMpData; ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled (); @@ -1035,32 +1049,33 @@ FillExchangeInfoData ( // Using latter way is simpler because it also eliminates the needs to // check whether platform wants to enable it. // - Cr4.UintN = AsmReadCr4 (); - ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); + Cr4.UintN = AsmReadCr4 (); + ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging)); - ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled; - ExchangeInfo->GhcbBase = (UINTN) CpuMpData->GhcbBase; + ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled; + ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase; // // Get the BSP's data of GDT and IDT // - AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile); - AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile); + AsmReadGdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->GdtrProfile); + AsmReadIdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->IdtrProfile); // // Find a 32-bit code segment // Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base; - Size = ExchangeInfo->GdtrProfile.Limit + 1; + Size = ExchangeInfo->GdtrProfile.Limit + 1; while (Size > 0) { - if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) { + if ((Selector->Bits.L == 0) && (Selector->Bits.Type >= 8)) { ExchangeInfo->ModeTransitionSegment = (UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base); break; } + Selector += 1; - Size -= sizeof (IA32_SEGMENT_DESCRIPTOR); + Size -= sizeof (IA32_SEGMENT_DESCRIPTOR); } // @@ -1069,8 +1084,8 @@ FillExchangeInfoData ( // if (CpuMpData->WakeupBufferHigh != 0) { Size = CpuMpData->AddressMap.RendezvousFunnelSize + - CpuMpData->AddressMap.SwitchToRealSize - - CpuMpData->AddressMap.ModeTransitionOffset; + CpuMpData->AddressMap.SwitchToRealSize - + CpuMpData->AddressMap.ModeTransitionOffset; CopyMem ( (VOID *)CpuMpData->WakeupBufferHigh, CpuMpData->AddressMap.RendezvousFunnelAddress + @@ -1081,12 +1096,12 @@ FillExchangeInfoData ( ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh; } else { ExchangeInfo->ModeTransitionMemory = (UINT32) - (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset); + (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset); } ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory + - (UINT32)ExchangeInfo->ModeOffset - - (UINT32)CpuMpData->AddressMap.ModeTransitionOffset; + (UINT32)ExchangeInfo->ModeOffset - + (UINT32)CpuMpData->AddressMap.ModeTransitionOffset; ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment; } @@ -1100,9 +1115,9 @@ FillExchangeInfoData ( **/ VOID TimedWaitForApFinish ( - IN CPU_MP_DATA *CpuMpData, - IN UINT32 FinishedApLimit, - IN UINT32 TimeLimit + IN CPU_MP_DATA *CpuMpData, + IN UINT32 FinishedApLimit, + IN UINT32 TimeLimit ); /** @@ -1111,20 +1126,20 @@ TimedWaitForApFinish ( @param[in] CpuMpData The pointer to CPU MP Data structure. **/ VOID -BackupAndPrepareWakeupBuffer( - IN CPU_MP_DATA *CpuMpData +BackupAndPrepareWakeupBuffer ( + IN CPU_MP_DATA *CpuMpData ) { CopyMem ( - (VOID *) CpuMpData->BackupBuffer, - (VOID *) CpuMpData->WakeupBuffer, + (VOID *)CpuMpData->BackupBuffer, + (VOID *)CpuMpData->WakeupBuffer, CpuMpData->BackupBufferSize ); CopyMem ( - (VOID *) CpuMpData->WakeupBuffer, - (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress, + (VOID *)CpuMpData->WakeupBuffer, + (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress, CpuMpData->AddressMap.RendezvousFunnelSize + - CpuMpData->AddressMap.SwitchToRealSize + CpuMpData->AddressMap.SwitchToRealSize ); } @@ -1134,13 +1149,13 @@ BackupAndPrepareWakeupBuffer( @param[in] CpuMpData The pointer to CPU MP Data structure. **/ VOID -RestoreWakeupBuffer( - IN CPU_MP_DATA *CpuMpData +RestoreWakeupBuffer ( + IN CPU_MP_DATA *CpuMpData ) { CopyMem ( - (VOID *) CpuMpData->WakeupBuffer, - (VOID *) CpuMpData->BackupBuffer, + (VOID *)CpuMpData->WakeupBuffer, + (VOID *)CpuMpData->BackupBuffer, CpuMpData->BackupBufferSize ); } @@ -1161,8 +1176,8 @@ GetApResetVectorSize ( UINTN Size; Size = AddressMap->RendezvousFunnelSize + - AddressMap->SwitchToRealSize + - sizeof (MP_CPU_EXCHANGE_INFO); + AddressMap->SwitchToRealSize + + sizeof (MP_CPU_EXCHANGE_INFO); return Size; } @@ -1174,21 +1189,21 @@ GetApResetVectorSize ( **/ VOID AllocateResetVector ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { - UINTN ApResetVectorSize; - UINTN ApResetStackSize; + UINTN ApResetVectorSize; + UINTN ApResetStackSize; - if (CpuMpData->WakeupBuffer == (UINTN) -1) { + if (CpuMpData->WakeupBuffer == (UINTN)-1) { ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap); CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize); - CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) - (CpuMpData->WakeupBuffer + - CpuMpData->AddressMap.RendezvousFunnelSize + - CpuMpData->AddressMap.SwitchToRealSize); - CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer ( + CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN) + (CpuMpData->WakeupBuffer + + CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize); + CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer ( CpuMpData->AddressMap.RendezvousFunnelSize + CpuMpData->AddressMap.SwitchToRealSize - CpuMpData->AddressMap.ModeTransitionOffset @@ -1228,6 +1243,7 @@ AllocateResetVector ( } } } + BackupAndPrepareWakeupBuffer (CpuMpData); } @@ -1238,7 +1254,7 @@ AllocateResetVector ( **/ VOID FreeResetVector ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { // @@ -1259,10 +1275,10 @@ FreeResetVector ( **/ VOID AllocateSevEsAPMemory ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { - if (CpuMpData->SevEsAPBuffer == (UINTN) -1) { + if (CpuMpData->SevEsAPBuffer == (UINTN)-1) { CpuMpData->SevEsAPBuffer = CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0; } @@ -1278,11 +1294,11 @@ SetSevEsJumpTable ( IN UINTN SipiVector ) { - SEV_ES_AP_JMP_FAR *JmpFar; - UINT32 Offset, InsnByte; - UINT8 LoNib, HiNib; + SEV_ES_AP_JMP_FAR *JmpFar; + UINT32 Offset, InsnByte; + UINT8 LoNib, HiNib; - JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase); + JmpFar = (SEV_ES_AP_JMP_FAR *)(UINTN)FixedPcdGet32 (PcdSevEsWorkAreaBase); ASSERT (JmpFar != NULL); // @@ -1290,10 +1306,10 @@ SetSevEsJumpTable ( // This will be set to a value derived from the SIPI vector and will // be the memory address used for the far jump below. // - Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase); + Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase); Offset += sizeof (JmpFar->InsnBuffer); - LoNib = (UINT8) Offset; - HiNib = (UINT8) (Offset >> 8); + LoNib = (UINT8)Offset; + HiNib = (UINT8)(Offset >> 8); // // Program the workarea (which is the initial AP boot address) with @@ -1302,7 +1318,7 @@ SetSevEsJumpTable ( // // JMP FAR [CS:XXYY] => 2E FF 2E YY XX // - InsnByte = 0; + InsnByte = 0; JmpFar->InsnBuffer[InsnByte++] = 0x2E; // CS override prefix JmpFar->InsnBuffer[InsnByte++] = 0xFF; // JMP (FAR) JmpFar->InsnBuffer[InsnByte++] = 0x2E; // ModRM (JMP memory location) @@ -1313,8 +1329,8 @@ SetSevEsJumpTable ( // Program the Segment/Rip based on the SIPI vector (always at least // 16-byte aligned, so Rip is set to 0). // - JmpFar->Rip = 0; - JmpFar->Segment = (UINT16) (SipiVector >> 4); + JmpFar->Rip = 0; + JmpFar->Segment = (UINT16)(SipiVector >> 4); } /** @@ -1330,25 +1346,26 @@ SetSevEsJumpTable ( **/ VOID WakeUpAP ( - IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN Broadcast, - IN UINTN ProcessorNumber, - IN EFI_AP_PROCEDURE Procedure OPTIONAL, - IN VOID *ProcedureArgument OPTIONAL, - IN BOOLEAN WakeUpDisabledAps + IN CPU_MP_DATA *CpuMpData, + IN BOOLEAN Broadcast, + IN UINTN ProcessorNumber, + IN EFI_AP_PROCEDURE Procedure OPTIONAL, + IN VOID *ProcedureArgument OPTIONAL, + IN BOOLEAN WakeUpDisabledAps ) { - volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; - UINTN Index; - CPU_AP_DATA *CpuData; - BOOLEAN ResetVectorRequired; - CPU_INFO_IN_HOB *CpuInfoInHob; + volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; + UINTN Index; + CPU_AP_DATA *CpuData; + BOOLEAN ResetVectorRequired; + CPU_INFO_IN_HOB *CpuInfoInHob; CpuMpData->FinishedCount = 0; - ResetVectorRequired = FALSE; + ResetVectorRequired = FALSE; if (CpuMpData->WakeUpByInitSipiSipi || - CpuMpData->InitFlag != ApInitDone) { + (CpuMpData->InitFlag != ApInitDone)) + { ResetVectorRequired = TRUE; AllocateResetVector (CpuMpData); AllocateSevEsAPMemory (CpuMpData); @@ -1375,18 +1392,19 @@ WakeUpAP ( // the AP procedure will be skipped for disabled AP because AP state // is not CpuStateReady. // - if (GetApState (CpuData) == CpuStateDisabled && !WakeUpDisabledAps) { + if ((GetApState (CpuData) == CpuStateDisabled) && !WakeUpDisabledAps) { continue; } - CpuData->ApFunction = (UINTN) Procedure; - CpuData->ApFunctionArgument = (UINTN) ProcedureArgument; + CpuData->ApFunction = (UINTN)Procedure; + CpuData->ApFunctionArgument = (UINTN)ProcedureArgument; SetApState (CpuData, CpuStateReady); if (CpuMpData->InitFlag != ApInitConfig) { - *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; + *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; } } } + if (ResetVectorRequired) { // // For SEV-ES, the initial AP boot address will be defined by @@ -1400,8 +1418,9 @@ WakeUpAP ( // // Wakeup all APs // - SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart); + SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart); } + if (CpuMpData->InitFlag == ApInitConfig) { if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) { // @@ -1462,7 +1481,7 @@ WakeUpAP ( ); while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) { - CpuPause(); + CpuPause (); } } } else { @@ -1477,17 +1496,17 @@ WakeUpAP ( } } } else { - CpuData = &CpuMpData->CpuData[ProcessorNumber]; - CpuData->ApFunction = (UINTN) Procedure; - CpuData->ApFunctionArgument = (UINTN) ProcedureArgument; + CpuData = &CpuMpData->CpuData[ProcessorNumber]; + CpuData->ApFunction = (UINTN)Procedure; + CpuData->ApFunctionArgument = (UINTN)ProcedureArgument; SetApState (CpuData, CpuStateReady); // // Wakeup specified AP // ASSERT (CpuMpData->InitFlag != ApInitConfig); - *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; + *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; if (ResetVectorRequired) { - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; // // For SEV-ES, the initial AP boot address will be defined by @@ -1500,9 +1519,10 @@ WakeUpAP ( SendInitSipiSipi ( CpuInfoInHob[ProcessorNumber].ApicId, - (UINT32) ExchangeInfo->BufferStart + (UINT32)ExchangeInfo->BufferStart ); } + // // Wait specified AP waken up // @@ -1542,8 +1562,8 @@ CalculateTimeout ( OUT UINT64 *CurrentTime ) { - UINT64 TimeoutInSeconds; - UINT64 TimestampCounterFreq; + UINT64 TimeoutInSeconds; + UINT64 TimestampCounterFreq; // // Read the current value of the performance counter @@ -1628,25 +1648,30 @@ CheckTimeout ( if (Timeout == 0) { return FALSE; } + GetPerformanceCounterProperties (&Start, &End); Cycle = End - Start; if (Cycle < 0) { Cycle = -Cycle; } + Cycle++; - CurrentTime = GetPerformanceCounter(); - Delta = (INT64) (CurrentTime - *PreviousTime); + CurrentTime = GetPerformanceCounter (); + Delta = (INT64)(CurrentTime - *PreviousTime); if (Start > End) { Delta = -Delta; } + if (Delta < 0) { Delta += Cycle; } - *TotalTime += Delta; + + *TotalTime += Delta; *PreviousTime = CurrentTime; if (*TotalTime > Timeout) { return TRUE; } + return FALSE; } @@ -1660,9 +1685,9 @@ CheckTimeout ( **/ VOID TimedWaitForApFinish ( - IN CPU_MP_DATA *CpuMpData, - IN UINT32 FinishedApLimit, - IN UINT32 TimeLimit + IN CPU_MP_DATA *CpuMpData, + IN UINT32 FinishedApLimit, + IN UINT32 TimeLimit ) { // @@ -1673,7 +1698,7 @@ TimedWaitForApFinish ( return; } - CpuMpData->TotalTime = 0; + CpuMpData->TotalTime = 0; CpuMpData->ExpectedTime = CalculateTimeout ( TimeLimit, &CpuMpData->CurrentTime @@ -1683,7 +1708,8 @@ TimedWaitForApFinish ( &CpuMpData->CurrentTime, &CpuMpData->TotalTime, CpuMpData->ExpectedTime - )) { + )) + { CpuPause (); } @@ -1712,10 +1738,10 @@ TimedWaitForApFinish ( **/ VOID ResetProcessorToIdleState ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - CPU_MP_DATA *CpuMpData; + CPU_MP_DATA *CpuMpData; CpuMpData = GetCpuMpData (); @@ -1724,6 +1750,7 @@ ResetProcessorToIdleState ( while (CpuMpData->FinishedCount < 1) { CpuPause (); } + CpuMpData->InitFlag = ApInitDone; SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); @@ -1742,11 +1769,11 @@ ResetProcessorToIdleState ( **/ EFI_STATUS GetNextWaitingProcessorNumber ( - OUT UINTN *NextProcessorNumber + OUT UINTN *NextProcessorNumber ) { - UINTN ProcessorNumber; - CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + CPU_MP_DATA *CpuMpData; CpuMpData = GetCpuMpData (); @@ -1773,11 +1800,11 @@ GetNextWaitingProcessorNumber ( **/ EFI_STATUS CheckThisAP ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - CPU_MP_DATA *CpuMpData; - CPU_AP_DATA *CpuData; + CPU_MP_DATA *CpuMpData; + CPU_AP_DATA *CpuData; CpuMpData = GetCpuMpData (); CpuData = &CpuMpData->CpuData[ProcessorNumber]; @@ -1790,10 +1817,11 @@ CheckThisAP ( // // If the AP finishes for StartupThisAP(), return EFI_SUCCESS. // - if (GetApState(CpuData) == CpuStateFinished) { + if (GetApState (CpuData) == CpuStateFinished) { if (CpuData->Finished != NULL) { *(CpuData->Finished) = TRUE; } + SetApState (CpuData, CpuStateIdle); return EFI_SUCCESS; } else { @@ -1804,6 +1832,7 @@ CheckThisAP ( if (CpuData->Finished != NULL) { *(CpuData->Finished) = FALSE; } + // // Reset failed AP to idle state // @@ -1812,6 +1841,7 @@ CheckThisAP ( return EFI_TIMEOUT; } } + return EFI_NOT_READY; } @@ -1830,12 +1860,12 @@ CheckAllAPs ( VOID ) { - UINTN ProcessorNumber; - UINTN NextProcessorNumber; - UINTN ListIndex; - EFI_STATUS Status; - CPU_MP_DATA *CpuMpData; - CPU_AP_DATA *CpuData; + UINTN ProcessorNumber; + UINTN NextProcessorNumber; + UINTN ListIndex; + EFI_STATUS Status; + CPU_MP_DATA *CpuMpData; + CPU_AP_DATA *CpuData; CpuMpData = GetCpuMpData (); @@ -1855,10 +1885,10 @@ CheckAllAPs ( // Only BSP and corresponding AP access this unit of CPU Data. This means the AP will not modify the // value of state after setting the it to CpuStateIdle, so BSP can safely make use of its value. // - if (GetApState(CpuData) == CpuStateFinished) { - CpuMpData->RunningCount --; + if (GetApState (CpuData) == CpuStateFinished) { + CpuMpData->RunningCount--; CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE; - SetApState(CpuData, CpuStateIdle); + SetApState (CpuData, CpuStateIdle); // // If in Single Thread mode, then search for the next waiting AP for execution. @@ -1870,12 +1900,12 @@ CheckAllAPs ( WakeUpAP ( CpuMpData, FALSE, - (UINT32) NextProcessorNumber, + (UINT32)NextProcessorNumber, CpuMpData->Procedure, CpuMpData->ProcArguments, TRUE ); - } + } } } } @@ -1891,18 +1921,21 @@ CheckAllAPs ( // If timeout expires, report timeout. // if (CheckTimeout ( - &CpuMpData->CurrentTime, - &CpuMpData->TotalTime, - CpuMpData->ExpectedTime) - ) { + &CpuMpData->CurrentTime, + &CpuMpData->TotalTime, + CpuMpData->ExpectedTime + ) + ) + { // // If FailedCpuList is not NULL, record all failed APs in it. // if (CpuMpData->FailedCpuList != NULL) { *CpuMpData->FailedCpuList = - AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN)); + AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN)); ASSERT (*CpuMpData->FailedCpuList != NULL); } + ListIndex = 0; for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) { @@ -1920,11 +1953,14 @@ CheckAllAPs ( } } } + if (CpuMpData->FailedCpuList != NULL) { (*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST; } + return EFI_TIMEOUT; } + return EFI_NOT_READY; } @@ -1967,16 +2003,17 @@ MpInitLibInitialize ( OldCpuMpData = GetCpuMpDataFromGuidedHob (); if (OldCpuMpData == NULL) { - MaxLogicalProcessorNumber = PcdGet32(PcdCpuMaxLogicalProcessorNumber); + MaxLogicalProcessorNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber); } else { MaxLogicalProcessorNumber = OldCpuMpData->CpuCount; } + ASSERT (MaxLogicalProcessorNumber != 0); AsmGetAddressMap (&AddressMap); ApResetVectorSize = GetApResetVectorSize (&AddressMap); - ApStackSize = PcdGet32(PcdCpuApStackSize); - ApLoopMode = GetApLoopMode (&MonitorFilterSize); + ApStackSize = PcdGet32 (PcdCpuApStackSize); + ApLoopMode = GetApLoopMode (&MonitorFilterSize); // // Save BSP's Control registers for APs. @@ -1993,7 +2030,7 @@ MpInitLibInitialize ( MpBuffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); ASSERT (MpBuffer != NULL); ZeroMem (MpBuffer, BufferSize); - Buffer = (UINTN) MpBuffer; + Buffer = (UINTN)MpBuffer; // // The layout of the Buffer is as below: @@ -2016,31 +2053,33 @@ MpInitLibInitialize ( // CPU_INFO_IN_HOB (N) // +--------------------+ // - MonitorBuffer = (UINT8 *) (Buffer + ApStackSize * MaxLogicalProcessorNumber); - BackupBufferAddr = (UINTN) MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber; - ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8); - CpuMpData = (CPU_MP_DATA *) (ApIdtBase + VolatileRegisters.Idtr.Limit + 1); + MonitorBuffer = (UINT8 *)(Buffer + ApStackSize * MaxLogicalProcessorNumber); + BackupBufferAddr = (UINTN)MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber; + ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8); + CpuMpData = (CPU_MP_DATA *)(ApIdtBase + VolatileRegisters.Idtr.Limit + 1); CpuMpData->Buffer = Buffer; CpuMpData->CpuApStackSize = ApStackSize; CpuMpData->BackupBuffer = BackupBufferAddr; CpuMpData->BackupBufferSize = ApResetVectorSize; - CpuMpData->WakeupBuffer = (UINTN) -1; + CpuMpData->WakeupBuffer = (UINTN)-1; CpuMpData->CpuCount = 1; CpuMpData->BspNumber = 0; CpuMpData->WaitEvent = NULL; CpuMpData->SwitchBspFlag = FALSE; - CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1); - CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber); - InitializeSpinLock(&CpuMpData->MpLock); + CpuMpData->CpuData = (CPU_AP_DATA *)(CpuMpData + 1); + CpuMpData->CpuInfoInHob = (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber); + InitializeSpinLock (&CpuMpData->MpLock); CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled); - CpuMpData->SevEsAPBuffer = (UINTN) -1; + CpuMpData->SevEsAPBuffer = (UINTN)-1; CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase); // // Make sure no memory usage outside of the allocated buffer. // - ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) == - Buffer + BufferSize); + ASSERT ( + (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) == + Buffer + BufferSize + ); // // Duplicate BSP's IDT to APs. @@ -2076,6 +2115,7 @@ MpInitLibInitialize ( CpuMpData->CpuData[Index].StartupApSignal = (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index); } + // // Enable the local APIC for Virtual Wire Mode. // @@ -2094,13 +2134,13 @@ MpInitLibInitialize ( // from HOB // OldCpuMpData->NewCpuMpData = CpuMpData; - CpuMpData->CpuCount = OldCpuMpData->CpuCount; - CpuMpData->BspNumber = OldCpuMpData->BspNumber; - CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob; - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuMpData->CpuCount = OldCpuMpData->CpuCount; + CpuMpData->BspNumber = OldCpuMpData->BspNumber; + CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob; + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; for (Index = 0; Index < CpuMpData->CpuCount; Index++) { - InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock); - CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE; + InitializeSpinLock (&CpuMpData->CpuData[Index].ApLock); + CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0) ? TRUE : FALSE; CpuMpData->CpuData[Index].ApFunction = 0; } } @@ -2108,7 +2148,8 @@ MpInitLibInitialize ( if (!GetMicrocodePatchInfoFromHob ( &CpuMpData->MicrocodePatchAddress, &CpuMpData->MicrocodePatchRegionSize - )) { + )) + { // // The microcode patch information cache HOB does not exist, which means // the microcode patches data has not been loaded into memory yet @@ -2137,6 +2178,7 @@ MpInitLibInitialize ( // CpuMpData->InitFlag = ApInitReconfig; } + WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); // // Wait for all APs finished initialization @@ -2144,9 +2186,11 @@ MpInitLibInitialize ( while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { CpuPause (); } + if (OldCpuMpData != NULL) { CpuMpData->InitFlag = ApInitDone; } + for (Index = 0; Index < CpuMpData->CpuCount; Index++) { SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); } @@ -2156,26 +2200,32 @@ MpInitLibInitialize ( // Dump the microcode revision for each core. // DEBUG_CODE_BEGIN (); - UINT32 ThreadId; - UINT32 ExpectedMicrocodeRevision; - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; - for (Index = 0; Index < CpuMpData->CpuCount; Index++) { - GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId); - if (ThreadId == 0) { - // - // MicrocodeDetect() loads microcode in first thread of each core, so, - // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core. - // - ExpectedMicrocodeRevision = 0; - if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) { - ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision; - } - DEBUG (( - DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n", - Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision - )); + UINT32 ThreadId; + UINT32 ExpectedMicrocodeRevision; + + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; + for (Index = 0; Index < CpuMpData->CpuCount; Index++) { + GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId); + if (ThreadId == 0) { + // + // MicrocodeDetect() loads microcode in first thread of each core, so, + // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core. + // + ExpectedMicrocodeRevision = 0; + if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) { + ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision; } + + DEBUG (( + DEBUG_INFO, + "CPU[%04d]: Microcode revision = %08x, expected = %08x\n", + Index, + CpuMpData->CpuData[Index].MicrocodeRevision, + ExpectedMicrocodeRevision + )); } + } + DEBUG_CODE_END (); // // Initialize global data for MP support @@ -2210,19 +2260,19 @@ MpInitLibGetProcessorInfo ( OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL ) { - CPU_MP_DATA *CpuMpData; - UINTN CallerNumber; - CPU_INFO_IN_HOB *CpuInfoInHob; - UINTN OriginalProcessorNumber; + CPU_MP_DATA *CpuMpData; + UINTN CallerNumber; + CPU_INFO_IN_HOB *CpuInfoInHob; + UINTN OriginalProcessorNumber; - CpuMpData = GetCpuMpData (); - CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + CpuMpData = GetCpuMpData (); + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; // // Lower 24 bits contains the actual processor number. // OriginalProcessorNumber = ProcessorNumber; - ProcessorNumber &= BIT24 - 1; + ProcessorNumber &= BIT24 - 1; // // Check whether caller processor is BSP @@ -2240,14 +2290,16 @@ MpInitLibGetProcessorInfo ( return EFI_NOT_FOUND; } - ProcessorInfoBuffer->ProcessorId = (UINT64) CpuInfoInHob[ProcessorNumber].ApicId; + ProcessorInfoBuffer->ProcessorId = (UINT64)CpuInfoInHob[ProcessorNumber].ApicId; ProcessorInfoBuffer->StatusFlag = 0; if (ProcessorNumber == CpuMpData->BspNumber) { ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; } + if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) { ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT; } + if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) { ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT; } else { @@ -2296,8 +2348,8 @@ MpInitLibGetProcessorInfo ( **/ EFI_STATUS SwitchBSPWorker ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ) { CPU_MP_DATA *CpuMpData; @@ -2370,7 +2422,7 @@ SwitchBSPWorker ( // // Clear the BSP bit of MSR_IA32_APIC_BASE // - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.BSP = 0; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); @@ -2384,7 +2436,7 @@ SwitchBSPWorker ( // // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP // - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.BSP = 1; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); ProgramVirtualWireMode (); @@ -2405,10 +2457,11 @@ SwitchBSPWorker ( } else { SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle); } + // // Save new BSP number // - CpuMpData->BspNumber = (UINT32) ProcessorNumber; + CpuMpData->BspNumber = (UINT32)ProcessorNumber; // // Restore interrupt state. @@ -2438,13 +2491,13 @@ SwitchBSPWorker ( **/ EFI_STATUS EnableDisableApWorker ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { - CPU_MP_DATA *CpuMpData; - UINTN CallerNumber; + CPU_MP_DATA *CpuMpData; + UINTN CallerNumber; CpuMpData = GetCpuMpData (); @@ -2472,7 +2525,7 @@ EnableDisableApWorker ( if (HealthFlag != NULL) { CpuMpData->CpuData[ProcessorNumber].CpuHealthy = - (BOOLEAN) ((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0); + (BOOLEAN)((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0); } return EFI_SUCCESS; @@ -2497,10 +2550,10 @@ EnableDisableApWorker ( EFI_STATUS EFIAPI MpInitLibWhoAmI ( - OUT UINTN *ProcessorNumber + OUT UINTN *ProcessorNumber ) { - CPU_MP_DATA *CpuMpData; + CPU_MP_DATA *CpuMpData; if (ProcessorNumber == NULL) { return EFI_INVALID_PARAMETER; @@ -2534,15 +2587,15 @@ MpInitLibWhoAmI ( EFI_STATUS EFIAPI MpInitLibGetNumberOfProcessors ( - OUT UINTN *NumberOfProcessors OPTIONAL, - OUT UINTN *NumberOfEnabledProcessors OPTIONAL + OUT UINTN *NumberOfProcessors OPTIONAL, + OUT UINTN *NumberOfEnabledProcessors OPTIONAL ) { - CPU_MP_DATA *CpuMpData; - UINTN CallerNumber; - UINTN ProcessorNumber; - UINTN EnabledProcessorNumber; - UINTN Index; + CPU_MP_DATA *CpuMpData; + UINTN CallerNumber; + UINTN ProcessorNumber; + UINTN EnabledProcessorNumber; + UINTN Index; CpuMpData = GetCpuMpData (); @@ -2562,13 +2615,14 @@ MpInitLibGetNumberOfProcessors ( EnabledProcessorNumber = 0; for (Index = 0; Index < ProcessorNumber; Index++) { if (GetApState (&CpuMpData->CpuData[Index]) != CpuStateDisabled) { - EnabledProcessorNumber ++; + EnabledProcessorNumber++; } } if (NumberOfProcessors != NULL) { *NumberOfProcessors = ProcessorNumber; } + if (NumberOfEnabledProcessors != NULL) { *NumberOfEnabledProcessors = EnabledProcessorNumber; } @@ -2576,7 +2630,6 @@ MpInitLibGetNumberOfProcessors ( return EFI_SUCCESS; } - /** Worker function to execute a caller provided function on all enabled APs. @@ -2611,23 +2664,23 @@ MpInitLibGetNumberOfProcessors ( **/ EFI_STATUS StartupAllCPUsWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN BOOLEAN ExcludeBsp, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN BOOLEAN ExcludeBsp, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ) { - EFI_STATUS Status; - CPU_MP_DATA *CpuMpData; - UINTN ProcessorCount; - UINTN ProcessorNumber; - UINTN CallerNumber; - CPU_AP_DATA *CpuData; - BOOLEAN HasEnabledAp; - CPU_STATE ApState; + EFI_STATUS Status; + CPU_MP_DATA *CpuMpData; + UINTN ProcessorCount; + UINTN ProcessorNumber; + UINTN CallerNumber; + CPU_AP_DATA *CpuData; + BOOLEAN HasEnabledAp; + CPU_STATE ApState; CpuMpData = GetCpuMpData (); @@ -2635,7 +2688,7 @@ StartupAllCPUsWorker ( *FailedCpuList = NULL; } - if (CpuMpData->CpuCount == 1 && ExcludeBsp) { + if ((CpuMpData->CpuCount == 1) && ExcludeBsp) { return EFI_NOT_STARTED; } @@ -2687,7 +2740,7 @@ StartupAllCPUsWorker ( CpuMpData->RunningCount = 0; for (ProcessorNumber = 0; ProcessorNumber < ProcessorCount; ProcessorNumber++) { - CpuData = &CpuMpData->CpuData[ProcessorNumber]; + CpuData = &CpuMpData->CpuData[ProcessorNumber]; CpuData->Waiting = FALSE; if (ProcessorNumber != CpuMpData->BspNumber) { if (CpuData->State == CpuStateIdle) { @@ -2709,8 +2762,8 @@ StartupAllCPUsWorker ( TimeoutInMicroseconds, &CpuMpData->CurrentTime ); - CpuMpData->TotalTime = 0; - CpuMpData->WaitEvent = WaitEvent; + CpuMpData->TotalTime = 0; + CpuMpData->WaitEvent = WaitEvent; if (!SingleThread) { WakeUpAP (CpuMpData, TRUE, 0, Procedure, ProcedureArgument, FALSE); @@ -2719,6 +2772,7 @@ StartupAllCPUsWorker ( if (ProcessorNumber == CallerNumber) { continue; } + if (CpuMpData->CpuData[ProcessorNumber].Waiting) { WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE); break; @@ -2768,18 +2822,18 @@ StartupAllCPUsWorker ( **/ EFI_STATUS StartupThisAPWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ) { - EFI_STATUS Status; - CPU_MP_DATA *CpuMpData; - CPU_AP_DATA *CpuData; - UINTN CallerNumber; + EFI_STATUS Status; + CPU_MP_DATA *CpuMpData; + CPU_AP_DATA *CpuData; + UINTN CallerNumber; CpuMpData = GetCpuMpData (); @@ -2833,7 +2887,7 @@ StartupThisAPWorker ( // BSP saves data for CheckAPsStatus(), and returns EFI_SUCCESS. // CheckAPsStatus() will check completion and timeout periodically. // - CpuData = &CpuMpData->CpuData[ProcessorNumber]; + CpuData = &CpuMpData->CpuData[ProcessorNumber]; CpuData->WaitEvent = WaitEvent; CpuData->Finished = Finished; CpuData->ExpectedTime = CalculateTimeout (TimeoutInMicroseconds, &CpuData->CurrentTime); @@ -2865,16 +2919,17 @@ GetCpuMpDataFromGuidedHob ( VOID ) { - EFI_HOB_GUID_TYPE *GuidHob; - VOID *DataInHob; - CPU_MP_DATA *CpuMpData; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *DataInHob; + CPU_MP_DATA *CpuMpData; CpuMpData = NULL; - GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid); + GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid); if (GuidHob != NULL) { DataInHob = GET_GUID_HOB_DATA (GuidHob); - CpuMpData = (CPU_MP_DATA *) (*(UINTN *) DataInHob); + CpuMpData = (CPU_MP_DATA *)(*(UINTN *)DataInHob); } + return CpuMpData; } @@ -2907,9 +2962,9 @@ GetCpuMpDataFromGuidedHob ( EFI_STATUS EFIAPI MpInitLibStartupAllCPUs ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ) { return StartupAllCPUsWorker ( diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 98a207c628..a647772088 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -36,7 +36,7 @@ #include -#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P') +#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P') #define CPU_INIT_MP_LIB_HOB_GUID \ { \ @@ -46,14 +46,14 @@ // // The MP data for switch BSP // -#define CPU_SWITCH_STATE_IDLE 0 -#define CPU_SWITCH_STATE_STORED 1 -#define CPU_SWITCH_STATE_LOADED 2 +#define CPU_SWITCH_STATE_IDLE 0 +#define CPU_SWITCH_STATE_STORED 1 +#define CPU_SWITCH_STATE_LOADED 2 // // Default maximum number of entries to store the microcode patches information // -#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 +#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 // // Data structure for microcode patch information @@ -67,10 +67,10 @@ typedef struct { // CPU exchange information for switch BSP // typedef struct { - UINT8 State; // offset 0 - UINTN StackPointer; // offset 4 / 8 - IA32_DESCRIPTOR Gdtr; // offset 8 / 16 - IA32_DESCRIPTOR Idtr; // offset 14 / 26 + UINT8 State; // offset 0 + UINTN StackPointer; // offset 4 / 8 + IA32_DESCRIPTOR Gdtr; // offset 8 / 16 + IA32_DESCRIPTOR Idtr; // offset 14 / 26 } CPU_EXCHANGE_ROLE_INFO; // @@ -111,41 +111,41 @@ typedef enum { // CPU volatile registers around INIT-SIPI-SIPI // typedef struct { - UINTN Cr0; - UINTN Cr3; - UINTN Cr4; - UINTN Dr0; - UINTN Dr1; - UINTN Dr2; - UINTN Dr3; - UINTN Dr6; - UINTN Dr7; - IA32_DESCRIPTOR Gdtr; - IA32_DESCRIPTOR Idtr; - UINT16 Tr; + UINTN Cr0; + UINTN Cr3; + UINTN Cr4; + UINTN Dr0; + UINTN Dr1; + UINTN Dr2; + UINTN Dr3; + UINTN Dr6; + UINTN Dr7; + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + UINT16 Tr; } CPU_VOLATILE_REGISTERS; // // AP related data // typedef struct { - SPIN_LOCK ApLock; - volatile UINT32 *StartupApSignal; - volatile UINTN ApFunction; - volatile UINTN ApFunctionArgument; - BOOLEAN CpuHealthy; - volatile CPU_STATE State; - CPU_VOLATILE_REGISTERS VolatileRegisters; - BOOLEAN Waiting; - BOOLEAN *Finished; - UINT64 ExpectedTime; - UINT64 CurrentTime; - UINT64 TotalTime; - EFI_EVENT WaitEvent; - UINT32 ProcessorSignature; - UINT8 PlatformId; - UINT64 MicrocodeEntryAddr; - UINT32 MicrocodeRevision; + SPIN_LOCK ApLock; + volatile UINT32 *StartupApSignal; + volatile UINTN ApFunction; + volatile UINTN ApFunctionArgument; + BOOLEAN CpuHealthy; + volatile CPU_STATE State; + CPU_VOLATILE_REGISTERS VolatileRegisters; + BOOLEAN Waiting; + BOOLEAN *Finished; + UINT64 ExpectedTime; + UINT64 CurrentTime; + UINT64 TotalTime; + EFI_EVENT WaitEvent; + UINT32 ProcessorSignature; + UINT8 PlatformId; + UINT64 MicrocodeEntryAddr; + UINT32 MicrocodeRevision; } CPU_AP_DATA; // @@ -156,10 +156,10 @@ typedef struct { // #pragma pack (1) typedef struct { - UINT32 InitialApicId; - UINT32 ApicId; - UINT32 Health; - UINT64 ApTopOfStack; + UINT32 InitialApicId; + UINT32 ApicId; + UINT32 Health; + UINT64 ApTopOfStack; } CPU_INFO_IN_HOB; #pragma pack () @@ -169,20 +169,20 @@ typedef struct { // It is natural aligned by design. // typedef struct { - UINT8 *RendezvousFunnelAddress; - UINTN ModeEntryOffset; - UINTN RendezvousFunnelSize; - UINT8 *RelocateApLoopFuncAddress; - UINTN RelocateApLoopFuncSize; - UINTN ModeTransitionOffset; - UINTN SwitchToRealSize; - UINTN SwitchToRealOffset; - UINTN SwitchToRealNoNxOffset; - UINTN SwitchToRealPM16ModeOffset; - UINTN SwitchToRealPM16ModeSize; + UINT8 *RendezvousFunnelAddress; + UINTN ModeEntryOffset; + UINTN RendezvousFunnelSize; + UINT8 *RelocateApLoopFuncAddress; + UINTN RelocateApLoopFuncSize; + UINTN ModeTransitionOffset; + UINTN SwitchToRealSize; + UINTN SwitchToRealOffset; + UINTN SwitchToRealNoNxOffset; + UINTN SwitchToRealPM16ModeOffset; + UINTN SwitchToRealPM16ModeSize; } MP_ASSEMBLY_ADDRESS_MAP; -typedef struct _CPU_MP_DATA CPU_MP_DATA; +typedef struct _CPU_MP_DATA CPU_MP_DATA; #pragma pack(1) @@ -192,33 +192,33 @@ typedef struct _CPU_MP_DATA CPU_MP_DATA; // into this structure are used in assembly code in this module // typedef struct { - UINTN StackStart; - UINTN StackSize; - UINTN CFunction; - IA32_DESCRIPTOR GdtrProfile; - IA32_DESCRIPTOR IdtrProfile; - UINTN BufferStart; - UINTN ModeOffset; - UINTN ApIndex; - UINTN CodeSegment; - UINTN DataSegment; - UINTN EnableExecuteDisable; - UINTN Cr3; - UINTN InitFlag; - CPU_INFO_IN_HOB *CpuInfo; - UINTN NumApsExecuting; - CPU_MP_DATA *CpuMpData; - UINTN InitializeFloatingPointUnitsAddress; - UINT32 ModeTransitionMemory; - UINT16 ModeTransitionSegment; - UINT32 ModeHighMemory; - UINT16 ModeHighSegment; + UINTN StackStart; + UINTN StackSize; + UINTN CFunction; + IA32_DESCRIPTOR GdtrProfile; + IA32_DESCRIPTOR IdtrProfile; + UINTN BufferStart; + UINTN ModeOffset; + UINTN ApIndex; + UINTN CodeSegment; + UINTN DataSegment; + UINTN EnableExecuteDisable; + UINTN Cr3; + UINTN InitFlag; + CPU_INFO_IN_HOB *CpuInfo; + UINTN NumApsExecuting; + CPU_MP_DATA *CpuMpData; + UINTN InitializeFloatingPointUnitsAddress; + UINT32 ModeTransitionMemory; + UINT16 ModeTransitionSegment; + UINT32 ModeHighMemory; + UINT16 ModeHighSegment; // // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode. // - BOOLEAN Enable5LevelPaging; - BOOLEAN SevEsIsEnabled; - UINTN GhcbBase; + BOOLEAN Enable5LevelPaging; + BOOLEAN SevEsIsEnabled; + UINTN GhcbBase; } MP_CPU_EXCHANGE_INFO; #pragma pack() @@ -227,55 +227,55 @@ typedef struct { // CPU MP Data save in memory // struct _CPU_MP_DATA { - UINT64 CpuInfoInHob; - UINT32 CpuCount; - UINT32 BspNumber; + UINT64 CpuInfoInHob; + UINT32 CpuCount; + UINT32 BspNumber; // // The above fields data will be passed from PEI to DXE // Please make sure the fields offset same in the different // architecture. // - SPIN_LOCK MpLock; - UINTN Buffer; - UINTN CpuApStackSize; - MP_ASSEMBLY_ADDRESS_MAP AddressMap; - UINTN WakeupBuffer; - UINTN WakeupBufferHigh; - UINTN BackupBuffer; - UINTN BackupBufferSize; - - volatile UINT32 FinishedCount; - UINT32 RunningCount; - BOOLEAN SingleThread; - EFI_AP_PROCEDURE Procedure; - VOID *ProcArguments; - BOOLEAN *Finished; - UINT64 ExpectedTime; - UINT64 CurrentTime; - UINT64 TotalTime; - EFI_EVENT WaitEvent; - UINTN **FailedCpuList; - - AP_INIT_STATE InitFlag; - BOOLEAN SwitchBspFlag; - UINTN NewBspNumber; - CPU_EXCHANGE_ROLE_INFO BSPInfo; - CPU_EXCHANGE_ROLE_INFO APInfo; - MTRR_SETTINGS MtrrTable; - UINT8 ApLoopMode; - UINT8 ApTargetCState; - UINT16 PmCodeSegment; - UINT16 Pm16CodeSegment; - CPU_AP_DATA *CpuData; - volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo; - - UINT32 CurrentTimerCount; - UINTN DivideValue; - UINT8 Vector; - BOOLEAN PeriodicMode; - BOOLEAN TimerInterruptState; - UINT64 MicrocodePatchAddress; - UINT64 MicrocodePatchRegionSize; + SPIN_LOCK MpLock; + UINTN Buffer; + UINTN CpuApStackSize; + MP_ASSEMBLY_ADDRESS_MAP AddressMap; + UINTN WakeupBuffer; + UINTN WakeupBufferHigh; + UINTN BackupBuffer; + UINTN BackupBufferSize; + + volatile UINT32 FinishedCount; + UINT32 RunningCount; + BOOLEAN SingleThread; + EFI_AP_PROCEDURE Procedure; + VOID *ProcArguments; + BOOLEAN *Finished; + UINT64 ExpectedTime; + UINT64 CurrentTime; + UINT64 TotalTime; + EFI_EVENT WaitEvent; + UINTN **FailedCpuList; + + AP_INIT_STATE InitFlag; + BOOLEAN SwitchBspFlag; + UINTN NewBspNumber; + CPU_EXCHANGE_ROLE_INFO BSPInfo; + CPU_EXCHANGE_ROLE_INFO APInfo; + MTRR_SETTINGS MtrrTable; + UINT8 ApLoopMode; + UINT8 ApTargetCState; + UINT16 PmCodeSegment; + UINT16 Pm16CodeSegment; + CPU_AP_DATA *CpuData; + volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo; + + UINT32 CurrentTimerCount; + UINTN DivideValue; + UINT8 Vector; + BOOLEAN PeriodicMode; + BOOLEAN TimerInterruptState; + UINT64 MicrocodePatchAddress; + UINT64 MicrocodePatchRegionSize; // // Whether need to use Init-Sipi-Sipi to wake up the APs. @@ -284,25 +284,25 @@ struct _CPU_MP_DATA { // will be hardcode change to HLT mode by PiSmmCpuDxeSmm // driver. // - BOOLEAN WakeUpByInitSipiSipi; + BOOLEAN WakeUpByInitSipiSipi; - BOOLEAN SevEsIsEnabled; - UINTN SevEsAPBuffer; - UINTN SevEsAPResetStackStart; - CPU_MP_DATA *NewCpuMpData; + BOOLEAN SevEsIsEnabled; + UINTN SevEsAPBuffer; + UINTN SevEsAPResetStackStart; + CPU_MP_DATA *NewCpuMpData; - UINT64 GhcbBase; + UINT64 GhcbBase; }; -#define AP_SAFE_STACK_SIZE 128 -#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE +#define AP_SAFE_STACK_SIZE 128 +#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE #pragma pack(1) typedef struct { - UINT8 InsnBuffer[8]; - UINT16 Rip; - UINT16 Segment; + UINT8 InsnBuffer[8]; + UINT16 Rip; + UINT16 Segment; } SEV_ES_AP_JMP_FAR; #pragma pack() @@ -322,14 +322,14 @@ typedef struct { **/ typedef VOID -(EFIAPI AP_RESET) ( +(EFIAPI AP_RESET)( IN UINTN BufferStart, IN UINT16 Code16, IN UINT16 Code32, IN UINTN StackStart ); -extern EFI_GUID mCpuInitMpLibHobGuid; +extern EFI_GUID mCpuInitMpLibHobGuid; /** Assembly code to place AP into safe loop mode. @@ -347,7 +347,7 @@ extern EFI_GUID mCpuInitMpLibHobGuid; **/ typedef VOID -(EFIAPI * ASM_RELOCATE_AP_LOOP) ( +(EFIAPI *ASM_RELOCATE_AP_LOOP)( IN BOOLEAN MwaitSupport, IN UINTN ApTargetCState, IN UINTN PmCodeSegment, @@ -367,7 +367,7 @@ VOID VOID EFIAPI AsmGetAddressMap ( - OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap + OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap ); /** @@ -382,8 +382,8 @@ AsmGetAddressMap ( VOID EFIAPI AsmExchangeRole ( - IN CPU_EXCHANGE_ROLE_INFO *MyInfo, - IN CPU_EXCHANGE_ROLE_INFO *OthersInfo + IN CPU_EXCHANGE_ROLE_INFO *MyInfo, + IN CPU_EXCHANGE_ROLE_INFO *OthersInfo ); /** @@ -403,10 +403,9 @@ GetCpuMpData ( **/ VOID SaveCpuMpData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ); - /** Get available system memory below 1MB by specified size. @@ -417,7 +416,7 @@ SaveCpuMpData ( **/ UINTN GetWakeupBuffer ( - IN UINTN WakeupBufferSize + IN UINTN WakeupBufferSize ); /** @@ -434,7 +433,7 @@ GetWakeupBuffer ( **/ UINTN GetModeTransitionBuffer ( - IN UINTN BufferSize + IN UINTN BufferSize ); /** @@ -463,12 +462,12 @@ GetSevEsAPMemory ( **/ VOID WakeUpAP ( - IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN Broadcast, - IN UINTN ProcessorNumber, - IN EFI_AP_PROCEDURE Procedure OPTIONAL, - IN VOID *ProcedureArgument OPTIONAL, - IN BOOLEAN WakeUpDisabledAps OPTIONAL + IN CPU_MP_DATA *CpuMpData, + IN BOOLEAN Broadcast, + IN UINTN ProcessorNumber, + IN EFI_AP_PROCEDURE Procedure OPTIONAL, + IN VOID *ProcedureArgument OPTIONAL, + IN BOOLEAN WakeUpDisabledAps OPTIONAL ); /** @@ -478,7 +477,7 @@ WakeUpAP ( **/ VOID InitMpGlobalData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ); /** @@ -515,13 +514,13 @@ InitMpGlobalData ( **/ EFI_STATUS StartupAllCPUsWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN BOOLEAN ExcludeBsp, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN BOOLEAN ExcludeBsp, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ); /** @@ -549,12 +548,12 @@ StartupAllCPUsWorker ( **/ EFI_STATUS StartupThisAPWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ); /** @@ -570,8 +569,8 @@ StartupThisAPWorker ( **/ EFI_STATUS SwitchBSPWorker ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ); /** @@ -590,9 +589,9 @@ SwitchBSPWorker ( **/ EFI_STATUS EnableDisableApWorker ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ); /** @@ -618,7 +617,7 @@ GetCpuMpDataFromGuidedHob ( **/ EFI_STATUS CheckThisAP ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ); /** @@ -655,8 +654,8 @@ CheckAndUpdateApsStatus ( **/ VOID MicrocodeDetect ( - IN CPU_MP_DATA *CpuMpData, - IN UINTN ProcessorNumber + IN CPU_MP_DATA *CpuMpData, + IN UINTN ProcessorNumber ); /** @@ -666,7 +665,7 @@ MicrocodeDetect ( **/ VOID ShadowMicrocodeUpdatePatch ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ); /** @@ -686,8 +685,8 @@ ShadowMicrocodeUpdatePatch ( **/ BOOLEAN GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize + UINT64 *Address, + UINT64 *RegionSize ); /** @@ -721,8 +720,8 @@ EnableDebugAgent ( **/ EFI_STATUS GetProcessorNumber ( - IN CPU_MP_DATA *CpuMpData, - OUT UINTN *ProcessorNumber + IN CPU_MP_DATA *CpuMpData, + OUT UINTN *ProcessorNumber ); /** @@ -738,7 +737,7 @@ GetProcessorNumber ( **/ EFI_STATUS PlatformShadowMicrocode ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ); #endif diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c index 90015c650c..ab79360bb9 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -11,7 +11,7 @@ #include #include -STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; +STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; /** S3 SMM Init Done notification function. @@ -26,16 +26,15 @@ STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; EFI_STATUS EFIAPI NotifyOnS3SmmInitDonePpi ( - IN EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, - IN VOID *InvokePpi + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *InvokePpi ); - // // Global function // -EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = { +EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, &gEdkiiS3SmmInitDoneGuid, NotifyOnS3SmmInitDonePpi @@ -54,12 +53,12 @@ EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = { EFI_STATUS EFIAPI NotifyOnS3SmmInitDonePpi ( - IN EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, - IN VOID *InvokePpi + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *InvokePpi ) { - CPU_MP_DATA *CpuMpData; + CPU_MP_DATA *CpuMpData; CpuMpData = GetCpuMpData (); @@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi ( return EFI_SUCCESS; } - /** Enable Debug Agent to support source debugging on AP function. @@ -110,8 +108,9 @@ GetCpuMpData ( ASSERT (CpuMpData != NULL); } else { AsmReadIdtr (&Idtr); - CpuMpData = (CPU_MP_DATA *) (Idtr.Base + Idtr.Limit + 1); + CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1); } + return CpuMpData; } @@ -122,17 +121,18 @@ GetCpuMpData ( **/ VOID SaveCpuMpData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - UINT64 Data64; + UINT64 Data64; + // // Build location of CPU MP DATA buffer in HOB // - Data64 = (UINT64) (UINTN) CpuMpData; + Data64 = (UINT64)(UINTN)CpuMpData; BuildGuidDataHob ( &mCpuInitMpLibHobGuid, - (VOID *) &Data64, + (VOID *)&Data64, sizeof (UINT64) ); } @@ -148,15 +148,15 @@ SaveCpuMpData ( **/ BOOLEAN CheckOverlapWithAllocatedBuffer ( - IN UINT64 WakeupBufferStart, - IN UINT64 WakeupBufferEnd + IN UINT64 WakeupBufferStart, + IN UINT64 WakeupBufferEnd ) { - EFI_PEI_HOB_POINTERS Hob; - EFI_HOB_MEMORY_ALLOCATION *MemoryHob; - BOOLEAN Overlapped; - UINT64 MemoryStart; - UINT64 MemoryEnd; + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_MEMORY_ALLOCATION *MemoryHob; + BOOLEAN Overlapped; + UINT64 MemoryStart; + UINT64 MemoryEnd; Overlapped = FALSE; // @@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer ( break; } } + Hob.Raw = GET_NEXT_HOB (Hob); } + return Overlapped; } @@ -191,12 +193,12 @@ CheckOverlapWithAllocatedBuffer ( **/ UINTN GetWakeupBuffer ( - IN UINTN WakeupBufferSize + IN UINTN WakeupBufferSize ) { - EFI_PEI_HOB_POINTERS Hob; - UINT64 WakeupBufferStart; - UINT64 WakeupBufferEnd; + EFI_PEI_HOB_POINTERS Hob; + UINT64 WakeupBufferStart; + UINT64 WakeupBufferEnd; WakeupBufferSize = (WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1); @@ -216,14 +218,16 @@ GetWakeupBuffer ( (EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED | EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED | EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED - )) == 0) - ) { + )) == 0) + ) + { // // Need memory under 1MB to be collected here // WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength; if (PcdGetBool (PcdSevEsIsEnabled) && - WakeupBufferEnd > mSevEsPeiWakeupBuffer) { + (WakeupBufferEnd > mSevEsPeiWakeupBuffer)) + { // // SEV-ES Wakeup buffer should be under 1MB and under any previous one // @@ -234,6 +238,7 @@ GetWakeupBuffer ( // WakeupBufferEnd = BASE_1MB; } + while (WakeupBufferEnd > WakeupBufferSize) { // // Wakeup buffer should be aligned on 4KB @@ -242,6 +247,7 @@ GetWakeupBuffer ( if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) { break; } + if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) { // // If this range is overlapped with existing allocated buffer, skip it @@ -250,8 +256,13 @@ GetWakeupBuffer ( WakeupBufferEnd -= WakeupBufferSize; continue; } - DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n", - WakeupBufferStart, WakeupBufferSize)); + + DEBUG (( + DEBUG_INFO, + "WakeupBufferStart = %x, WakeupBufferSize = %x\n", + WakeupBufferStart, + WakeupBufferSize + )); if (PcdGetBool (PcdSevEsIsEnabled)) { // @@ -265,13 +276,14 @@ GetWakeupBuffer ( } } } + // // Find the next HOB // Hob.Raw = GET_NEXT_HOB (Hob); } - return (UINTN) -1; + return (UINTN)-1; } /** @@ -288,7 +300,7 @@ GetWakeupBuffer ( **/ UINTN GetModeTransitionBuffer ( - IN UINTN BufferSize + IN UINTN BufferSize ) { // @@ -336,17 +348,17 @@ CheckAndUpdateApsStatus ( **/ VOID BuildMicrocodeCacheHob ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { - EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; - UINTN HobDataLength; - UINT32 Index; + EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; + UINTN HobDataLength; + UINT32 Index; HobDataLength = sizeof (EDKII_MICROCODE_PATCH_HOB) + sizeof (UINT64) * CpuMpData->CpuCount; - MicrocodeHob = AllocatePool (HobDataLength); + MicrocodeHob = AllocatePool (HobDataLength); if (MicrocodeHob == NULL) { ASSERT (FALSE); return; @@ -387,7 +399,7 @@ BuildMicrocodeCacheHob ( **/ VOID InitMpGlobalData ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData ) { EFI_STATUS Status; @@ -480,12 +492,12 @@ InitMpGlobalData ( EFI_STATUS EFIAPI MpInitLibStartupAllAPs ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ) { if (WaitEvent != NULL) { @@ -577,12 +589,12 @@ MpInitLibStartupAllAPs ( EFI_STATUS EFIAPI MpInitLibStartupThisAP ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ) { if (WaitEvent != NULL) { @@ -628,8 +640,8 @@ MpInitLibStartupThisAP ( EFI_STATUS EFIAPI MpInitLibSwitchBSP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ) { return SwitchBSPWorker (ProcessorNumber, EnableOldBSP); @@ -668,9 +680,9 @@ MpInitLibSwitchBSP ( EFI_STATUS EFIAPI MpInitLibEnableDisableAP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag); @@ -689,29 +701,29 @@ MpInitLibEnableDisableAP ( **/ EFI_STATUS PlatformShadowMicrocode ( - IN OUT CPU_MP_DATA *CpuMpData + IN OUT CPU_MP_DATA *CpuMpData ) { - EFI_STATUS Status; - EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi; - UINTN CpuCount; - EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId; - UINTN Index; - UINTN BufferSize; - VOID *Buffer; + EFI_STATUS Status; + EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi; + UINTN CpuCount; + EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId; + UINTN Index; + UINTN BufferSize; + VOID *Buffer; Status = PeiServicesLocatePpi ( &gEdkiiPeiShadowMicrocodePpiGuid, 0, NULL, - (VOID **) &ShadowMicrocodePpi + (VOID **)&ShadowMicrocodePpi ); if (EFI_ERROR (Status)) { return EFI_UNSUPPORTED; } - CpuCount = CpuMpData->CpuCount; - MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *) AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount); + CpuCount = CpuMpData->CpuCount; + MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *)AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount); if (MicrocodeCpuId == NULL) { return EFI_OUT_OF_RESOURCES; } @@ -722,24 +734,26 @@ PlatformShadowMicrocode ( } Status = ShadowMicrocodePpi->ShadowMicrocode ( - ShadowMicrocodePpi, - CpuCount, - MicrocodeCpuId, - &BufferSize, - &Buffer - ); + ShadowMicrocodePpi, + CpuCount, + MicrocodeCpuId, + &BufferSize, + &Buffer + ); FreePool (MicrocodeCpuId); if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; } - CpuMpData->MicrocodePatchAddress = (UINTN) Buffer; + CpuMpData->MicrocodePatchAddress = (UINTN)Buffer; CpuMpData->MicrocodePatchRegionSize = BufferSize; DEBUG (( DEBUG_INFO, "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", - __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize + __FUNCTION__, + CpuMpData->MicrocodePatchAddress, + CpuMpData->MicrocodePatchRegionSize )); return EFI_SUCCESS; diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c index 7a461af9b1..86f9fbf903 100644 --- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c +++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c @@ -63,8 +63,8 @@ MpInitLibInitialize ( EFI_STATUS EFIAPI MpInitLibGetNumberOfProcessors ( - OUT UINTN *NumberOfProcessors OPTIONAL, - OUT UINTN *NumberOfEnabledProcessors OPTIONAL + OUT UINTN *NumberOfProcessors OPTIONAL, + OUT UINTN *NumberOfEnabledProcessors OPTIONAL ) { *NumberOfProcessors = 1; @@ -103,13 +103,15 @@ MpInitLibGetProcessorInfo ( if (ProcessorInfoBuffer == NULL) { return EFI_INVALID_PARAMETER; } + if (ProcessorNumber != 0) { return EFI_NOT_FOUND; } - ProcessorInfoBuffer->ProcessorId = 0; - ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT | - PROCESSOR_ENABLED_BIT | - PROCESSOR_HEALTH_STATUS_BIT; + + ProcessorInfoBuffer->ProcessorId = 0; + ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT | + PROCESSOR_ENABLED_BIT | + PROCESSOR_HEALTH_STATUS_BIT; ProcessorInfoBuffer->Location.Package = 0; ProcessorInfoBuffer->Location.Core = 0; ProcessorInfoBuffer->Location.Thread = 0; @@ -117,12 +119,13 @@ MpInitLibGetProcessorInfo ( GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); if (GuidHob != NULL) { SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob); - HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; + HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; } else { DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n")); HealthData->Uint32 = 0; } } + return EFI_SUCCESS; } @@ -204,12 +207,12 @@ MpInitLibGetProcessorInfo ( EFI_STATUS EFIAPI MpInitLibStartupAllAPs ( - IN EFI_AP_PROCEDURE Procedure, - IN BOOLEAN SingleThread, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT UINTN **FailedCpuList OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL ) { return EFI_NOT_STARTED; @@ -289,12 +292,12 @@ MpInitLibStartupAllAPs ( EFI_STATUS EFIAPI MpInitLibStartupThisAP ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN ProcessorNumber, - IN EFI_EVENT WaitEvent OPTIONAL, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL, - OUT BOOLEAN *Finished OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL ) { return EFI_INVALID_PARAMETER; @@ -329,8 +332,8 @@ MpInitLibStartupThisAP ( EFI_STATUS EFIAPI MpInitLibSwitchBSP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableOldBSP + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP ) { return EFI_UNSUPPORTED; @@ -369,9 +372,9 @@ MpInitLibSwitchBSP ( EFI_STATUS EFIAPI MpInitLibEnableDisableAP ( - IN UINTN ProcessorNumber, - IN BOOLEAN EnableAP, - IN UINT32 *HealthFlag OPTIONAL + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL ) { return EFI_UNSUPPORTED; @@ -396,12 +399,13 @@ MpInitLibEnableDisableAP ( EFI_STATUS EFIAPI MpInitLibWhoAmI ( - OUT UINTN *ProcessorNumber + OUT UINTN *ProcessorNumber ) { if (ProcessorNumber == NULL) { return EFI_INVALID_PARAMETER; } + *ProcessorNumber = 0; return EFI_SUCCESS; } @@ -427,9 +431,9 @@ MpInitLibWhoAmI ( EFI_STATUS EFIAPI MpInitLibStartupAllCPUs ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN TimeoutInMicroseconds, - IN VOID *ProcedureArgument OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL ) { if (Procedure == NULL) { diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index 805a2f8d21..e5c862c83d 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -20,35 +20,35 @@ #include #include -#define OR_SEED 0x0101010101010101ull -#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull -#define MAX_WEIGHT MAX_UINT8 -#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB) -#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B); +#define OR_SEED 0x0101010101010101ull +#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull +#define MAX_WEIGHT MAX_UINT8 +#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB) +#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B); -#define M(x,y) ((x) * VertexCount + (y)) -#define O(x,y) ((y) * VertexCount + (x)) +#define M(x, y) ((x) * VertexCount + (y)) +#define O(x, y) ((y) * VertexCount + (x)) // // Context to save and restore when MTRRs are programmed // typedef struct { - UINTN Cr4; - BOOLEAN InterruptState; + UINTN Cr4; + BOOLEAN InterruptState; } MTRR_CONTEXT; typedef struct { - UINT64 Address; - UINT64 Alignment; - UINT64 Length; - MTRR_MEMORY_CACHE_TYPE Type : 7; + UINT64 Address; + UINT64 Alignment; + UINT64 Length; + MTRR_MEMORY_CACHE_TYPE Type : 7; // // Temprary use for calculating the best MTRR settings. // - BOOLEAN Visited : 1; - UINT8 Weight; - UINT16 Previous; + BOOLEAN Visited : 1; + UINT8 Weight; + UINT16 Previous; } MTRR_LIB_ADDRESS; // @@ -115,7 +115,7 @@ CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = { // // Lookup table used to print MTRRs // -GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { +GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { "UC", // CacheUncacheable "WC", // CacheWriteCombining "R*", // Invalid @@ -126,7 +126,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { "R*" // Invalid }; - /** Worker function prints all MTRRs for debugging. @@ -138,7 +137,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { **/ VOID MtrrDebugPrintAllMtrrsWorker ( - IN MTRR_SETTINGS *MtrrSetting + IN MTRR_SETTINGS *MtrrSetting ); /** @@ -152,10 +151,10 @@ GetVariableMtrrCountWorker ( VOID ) { - MSR_IA32_MTRRCAP_REGISTER MtrrCap; + MSR_IA32_MTRRCAP_REGISTER MtrrCap; MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); - ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr)); + ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *)0)->Mtrr)); return MtrrCap.Bits.VCNT; } @@ -174,6 +173,7 @@ GetVariableMtrrCount ( if (!IsMtrrSupported ()) { return 0; } + return GetVariableMtrrCountWorker (); } @@ -191,7 +191,7 @@ GetFirmwareVariableMtrrCountWorker ( UINT32 VariableMtrrCount; UINT32 ReservedMtrrNumber; - VariableMtrrCount = GetVariableMtrrCountWorker (); + VariableMtrrCount = GetVariableMtrrCountWorker (); ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs); if (VariableMtrrCount < ReservedMtrrNumber) { return 0; @@ -215,6 +215,7 @@ GetFirmwareVariableMtrrCount ( if (!IsMtrrSupported ()) { return 0; } + return GetFirmwareVariableMtrrCountWorker (); } @@ -232,10 +233,10 @@ GetFirmwareVariableMtrrCount ( **/ MTRR_MEMORY_CACHE_TYPE MtrrGetDefaultMemoryTypeWorker ( - IN MTRR_SETTINGS *MtrrSetting + IN MTRR_SETTINGS *MtrrSetting ) { - MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; if (MtrrSetting == NULL) { DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); @@ -243,10 +244,9 @@ MtrrGetDefaultMemoryTypeWorker ( DefType.Uint64 = MtrrSetting->MtrrDefType; } - return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type; + return (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type; } - /** Returns the default MTRR cache type for the system. @@ -262,6 +262,7 @@ MtrrGetDefaultMemoryType ( if (!IsMtrrSupported ()) { return CacheUncacheable; } + return MtrrGetDefaultMemoryTypeWorker (NULL); } @@ -280,10 +281,11 @@ MtrrLibPreMtrrChange ( ) { MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + // // Disable interrupts and save current interrupt state // - MtrrContext->InterruptState = SaveAndDisableInterrupts(); + MtrrContext->InterruptState = SaveAndDisableInterrupts (); // // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29) @@ -359,11 +361,12 @@ MtrrLibPostMtrrChange ( ) { MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + // // Enable Cache MTRR // - DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); - DefType.Bits.E = 1; + DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); + DefType.Bits.E = 1; DefType.Bits.FE = 1; AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); @@ -378,22 +381,21 @@ MtrrLibPostMtrrChange ( @retval The pointer of FixedSettings **/ -MTRR_FIXED_SETTINGS* +MTRR_FIXED_SETTINGS * MtrrGetFixedMtrrWorker ( - OUT MTRR_FIXED_SETTINGS *FixedSettings + OUT MTRR_FIXED_SETTINGS *FixedSettings ) { UINT32 Index; for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - FixedSettings->Mtrr[Index] = - AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr); + FixedSettings->Mtrr[Index] = + AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr); } return FixedSettings; } - /** This function gets the content in fixed MTRRs @@ -402,10 +404,10 @@ MtrrGetFixedMtrrWorker ( @retval The pointer of FixedSettings **/ -MTRR_FIXED_SETTINGS* +MTRR_FIXED_SETTINGS * EFIAPI MtrrGetFixedMtrr ( - OUT MTRR_FIXED_SETTINGS *FixedSettings + OUT MTRR_FIXED_SETTINGS *FixedSettings ) { if (!IsMtrrSupported ()) { @@ -415,7 +417,6 @@ MtrrGetFixedMtrr ( return MtrrGetFixedMtrrWorker (FixedSettings); } - /** Worker function will get the raw value in variable MTRRs @@ -430,7 +431,7 @@ MtrrGetFixedMtrr ( @return The VariableSettings input pointer **/ -MTRR_VARIABLE_SETTINGS* +MTRR_VARIABLE_SETTINGS * MtrrGetVariableMtrrWorker ( IN MTRR_SETTINGS *MtrrSetting, IN UINT32 VariableMtrrCount, @@ -453,7 +454,7 @@ MtrrGetVariableMtrrWorker ( } } - return VariableSettings; + return VariableSettings; } /** @@ -493,12 +494,13 @@ MtrrLibProgramFixedMtrr ( for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) { if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) && (*Base < - ( - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress + - (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length) - ) - ) - ) { + ( + mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress + + (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length) + ) + ) + ) + { break; } } @@ -514,6 +516,7 @@ MtrrLibProgramFixedMtrr ( // return RETURN_UNSUPPORTED; } + LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length; ASSERT (LeftByteShift < 8); @@ -530,6 +533,7 @@ MtrrLibProgramFixedMtrr ( // return RETURN_UNSUPPORTED; } + RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length; // // Update SubLength by actual length @@ -538,14 +542,14 @@ MtrrLibProgramFixedMtrr ( } *ClearMask = CLEAR_SEED; - *OrMask = MultU64x32 (OR_SEED, (UINT32) Type); + *OrMask = MultU64x32 (OR_SEED, (UINT32)Type); if (LeftByteShift != 0) { // // Clear the low bits by LeftByteShift // *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8); - *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8); + *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8); } if (RightByteShift != 0) { @@ -553,18 +557,17 @@ MtrrLibProgramFixedMtrr ( // Clear the high bits by RightByteShift // *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8); - *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8); + *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8); } *Length -= SubLength; *Base += SubLength; - *LastMsrIndex = MsrIndex; + *LastMsrIndex = MsrIndex; return RETURN_SUCCESS; } - /** Worker function gets the attribute of variable MTRRs. @@ -594,17 +597,18 @@ MtrrGetMemoryAttributeInVariableMtrrWorker ( ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr)); for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) { - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { VariableMtrr[Index].Msr = (UINT32)Index; VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask); VariableMtrr[Index].Length = ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; - VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff); - VariableMtrr[Index].Valid = TRUE; - VariableMtrr[Index].Used = TRUE; + VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff); + VariableMtrr[Index].Valid = TRUE; + VariableMtrr[Index].Used = TRUE; UsedMtrr++; } } + return UsedMtrr; } @@ -636,14 +640,15 @@ MtrrLibGetRawVariableRanges ( ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr)); for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) { - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask); VariableMtrr[Index].Length = ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; - VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff); + VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff); UsedMtrr++; } } + return UsedMtrr; } @@ -664,9 +669,9 @@ MtrrLibGetRawVariableRanges ( UINT32 EFIAPI MtrrGetMemoryAttributeInVariableMtrr ( - IN UINT64 MtrrValidBitsMask, - IN UINT64 MtrrValidAddressMask, - OUT VARIABLE_MTRR *VariableMtrr + IN UINT64 MtrrValidBitsMask, + IN UINT64 MtrrValidAddressMask, + OUT VARIABLE_MTRR *VariableMtrr ) { MTRR_VARIABLE_SETTINGS VariableSettings; @@ -701,9 +706,9 @@ MtrrGetMemoryAttributeInVariableMtrr ( **/ UINT64 MtrrLibBiggestAlignment ( - UINT64 Address, - UINT64 Alignment0 -) + UINT64 Address, + UINT64 Alignment0 + ) { if (Address == 0) { return Alignment0; @@ -731,9 +736,9 @@ BOOLEAN MtrrLibTypeLeftPrecedeRight ( IN MTRR_MEMORY_CACHE_TYPE Left, IN MTRR_MEMORY_CACHE_TYPE Right -) + ) { - return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack)); + return (BOOLEAN)(Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack)); } /** @@ -747,14 +752,13 @@ MtrrLibTypeLeftPrecedeRight ( **/ VOID MtrrLibInitializeMtrrMask ( - OUT UINT64 *MtrrValidBitsMask, - OUT UINT64 *MtrrValidAddressMask + OUT UINT64 *MtrrValidBitsMask, + OUT UINT64 *MtrrValidAddressMask ) { UINT32 MaxExtendedFunction; CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL); if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) { @@ -763,11 +767,10 @@ MtrrLibInitializeMtrrMask ( VirPhyAddressSize.Bits.PhysicalAddressBits = 36; } - *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; + *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL; } - /** Determines the real attribute of a memory range. @@ -782,8 +785,8 @@ MtrrLibInitializeMtrrMask ( **/ MTRR_MEMORY_CACHE_TYPE MtrrLibPrecedence ( - IN MTRR_MEMORY_CACHE_TYPE MtrrType1, - IN MTRR_MEMORY_CACHE_TYPE MtrrType2 + IN MTRR_MEMORY_CACHE_TYPE MtrrType1, + IN MTRR_MEMORY_CACHE_TYPE MtrrType2 ) { if (MtrrType1 == MtrrType2) { @@ -793,7 +796,7 @@ MtrrLibPrecedence ( ASSERT ( MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) || MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1) - ); + ); if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) { return MtrrType1; @@ -817,20 +820,20 @@ MtrrLibPrecedence ( **/ MTRR_MEMORY_CACHE_TYPE MtrrGetMemoryAttributeByAddressWorker ( - IN MTRR_SETTINGS *MtrrSetting, - IN PHYSICAL_ADDRESS Address + IN MTRR_SETTINGS *MtrrSetting, + IN PHYSICAL_ADDRESS Address ) { - MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; - UINT64 FixedMtrr; - UINTN Index; - UINTN SubIndex; - MTRR_MEMORY_CACHE_TYPE MtrrType; - MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - UINT32 VariableMtrrCount; - MTRR_VARIABLE_SETTINGS VariableSettings; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + UINT64 FixedMtrr; + UINTN Index; + UINTN SubIndex; + MTRR_MEMORY_CACHE_TYPE MtrrType; + MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + UINT32 VariableMtrrCount; + MTRR_VARIABLE_SETTINGS VariableSettings; // // Check if MTRR is enabled, if not, return UC as attribute @@ -854,18 +857,20 @@ MtrrGetMemoryAttributeByAddressWorker ( // Go through the fixed MTRR // for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress && - Address < mMtrrLibFixedMtrrTable[Index].BaseAddress + - (mMtrrLibFixedMtrrTable[Index].Length * 8)) { + if ((Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress) && + (Address < mMtrrLibFixedMtrrTable[Index].BaseAddress + + (mMtrrLibFixedMtrrTable[Index].Length * 8))) + { SubIndex = - ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) / + ((UINTN)Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) / mMtrrLibFixedMtrrTable[Index].Length; if (MtrrSetting == NULL) { FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr); } else { FixedMtrr = MtrrSetting->Fixed.Mtrr[Index]; } - return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF); + + return (MTRR_MEMORY_CACHE_TYPE)(RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF); } } } @@ -882,7 +887,7 @@ MtrrGetMemoryAttributeByAddressWorker ( MtrrValidBitsMask, MtrrValidAddressMask, VariableMtrr - ); + ); // // Go through the variable MTRR @@ -890,12 +895,13 @@ MtrrGetMemoryAttributeByAddressWorker ( MtrrType = CacheInvalid; for (Index = 0; Index < VariableMtrrCount; Index++) { if (VariableMtrr[Index].Length != 0) { - if (Address >= VariableMtrr[Index].BaseAddress && - Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) { + if ((Address >= VariableMtrr[Index].BaseAddress) && + (Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length)) + { if (MtrrType == CacheInvalid) { - MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type; + MtrrType = (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type; } else { - MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type); + MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type); } } } @@ -905,13 +911,12 @@ MtrrGetMemoryAttributeByAddressWorker ( // If there is no MTRR which covers the Address, use the default MTRR type. // if (MtrrType == CacheInvalid) { - MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type; + MtrrType = (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type; } return MtrrType; } - /** This function will get the memory cache type of the specific address. @@ -925,7 +930,7 @@ MtrrGetMemoryAttributeByAddressWorker ( MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetMemoryAttribute ( - IN PHYSICAL_ADDRESS Address + IN PHYSICAL_ADDRESS Address ) { if (!IsMtrrSupported ()) { @@ -955,46 +960,48 @@ MtrrGetMemoryAttribute ( **/ RETURN_STATUS MtrrLibSetMemoryType ( - IN MTRR_MEMORY_RANGE *Ranges, - IN UINTN Capacity, - IN OUT UINTN *Count, - IN UINT64 BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN Capacity, + IN OUT UINTN *Count, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN MTRR_MEMORY_CACHE_TYPE Type ) { - UINTN Index; - UINT64 Limit; - UINT64 LengthLeft; - UINT64 LengthRight; - UINTN StartIndex; - UINTN EndIndex; - UINTN DeltaCount; + UINTN Index; + UINT64 Limit; + UINT64 LengthLeft; + UINT64 LengthRight; + UINTN StartIndex; + UINTN EndIndex; + UINTN DeltaCount; LengthRight = 0; LengthLeft = 0; - Limit = BaseAddress + Length; - StartIndex = *Count; - EndIndex = *Count; + Limit = BaseAddress + Length; + StartIndex = *Count; + EndIndex = *Count; for (Index = 0; Index < *Count; Index++) { if ((StartIndex == *Count) && (Ranges[Index].BaseAddress <= BaseAddress) && - (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) { + (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) + { StartIndex = Index; LengthLeft = BaseAddress - Ranges[Index].BaseAddress; } if ((EndIndex == *Count) && (Ranges[Index].BaseAddress < Limit) && - (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) { - EndIndex = Index; + (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) + { + EndIndex = Index; LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit; break; } } ASSERT (StartIndex != *Count && EndIndex != *Count); - if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) { + if ((StartIndex == EndIndex) && (Ranges[StartIndex].Type == Type)) { return RETURN_ALREADY_STARTED; } @@ -1004,14 +1011,15 @@ MtrrLibSetMemoryType ( // logic doesn't need to consider merging. // if (StartIndex != 0) { - if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) { + if ((LengthLeft == 0) && (Ranges[StartIndex - 1].Type == Type)) { StartIndex--; - Length += Ranges[StartIndex].Length; + Length += Ranges[StartIndex].Length; BaseAddress -= Ranges[StartIndex].Length; } } + if (EndIndex != (*Count) - 1) { - if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) { + if ((LengthRight == 0) && (Ranges[EndIndex + 1].Type == Type)) { EndIndex++; Length += Ranges[EndIndex].Length; } @@ -1029,9 +1037,11 @@ MtrrLibSetMemoryType ( if (LengthLeft == 0) { DeltaCount++; } + if (LengthRight == 0) { DeltaCount++; } + if (*Count - DeltaCount > Capacity) { return RETURN_OUT_OF_RESOURCES; } @@ -1046,14 +1056,16 @@ MtrrLibSetMemoryType ( Ranges[StartIndex].Length = LengthLeft; StartIndex++; } + if (LengthRight != 0) { Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length; - Ranges[EndIndex - DeltaCount].Length = LengthRight; - Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type; + Ranges[EndIndex - DeltaCount].Length = LengthRight; + Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type; } + Ranges[StartIndex].BaseAddress = BaseAddress; - Ranges[StartIndex].Length = Length; - Ranges[StartIndex].Type = Type; + Ranges[StartIndex].Length = Length; + Ranges[StartIndex].Type = Type; return RETURN_SUCCESS; } @@ -1070,30 +1082,31 @@ MtrrLibSetMemoryType ( **/ UINT8 MtrrLibGetNumberOfTypes ( - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount, - IN UINT64 BaseAddress, - IN UINT64 Length, - IN OUT UINT8 *Types OPTIONAL + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN OUT UINT8 *Types OPTIONAL ) { - UINTN Index; - UINT8 TypeCount; - UINT8 LocalTypes; + UINTN Index; + UINT8 TypeCount; + UINT8 LocalTypes; - TypeCount = 0; + TypeCount = 0; LocalTypes = 0; for (Index = 0; Index < RangeCount; Index++) { if ((Ranges[Index].BaseAddress <= BaseAddress) && (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length) - ) { + ) + { if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) { LocalTypes |= (UINT8)(1 << Ranges[Index].Type); TypeCount++; } if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) { - Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress; + Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress; BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length; } else { break; @@ -1104,6 +1117,7 @@ MtrrLibGetNumberOfTypes ( if (Types != NULL) { *Types = LocalTypes; } + return TypeCount; } @@ -1121,32 +1135,32 @@ MtrrLibGetNumberOfTypes ( **/ VOID MtrrLibCalculateLeastMtrrs ( - IN UINT16 VertexCount, - IN MTRR_LIB_ADDRESS *Vertices, - IN OUT CONST UINT8 *Weight, - IN UINT16 Start, - IN UINT16 Stop, - IN BOOLEAN IncludeOptional + IN UINT16 VertexCount, + IN MTRR_LIB_ADDRESS *Vertices, + IN OUT CONST UINT8 *Weight, + IN UINT16 Start, + IN UINT16 Stop, + IN BOOLEAN IncludeOptional ) { - UINT16 Index; - UINT8 MinWeight; - UINT16 MinI; - UINT8 Mandatory; - UINT8 Optional; + UINT16 Index; + UINT8 MinWeight; + UINT16 MinI; + UINT8 Mandatory; + UINT8 Optional; for (Index = Start; Index <= Stop; Index++) { Vertices[Index].Visited = FALSE; - Mandatory = Weight[M(Start,Index)]; - Vertices[Index].Weight = Mandatory; + Mandatory = Weight[M (Start, Index)]; + Vertices[Index].Weight = Mandatory; if (Mandatory != MAX_WEIGHT) { - Optional = IncludeOptional ? Weight[O(Start, Index)] : 0; + Optional = IncludeOptional ? Weight[O (Start, Index)] : 0; Vertices[Index].Weight += Optional; ASSERT (Vertices[Index].Weight >= Optional); } } - MinI = Start; + MinI = Start; MinWeight = 0; while (!Vertices[Stop].Visited) { // @@ -1154,9 +1168,9 @@ MtrrLibCalculateLeastMtrrs ( // for (Index = Start + 1; Index <= Stop; Index++) { if (!Vertices[Index].Visited) { - Mandatory = Weight[M(MinI, Index)]; + Mandatory = Weight[M (MinI, Index)]; if (Mandatory != MAX_WEIGHT) { - Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0; + Optional = IncludeOptional ? Weight[O (MinI, Index)] : 0; if (MinWeight + Mandatory + Optional <= Vertices[Index].Weight) { Vertices[Index].Weight = MinWeight + Mandatory + Optional; Vertices[Index].Previous = MinI; // Previous is Start based. @@ -1171,7 +1185,7 @@ MtrrLibCalculateLeastMtrrs ( MinI = VertexCount; MinWeight = MAX_WEIGHT; for (Index = Start + 1; Index <= Stop; Index++) { - if (!Vertices[Index].Visited && MinWeight > Vertices[Index].Weight) { + if (!Vertices[Index].Visited && (MinWeight > Vertices[Index].Weight)) { MinI = Index; MinWeight = Vertices[Index].Weight; } @@ -1227,13 +1241,15 @@ MtrrLibAppendVariableMtrr ( **/ MTRR_MEMORY_CACHE_TYPE MtrrLibLowestType ( - IN UINT8 TypeBits -) + IN UINT8 TypeBits + ) { - INT8 Type; + INT8 Type; ASSERT (TypeBits != 0); - for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1); + for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1) { + } + return (MTRR_MEMORY_CACHE_TYPE)Type; } @@ -1245,11 +1261,11 @@ MtrrLibLowestType ( **/ BOOLEAN MtrrLibIsPowerOfTwo ( - IN UINT64 Operand -) + IN UINT64 Operand + ) { ASSERT (Operand != 0); - return (BOOLEAN) ((Operand & (Operand - 1)) == 0); + return (BOOLEAN)((Operand & (Operand - 1)) == 0); } /** @@ -1276,36 +1292,36 @@ MtrrLibIsPowerOfTwo ( **/ RETURN_STATUS MtrrLibCalculateSubtractivePath ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT64 A0, - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount, - IN UINT16 VertexCount, - IN MTRR_LIB_ADDRESS *Vertices, - IN OUT UINT8 *Weight, - IN UINT16 Start, - IN UINT16 Stop, - IN UINT8 Types, - IN UINT8 TypeCount, - IN OUT MTRR_MEMORY_RANGE *Mtrrs OPTIONAL, - IN UINT32 MtrrCapacity OPTIONAL, - IN OUT UINT32 *MtrrCount OPTIONAL + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN UINT16 VertexCount, + IN MTRR_LIB_ADDRESS *Vertices, + IN OUT UINT8 *Weight, + IN UINT16 Start, + IN UINT16 Stop, + IN UINT8 Types, + IN UINT8 TypeCount, + IN OUT MTRR_MEMORY_RANGE *Mtrrs OPTIONAL, + IN UINT32 MtrrCapacity OPTIONAL, + IN OUT UINT32 *MtrrCount OPTIONAL ) { - RETURN_STATUS Status; - UINT64 Base; - UINT64 Length; - UINT8 PrecedentTypes; - UINTN Index; - UINT64 HBase; - UINT64 HLength; - UINT64 SubLength; - UINT16 SubStart; - UINT16 SubStop; - UINT16 Cur; - UINT16 Pre; - MTRR_MEMORY_CACHE_TYPE LowestType; - MTRR_MEMORY_CACHE_TYPE LowestPrecedentType; + RETURN_STATUS Status; + UINT64 Base; + UINT64 Length; + UINT8 PrecedentTypes; + UINTN Index; + UINT64 HBase; + UINT64 HLength; + UINT64 SubLength; + UINT16 SubStart; + UINT16 SubStop; + UINT16 Cur; + UINT16 Pre; + MTRR_MEMORY_CACHE_TYPE LowestType; + MTRR_MEMORY_CACHE_TYPE LowestPrecedentType; Base = Vertices[Start].Address; Length = Vertices[Stop].Address - Base; @@ -1315,21 +1331,22 @@ MtrrLibCalculateSubtractivePath ( // // Clear the lowest type (highest bit) to get the precedent types // - PrecedentTypes = ~(1 << LowestType) & Types; + PrecedentTypes = ~(1 << LowestType) & Types; LowestPrecedentType = MtrrLibLowestType (PrecedentTypes); if (Mtrrs == NULL) { - Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1); - Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0); + Weight[M (Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1); + Weight[O (Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0); } // Add all high level ranges - HBase = MAX_UINT64; + HBase = MAX_UINT64; HLength = 0; for (Index = 0; Index < RangeCount; Index++) { if (Length == 0) { break; } + if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) { continue; } @@ -1342,6 +1359,7 @@ MtrrLibCalculateSubtractivePath ( } else { SubLength = Length; } + if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) { // // Meet a range whose types take precedence. @@ -1351,17 +1369,19 @@ MtrrLibCalculateSubtractivePath ( if (HBase == MAX_UINT64) { HBase = Base; } + HLength += SubLength; } - Base += SubLength; + Base += SubLength; Length -= SubLength; if (HLength == 0) { continue; } - if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end + if ((Ranges[Index].Type == LowestType) || (Length == 0)) { + // meet low type or end // // Add the MTRRs for each high priority type range @@ -1379,6 +1399,7 @@ MtrrLibCalculateSubtractivePath ( break; } } + ASSERT (Vertices[SubStart].Address == HBase); ASSERT (Vertices[SubStop].Address == HBase + HLength); @@ -1393,12 +1414,17 @@ MtrrLibCalculateSubtractivePath ( } else { while (SubStart != SubStop) { Status = MtrrLibAppendVariableMtrr ( - Mtrrs, MtrrCapacity, MtrrCount, - Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type - ); + Mtrrs, + MtrrCapacity, + MtrrCount, + Vertices[SubStart].Address, + Vertices[SubStart].Length, + Vertices[SubStart].Type + ); if (RETURN_ERROR (Status)) { return Status; } + SubStart++; } } @@ -1411,43 +1437,57 @@ MtrrLibCalculateSubtractivePath ( } else { // When we need to collect the optimal path from SubStart to SubStop while (SubStop != SubStart) { - Cur = SubStop; - Pre = Vertices[Cur].Previous; + Cur = SubStop; + Pre = Vertices[Cur].Previous; SubStop = Pre; if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) { Status = MtrrLibAppendVariableMtrr ( - Mtrrs, MtrrCapacity, MtrrCount, - Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address, - (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type - ); + Mtrrs, + MtrrCapacity, + MtrrCount, + Vertices[Pre].Address, + Vertices[Cur].Address - Vertices[Pre].Address, + (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type + ); if (RETURN_ERROR (Status)) { return Status; } } + if (Pre != Cur - 1) { Status = MtrrLibCalculateSubtractivePath ( - DefaultType, A0, - Ranges, RangeCount, - VertexCount, Vertices, Weight, - Pre, Cur, PrecedentTypes, 2, - Mtrrs, MtrrCapacity, MtrrCount - ); + DefaultType, + A0, + Ranges, + RangeCount, + VertexCount, + Vertices, + Weight, + Pre, + Cur, + PrecedentTypes, + 2, + Mtrrs, + MtrrCapacity, + MtrrCount + ); if (RETURN_ERROR (Status)) { return Status; } } } } - } + // // Reset HBase, HLength // - HBase = MAX_UINT64; + HBase = MAX_UINT64; HLength = 0; } } + return RETURN_SUCCESS; } @@ -1474,34 +1514,34 @@ MtrrLibCalculateSubtractivePath ( **/ RETURN_STATUS MtrrLibCalculateMtrrs ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT64 A0, - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount, - IN VOID *Scratch, - IN OUT UINTN *ScratchSize, - IN OUT MTRR_MEMORY_RANGE *Mtrrs, - IN UINT32 MtrrCapacity, - IN OUT UINT32 *MtrrCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN OUT MTRR_MEMORY_RANGE *Mtrrs, + IN UINT32 MtrrCapacity, + IN OUT UINT32 *MtrrCount ) { - UINT64 Base0; - UINT64 Base1; - UINTN Index; - UINT64 Base; - UINT64 Length; - UINT64 Alignment; - UINT64 SubLength; - MTRR_LIB_ADDRESS *Vertices; - UINT8 *Weight; - UINT32 VertexIndex; - UINT32 VertexCount; - UINTN RequiredScratchSize; - UINT8 TypeCount; - UINT16 Start; - UINT16 Stop; - UINT8 Type; - RETURN_STATUS Status; + UINT64 Base0; + UINT64 Base1; + UINTN Index; + UINT64 Base; + UINT64 Length; + UINT64 Alignment; + UINT64 SubLength; + MTRR_LIB_ADDRESS *Vertices; + UINT8 *Weight; + UINT32 VertexIndex; + UINT32 VertexCount; + UINTN RequiredScratchSize; + UINT8 TypeCount; + UINT16 Start; + UINT16 Stop; + UINT8 Type; + RETURN_STATUS Status; Base0 = Ranges[0].BaseAddress; Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length; @@ -1510,9 +1550,9 @@ MtrrLibCalculateMtrrs ( // // Count the number of vertices. // - Vertices = (MTRR_LIB_ADDRESS*)Scratch; + Vertices = (MTRR_LIB_ADDRESS *)Scratch; for (VertexIndex = 0, Index = 0; Index < RangeCount; Index++) { - Base = Ranges[Index].BaseAddress; + Base = Ranges[Index].BaseAddress; Length = Ranges[Index].Length; while (Length != 0) { Alignment = MtrrLibBiggestAlignment (Base, A0); @@ -1520,24 +1560,30 @@ MtrrLibCalculateMtrrs ( if (SubLength > Length) { SubLength = GetPowerOfTwo64 (Length); } + if (VertexIndex < *ScratchSize / sizeof (*Vertices)) { Vertices[VertexIndex].Address = Base; Vertices[VertexIndex].Alignment = Alignment; Vertices[VertexIndex].Type = Ranges[Index].Type; Vertices[VertexIndex].Length = SubLength; } + Base += SubLength; Length -= SubLength; VertexIndex++; } } + // // Vertices[VertexIndex] = Base1, so whole vertex count is (VertexIndex + 1). // VertexCount = VertexIndex + 1; DEBUG (( - DEBUG_CACHE, " Count of vertices (%016llx - %016llx) = %d\n", - Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VertexCount + DEBUG_CACHE, + " Count of vertices (%016llx - %016llx) = %d\n", + Ranges[0].BaseAddress, + Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, + VertexCount )); ASSERT (VertexCount < MAX_UINT16); @@ -1546,14 +1592,15 @@ MtrrLibCalculateMtrrs ( *ScratchSize = RequiredScratchSize; return RETURN_BUFFER_TOO_SMALL; } + Vertices[VertexCount - 1].Address = Base1; - Weight = (UINT8 *) &Vertices[VertexCount]; + Weight = (UINT8 *)&Vertices[VertexCount]; for (VertexIndex = 0; VertexIndex < VertexCount; VertexIndex++) { // // Set optional weight between vertices and self->self to 0 // - SetMem (&Weight[M(VertexIndex, 0)], VertexIndex + 1, 0); + SetMem (&Weight[M (VertexIndex, 0)], VertexIndex + 1, 0); // // Set mandatory weight between vertices to MAX_WEIGHT // @@ -1590,19 +1637,34 @@ MtrrLibCalculateMtrrs ( // break; } - if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) { + + if ((Weight[M (Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) { if (MtrrLibGetNumberOfTypes ( - Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type - ) == TypeCount) { + Ranges, + RangeCount, + Vertices[Start].Address, + Vertices[Stop].Address - Vertices[Start].Address, + &Type + ) == TypeCount) + { // // Update the Weight[Start, Stop] using subtractive path. // MtrrLibCalculateSubtractivePath ( - DefaultType, A0, - Ranges, RangeCount, - (UINT16)VertexCount, Vertices, Weight, - Start, Stop, Type, TypeCount, - NULL, 0, NULL + DefaultType, + A0, + Ranges, + RangeCount, + (UINT16)VertexCount, + Vertices, + Weight, + Start, + Stop, + Type, + TypeCount, + NULL, + 0, + NULL ); } else if (TypeCount == 2) { // @@ -1617,19 +1679,22 @@ MtrrLibCalculateMtrrs ( } Status = RETURN_SUCCESS; - MtrrLibCalculateLeastMtrrs ((UINT16) VertexCount, Vertices, Weight, 0, (UINT16) VertexCount - 1, FALSE); - Stop = (UINT16) VertexCount - 1; + MtrrLibCalculateLeastMtrrs ((UINT16)VertexCount, Vertices, Weight, 0, (UINT16)VertexCount - 1, FALSE); + Stop = (UINT16)VertexCount - 1; while (Stop != 0) { - Start = Vertices[Stop].Previous; + Start = Vertices[Stop].Previous; TypeCount = MAX_UINT8; - Type = 0; - if (Weight[M(Start, Stop)] != 0) { + Type = 0; + if (Weight[M (Start, Stop)] != 0) { TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type); - Status = MtrrLibAppendVariableMtrr ( - Mtrrs, MtrrCapacity, MtrrCount, - Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, - MtrrLibLowestType (Type) - ); + Status = MtrrLibAppendVariableMtrr ( + Mtrrs, + MtrrCapacity, + MtrrCount, + Vertices[Start].Address, + Vertices[Stop].Address - Vertices[Start].Address, + MtrrLibLowestType (Type) + ); if (RETURN_ERROR (Status)) { break; } @@ -1641,26 +1706,41 @@ MtrrLibCalculateMtrrs ( // if (TypeCount == MAX_UINT8) { TypeCount = MtrrLibGetNumberOfTypes ( - Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type + Ranges, + RangeCount, + Vertices[Start].Address, + Vertices[Stop].Address - Vertices[Start].Address, + &Type ); } + Status = MtrrLibCalculateSubtractivePath ( - DefaultType, A0, - Ranges, RangeCount, - (UINT16) VertexCount, Vertices, Weight, Start, Stop, - Type, TypeCount, - Mtrrs, MtrrCapacity, MtrrCount + DefaultType, + A0, + Ranges, + RangeCount, + (UINT16)VertexCount, + Vertices, + Weight, + Start, + Stop, + Type, + TypeCount, + Mtrrs, + MtrrCapacity, + MtrrCount ); if (RETURN_ERROR (Status)) { break; } } + Stop = Start; } + return Status; } - /** Apply the fixed MTRR settings to memory range array. @@ -1681,26 +1761,33 @@ MtrrLibApplyFixedMtrrs ( IN OUT UINTN *RangeCount ) { - RETURN_STATUS Status; - UINTN MsrIndex; - UINTN Index; - MTRR_MEMORY_CACHE_TYPE MemoryType; - UINT64 Base; + RETURN_STATUS Status; + UINTN MsrIndex; + UINTN Index; + MTRR_MEMORY_CACHE_TYPE MemoryType; + UINT64 Base; Base = 0; for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) { ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress); for (Index = 0; Index < sizeof (UINT64); Index++) { MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index]; - Status = MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType - ); + Status = MtrrLibSetMemoryType ( + Ranges, + RangeCapacity, + RangeCount, + Base, + mMtrrLibFixedMtrrTable[MsrIndex].Length, + MemoryType + ); if (Status == RETURN_OUT_OF_RESOURCES) { return Status; } + Base += mMtrrLibFixedMtrrTable[MsrIndex].Length; } } + ASSERT (Base == BASE_1MB); return RETURN_SUCCESS; } @@ -1719,15 +1806,15 @@ MtrrLibApplyFixedMtrrs ( **/ RETURN_STATUS MtrrLibApplyVariableMtrrs ( - IN CONST MTRR_MEMORY_RANGE *VariableMtrr, - IN UINT32 VariableMtrrCount, - IN OUT MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCapacity, - IN OUT UINTN *RangeCount + IN CONST MTRR_MEMORY_RANGE *VariableMtrr, + IN UINT32 VariableMtrrCount, + IN OUT MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCapacity, + IN OUT UINTN *RangeCount ) { - RETURN_STATUS Status; - UINTN Index; + RETURN_STATUS Status; + UINTN Index; // // WT > WB @@ -1741,9 +1828,13 @@ MtrrLibApplyVariableMtrrs ( for (Index = 0; Index < VariableMtrrCount; Index++) { if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) { Status = MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type - ); + Ranges, + RangeCapacity, + RangeCount, + VariableMtrr[Index].BaseAddress, + VariableMtrr[Index].Length, + VariableMtrr[Index].Type + ); if (Status == RETURN_OUT_OF_RESOURCES) { return Status; } @@ -1755,10 +1846,15 @@ MtrrLibApplyVariableMtrrs ( // for (Index = 0; Index < VariableMtrrCount; Index++) { if ((VariableMtrr[Index].Length != 0) && - (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) { + (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) + { Status = MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type + Ranges, + RangeCapacity, + RangeCount, + VariableMtrr[Index].BaseAddress, + VariableMtrr[Index].Length, + VariableMtrr[Index].Type ); if (Status == RETURN_OUT_OF_RESOURCES) { return Status; @@ -1770,16 +1866,21 @@ MtrrLibApplyVariableMtrrs ( // 3. Set UC // for (Index = 0; Index < VariableMtrrCount; Index++) { - if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) { + if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheUncacheable)) { Status = MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type + Ranges, + RangeCapacity, + RangeCount, + VariableMtrr[Index].BaseAddress, + VariableMtrr[Index].Length, + VariableMtrr[Index].Type ); if (Status == RETURN_OUT_OF_RESOURCES) { return Status; } } } + return RETURN_SUCCESS; } @@ -1794,35 +1895,37 @@ MtrrLibApplyVariableMtrrs ( **/ UINT8 MtrrLibGetCompatibleTypes ( - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount ) { ASSERT (RangeCount != 0); switch (Ranges[0].Type) { - case CacheWriteBack: - case CacheWriteThrough: - return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable); - break; - - case CacheWriteCombining: - case CacheWriteProtected: - return (1 << Ranges[0].Type) | (1 << CacheUncacheable); - break; - - case CacheUncacheable: - if (RangeCount == 1) { - return (1 << CacheUncacheable); - } - return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1); - break; + case CacheWriteBack: + case CacheWriteThrough: + return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable); + break; + + case CacheWriteCombining: + case CacheWriteProtected: + return (1 << Ranges[0].Type) | (1 << CacheUncacheable); + break; + + case CacheUncacheable: + if (RangeCount == 1) { + return (1 << CacheUncacheable); + } - case CacheInvalid: - default: - ASSERT (FALSE); - break; + return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1); + break; + + case CacheInvalid: + default: + ASSERT (FALSE); + break; } + return 0; } @@ -1839,15 +1942,15 @@ MtrrLibGetCompatibleTypes ( **/ VOID MtrrLibMergeVariableMtrr ( - MTRR_MEMORY_RANGE *DstMtrrs, - UINT32 DstMtrrCount, - MTRR_MEMORY_RANGE *SrcMtrrs, - UINT32 SrcMtrrCount, - BOOLEAN *Modified + MTRR_MEMORY_RANGE *DstMtrrs, + UINT32 DstMtrrCount, + MTRR_MEMORY_RANGE *SrcMtrrs, + UINT32 SrcMtrrCount, + BOOLEAN *Modified ) { - UINT32 DstIndex; - UINT32 SrcIndex; + UINT32 DstIndex; + UINT32 SrcIndex; ASSERT (SrcMtrrCount <= DstMtrrCount); @@ -1857,10 +1960,12 @@ MtrrLibMergeVariableMtrr ( if (DstMtrrs[DstIndex].Length == 0) { continue; } + for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) { - if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress && - DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length && - DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) { + if ((DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress) && + (DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length) && + (DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type)) + { break; } } @@ -1870,7 +1975,7 @@ MtrrLibMergeVariableMtrr ( // Remove the one from DstMtrrs which is not in SrcMtrrs // DstMtrrs[DstIndex].Length = 0; - Modified[DstIndex] = TRUE; + Modified[DstIndex] = TRUE; } else { // // Remove the one from SrcMtrrs which is also in DstMtrrs @@ -1886,7 +1991,6 @@ MtrrLibMergeVariableMtrr ( DstIndex = 0; for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) { if (SrcMtrrs[SrcIndex].Length != 0) { - // // Find the empty slot in DstMtrrs // @@ -1894,8 +1998,10 @@ MtrrLibMergeVariableMtrr ( if (DstMtrrs[DstIndex].Length == 0) { break; } + DstIndex++; } + ASSERT (DstIndex < DstMtrrCount); CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0])); Modified[DstIndex] = TRUE; @@ -1924,27 +2030,27 @@ MtrrLibMergeVariableMtrr ( **/ RETURN_STATUS MtrrLibSetMemoryRanges ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT64 A0, - IN MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount, - IN VOID *Scratch, - IN OUT UINTN *ScratchSize, - OUT MTRR_MEMORY_RANGE *VariableMtrr, - IN UINT32 VariableMtrrCapacity, - OUT UINT32 *VariableMtrrCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + OUT MTRR_MEMORY_RANGE *VariableMtrr, + IN UINT32 VariableMtrrCapacity, + OUT UINT32 *VariableMtrrCount ) { - RETURN_STATUS Status; - UINT32 Index; - UINT64 Base0; - UINT64 Base1; - UINT64 Alignment; - UINT8 CompatibleTypes; - UINT64 Length; - UINT32 End; - UINTN ActualScratchSize; - UINTN BiggestScratchSize; + RETURN_STATUS Status; + UINT32 Index; + UINT64 Base0; + UINT64 Base1; + UINT64 Alignment; + UINT8 CompatibleTypes; + UINT64 Length; + UINT32 End; + UINTN ActualScratchSize; + UINTN BiggestScratchSize; *VariableMtrrCount = 0; @@ -1969,21 +2075,26 @@ MtrrLibSetMemoryRanges ( while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) { if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) { Status = MtrrLibAppendVariableMtrr ( - VariableMtrr, VariableMtrrCapacity, VariableMtrrCount, - Base0, Alignment, Ranges[Index].Type - ); + VariableMtrr, + VariableMtrrCapacity, + VariableMtrrCount, + Base0, + Alignment, + Ranges[Index].Type + ); if (RETURN_ERROR (Status)) { return Status; } } - Base0 += Alignment; + + Base0 += Alignment; Alignment = MtrrLibBiggestAlignment (Base0, A0); } // // Remove the above range from Ranges[Index] // - Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress; + Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress; Ranges[Index].BaseAddress = Base0; if (Ranges[Index].Length != 0) { break; @@ -2010,8 +2121,10 @@ MtrrLibSetMemoryRanges ( if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) { break; } + End++; } + Alignment = MtrrLibBiggestAlignment (Base0, A0); Length = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0); Base1 = Base0 + MIN (Alignment, Length); @@ -2024,18 +2137,24 @@ MtrrLibSetMemoryRanges ( if (Base1 <= Ranges[End + 1].BaseAddress) { break; } + End++; } - Length = Ranges[End].Length; + Length = Ranges[End].Length; Ranges[End].Length = Base1 - Ranges[End].BaseAddress; ActualScratchSize = *ScratchSize; - Status = MtrrLibCalculateMtrrs ( - DefaultType, A0, - &Ranges[Index], End + 1 - Index, - Scratch, &ActualScratchSize, - VariableMtrr, VariableMtrrCapacity, VariableMtrrCount - ); + Status = MtrrLibCalculateMtrrs ( + DefaultType, + A0, + &Ranges[Index], + End + 1 - Index, + Scratch, + &ActualScratchSize, + VariableMtrr, + VariableMtrrCapacity, + VariableMtrrCount + ); if (Status == RETURN_BUFFER_TOO_SMALL) { BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize); // @@ -2044,14 +2163,15 @@ MtrrLibSetMemoryRanges ( // Status = RETURN_SUCCESS; } + if (RETURN_ERROR (Status)) { return Status; } if (Length != Ranges[End].Length) { Ranges[End].BaseAddress = Base1; - Ranges[End].Length = Length - Ranges[End].Length; - Index = End; + Ranges[End].Length = Length - Ranges[End].Length; + Index = End; } else { Index = End + 1; } @@ -2061,6 +2181,7 @@ MtrrLibSetMemoryRanges ( *ScratchSize = BiggestScratchSize; return RETURN_BUFFER_TOO_SMALL; } + return RETURN_SUCCESS; } @@ -2080,17 +2201,17 @@ MtrrLibSetMemoryRanges ( **/ RETURN_STATUS MtrrLibSetBelow1MBMemoryAttribute ( - IN OUT UINT64 *ClearMasks, - IN OUT UINT64 *OrMasks, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type + IN OUT UINT64 *ClearMasks, + IN OUT UINT64 *OrMasks, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN MTRR_MEMORY_CACHE_TYPE Type ) { - RETURN_STATUS Status; - UINT32 MsrIndex; - UINT64 ClearMask; - UINT64 OrMask; + RETURN_STATUS Status; + UINT32 MsrIndex; + UINT64 ClearMask; + UINT64 OrMask; ASSERT (BaseAddress < BASE_1MB); @@ -2100,9 +2221,11 @@ MtrrLibSetBelow1MBMemoryAttribute ( if (RETURN_ERROR (Status)) { return Status; } + ClearMasks[MsrIndex] = ClearMasks[MsrIndex] | ClearMask; OrMasks[MsrIndex] = (OrMasks[MsrIndex] & ~ClearMask) | OrMask; } + return RETURN_SUCCESS; } @@ -2135,39 +2258,39 @@ MtrrLibSetBelow1MBMemoryAttribute ( RETURN_STATUS EFIAPI MtrrSetMemoryAttributesInMtrrSettings ( - IN OUT MTRR_SETTINGS *MtrrSetting, - IN VOID *Scratch, - IN OUT UINTN *ScratchSize, - IN CONST MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount + IN OUT MTRR_SETTINGS *MtrrSetting, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount ) { - RETURN_STATUS Status; - UINT32 Index; - UINT64 BaseAddress; - UINT64 Length; - BOOLEAN Above1MbExist; - - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - MTRR_MEMORY_CACHE_TYPE DefaultType; - MTRR_VARIABLE_SETTINGS VariableSettings; - MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2]; - UINTN WorkingRangeCount; - BOOLEAN Modified; - MTRR_VARIABLE_SETTING VariableSetting; - UINT32 OriginalVariableMtrrCount; - UINT32 FirmwareVariableMtrrCount; - UINT32 WorkingVariableMtrrCount; - MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; - MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; - BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; - - UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)]; - UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)]; - - MTRR_CONTEXT MtrrContext; - BOOLEAN MtrrContextValid; + RETURN_STATUS Status; + UINT32 Index; + UINT64 BaseAddress; + UINT64 Length; + BOOLEAN Above1MbExist; + + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + MTRR_MEMORY_CACHE_TYPE DefaultType; + MTRR_VARIABLE_SETTINGS VariableSettings; + MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2]; + UINTN WorkingRangeCount; + BOOLEAN Modified; + MTRR_VARIABLE_SETTING VariableSetting; + UINT32 OriginalVariableMtrrCount; + UINT32 FirmwareVariableMtrrCount; + UINT32 WorkingVariableMtrrCount; + MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; + MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; + BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)]; + + UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)]; + UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)]; + + MTRR_CONTEXT MtrrContext; + BOOLEAN MtrrContextValid; Status = RETURN_SUCCESS; MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); @@ -2187,16 +2310,23 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 0. Dump the requests. // DEBUG_CODE_BEGIN (); - DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a", - (MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize, - (RangeCount <= 1) ? "," : "\n" - )); - for (Index = 0; Index < RangeCount; Index++) { - DEBUG ((DEBUG_CACHE, " %a: [%016lx, %016lx)\n", - mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)], - Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - )); - } + DEBUG (( + DEBUG_CACHE, + "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a", + (MtrrSetting == NULL) ? "Hardware" : "Buffer", + *ScratchSize, + (RangeCount <= 1) ? "," : "\n" + )); + for (Index = 0; Index < RangeCount; Index++) { + DEBUG (( + DEBUG_CACHE, + " %a: [%016lx, %016lx)\n", + mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)], + Ranges[Index].BaseAddress, + Ranges[Index].BaseAddress + Ranges[Index].Length + )); + } + DEBUG_CODE_END (); // @@ -2212,10 +2342,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( Status = RETURN_INVALID_PARAMETER; goto Exit; } + if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) || ((((Ranges[Index].BaseAddress + Ranges[Index].Length) & ~MtrrValidAddressMask) != 0) && - (Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1) - ) { + ((Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1)) + ) + { // // Either the BaseAddress or the Limit doesn't follow the alignment requirement. // Note: It's still valid if Limit doesn't follow the alignment requirement but equals to MAX Address. @@ -2223,14 +2355,17 @@ MtrrSetMemoryAttributesInMtrrSettings ( Status = RETURN_UNSUPPORTED; goto Exit; } + if ((Ranges[Index].Type != CacheUncacheable) && (Ranges[Index].Type != CacheWriteCombining) && (Ranges[Index].Type != CacheWriteThrough) && (Ranges[Index].Type != CacheWriteProtected) && - (Ranges[Index].Type != CacheWriteBack)) { + (Ranges[Index].Type != CacheWriteBack)) + { Status = RETURN_INVALID_PARAMETER; goto Exit; } + if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) { Above1MbExist = TRUE; } @@ -2246,19 +2381,26 @@ MtrrSetMemoryAttributesInMtrrSettings ( OriginalVariableMtrrCount = GetVariableMtrrCountWorker (); MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings); MtrrLibGetRawVariableRanges ( - &VariableSettings, OriginalVariableMtrrCount, - MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr + &VariableSettings, + OriginalVariableMtrrCount, + MtrrValidBitsMask, + MtrrValidAddressMask, + OriginalVariableMtrr ); - DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting); - WorkingRangeCount = 1; + DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting); + WorkingRangeCount = 1; WorkingRanges[0].BaseAddress = 0; WorkingRanges[0].Length = MtrrValidBitsMask + 1; WorkingRanges[0].Type = DefaultType; Status = MtrrLibApplyVariableMtrrs ( - OriginalVariableMtrr, OriginalVariableMtrrCount, - WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount); + OriginalVariableMtrr, + OriginalVariableMtrrCount, + WorkingRanges, + ARRAY_SIZE (WorkingRanges), + &WorkingRangeCount + ); ASSERT_RETURN_ERROR (Status); ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs)); @@ -2269,8 +2411,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm. // Status = MtrrLibSetMemoryType ( - WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount, - 0, SIZE_1MB, CacheUncacheable + WorkingRanges, + ARRAY_SIZE (WorkingRanges), + &WorkingRangeCount, + 0, + SIZE_1MB, + CacheUncacheable ); ASSERT (Status != RETURN_OUT_OF_RESOURCES); @@ -2280,17 +2426,23 @@ MtrrSetMemoryAttributesInMtrrSettings ( Modified = FALSE; for (Index = 0; Index < RangeCount; Index++) { BaseAddress = Ranges[Index].BaseAddress; - Length = Ranges[Index].Length; + Length = Ranges[Index].Length; if (BaseAddress < BASE_1MB) { if (Length <= BASE_1MB - BaseAddress) { continue; } - Length -= BASE_1MB - BaseAddress; + + Length -= BASE_1MB - BaseAddress; BaseAddress = BASE_1MB; } + Status = MtrrLibSetMemoryType ( - WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount, - BaseAddress, Length, Ranges[Index].Type + WorkingRanges, + ARRAY_SIZE (WorkingRanges), + &WorkingRangeCount, + BaseAddress, + Length, + Ranges[Index].Type ); if (Status == RETURN_ALREADY_STARTED) { Status = RETURN_SUCCESS; @@ -2308,9 +2460,15 @@ MtrrSetMemoryAttributesInMtrrSettings ( // Buffer Too Small may be returned if the scratch buffer size is insufficient. // Status = MtrrLibSetMemoryRanges ( - DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount, - Scratch, ScratchSize, - WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount + DefaultType, + LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), + WorkingRanges, + WorkingRangeCount, + Scratch, + ScratchSize, + WorkingVariableMtrr, + FirmwareVariableMtrrCount + 1, + &WorkingVariableMtrrCount ); if (RETURN_ERROR (Status)) { goto Exit; @@ -2320,11 +2478,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range) // for (Index = 0; Index < WorkingVariableMtrrCount; Index++) { - if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) { + if ((WorkingVariableMtrr[Index].BaseAddress == 0) && (WorkingVariableMtrr[Index].Length == SIZE_1MB)) { ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable); WorkingVariableMtrrCount--; CopyMem ( - &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1], + &WorkingVariableMtrr[Index], + &WorkingVariableMtrr[Index + 1], (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0]) ); break; @@ -2341,10 +2500,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // Make sure least modification is made to OriginalVariableMtrr. // MtrrLibMergeVariableMtrr ( - OriginalVariableMtrr, OriginalVariableMtrrCount, - WorkingVariableMtrr, WorkingVariableMtrrCount, + OriginalVariableMtrr, + OriginalVariableMtrrCount, + WorkingVariableMtrr, + WorkingVariableMtrrCount, VariableSettingModified - ); + ); } } @@ -2361,8 +2522,11 @@ MtrrSetMemoryAttributesInMtrrSettings ( } Status = MtrrLibSetBelow1MBMemoryAttribute ( - ClearMasks, OrMasks, - Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type + ClearMasks, + OrMasks, + Ranges[Index].BaseAddress, + Ranges[Index].Length, + Ranges[Index].Type ); if (RETURN_ERROR (Status)) { goto Exit; @@ -2382,6 +2546,7 @@ MtrrSetMemoryAttributesInMtrrSettings ( MtrrLibPreMtrrChange (&MtrrContext); MtrrContextValid = TRUE; } + AsmMsrAndThenOr64 (mMtrrLibFixedMtrrTable[Index].Msr, ~ClearMasks[Index], OrMasks[Index]); } } @@ -2394,12 +2559,13 @@ MtrrSetMemoryAttributesInMtrrSettings ( if (VariableSettingModified[Index]) { if (OriginalVariableMtrr[Index].Length != 0) { VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask) - | (UINT8)OriginalVariableMtrr[Index].Type; + | (UINT8)OriginalVariableMtrr[Index].Type; VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11; } else { VariableSetting.Base = 0; VariableSetting.Mask = 0; } + if (MtrrSetting != NULL) { CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting)); } else { @@ -2407,20 +2573,21 @@ MtrrSetMemoryAttributesInMtrrSettings ( MtrrLibPreMtrrChange (&MtrrContext); MtrrContextValid = TRUE; } + AsmWriteMsr64 ( MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting.Base - ); + ); AsmWriteMsr64 ( MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting.Mask - ); + ); } } } if (MtrrSetting != NULL) { - ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1; + ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1; ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1; } else { if (MtrrContextValid) { @@ -2433,6 +2600,7 @@ Exit: if (!RETURN_ERROR (Status)) { MtrrDebugPrintAllMtrrsWorker (MtrrSetting); } + return Status; } @@ -2474,14 +2642,14 @@ MtrrSetMemoryAttributeInMtrrSettings ( IN MTRR_MEMORY_CACHE_TYPE Attribute ) { - UINT8 Scratch[SCRATCH_BUFFER_SIZE]; - UINTN ScratchSize; - MTRR_MEMORY_RANGE Range; + UINT8 Scratch[SCRATCH_BUFFER_SIZE]; + UINTN ScratchSize; + MTRR_MEMORY_RANGE Range; Range.BaseAddress = BaseAddress; Range.Length = Length; Range.Type = Attribute; - ScratchSize = sizeof (Scratch); + ScratchSize = sizeof (Scratch); return MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1); } @@ -2537,7 +2705,7 @@ MtrrSetMemoryAttribute ( **/ VOID MtrrSetVariableMtrrWorker ( - IN MTRR_VARIABLE_SETTINGS *VariableSettings + IN MTRR_VARIABLE_SETTINGS *VariableSettings ) { UINT32 Index; @@ -2566,20 +2734,19 @@ MtrrSetVariableMtrrWorker ( **/ VOID MtrrSetFixedMtrrWorker ( - IN MTRR_FIXED_SETTINGS *FixedSettings + IN MTRR_FIXED_SETTINGS *FixedSettings ) { UINT32 Index; for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - AsmWriteMsr64 ( - mMtrrLibFixedMtrrTable[Index].Msr, - FixedSettings->Mtrr[Index] - ); + AsmWriteMsr64 ( + mMtrrLibFixedMtrrTable[Index].Msr, + FixedSettings->Mtrr[Index] + ); } } - /** This function gets the content in all MTRRs (variable and fixed) @@ -2591,7 +2758,7 @@ MtrrSetFixedMtrrWorker ( MTRR_SETTINGS * EFIAPI MtrrGetAllMtrrs ( - OUT MTRR_SETTINGS *MtrrSetting + OUT MTRR_SETTINGS *MtrrSetting ) { if (!IsMtrrSupported ()) { @@ -2620,7 +2787,6 @@ MtrrGetAllMtrrs ( return MtrrSetting; } - /** This function sets all MTRRs (variable and fixed) @@ -2632,7 +2798,7 @@ MtrrGetAllMtrrs ( MTRR_SETTINGS * EFIAPI MtrrSetAllMtrrs ( - IN MTRR_SETTINGS *MtrrSetting + IN MTRR_SETTINGS *MtrrSetting ) { MTRR_CONTEXT MtrrContext; @@ -2663,7 +2829,6 @@ MtrrSetAllMtrrs ( return MtrrSetting; } - /** Checks if MTRR is supported. @@ -2677,8 +2842,8 @@ IsMtrrSupported ( VOID ) { - CPUID_VERSION_INFO_EDX Edx; - MSR_IA32_MTRRCAP_REGISTER MtrrCap; + CPUID_VERSION_INFO_EDX Edx; + MSR_IA32_MTRRCAP_REGISTER MtrrCap; // // Check CPUID(1).EDX[12] for MTRR capability @@ -2697,10 +2862,10 @@ IsMtrrSupported ( if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) { return FALSE; } + return TRUE; } - /** Worker function prints all MTRRs for debugging. @@ -2712,93 +2877,109 @@ IsMtrrSupported ( **/ VOID MtrrDebugPrintAllMtrrsWorker ( - IN MTRR_SETTINGS *MtrrSetting + IN MTRR_SETTINGS *MtrrSetting ) { DEBUG_CODE_BEGIN (); - MTRR_SETTINGS LocalMtrrs; - MTRR_SETTINGS *Mtrrs; - UINTN Index; - UINTN RangeCount; - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - UINT32 VariableMtrrCount; - BOOLEAN ContainVariableMtrr; - MTRR_MEMORY_RANGE Ranges[ - ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1 - ]; - MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)]; - - if (!IsMtrrSupported ()) { - return; - } + MTRR_SETTINGS LocalMtrrs; + MTRR_SETTINGS *Mtrrs; + UINTN Index; + UINTN RangeCount; + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + UINT32 VariableMtrrCount; + BOOLEAN ContainVariableMtrr; + MTRR_MEMORY_RANGE Ranges[ + ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1 + ]; + MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)]; - VariableMtrrCount = GetVariableMtrrCountWorker (); + if (!IsMtrrSupported ()) { + return; + } - if (MtrrSetting != NULL) { - Mtrrs = MtrrSetting; - } else { - MtrrGetAllMtrrs (&LocalMtrrs); - Mtrrs = &LocalMtrrs; - } + VariableMtrrCount = GetVariableMtrrCountWorker (); - // - // Dump RAW MTRR contents - // - DEBUG ((DEBUG_CACHE, "MTRR Settings:\n")); - DEBUG ((DEBUG_CACHE, "=============\n")); - DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType)); - for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) { - DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index])); - } - ContainVariableMtrr = FALSE; - for (Index = 0; Index < VariableMtrrCount; Index++) { - if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) { - // - // If mask is not valid, then do not display range - // - continue; - } - ContainVariableMtrr = TRUE; - DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n", - Index, - Mtrrs->Variables.Mtrr[Index].Base, - Mtrrs->Variables.Mtrr[Index].Mask - )); - } - if (!ContainVariableMtrr) { - DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n")); + if (MtrrSetting != NULL) { + Mtrrs = MtrrSetting; + } else { + MtrrGetAllMtrrs (&LocalMtrrs); + Mtrrs = &LocalMtrrs; + } + + // + // Dump RAW MTRR contents + // + DEBUG ((DEBUG_CACHE, "MTRR Settings:\n")); + DEBUG ((DEBUG_CACHE, "=============\n")); + DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType)); + for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) { + DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index])); + } + + ContainVariableMtrr = FALSE; + for (Index = 0; Index < VariableMtrrCount; Index++) { + if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) { + // + // If mask is not valid, then do not display range + // + continue; } - DEBUG((DEBUG_CACHE, "\n")); - // - // Dump MTRR setting in ranges - // - DEBUG((DEBUG_CACHE, "Memory Ranges:\n")); - DEBUG((DEBUG_CACHE, "====================================\n")); - MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); - Ranges[0].BaseAddress = 0; - Ranges[0].Length = MtrrValidBitsMask + 1; - Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs); - RangeCount = 1; + ContainVariableMtrr = TRUE; + DEBUG (( + DEBUG_CACHE, + "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n", + Index, + Mtrrs->Variables.Mtrr[Index].Base, + Mtrrs->Variables.Mtrr[Index].Mask + )); + } - MtrrLibGetRawVariableRanges ( - &Mtrrs->Variables, VariableMtrrCount, - MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges - ); - MtrrLibApplyVariableMtrrs ( - RawVariableRanges, VariableMtrrCount, - Ranges, ARRAY_SIZE (Ranges), &RangeCount - ); + if (!ContainVariableMtrr) { + DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n")); + } - MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount); + DEBUG ((DEBUG_CACHE, "\n")); + + // + // Dump MTRR setting in ranges + // + DEBUG ((DEBUG_CACHE, "Memory Ranges:\n")); + DEBUG ((DEBUG_CACHE, "====================================\n")); + MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); + Ranges[0].BaseAddress = 0; + Ranges[0].Length = MtrrValidBitsMask + 1; + Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs); + RangeCount = 1; + + MtrrLibGetRawVariableRanges ( + &Mtrrs->Variables, + VariableMtrrCount, + MtrrValidBitsMask, + MtrrValidAddressMask, + RawVariableRanges + ); + MtrrLibApplyVariableMtrrs ( + RawVariableRanges, + VariableMtrrCount, + Ranges, + ARRAY_SIZE (Ranges), + &RangeCount + ); + + MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount); + + for (Index = 0; Index < RangeCount; Index++) { + DEBUG (( + DEBUG_CACHE, + "%a:%016lx-%016lx\n", + mMtrrMemoryCacheTypeShortName[Ranges[Index].Type], + Ranges[Index].BaseAddress, + Ranges[Index].BaseAddress + Ranges[Index].Length - 1 + )); + } - for (Index = 0; Index < RangeCount; Index++) { - DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n", - mMtrrMemoryCacheTypeShortName[Ranges[Index].Type], - Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1 - )); - } DEBUG_CODE_END (); } diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c index e84b939060..b9a97dee09 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c @@ -8,11 +8,11 @@ #include "MtrrLibUnitTest.h" -STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = { +STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = { 42, TRUE, TRUE, CacheUncacheable, 12 }; -STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = { +STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = { { 38, TRUE, TRUE, CacheUncacheable, 12 }, { 38, TRUE, TRUE, CacheWriteBack, 12 }, { 38, TRUE, TRUE, CacheWriteThrough, 12 }, @@ -32,7 +32,7 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = { { 48, TRUE, TRUE, CacheWriteCombining, 12 }, }; -UINT32 mFixedMtrrsIndex[] = { +UINT32 mFixedMtrrsIndex[] = { MSR_IA32_MTRR_FIX64K_00000, MSR_IA32_MTRR_FIX16K_80000, MSR_IA32_MTRR_FIX16K_A0000, @@ -54,18 +54,18 @@ STATIC_ASSERT ( // Context structure to be used for most of the test cases. // typedef struct { - CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; + CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; } MTRR_LIB_TEST_CONTEXT; // // Context structure to be used for GetFirmwareVariableMtrrCount() test. // typedef struct { - UINT32 NumberOfReservedVariableMtrrs; - CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; + UINT32 NumberOfReservedVariableMtrrs; + CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; } MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT; -STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" }; +STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" }; /** Compare the actual memory ranges against expected memory ranges and return PASS when they match. @@ -87,6 +87,7 @@ VerifyMemoryRanges ( ) { UINTN Index; + UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount); for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) { UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress); @@ -105,11 +106,12 @@ VerifyMemoryRanges ( **/ VOID DumpMemoryRanges ( - MTRR_MEMORY_RANGE *Ranges, - UINTN RangeCount + MTRR_MEMORY_RANGE *Ranges, + UINTN RangeCount ) { - UINTN Index; + UINTN Index; + for (Index = 0; Index < RangeCount; Index++) { UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]); } @@ -130,17 +132,17 @@ DumpMemoryRanges ( **/ VOID GenerateRandomMemoryTypeCombination ( - IN UINT32 TotalCount, - OUT UINT32 *UcCount, - OUT UINT32 *WtCount, - OUT UINT32 *WbCount, - OUT UINT32 *WpCount, - OUT UINT32 *WcCount + IN UINT32 TotalCount, + OUT UINT32 *UcCount, + OUT UINT32 *WtCount, + OUT UINT32 *WbCount, + OUT UINT32 *WpCount, + OUT UINT32 *WcCount ) { - UINTN Index; - UINT32 TotalMtrrCount; - UINT32 *CountPerType[5]; + UINTN Index; + UINT32 TotalMtrrCount; + UINT32 *CountPerType[5]; CountPerType[0] = UcCount; CountPerType[1] = WtCount; @@ -183,38 +185,47 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( IN UNIT_TEST_CONTEXT Context ) { - CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; - RETURN_STATUS Status; - UINT32 UcCount; - UINT32 WtCount; - UINT32 WbCount; - UINT32 WpCount; - UINT32 WcCount; - - UINT32 MtrrIndex; - UINT8 *Scratch; - UINTN ScratchSize; - MTRR_SETTINGS LocalMtrrs; - - MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; - MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; - UINT32 ExpectedVariableMtrrUsage; - UINTN ExpectedMemoryRangesCount; - - MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; - UINT32 ActualVariableMtrrUsage; - UINTN ActualMemoryRangesCount; - - MTRR_SETTINGS *Mtrrs[2]; - - SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; + CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; + RETURN_STATUS Status; + UINT32 UcCount; + UINT32 WtCount; + UINT32 WbCount; + UINT32 WpCount; + UINT32 WcCount; + + UINT32 MtrrIndex; + UINT8 *Scratch; + UINTN ScratchSize; + MTRR_SETTINGS LocalMtrrs; + + MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; + MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; + UINT32 ExpectedVariableMtrrUsage; + UINTN ExpectedMemoryRangesCount; + + MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; + UINT32 ActualVariableMtrrUsage; + UINTN ActualMemoryRangesCount; + + MTRR_SETTINGS *Mtrrs[2]; + + SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context; GenerateRandomMemoryTypeCombination ( SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), - &UcCount, &WtCount, &WbCount, &WpCount, &WcCount + &UcCount, + &WtCount, + &WbCount, + &WpCount, + &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, RawMtrrRange, - UcCount, WtCount, WbCount, WpCount, WcCount + SystemParameter->PhysicalAddressBits, + RawMtrrRange, + UcCount, + WtCount, + WbCount, + WpCount, + WcCount ); ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; @@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, - RawMtrrRange, ExpectedVariableMtrrUsage, - ExpectedMemoryRanges, &ExpectedMemoryRangesCount + RawMtrrRange, + ExpectedVariableMtrrUsage, + ExpectedMemoryRanges, + &ExpectedMemoryRangesCount ); UT_LOG_INFO ( "Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n", - ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount + ExpectedVariableMtrrUsage, + UcCount, + WtCount, + WbCount, + WpCount, + WcCount ); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount); @@ -244,21 +262,28 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( for (MtrrIndex = 0; MtrrIndex < ARRAY_SIZE (Mtrrs); MtrrIndex++) { Scratch = calloc (ScratchSize, sizeof (UINT8)); - Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); + Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); if (Status == RETURN_BUFFER_TOO_SMALL) { Scratch = realloc (Scratch, ScratchSize); - Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); + Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); } + UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS); if (Mtrrs[MtrrIndex] == NULL) { ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); MtrrGetAllMtrrs (&LocalMtrrs); } + ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( - SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, - &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage + SystemParameter->DefaultCacheType, + SystemParameter->PhysicalAddressBits, + SystemParameter->VariableMtrrCount, + &LocalMtrrs, + ActualMemoryRanges, + &ActualMemoryRangesCount, + &ActualVariableMtrrUsage ); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); @@ -284,20 +309,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( UNIT_TEST_STATUS EFIAPI UnitTestInvalidMemoryLayouts ( - IN UNIT_TEST_CONTEXT Context + IN UNIT_TEST_CONTEXT Context ) { - CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; - MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1]; - UINTN RangeCount; - UINT64 MaxAddress; - UINT32 Index; - UINT64 BaseAddress; - UINT64 Length; - RETURN_STATUS Status; - UINTN ScratchSize; - - SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; + CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; + MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1]; + UINTN RangeCount; + UINT64 MaxAddress; + UINT32 Index; + UINT64 BaseAddress; + UINT64 Length; + RETURN_STATUS Status; + UINTN ScratchSize; + + SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context; RangeCount = Random32 (1, ARRAY_SIZE (Ranges)); MaxAddress = 1ull << SystemParameter->PhysicalAddressBits; @@ -313,13 +338,15 @@ UnitTestInvalidMemoryLayouts ( Ranges[Index].Type = GenerateRandomCacheType (); Status = MtrrSetMemoryAttribute ( - Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type - ); + Ranges[Index].BaseAddress, + Ranges[Index].Length, + Ranges[Index].Type + ); UT_ASSERT_TRUE (RETURN_ERROR (Status)); } ScratchSize = 0; - Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount); + Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount); UT_ASSERT_TRUE (RETURN_ERROR (Status)); return UNIT_TEST_PASSED; @@ -344,7 +371,7 @@ UnitTestIsMtrrSupported ( MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_TEST_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); // @@ -357,8 +384,8 @@ UnitTestIsMtrrSupported ( // // MTRR capability on in CPUID leaf, but no variable or fixed MTRRs. // - SystemParameter.MtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = 0; + SystemParameter.MtrrSupported = TRUE; + SystemParameter.VariableMtrrCount = 0; SystemParameter.FixedMtrrSupported = FALSE; InitializeMtrrRegs (&SystemParameter); UT_ASSERT_FALSE (IsMtrrSupported ()); @@ -366,8 +393,8 @@ UnitTestIsMtrrSupported ( // // MTRR capability on in CPUID leaf, but no variable MTRRs. // - SystemParameter.MtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = 0; + SystemParameter.MtrrSupported = TRUE; + SystemParameter.VariableMtrrCount = 0; SystemParameter.FixedMtrrSupported = TRUE; InitializeMtrrRegs (&SystemParameter); UT_ASSERT_FALSE (IsMtrrSupported ()); @@ -375,8 +402,8 @@ UnitTestIsMtrrSupported ( // // MTRR capability on in CPUID leaf, but no fixed MTRRs. // - SystemParameter.MtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = 7; + SystemParameter.MtrrSupported = TRUE; + SystemParameter.VariableMtrrCount = 7; SystemParameter.FixedMtrrSupported = FALSE; InitializeMtrrRegs (&SystemParameter); UT_ASSERT_FALSE (IsMtrrSupported ()); @@ -384,8 +411,8 @@ UnitTestIsMtrrSupported ( // // MTRR capability on in CPUID leaf with both variable and fixed MTRRs. // - SystemParameter.MtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = 7; + SystemParameter.MtrrSupported = TRUE; + SystemParameter.VariableMtrrCount = 7; SystemParameter.FixedMtrrSupported = TRUE; InitializeMtrrRegs (&SystemParameter); UT_ASSERT_TRUE (IsMtrrSupported ()); @@ -409,11 +436,11 @@ UnitTestGetVariableMtrrCount ( IN UNIT_TEST_CONTEXT Context ) { - UINT32 Result; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_LIB_TEST_CONTEXT *LocalContext; + UINT32 Result; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_LIB_TEST_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); // @@ -445,7 +472,7 @@ UnitTestGetVariableMtrrCount ( InitializeMtrrRegs (&SystemParameter); UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL); - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.VariableMtrrCount = MAX_UINT8; InitializeMtrrRegs (&SystemParameter); UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL); @@ -469,12 +496,12 @@ UnitTestGetFirmwareVariableMtrrCount ( IN UNIT_TEST_CONTEXT Context ) { - UINT32 Result; - UINT32 ReservedMtrrs; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; + UINT32 Result; + UINT32 ReservedMtrrs; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; + LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); @@ -516,7 +543,7 @@ UnitTestGetFirmwareVariableMtrrCount ( // // Negative test case when Fixed MTRRs are not supported // - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = FALSE; InitializeMtrrRegs (&SystemParameter); PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, 2); @@ -527,7 +554,7 @@ UnitTestGetFirmwareVariableMtrrCount ( // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // SystemParameter.FixedMtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; + SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; InitializeMtrrRegs (&SystemParameter); UT_EXPECT_ASSERT_FAILURE (GetFirmwareVariableMtrrCount (), NULL); @@ -569,17 +596,17 @@ UnitTestMtrrGetFixedMtrr ( IN UNIT_TEST_CONTEXT Context ) { - MTRR_FIXED_SETTINGS *Result; - MTRR_FIXED_SETTINGS ExpectedFixedSettings; - MTRR_FIXED_SETTINGS FixedSettings; - UINTN Index; - UINTN MsrIndex; - UINTN ByteIndex; - UINT64 MsrValue; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_LIB_TEST_CONTEXT *LocalContext; - - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + MTRR_FIXED_SETTINGS *Result; + MTRR_FIXED_SETTINGS ExpectedFixedSettings; + MTRR_FIXED_SETTINGS FixedSettings; + UINTN Index; + UINTN MsrIndex; + UINTN ByteIndex; + UINT64 MsrValue; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_LIB_TEST_CONTEXT *LocalContext; + + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); InitializeMtrrRegs (&SystemParameter); @@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr ( for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) { MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8); } + ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue; AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue); } @@ -631,18 +659,18 @@ UnitTestMtrrGetFixedMtrr ( UNIT_TEST_STATUS EFIAPI UnitTestMtrrGetAllMtrrs ( - IN UNIT_TEST_CONTEXT Context + IN UNIT_TEST_CONTEXT Context ) { - MTRR_SETTINGS *Result; - MTRR_SETTINGS Mtrrs; - MTRR_SETTINGS ExpectedMtrrs; - MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; - UINT32 Index; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_LIB_TEST_CONTEXT *LocalContext; + MTRR_SETTINGS *Result; + MTRR_SETTINGS Mtrrs; + MTRR_SETTINGS ExpectedMtrrs; + MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; + UINT32 Index; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_LIB_TEST_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); InitializeMtrrRegs (&SystemParameter); @@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs ( AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask); } + Result = MtrrGetAllMtrrs (&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount); @@ -671,7 +700,7 @@ UnitTestMtrrGetAllMtrrs ( // // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; InitializeMtrrRegs (&SystemParameter); UT_EXPECT_ASSERT_FAILURE (MtrrGetAllMtrrs (&Mtrrs), NULL); @@ -695,21 +724,21 @@ UnitTestMtrrSetAllMtrrs ( IN UNIT_TEST_CONTEXT Context ) { - MTRR_SETTINGS *Result; - MTRR_SETTINGS Mtrrs; - UINT32 Index; - MSR_IA32_MTRR_DEF_TYPE_REGISTER Default; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_LIB_TEST_CONTEXT *LocalContext; + MTRR_SETTINGS *Result; + MTRR_SETTINGS Mtrrs; + UINT32 Index; + MSR_IA32_MTRR_DEF_TYPE_REGISTER Default; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_LIB_TEST_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); InitializeMtrrRegs (&SystemParameter); - Default.Uint64 = 0; - Default.Bits.E = 1; - Default.Bits.FE = 1; + Default.Uint64 = 0; + Default.Bits.E = 1; + Default.Bits.FE = 1; Default.Bits.Type = GenerateRandomCacheType (); ZeroMem (&Mtrrs, sizeof (Mtrrs)); @@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs ( for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL); } + Result = MtrrSetAllMtrrs (&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); @@ -745,18 +775,18 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( IN UNIT_TEST_CONTEXT Context ) { - MTRR_LIB_TEST_CONTEXT *LocalContext; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - UINT32 Result; - MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR]; - VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; - UINT64 ValidMtrrBitsMask; - UINT64 ValidMtrrAddressMask; - UINT32 Index; - MSR_IA32_MTRR_PHYSBASE_REGISTER Base; - MSR_IA32_MTRR_PHYSMASK_REGISTER Mask; - - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + MTRR_LIB_TEST_CONTEXT *LocalContext; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + UINT32 Result; + MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR]; + VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; + UINT64 ValidMtrrBitsMask; + UINT64 ValidMtrrAddressMask; + UINT32 Index; + MSR_IA32_MTRR_PHYSBASE_REGISTER Base; + MSR_IA32_MTRR_PHYSMASK_REGISTER Mask; + + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); @@ -770,16 +800,17 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask); } + Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr); UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount); for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { Base.Uint64 = VariableMtrr[Index].BaseAddress; - Base.Bits.Type = (UINT32) VariableMtrr[Index].Type; + Base.Bits.Type = (UINT32)VariableMtrr[Index].Type; UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base); - Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask; - Mask.Bits.V = 1; + Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask; + Mask.Bits.V = 1; UT_ASSERT_EQUAL (Mask.Uint64, VariableSetting[Index].Mask); } @@ -794,7 +825,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( // // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; InitializeMtrrRegs (&SystemParameter); UT_EXPECT_ASSERT_FAILURE (MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr), NULL); @@ -837,11 +868,11 @@ UnitTestMtrrGetDefaultMemoryType ( IN UNIT_TEST_CONTEXT Context ) { - MTRR_LIB_TEST_CONTEXT *LocalContext; - UINTN Index; - MTRR_MEMORY_CACHE_TYPE Result; - MTRR_LIB_SYSTEM_PARAMETER SystemParameter; - MTRR_MEMORY_CACHE_TYPE CacheType[5]; + MTRR_LIB_TEST_CONTEXT *LocalContext; + UINTN Index; + MTRR_MEMORY_CACHE_TYPE Result; + MTRR_LIB_SYSTEM_PARAMETER SystemParameter; + MTRR_MEMORY_CACHE_TYPE CacheType[5]; CacheType[0] = CacheUncacheable; CacheType[1] = CacheWriteCombining; @@ -849,7 +880,7 @@ UnitTestMtrrGetDefaultMemoryType ( CacheType[3] = CacheWriteProtected; CacheType[4] = CacheWriteBack; - LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; + LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context; CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); // @@ -871,15 +902,15 @@ UnitTestMtrrGetDefaultMemoryType ( Result = MtrrGetDefaultMemoryType (); UT_ASSERT_EQUAL (Result, CacheUncacheable); - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = FALSE; InitializeMtrrRegs (&SystemParameter); Result = MtrrGetDefaultMemoryType (); UT_ASSERT_EQUAL (Result, CacheUncacheable); - SystemParameter.MtrrSupported = TRUE; + SystemParameter.MtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = TRUE; - SystemParameter.VariableMtrrCount = 0; + SystemParameter.VariableMtrrCount = 0; InitializeMtrrRegs (&SystemParameter); Result = MtrrGetDefaultMemoryType (); UT_ASSERT_EQUAL (Result, CacheUncacheable); @@ -903,37 +934,46 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( IN UNIT_TEST_CONTEXT Context ) { - CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; - RETURN_STATUS Status; - UINT32 UcCount; - UINT32 WtCount; - UINT32 WbCount; - UINT32 WpCount; - UINT32 WcCount; - - UINTN MtrrIndex; - UINTN Index; - MTRR_SETTINGS LocalMtrrs; - - MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; - MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; - UINT32 ExpectedVariableMtrrUsage; - UINTN ExpectedMemoryRangesCount; - - MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; - UINT32 ActualVariableMtrrUsage; - UINTN ActualMemoryRangesCount; - - MTRR_SETTINGS *Mtrrs[2]; - - SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; + CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; + RETURN_STATUS Status; + UINT32 UcCount; + UINT32 WtCount; + UINT32 WbCount; + UINT32 WpCount; + UINT32 WcCount; + + UINTN MtrrIndex; + UINTN Index; + MTRR_SETTINGS LocalMtrrs; + + MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; + MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; + UINT32 ExpectedVariableMtrrUsage; + UINTN ExpectedMemoryRangesCount; + + MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; + UINT32 ActualVariableMtrrUsage; + UINTN ActualMemoryRangesCount; + + MTRR_SETTINGS *Mtrrs[2]; + + SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context; GenerateRandomMemoryTypeCombination ( SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), - &UcCount, &WtCount, &WbCount, &WpCount, &WcCount + &UcCount, + &WtCount, + &WbCount, + &WpCount, + &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, RawMtrrRange, - UcCount, WtCount, WbCount, WpCount, WcCount + SystemParameter->PhysicalAddressBits, + RawMtrrRange, + UcCount, + WtCount, + WbCount, + WpCount, + WcCount ); ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; @@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, - RawMtrrRange, ExpectedVariableMtrrUsage, - ExpectedMemoryRanges, &ExpectedMemoryRangesCount + RawMtrrRange, + ExpectedVariableMtrrUsage, + ExpectedMemoryRanges, + &ExpectedMemoryRangesCount ); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); @@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ExpectedMemoryRanges[Index].Type ); UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL); - if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) { + if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) { return UNIT_TEST_SKIPPED; } } @@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); MtrrGetAllMtrrs (&LocalMtrrs); } + ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( - SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, - &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage + SystemParameter->DefaultCacheType, + SystemParameter->PhysicalAddressBits, + SystemParameter->VariableMtrrCount, + &LocalMtrrs, + ActualMemoryRanges, + &ActualMemoryRangesCount, + &ActualVariableMtrrUsage ); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount); @@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( return UNIT_TEST_PASSED; } - /** Prep routine for UnitTestGetFirmwareVariableMtrrCount(). @@ -1003,7 +1050,7 @@ SavePcdValue ( { MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; + LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context; LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs); return UNIT_TEST_PASSED; } @@ -1021,7 +1068,7 @@ RestorePcdValue ( { MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; - LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; + LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context; PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs); } @@ -1040,20 +1087,20 @@ STATIC EFI_STATUS EFIAPI UnitTestingEntry ( - UINTN Iteration + UINTN Iteration ) { - EFI_STATUS Status; - UNIT_TEST_FRAMEWORK_HANDLE Framework; - UNIT_TEST_SUITE_HANDLE MtrrApiTests; - UINTN Index; - UINTN SystemIndex; - MTRR_LIB_TEST_CONTEXT Context; - MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext; + EFI_STATUS Status; + UNIT_TEST_FRAMEWORK_HANDLE Framework; + UNIT_TEST_SUITE_HANDLE MtrrApiTests; + UINTN Index; + UINTN SystemIndex; + MTRR_LIB_TEST_CONTEXT Context; + MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext; Context.SystemParameter = &mDefaultSystemParameter; GetFirmwareVariableMtrrCountContext.SystemParameter = &mDefaultSystemParameter; - Framework = NULL; + Framework = NULL; // // Setup the test framework for running the tests. @@ -1077,24 +1124,26 @@ UnitTestingEntry ( Status = EFI_OUT_OF_RESOURCES; goto EXIT; } - AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext); - AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context); + + AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext); + AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttributeInVariableMtrr", "MtrrGetMemoryAttributeInVariableMtrr", UnitTestMtrrGetMemoryAttributeInVariableMtrr, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context); - AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context); + AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context); for (SystemIndex = 0; SystemIndex < ARRAY_SIZE (mSystemParameters); SystemIndex++) { for (Index = 0; Index < Iteration; Index++) { - AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); - AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); + AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); + AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); } } + // // Execute the tests. // @@ -1118,14 +1167,14 @@ EXIT: **/ INT32 main ( - INT32 Argc, - CHAR8 *Argv[] + INT32 Argc, + CHAR8 *Argv[] ) { - UINTN Count; + UINTN Count; DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION)); - srand ((unsigned int) time (NULL)); + srand ((unsigned int)time (NULL)); // // MtrrLibUnitTest generate-random-numbers diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h index 071c858a4c..57e656c555 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h @@ -29,21 +29,21 @@ #include #include -#define UNIT_TEST_APP_NAME "MtrrLib Unit Tests" -#define UNIT_TEST_APP_VERSION "1.0" +#define UNIT_TEST_APP_NAME "MtrrLib Unit Tests" +#define UNIT_TEST_APP_VERSION "1.0" -#define SCRATCH_BUFFER_SIZE SIZE_16KB +#define SCRATCH_BUFFER_SIZE SIZE_16KB typedef struct { - UINT8 PhysicalAddressBits; - BOOLEAN MtrrSupported; - BOOLEAN FixedMtrrSupported; - MTRR_MEMORY_CACHE_TYPE DefaultCacheType; - UINT32 VariableMtrrCount; + UINT8 PhysicalAddressBits; + BOOLEAN MtrrSupported; + BOOLEAN FixedMtrrSupported; + MTRR_MEMORY_CACHE_TYPE DefaultCacheType; + UINT32 VariableMtrrCount; } MTRR_LIB_SYSTEM_PARAMETER; -extern UINT32 mFixedMtrrsIndex[]; -extern BOOLEAN mRandomInput; +extern UINT32 mFixedMtrrsIndex[]; +extern BOOLEAN mRandomInput; /** Initialize the MTRR registers. @@ -64,7 +64,7 @@ InitializeMtrrRegs ( UNIT_TEST_STATUS EFIAPI InitializeSystem ( - IN UNIT_TEST_CONTEXT Context + IN UNIT_TEST_CONTEXT Context ); /** @@ -88,13 +88,13 @@ GenerateRandomCacheType ( **/ VOID GenerateValidAndConfigurableMtrrPairs ( - IN UINT32 PhysicalAddressBits, - IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 UcCount, - IN UINT32 WtCount, - IN UINT32 WbCount, - IN UINT32 WpCount, - IN UINT32 WcCount + IN UINT32 PhysicalAddressBits, + IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 UcCount, + IN UINT32 WtCount, + IN UINT32 WbCount, + IN UINT32 WpCount, + IN UINT32 WcCount ); /** @@ -109,12 +109,12 @@ GenerateValidAndConfigurableMtrrPairs ( **/ VOID GetEffectiveMemoryRanges ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT32 PhysicalAddressBits, - IN MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 RawMemoryRangeCount, - OUT MTRR_MEMORY_RANGE *MemoryRanges, - OUT UINTN *MemoryRangeCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT32 PhysicalAddressBits, + IN MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 RawMemoryRangeCount, + OUT MTRR_MEMORY_RANGE *MemoryRanges, + OUT UINTN *MemoryRangeCount ); /** @@ -127,10 +127,10 @@ GetEffectiveMemoryRanges ( **/ VOID GenerateRandomMtrrPair ( - IN UINT32 PhysicalAddressBits, - IN MTRR_MEMORY_CACHE_TYPE CacheType, - OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, - OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL + IN UINT32 PhysicalAddressBits, + IN MTRR_MEMORY_CACHE_TYPE CacheType, + OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, + OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL ); /** @@ -146,13 +146,13 @@ GenerateRandomMtrrPair ( **/ VOID CollectTestResult ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT32 PhysicalAddressBits, - IN UINT32 VariableMtrrCount, - IN MTRR_SETTINGS *Mtrrs, - OUT MTRR_MEMORY_RANGE *Ranges, - IN OUT UINTN *RangeCount, - OUT UINT32 *MtrrCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT32 PhysicalAddressBits, + IN UINT32 VariableMtrrCount, + IN MTRR_SETTINGS *Mtrrs, + OUT MTRR_MEMORY_RANGE *Ranges, + IN OUT UINTN *RangeCount, + OUT UINT32 *MtrrCount ); /** @@ -189,7 +189,8 @@ Random32 ( **/ VOID GenerateRandomNumbers ( - CHAR8 *FilePath, - UINTN Count + CHAR8 *FilePath, + UINTN Count ); + #endif diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c index 06104d8928..7190decc98 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c @@ -4,5006 +4,5006 @@ Copyright (c) 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -UINTN mNumberCount = 50000; -UINTN mNumbers[] = { - 7791, 9427, 6867, 23807, 10984, 16661, 1863, 16690, 14810, 14550, - 11382, 15755, 19806, 32737, 209, 14661, 4112, 13680, 2425, 15502, - 25268, 2882, 29953, 12346, 27936, 8942, 21365, 17849, 13910, 21879, - 3995, 6982, 2032, 6432, 3448, 28770, 8385, 31106, 4630, 32385, - 31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952, 25464, - 17, 12473, 28757, 19960, 27672, 1875, 17598, 20306, 22152, 15814, - 31841, 25276, 2962, 30223, 23953, 28748, 25029, 16399, 15868, 9993, - 31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870, 20065, 30191, - 3589, 13233, 27221, 15138, 26492, 20316, 13666, 15632, 180, 19954, - 25895, 3179, 21221, 474, 2111, 11252, 2588, 2556, 6338, 26862, - 19424, 3540, 6158, 6099, 20758, 32708, 6087, 2375, 22306, 22959, - 21532, 19274, 11343, 1987, 17228, 2737, 23409, 30102, 15977, 10455, +UINTN mNumberCount = 50000; +UINTN mNumbers[] = { + 7791, 9427, 6867, 23807, 10984, 16661, 1863, 16690, 14810, 14550, + 11382, 15755, 19806, 32737, 209, 14661, 4112, 13680, 2425, 15502, + 25268, 2882, 29953, 12346, 27936, 8942, 21365, 17849, 13910, 21879, + 3995, 6982, 2032, 6432, 3448, 28770, 8385, 31106, 4630, 32385, + 31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952, 25464, + 17, 12473, 28757, 19960, 27672, 1875, 17598, 20306, 22152, 15814, + 31841, 25276, 2962, 30223, 23953, 28748, 25029, 16399, 15868, 9993, + 31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870, 20065, 30191, + 3589, 13233, 27221, 15138, 26492, 20316, 13666, 15632, 180, 19954, + 25895, 3179, 21221, 474, 2111, 11252, 2588, 2556, 6338, 26862, + 19424, 3540, 6158, 6099, 20758, 32708, 6087, 2375, 22306, 22959, + 21532, 19274, 11343, 1987, 17228, 2737, 23409, 30102, 15977, 10455, 15049, 29045, 10077, 22928, 25128, 23033, 12330, 23902, 19543, 18906, - 10102, 11240, 10167, 13832, 28230, 8871, 6693, 12792, 31498, 3043, - 31776, 20028, 3546, 4574, 20270, 17751, 31231, 29263, 29563, 27343, - 10421, 1553, 24772, 4228, 14639, 28957, 26227, 22079, 25052, 3766, - 14092, 6030, 30441, 28131, 17095, 27600, 14855, 29218, 9599, 27788, + 10102, 11240, 10167, 13832, 28230, 8871, 6693, 12792, 31498, 3043, + 31776, 20028, 3546, 4574, 20270, 17751, 31231, 29263, 29563, 27343, + 10421, 1553, 24772, 4228, 14639, 28957, 26227, 22079, 25052, 3766, + 14092, 6030, 30441, 28131, 17095, 27600, 14855, 29218, 9599, 27788, 22382, 27739, 11210, 13831, 13345, 16403, 13162, 22037, 29044, 26850, - 27364, 7471, 18892, 29735, 13422, 1478, 10919, 17146, 12302, 9687, - 12252, 10338, 12545, 24256, 25635, 14280, 8794, 16210, 27351, 22444, - 7915, 19495, 30459, 27799, 16488, 8757, 13180, 12369, 27082, 10148, - 181, 2387, 4338, 16093, 11064, 30335, 19343, 12260, 32716, 25359, - 9025, 15335, 24754, 30412, 29951, 3863, 16429, 13952, 24502, 1206, - 9281, 2221, 1586, 29041, 6074, 29311, 10306, 26609, 11376, 8448, - 22295, 11181, 29386, 4747, 18670, 17922, 2689, 29827, 4079, 29061, - 12454, 2372, 14420, 20376, 28391, 10842, 4557, 7227, 20494, 15090, - 10275, 21541, 15818, 7821, 12060, 276, 27570, 2044, 26016, 8289, - 29575, 13448, 13337, 22487, 1721, 26481, 2592, 27845, 22829, 14746, - 16213, 12626, 10558, 4482, 31630, 23569, 2306, 22390, 27189, 32213, - 19662, 14853, 15595, 2503, 17148, 5813, 16753, 9141, 6379, 23284, - 3785, 10413, 4424, 29009, 3480, 9675, 28556, 3820, 24527, 12623, - 15558, 29995, 27530, 23026, 18843, 31663, 3385, 8315, 4491, 30343, + 27364, 7471, 18892, 29735, 13422, 1478, 10919, 17146, 12302, 9687, + 12252, 10338, 12545, 24256, 25635, 14280, 8794, 16210, 27351, 22444, + 7915, 19495, 30459, 27799, 16488, 8757, 13180, 12369, 27082, 10148, + 181, 2387, 4338, 16093, 11064, 30335, 19343, 12260, 32716, 25359, + 9025, 15335, 24754, 30412, 29951, 3863, 16429, 13952, 24502, 1206, + 9281, 2221, 1586, 29041, 6074, 29311, 10306, 26609, 11376, 8448, + 22295, 11181, 29386, 4747, 18670, 17922, 2689, 29827, 4079, 29061, + 12454, 2372, 14420, 20376, 28391, 10842, 4557, 7227, 20494, 15090, + 10275, 21541, 15818, 7821, 12060, 276, 27570, 2044, 26016, 8289, + 29575, 13448, 13337, 22487, 1721, 26481, 2592, 27845, 22829, 14746, + 16213, 12626, 10558, 4482, 31630, 23569, 2306, 22390, 27189, 32213, + 19662, 14853, 15595, 2503, 17148, 5813, 16753, 9141, 6379, 23284, + 3785, 10413, 4424, 29009, 3480, 9675, 28556, 3820, 24527, 12623, + 15558, 29995, 27530, 23026, 18843, 31663, 3385, 8315, 4491, 30343, 13565, 12173, 25462, 19619, 29525, 17859, 29534, 21131, 14585, 1535, - 14702, 15697, 19974, 8702, 16955, 16835, 17500, 4912, 21579, 13286, - 26948, 21959, 3796, 15008, 31319, 23054, 26053, 27573, 8603, 8189, - 7946, 25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008, - 25980, 22679, 23362, 9465, 24991, 29052, 30441, 29767, 3372, 8623, - 20476, 9542, 22984, 24662, 23773, 352, 9602, 9294, 17861, 10618, - 252, 8640, 31752, 24615, 8400, 1525, 22171, 17436, 32301, 9579, - 22483, 3813, 27329, 20520, 111, 11222, 7132, 16462, 21465, 15171, - 28882, 22256, 29097, 22004, 30881, 6948, 26731, 9427, 31443, 12121, - 9634, 8424, 1958, 12523, 9997, 3975, 21355, 13813, 20776, 3784, - 24876, 23911, 3830, 17976, 16529, 9560, 7934, 4046, 25348, 31645, - 12691, 11553, 19476, 15514, 15449, 23767, 8471, 5208, 9989, 25697, - 23572, 30168, 13668, 25062, 9696, 7335, 21151, 31356, 7046, 19635, - 8637, 14494, 748, 17501, 30569, 11995, 12980, 5327, 8438, 13003, - 12641, 21648, 7328, 17479, 20411, 24661, 10005, 29913, 17012, 7707, - 16948, 25458, 32523, 30322, 6420, 8283, 24561, 30748, 25928, 3438, - 21483, 22998, 14689, 3718, 7351, 20086, 21685, 7732, 24818, 24374, - 25695, 6836, 5433, 16464, 21895, 24351, 143, 21451, 7396, 31969, - 24574, 20116, 6014, 10606, 28033, 13264, 26809, 13361, 20002, 6769, - 31119, 6341, 11104, 28935, 32029, 360, 31699, 13273, 7777, 19885, + 14702, 15697, 19974, 8702, 16955, 16835, 17500, 4912, 21579, 13286, + 26948, 21959, 3796, 15008, 31319, 23054, 26053, 27573, 8603, 8189, + 7946, 25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008, + 25980, 22679, 23362, 9465, 24991, 29052, 30441, 29767, 3372, 8623, + 20476, 9542, 22984, 24662, 23773, 352, 9602, 9294, 17861, 10618, + 252, 8640, 31752, 24615, 8400, 1525, 22171, 17436, 32301, 9579, + 22483, 3813, 27329, 20520, 111, 11222, 7132, 16462, 21465, 15171, + 28882, 22256, 29097, 22004, 30881, 6948, 26731, 9427, 31443, 12121, + 9634, 8424, 1958, 12523, 9997, 3975, 21355, 13813, 20776, 3784, + 24876, 23911, 3830, 17976, 16529, 9560, 7934, 4046, 25348, 31645, + 12691, 11553, 19476, 15514, 15449, 23767, 8471, 5208, 9989, 25697, + 23572, 30168, 13668, 25062, 9696, 7335, 21151, 31356, 7046, 19635, + 8637, 14494, 748, 17501, 30569, 11995, 12980, 5327, 8438, 13003, + 12641, 21648, 7328, 17479, 20411, 24661, 10005, 29913, 17012, 7707, + 16948, 25458, 32523, 30322, 6420, 8283, 24561, 30748, 25928, 3438, + 21483, 22998, 14689, 3718, 7351, 20086, 21685, 7732, 24818, 24374, + 25695, 6836, 5433, 16464, 21895, 24351, 143, 21451, 7396, 31969, + 24574, 20116, 6014, 10606, 28033, 13264, 26809, 13361, 20002, 6769, + 31119, 6341, 11104, 28935, 32029, 360, 31699, 13273, 7777, 19885, 16147, 18741, 15170, 29041, 12501, 30724, 20688, 16399, 14167, 11425, - 31950, 30680, 4351, 32748, 14446, 8637, 1343, 13466, 12379, 6479, - 7355, 7887, 24060, 20714, 9390, 10734, 17912, 9772, 393, 28848, - 32757, 23212, 5342, 7027, 27558, 1257, 14973, 30933, 14084, 3457, - 8413, 1154, 6619, 3236, 189, 20554, 27273, 7111, 30730, 887, - 28674, 28573, 3076, 25693, 5400, 20035, 5789, 8242, 24826, 13755, - 8993, 17696, 22778, 18075, 32284, 8857, 12179, 18182, 31865, 1003, - 25770, 20956, 15847, 30996, 15124, 1582, 28289, 8663, 10073, 19189, - 19373, 12047, 7095, 31491, 28740, 3652, 21866, 3385, 11252, 29564, - 3883, 3323, 27107, 13651, 15607, 30433, 27285, 12110, 13585, 19887, - 21776, 7789, 27210, 31624, 25406, 11263, 7040, 21342, 11666, 6842, - 7269, 18093, 23022, 18955, 7041, 9065, 12741, 939, 2427, 28213, - 25469, 18291, 1428, 11477, 29463, 2417, 29556, 13542, 7697, 5691, - 7721, 21196, 13963, 4483, 3181, 23789, 14762, 17132, 27175, 1821, - 9530, 9500, 11061, 2648, 20631, 27411, 19305, 29879, 19661, 28603, - 20433, 13725, 4094, 17344, 27964, 14897, 28676, 19873, 30713, 11794, - 12376, 12296, 226, 13382, 10034, 27223, 17306, 11379, 15858, 26499, + 31950, 30680, 4351, 32748, 14446, 8637, 1343, 13466, 12379, 6479, + 7355, 7887, 24060, 20714, 9390, 10734, 17912, 9772, 393, 28848, + 32757, 23212, 5342, 7027, 27558, 1257, 14973, 30933, 14084, 3457, + 8413, 1154, 6619, 3236, 189, 20554, 27273, 7111, 30730, 887, + 28674, 28573, 3076, 25693, 5400, 20035, 5789, 8242, 24826, 13755, + 8993, 17696, 22778, 18075, 32284, 8857, 12179, 18182, 31865, 1003, + 25770, 20956, 15847, 30996, 15124, 1582, 28289, 8663, 10073, 19189, + 19373, 12047, 7095, 31491, 28740, 3652, 21866, 3385, 11252, 29564, + 3883, 3323, 27107, 13651, 15607, 30433, 27285, 12110, 13585, 19887, + 21776, 7789, 27210, 31624, 25406, 11263, 7040, 21342, 11666, 6842, + 7269, 18093, 23022, 18955, 7041, 9065, 12741, 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19113, 10190, + 18949, 14746, 7834, 28940, 24401, 26084, 6012, 18031, 29520, 28846, + 6404, 31077, 23561, 14586, 8959, 29717, 24144, 9813, 7318, 26520, 29491, 26797, 25808, 10854, 31893, 27235, 19544, 23310, 11545, 10401, - 23681, 6955, 10050, 26094, 3975, 30355, 6104, 27391, 24088, 19153, - 20365, 18896, 17938, 17110, 8160, 22260, 11919, 15083, 32578, 19754, - 19743, 8426, 14455, 20272, 28756, 9390, 10560, 15324, 21380, 19656, - 21559, 2152, 24522, 17267, 18938, 5390, 32334, 28619, 11659, 12244, - 24518, 12089, 22519, 14762, 23869, 17202, 24374, 8626, 22035, 18209, - 1107, 10975, 12102, 17057, 19661, 12225, 22511, 11248, 19260, 22687, - 30480, 28320, 23351, 30663, 9868, 19088, 21622, 34, 24439, 7963, - 31028, 18955, 31632, 30351, 9175, 6753, 28684, 26081, 30675, 8155, - 9622, 5279, 6604, 23196, 4499, 293, 13051, 8712, 29866, 21780, - 17362, 15573, 25220, 24064, 2531, 16229, 30416, 32361, 31998, 9299, - 23435, 10989, 10137, 21324, 1150, 18363, 24181, 2592, 17416, 31307, - 7039, 23576, 7453, 17229, 32757, 15243, 30351, 29919, 16841, 16812, - 5004, 22786, 2122, 10406, 30057, 7247, 31745, 11243, 2717, 20710, - 3545, 17096, 20241, 7592, 14724, 26942, 16791, 28070, 18201, 27405, - 21175, 13272, 20482, 25873, 12466, 5907, 2837, 28881, 5313, 6709, - 9217, 11862, 30110, 5283, 8684, 8249, 17221, 3829, 8538, 3584, - 4092, 22511, 25937, 24747, 19089, 26035, 955, 11657, 28131, 22326, - 12555, 25424, 18851, 10737, 28451, 19821, 18524, 30681, 9077, 24985, - 22193, 20880, 22633, 2989, 20455, 2269, 11775, 27575, 5027, 32602, - 15798, 14925, 10484, 19820, 30124, 18209, 4755, 21880, 12038, 17878, - 14442, 5972, 914, 23826, 2644, 22524, 9899, 11221, 16420, 29063, - 17758, 14601, 23272, 24409, 12747, 346, 19311, 23193, 24013, 5959, - 25096, 6886, 26845, 2425, 27533, 3909, 17715, 852, 8096, 9054, - 14383, 23501, 17461, 25833, 14840, 1659, 10833, 7523, 30819, 6896, - 26640, 13317, 278, 26185, 29677, 27638, 22253, 15108, 1342, 21184, - 30364, 29458, 24062, 29441, 3734, 22573, 25039, 8035, 28206, 26220, - 7743, 27085, 28668, 7445, 10315, 6875, 25475, 20914, 29474, 15756, - 14864, 14695, 1067, 4923, 31461, 7298, 10312, 977, 17047, 26708, - 3677, 24120, 20917, 4928, 27404, 32019, 28330, 1809, 2499, 9132, - 7909, 1424, 28409, 10029, 31543, 15191, 28596, 14356, 9084, 29920, - 25167, 24545, 5501, 10721, 19578, 1809, 27413, 21212, 12930, 5968, - 17299, 15601, 27603, 3563, 23648, 20472, 8379, 4740, 7394, 31436, - 21872, 26121, 6559, 14825, 9813, 15847, 21158, 27706, 6521, 24442, - 12587, 27180, 10592, 4040, 2161, 4871, 27911, 11120, 7661, 17534, - 290, 31453, 31912, 28805, 5800, 5823, 6117, 17762, 19089, 28860, - 260, 7175, 10975, 21602, 13478, 8351, 3291, 29793, 17170, 26983, - 6305, 22519, 22487, 28607, 11742, 15531, 25779, 8065, 1497, 16446, - 29620, 28817, 14000, 26335, 25757, 16053, 31716, 20894, 6539, 21415, - 26648, 14627, 22232, 22377, 25622, 160, 23104, 6873, 7955, 29956, + 23681, 6955, 10050, 26094, 3975, 30355, 6104, 27391, 24088, 19153, + 20365, 18896, 17938, 17110, 8160, 22260, 11919, 15083, 32578, 19754, + 19743, 8426, 14455, 20272, 28756, 9390, 10560, 15324, 21380, 19656, + 21559, 2152, 24522, 17267, 18938, 5390, 32334, 28619, 11659, 12244, + 24518, 12089, 22519, 14762, 23869, 17202, 24374, 8626, 22035, 18209, + 1107, 10975, 12102, 17057, 19661, 12225, 22511, 11248, 19260, 22687, + 30480, 28320, 23351, 30663, 9868, 19088, 21622, 34, 24439, 7963, + 31028, 18955, 31632, 30351, 9175, 6753, 28684, 26081, 30675, 8155, + 9622, 5279, 6604, 23196, 4499, 293, 13051, 8712, 29866, 21780, + 17362, 15573, 25220, 24064, 2531, 16229, 30416, 32361, 31998, 9299, + 23435, 10989, 10137, 21324, 1150, 18363, 24181, 2592, 17416, 31307, + 7039, 23576, 7453, 17229, 32757, 15243, 30351, 29919, 16841, 16812, + 5004, 22786, 2122, 10406, 30057, 7247, 31745, 11243, 2717, 20710, + 3545, 17096, 20241, 7592, 14724, 26942, 16791, 28070, 18201, 27405, + 21175, 13272, 20482, 25873, 12466, 5907, 2837, 28881, 5313, 6709, + 9217, 11862, 30110, 5283, 8684, 8249, 17221, 3829, 8538, 3584, + 4092, 22511, 25937, 24747, 19089, 26035, 955, 11657, 28131, 22326, + 12555, 25424, 18851, 10737, 28451, 19821, 18524, 30681, 9077, 24985, + 22193, 20880, 22633, 2989, 20455, 2269, 11775, 27575, 5027, 32602, + 15798, 14925, 10484, 19820, 30124, 18209, 4755, 21880, 12038, 17878, + 14442, 5972, 914, 23826, 2644, 22524, 9899, 11221, 16420, 29063, + 17758, 14601, 23272, 24409, 12747, 346, 19311, 23193, 24013, 5959, + 25096, 6886, 26845, 2425, 27533, 3909, 17715, 852, 8096, 9054, + 14383, 23501, 17461, 25833, 14840, 1659, 10833, 7523, 30819, 6896, + 26640, 13317, 278, 26185, 29677, 27638, 22253, 15108, 1342, 21184, + 30364, 29458, 24062, 29441, 3734, 22573, 25039, 8035, 28206, 26220, + 7743, 27085, 28668, 7445, 10315, 6875, 25475, 20914, 29474, 15756, + 14864, 14695, 1067, 4923, 31461, 7298, 10312, 977, 17047, 26708, + 3677, 24120, 20917, 4928, 27404, 32019, 28330, 1809, 2499, 9132, + 7909, 1424, 28409, 10029, 31543, 15191, 28596, 14356, 9084, 29920, + 25167, 24545, 5501, 10721, 19578, 1809, 27413, 21212, 12930, 5968, + 17299, 15601, 27603, 3563, 23648, 20472, 8379, 4740, 7394, 31436, + 21872, 26121, 6559, 14825, 9813, 15847, 21158, 27706, 6521, 24442, + 12587, 27180, 10592, 4040, 2161, 4871, 27911, 11120, 7661, 17534, + 290, 31453, 31912, 28805, 5800, 5823, 6117, 17762, 19089, 28860, + 260, 7175, 10975, 21602, 13478, 8351, 3291, 29793, 17170, 26983, + 6305, 22519, 22487, 28607, 11742, 15531, 25779, 8065, 1497, 16446, + 29620, 28817, 14000, 26335, 25757, 16053, 31716, 20894, 6539, 21415, + 26648, 14627, 22232, 22377, 25622, 160, 23104, 6873, 7955, 29956, }; diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c index d8511fefe8..748c403281 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -8,9 +8,9 @@ #include "MtrrLibUnitTest.h" -MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = { +MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = { CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack - }; +}; UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR]; MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR]; @@ -20,10 +20,10 @@ MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; -BOOLEAN mRandomInput; -UINTN mNumberIndex = 0; -extern UINTN mNumbers[]; -extern UINTN mNumberCount; +BOOLEAN mRandomInput; +UINTN mNumberIndex = 0; +extern UINTN mNumbers[]; +extern UINTN mNumberCount; /** Return a random number between 0 and RAND_MAX. @@ -65,8 +65,8 @@ CHAR8 mContentTemplate[] = { **/ VOID GenerateRandomNumbers ( - CHAR8 *FilePath, - UINTN Count + CHAR8 *FilePath, + UINTN Count ) { FILE *File; @@ -78,8 +78,10 @@ GenerateRandomNumbers ( if (Index % 10 == 0) { fprintf (File, "\n "); } + fprintf (File, " %d,", rand ()); } + fprintf (File, "\n};\n"); fclose (File); } @@ -112,38 +114,41 @@ GenerateRandomNumbers ( UINT32 EFIAPI UnitTestMtrrLibAsmCpuid ( - IN UINT32 Index, - OUT UINT32 *Eax OPTIONAL, - OUT UINT32 *Ebx OPTIONAL, - OUT UINT32 *Ecx OPTIONAL, - OUT UINT32 *Edx OPTIONAL + IN UINT32 Index, + OUT UINT32 *Eax OPTIONAL, + OUT UINT32 *Ebx OPTIONAL, + OUT UINT32 *Ecx OPTIONAL, + OUT UINT32 *Edx OPTIONAL ) { switch (Index) { - case CPUID_VERSION_INFO: - if (Edx != NULL) { - *Edx = mCpuidVersionInfoEdx.Uint32; - } - return Index; - break; - case CPUID_EXTENDED_FUNCTION: - if (Eax != NULL) { - *Eax = CPUID_VIR_PHY_ADDRESS_SIZE; - } - return Index; - break; - case CPUID_VIR_PHY_ADDRESS_SIZE: - if (Eax != NULL) { - *Eax = mCpuidVirPhyAddressSizeEax.Uint32; - } - return Index; - break; + case CPUID_VERSION_INFO: + if (Edx != NULL) { + *Edx = mCpuidVersionInfoEdx.Uint32; + } + + return Index; + break; + case CPUID_EXTENDED_FUNCTION: + if (Eax != NULL) { + *Eax = CPUID_VIR_PHY_ADDRESS_SIZE; + } + + return Index; + break; + case CPUID_VIR_PHY_ADDRESS_SIZE: + if (Eax != NULL) { + *Eax = mCpuidVirPhyAddressSizeEax.Uint32; + } + + return Index; + break; } // // Should never fall through to here // - ASSERT(FALSE); + ASSERT (FALSE); return Index; } @@ -163,11 +168,11 @@ UnitTestMtrrLibAsmCpuid ( **/ UINT64 EFIAPI -UnitTestMtrrLibAsmReadMsr64( +UnitTestMtrrLibAsmReadMsr64 ( IN UINT32 MsrIndex ) { - UINT32 Index; + UINT32 Index; for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) { if (MsrIndex == mFixedMtrrsIndex[Index]) { @@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64( } if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && - (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { + (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) + { if (MsrIndex % 2 == 0) { Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; return mVariableMtrrsPhysBase[Index].Uint64; @@ -197,7 +203,7 @@ UnitTestMtrrLibAsmReadMsr64( // // Should never fall through to here // - ASSERT(FALSE); + ASSERT (FALSE); return 0; } @@ -220,12 +226,12 @@ UnitTestMtrrLibAsmReadMsr64( **/ UINT64 EFIAPI -UnitTestMtrrLibAsmWriteMsr64( - IN UINT32 MsrIndex, - IN UINT64 Value +UnitTestMtrrLibAsmWriteMsr64 ( + IN UINT32 MsrIndex, + IN UINT64 Value ) { - UINT32 Index; + UINT32 Index; for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) { if (MsrIndex == mFixedMtrrsIndex[Index]) { @@ -235,13 +241,14 @@ UnitTestMtrrLibAsmWriteMsr64( } if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && - (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { + (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) + { if (MsrIndex % 2 == 0) { - Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; + Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; mVariableMtrrsPhysBase[Index].Uint64 = Value; return Value; } else { - Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1; + Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1; mVariableMtrrsPhysMask[Index].Uint64 = Value; return Value; } @@ -260,7 +267,7 @@ UnitTestMtrrLibAsmWriteMsr64( // // Should never fall through to here // - ASSERT(FALSE); + ASSERT (FALSE); return 0; } @@ -275,7 +282,7 @@ InitializeMtrrRegs ( IN MTRR_LIB_SYSTEM_PARAMETER *SystemParameter ) { - UINT32 Index; + UINT32 Index; SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType); @@ -325,10 +332,10 @@ InitializeMtrrRegs ( UNIT_TEST_STATUS EFIAPI InitializeSystem ( - IN UNIT_TEST_CONTEXT Context + IN UNIT_TEST_CONTEXT Context ) { - return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *) Context); + return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *)Context); } /** @@ -344,34 +351,34 @@ InitializeSystem ( **/ VOID CollectTestResult ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT32 PhysicalAddressBits, - IN UINT32 VariableMtrrCount, - IN MTRR_SETTINGS *Mtrrs, - OUT MTRR_MEMORY_RANGE *Ranges, - IN OUT UINTN *RangeCount, - OUT UINT32 *MtrrCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT32 PhysicalAddressBits, + IN UINT32 VariableMtrrCount, + IN MTRR_SETTINGS *Mtrrs, + OUT MTRR_MEMORY_RANGE *Ranges, + IN OUT UINTN *RangeCount, + OUT UINT32 *MtrrCount ) { - UINTN Index; - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)]; + UINTN Index; + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)]; ASSERT (Mtrrs != NULL); ASSERT (VariableMtrrCount <= ARRAY_SIZE (Mtrrs->Variables.Mtrr)); - MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1; + MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1; MtrrValidAddressMask = MtrrValidBitsMask & ~0xFFFull; *MtrrCount = 0; for (Index = 0; Index < VariableMtrrCount; Index++) { - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) { RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask; RawMemoryRanges[*MtrrCount].Type = - ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type; - RawMemoryRanges[*MtrrCount].Length = - ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type; + RawMemoryRanges[*MtrrCount].Length = + ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; (*MtrrCount)++; } } @@ -392,7 +399,7 @@ Random32 ( UINT32 Limit ) { - return (UINT32) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; + return (UINT32)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start; } /** @@ -408,7 +415,7 @@ Random64 ( UINT64 Limit ) { - return (UINT64) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; + return (UINT64)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start; } /** @@ -421,30 +428,30 @@ Random64 ( **/ VOID GenerateRandomMtrrPair ( - IN UINT32 PhysicalAddressBits, - IN MTRR_MEMORY_CACHE_TYPE CacheType, - OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, - OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL + IN UINT32 PhysicalAddressBits, + IN MTRR_MEMORY_CACHE_TYPE CacheType, + OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, + OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL ) { - MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase; - MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask; - UINT32 SizeShift; - UINT32 BaseShift; - UINT64 RandomBoundary; - UINT64 MaxPhysicalAddress; - UINT64 RangeSize; - UINT64 RangeBase; - UINT64 PhysBasePhyMaskValidBitsMask; + MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase; + MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask; + UINT32 SizeShift; + UINT32 BaseShift; + UINT64 RandomBoundary; + UINT64 MaxPhysicalAddress; + UINT64 RangeSize; + UINT64 RangeBase; + UINT64 PhysBasePhyMaskValidBitsMask; MaxPhysicalAddress = 1ull << PhysicalAddressBits; do { SizeShift = Random32 (12, PhysicalAddressBits - 1); RangeSize = 1ull << SizeShift; - BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1); + BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1); RandomBoundary = Random64 (0, 1ull << (PhysicalAddressBits - BaseShift)); - RangeBase = RandomBoundary << BaseShift; + RangeBase = RandomBoundary << BaseShift; } while (RangeBase < SIZE_1MB || RangeBase > MaxPhysicalAddress - 1); PhysBasePhyMaskValidBitsMask = (MaxPhysicalAddress - 1) & 0xfffffffffffff000ULL; @@ -468,7 +475,6 @@ GenerateRandomMtrrPair ( } } - /** Check whether the Range overlaps with any one in Ranges. @@ -480,9 +486,9 @@ GenerateRandomMtrrPair ( **/ BOOLEAN RangesOverlap ( - IN MTRR_MEMORY_RANGE *Range, - IN MTRR_MEMORY_RANGE *Ranges, - IN UINTN Count + IN MTRR_MEMORY_RANGE *Range, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN Count ) { while (Count-- != 0) { @@ -491,11 +497,13 @@ RangesOverlap ( // 1. range#2.base is in the middle of range#1 // 2. range#1.base is in the middle of range#2 // - if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length) - || (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) { + if ( ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length)) + || ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length))) + { return TRUE; } } + return FALSE; } @@ -512,16 +520,16 @@ RangesOverlap ( **/ VOID GenerateValidAndConfigurableMtrrPairs ( - IN UINT32 PhysicalAddressBits, - IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 UcCount, - IN UINT32 WtCount, - IN UINT32 WbCount, - IN UINT32 WpCount, - IN UINT32 WcCount + IN UINT32 PhysicalAddressBits, + IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 UcCount, + IN UINT32 WtCount, + IN UINT32 WbCount, + IN UINT32 WpCount, + IN UINT32 WcCount ) { - UINT32 Index; + UINT32 Index; // // 1. Generate UC, WT, WB in order. @@ -567,7 +575,7 @@ GenerateRandomCacheType ( VOID ) { - return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)]; + return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)]; } /** @@ -586,19 +594,20 @@ GenerateRandomCacheType ( **/ INT32 CompareFuncUint64 ( - CONST VOID * Left, - CONST VOID * Right + CONST VOID *Left, + CONST VOID *Right ) { - INT64 Delta; - Delta = (*(UINT64*)Left - *(UINT64*)Right); - if (Delta > 0) { - return 1; - } else if (Delta == 0) { - return 0; - } else { - return -1; - } + INT64 Delta; + + Delta = (*(UINT64 *)Left - *(UINT64 *)Right); + if (Delta > 0) { + return 1; + } else if (Delta == 0) { + return 0; + } else { + return -1; + } } /** @@ -611,13 +620,14 @@ CompareFuncUint64 ( **/ VOID DetermineMemoryCacheType ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN OUT MTRR_MEMORY_RANGE *Range, - IN MTRR_MEMORY_RANGE *Ranges, - IN UINT32 RangeCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN OUT MTRR_MEMORY_RANGE *Range, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINT32 RangeCount ) { - UINT32 Index; + UINT32 Index; + Range->Type = CacheInvalid; for (Index = 0; Index < RangeCount; Index++) { if (RangesOverlap (Range, &Ranges[Index], 1)) { @@ -643,16 +653,18 @@ DetermineMemoryCacheType ( **/ UINT32 GetNextDifferentElementInSortedArray ( - IN UINT32 Index, - IN UINT64 *Array, - IN UINT32 Count + IN UINT32 Index, + IN UINT64 *Array, + IN UINT32 Count ) { - UINT64 CurrentElement; + UINT64 CurrentElement; + CurrentElement = Array[Index]; while (CurrentElement == Array[Index] && Index < Count) { Index++; } + return Index; } @@ -664,12 +676,12 @@ GetNextDifferentElementInSortedArray ( **/ VOID RemoveDuplicatesInSortedArray ( - IN OUT UINT64 *Array, - IN OUT UINT32 *Count + IN OUT UINT64 *Array, + IN OUT UINT32 *Count ) { - UINT32 Index; - UINT32 NewCount; + UINT32 Index; + UINT32 NewCount; Index = 0; NewCount = 0; @@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray ( NewCount++; Index = GetNextDifferentElementInSortedArray (Index, Array, *Count); } + *Count = NewCount; } @@ -690,11 +703,11 @@ RemoveDuplicatesInSortedArray ( **/ BOOLEAN AddressInRange ( - IN UINT64 Address, - IN MTRR_MEMORY_RANGE Range + IN UINT64 Address, + IN MTRR_MEMORY_RANGE Range ) { - return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1); + return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1); } /** @@ -706,13 +719,14 @@ AddressInRange ( **/ UINT64 GetOverlapBitFlag ( - IN MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 RawMemoryRangeCount, - IN UINT64 Address + IN MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 RawMemoryRangeCount, + IN UINT64 Address ) { - UINT64 OverlapBitFlag; - UINT32 Index; + UINT64 OverlapBitFlag; + UINT32 Index; + OverlapBitFlag = 0; for (Index = 0; Index < RawMemoryRangeCount; Index++) { if (AddressInRange (Address, RawMemoryRanges[Index])) { @@ -736,14 +750,23 @@ GetOverlapBitFlag ( **/ UINT32 CheckOverlapBitFlagsRelation ( - IN UINT64 Flag1, - IN UINT64 Flag2 + IN UINT64 Flag1, + IN UINT64 Flag2 ) { - if (Flag1 == Flag2) return 0; - if ((Flag1 | Flag2) == Flag2) return 1; - if ((Flag1 | Flag2) == Flag1) return 2; - return 3; + if (Flag1 == Flag2) { + return 0; + } + + if ((Flag1 | Flag2) == Flag2) { + return 1; + } + + if ((Flag1 | Flag2) == Flag1) { + return 2; + } + + return 3; } /** @@ -758,20 +781,21 @@ CheckOverlapBitFlagsRelation ( **/ BOOLEAN IsEndpointInRanges ( - IN UINT64 Endpoint, - IN MTRR_MEMORY_RANGE *Ranges, - IN UINTN RangeCount + IN UINT64 Endpoint, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount ) { - UINT32 Index; - for (Index = 0; Index < RangeCount; Index++) { - if (AddressInRange (Endpoint, Ranges[Index])) { - return TRUE; - } + UINT32 Index; + + for (Index = 0; Index < RangeCount; Index++) { + if (AddressInRange (Endpoint, Ranges[Index])) { + return TRUE; } - return FALSE; -} + } + return FALSE; +} /** Compact adjacent ranges of the same type. @@ -783,26 +807,26 @@ IsEndpointInRanges ( **/ VOID CompactAndExtendEffectiveMtrrMemoryRanges ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT32 PhysicalAddressBits, - IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges, - IN OUT UINTN *EffectiveMtrrMemoryRangesCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT32 PhysicalAddressBits, + IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges, + IN OUT UINTN *EffectiveMtrrMemoryRangesCount ) { - UINT64 MaxAddress; - UINTN NewRangesCountAtMost; - MTRR_MEMORY_RANGE *NewRanges; - UINTN NewRangesCountActual; - MTRR_MEMORY_RANGE *CurrentRangeInNewRanges; - MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges; + UINT64 MaxAddress; + UINTN NewRangesCountAtMost; + MTRR_MEMORY_RANGE *NewRanges; + UINTN NewRangesCountActual; + MTRR_MEMORY_RANGE *CurrentRangeInNewRanges; + MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges; - MTRR_MEMORY_RANGE *OldRanges; - MTRR_MEMORY_RANGE OldLastRange; - UINTN OldRangesIndex; + MTRR_MEMORY_RANGE *OldRanges; + MTRR_MEMORY_RANGE OldLastRange; + UINTN OldRangesIndex; NewRangesCountActual = 0; NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries. - NewRanges = (MTRR_MEMORY_RANGE *) calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE)); + NewRanges = (MTRR_MEMORY_RANGE *)calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE)); OldRanges = *EffectiveMtrrMemoryRanges; if (OldRanges[0].BaseAddress > 0) { NewRanges[NewRangesCountActual].BaseAddress = 0; @@ -814,44 +838,45 @@ CompactAndExtendEffectiveMtrrMemoryRanges ( OldRangesIndex = 0; while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) { CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type; - CurrentRangeInNewRanges = NULL; - if (NewRangesCountActual > 0) // We need to check CurrentNewRange first before generate a new NewRange. - { + CurrentRangeInNewRanges = NULL; + if (NewRangesCountActual > 0) { + // We need to check CurrentNewRange first before generate a new NewRange. CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1]; } - if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) { + + if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) { CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length; } else { NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges; - while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) - { + while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) { OldRangesIndex++; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; } + NewRangesCountActual++; } OldRangesIndex++; } - MaxAddress = (1ull << PhysicalAddressBits) - 1; - OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1]; + MaxAddress = (1ull << PhysicalAddressBits) - 1; + OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1]; CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1]; if (OldLastRange.BaseAddress + OldLastRange.Length - 1 < MaxAddress) { if (CurrentRangeInNewRanges->Type == DefaultType) { CurrentRangeInNewRanges->Length = MaxAddress - CurrentRangeInNewRanges->BaseAddress + 1; } else { NewRanges[NewRangesCountActual].BaseAddress = OldLastRange.BaseAddress + OldLastRange.Length; - NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1; - NewRanges[NewRangesCountActual].Type = DefaultType; + NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1; + NewRanges[NewRangesCountActual].Type = DefaultType; NewRangesCountActual++; } } free (*EffectiveMtrrMemoryRanges); - *EffectiveMtrrMemoryRanges = NewRanges; + *EffectiveMtrrMemoryRanges = NewRanges; *EffectiveMtrrMemoryRangesCount = NewRangesCountActual; } @@ -865,20 +890,20 @@ CompactAndExtendEffectiveMtrrMemoryRanges ( **/ VOID CollectEndpoints ( - IN OUT UINT64 *Endpoints, - IN OUT UINT32 *EndPointCount, - IN MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 RawMemoryRangeCount + IN OUT UINT64 *Endpoints, + IN OUT UINT32 *EndPointCount, + IN MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 RawMemoryRangeCount ) { - UINT32 Index; - UINT32 RawRangeIndex; + UINT32 Index; + UINT32 RawRangeIndex; ASSERT ((RawMemoryRangeCount << 1) == *EndPointCount); for (Index = 0; Index < *EndPointCount; Index += 2) { - RawRangeIndex = Index >> 1; - Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress; + RawRangeIndex = Index >> 1; + Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress; Endpoints[Index + 1] = RawMemoryRanges[RawRangeIndex].BaseAddress + RawMemoryRanges[RawRangeIndex].Length - 1; } @@ -898,41 +923,41 @@ CollectEndpoints ( **/ VOID GetEffectiveMemoryRanges ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT32 PhysicalAddressBits, - IN MTRR_MEMORY_RANGE *RawMemoryRanges, - IN UINT32 RawMemoryRangeCount, - OUT MTRR_MEMORY_RANGE *MemoryRanges, - OUT UINTN *MemoryRangeCount + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT32 PhysicalAddressBits, + IN MTRR_MEMORY_RANGE *RawMemoryRanges, + IN UINT32 RawMemoryRangeCount, + OUT MTRR_MEMORY_RANGE *MemoryRanges, + OUT UINTN *MemoryRangeCount ) { - UINTN Index; - UINT32 AllEndPointsCount; - UINT64 *AllEndPointsInclusive; - UINT32 AllRangePiecesCountMax; - MTRR_MEMORY_RANGE *AllRangePieces; - UINTN AllRangePiecesCountActual; - UINT64 OverlapBitFlag1; - UINT64 OverlapBitFlag2; - INT32 OverlapFlagRelation; + UINTN Index; + UINT32 AllEndPointsCount; + UINT64 *AllEndPointsInclusive; + UINT32 AllRangePiecesCountMax; + MTRR_MEMORY_RANGE *AllRangePieces; + UINTN AllRangePiecesCountActual; + UINT64 OverlapBitFlag1; + UINT64 OverlapBitFlag2; + INT32 OverlapFlagRelation; if (RawMemoryRangeCount == 0) { MemoryRanges[0].BaseAddress = 0; MemoryRanges[0].Length = (1ull << PhysicalAddressBits); MemoryRanges[0].Type = DefaultType; - *MemoryRangeCount = 1; + *MemoryRangeCount = 1; return; } - AllEndPointsCount = RawMemoryRangeCount << 1; - AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64)); - AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1; - AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE)); + AllEndPointsCount = RawMemoryRangeCount << 1; + AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64)); + AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1; + AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE)); CollectEndpoints (AllEndPointsInclusive, &AllEndPointsCount, RawMemoryRanges, RawMemoryRangeCount); for (Index = 0, AllRangePiecesCountActual = 0; Index < AllEndPointsCount - 1; Index++) { - OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]); - OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]); + OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]); + OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]); OverlapFlagRelation = CheckOverlapBitFlagsRelation (OverlapBitFlag1, OverlapBitFlag2); switch (OverlapFlagRelation) { case 0: // [1, 2] @@ -955,18 +980,23 @@ GetEffectiveMemoryRanges ( AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePiecesCountActual++; } + break; case 3: // (1, 2) AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1; AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1; - if (AllRangePieces[AllRangePiecesCountActual].Length == 0) // Only in case 3 can exists Length=0, we should skip such "segment". + if (AllRangePieces[AllRangePiecesCountActual].Length == 0) { + // Only in case 3 can exists Length=0, we should skip such "segment". break; + } + AllRangePiecesCountActual++; if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) { AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index]; AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePiecesCountActual++; } + break; default: ASSERT (FALSE); diff --git a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c index cebaa81399..9f71c2611c 100644 --- a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c +++ b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c @@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_PEI_PPI_DESCRIPTOR * EFIAPI SecPlatformMain ( - IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData ) { return NULL; @@ -50,9 +50,9 @@ SecPlatformMain ( EFI_STATUS EFIAPI SecPlatformInformation ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ) { return EFI_SUCCESS; diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 2f77ab3aeb..a8e4f920fc 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -8,7 +8,7 @@ #include "RegisterCpuFeatures.h" -CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package", L"Invalid" }; +CHAR16 *mDependTypeStr[] = { L"None", L"Thread", L"Core", L"Package", L"Invalid" }; /** Worker function to save PcdCpuFeaturesCapability. @@ -19,11 +19,11 @@ CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package", L"Invalid **/ VOID SetCapabilityPcd ( - IN UINT8 *SupportedFeatureMask, - IN UINTN BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN UINTN BitMaskSize ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = PcdSetPtrS (PcdCpuFeaturesCapability, &BitMaskSize, SupportedFeatureMask); ASSERT_EFI_ERROR (Status); @@ -37,11 +37,11 @@ SetCapabilityPcd ( **/ VOID SetSettingPcd ( - IN UINT8 *SupportedFeatureMask, - IN UINTN BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN UINTN BitMaskSize ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = PcdSetPtrS (PcdCpuFeaturesSetting, &BitMaskSize, SupportedFeatureMask); ASSERT_EFI_ERROR (Status); @@ -54,14 +54,14 @@ SetSettingPcd ( **/ VOID FillProcessorInfo ( - IN OUT REGISTER_CPU_FEATURE_INFORMATION *CpuInfo + IN OUT REGISTER_CPU_FEATURE_INFORMATION *CpuInfo ) { - CPUID_VERSION_INFO_EAX Eax; - CPUID_VERSION_INFO_ECX Ecx; - CPUID_VERSION_INFO_EDX Edx; - UINT32 DisplayedFamily; - UINT32 DisplayedModel; + CPUID_VERSION_INFO_EAX Eax; + CPUID_VERSION_INFO_ECX Ecx; + CPUID_VERSION_INFO_EDX Edx; + UINT32 DisplayedFamily; + UINT32 DisplayedModel; AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, &Ecx.Uint32, &Edx.Uint32); @@ -71,14 +71,14 @@ FillProcessorInfo ( } DisplayedModel = Eax.Bits.Model; - if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) { + if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) { DisplayedModel |= (Eax.Bits.ExtendedModelId << 4); } - CpuInfo->DisplayFamily = DisplayedFamily; - CpuInfo->DisplayModel = DisplayedModel; - CpuInfo->SteppingId = Eax.Bits.SteppingId; - CpuInfo->ProcessorType = Eax.Bits.ProcessorType; + CpuInfo->DisplayFamily = DisplayedFamily; + CpuInfo->DisplayModel = DisplayedModel; + CpuInfo->SteppingId = Eax.Bits.SteppingId; + CpuInfo->ProcessorType = Eax.Bits.ProcessorType; CpuInfo->CpuIdVersionInfoEcx.Uint32 = Ecx.Uint32; CpuInfo->CpuIdVersionInfoEdx.Uint32 = Edx.Uint32; } @@ -92,29 +92,29 @@ CpuInitDataInitialize ( VOID ) { - EFI_STATUS Status; - UINTN ProcessorNumber; - EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; - CPU_FEATURES_ENTRY *CpuFeature; - CPU_FEATURES_INIT_ORDER *InitOrder; - CPU_FEATURES_DATA *CpuFeaturesData; - LIST_ENTRY *Entry; - UINT32 Core; - UINT32 Package; - UINT32 Thread; - EFI_CPU_PHYSICAL_LOCATION *Location; - UINT32 PackageIndex; - UINT32 CoreIndex; - UINTN Pages; - UINT32 FirstPackage; - UINT32 *FirstCore; - UINT32 *FirstThread; - ACPI_CPU_DATA *AcpiCpuData; - CPU_STATUS_INFORMATION *CpuStatus; - UINT32 *ThreadCountPerPackage; - UINT8 *ThreadCountPerCore; - UINTN NumberOfCpus; - UINTN NumberOfEnabledProcessors; + EFI_STATUS Status; + UINTN ProcessorNumber; + EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; + CPU_FEATURES_ENTRY *CpuFeature; + CPU_FEATURES_INIT_ORDER *InitOrder; + CPU_FEATURES_DATA *CpuFeaturesData; + LIST_ENTRY *Entry; + UINT32 Core; + UINT32 Package; + UINT32 Thread; + EFI_CPU_PHYSICAL_LOCATION *Location; + UINT32 PackageIndex; + UINT32 CoreIndex; + UINTN Pages; + UINT32 FirstPackage; + UINT32 *FirstCore; + UINT32 *FirstThread; + ACPI_CPU_DATA *AcpiCpuData; + CPU_STATUS_INFORMATION *CpuStatus; + UINT32 *ThreadCountPerPackage; + UINT8 *ThreadCountPerCore; + UINTN NumberOfCpus; + UINTN NumberOfEnabledProcessors; Core = 0; Package = 0; @@ -143,23 +143,24 @@ CpuInitDataInitialize ( if (CpuFeature->GetConfigDataFunc != NULL) { CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus); } + Entry = Entry->ForwardLink; } - CpuFeaturesData->NumberOfCpus = (UINT32) NumberOfCpus; + CpuFeaturesData->NumberOfCpus = (UINT32)NumberOfCpus; AcpiCpuData = GetAcpiCpuData (); ASSERT (AcpiCpuData != NULL); - CpuFeaturesData->AcpiCpuData= AcpiCpuData; + CpuFeaturesData->AcpiCpuData = AcpiCpuData; CpuStatus = &AcpiCpuData->CpuFeatureInitData.CpuStatus; - Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus)); + Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus)); ASSERT (Location != NULL); ZeroMem (Location, sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus); AcpiCpuData->CpuFeatureInitData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)Location; for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) { - InitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber]; + InitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber]; InitOrder->FeaturesSupportedMask = AllocateZeroPool (CpuFeaturesData->BitMaskSize); ASSERT (InitOrder->FeaturesSupportedMask != NULL); InitializeListHead (&InitOrder->OrderList); @@ -182,12 +183,14 @@ CpuInitDataInitialize ( if (Package < ProcessorInfoBuffer.Location.Package) { Package = ProcessorInfoBuffer.Location.Package; } + // // Collect CPU max core count info. // if (Core < ProcessorInfoBuffer.Location.Core) { Core = ProcessorInfoBuffer.Location.Core; } + // // Collect CPU max thread count info. // @@ -195,13 +198,17 @@ CpuInitDataInitialize ( Thread = ProcessorInfoBuffer.Location.Thread; } } - CpuStatus->PackageCount = Package + 1; - CpuStatus->MaxCoreCount = Core + 1; - CpuStatus->MaxThreadCount = Thread + 1; - DEBUG ((DEBUG_INFO, "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n", - CpuStatus->PackageCount, - CpuStatus->MaxCoreCount, - CpuStatus->MaxThreadCount)); + + CpuStatus->PackageCount = Package + 1; + CpuStatus->MaxCoreCount = Core + 1; + CpuStatus->MaxThreadCount = Thread + 1; + DEBUG (( + DEBUG_INFO, + "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n", + CpuStatus->PackageCount, + CpuStatus->MaxCoreCount, + CpuStatus->MaxThreadCount + )); // // Collect valid core count in each package because not all cores are valid. @@ -228,7 +235,10 @@ CpuInitDataInitialize ( for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) { if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) { DEBUG (( - DEBUG_INFO, " P%02d C%04d, Thread Count = %d\n", PackageIndex, CoreIndex, + DEBUG_INFO, + " P%02d C%04d, Thread Count = %d\n", + PackageIndex, + CoreIndex, ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] )); } @@ -248,13 +258,13 @@ CpuInitDataInitialize ( Pages = EFI_SIZE_TO_PAGES (CpuStatus->PackageCount * sizeof (UINT32) + CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32)); FirstCore = AllocatePages (Pages); ASSERT (FirstCore != NULL); - FirstThread = FirstCore + CpuStatus->PackageCount; + FirstThread = FirstCore + CpuStatus->PackageCount; // // Set FirstPackage, FirstCore[], FirstThread[] to maximum package ID, core ID, thread ID. // FirstPackage = MAX_UINT32; - SetMem32 (FirstCore, CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32); + SetMem32 (FirstCore, CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32); SetMem32 (FirstThread, CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32), MAX_UINT32); for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) { @@ -263,7 +273,7 @@ CpuInitDataInitialize ( // // Save the minimum package ID in the platform. // - FirstPackage = MIN (Location->Package, FirstPackage); + FirstPackage = MIN (Location->Package, FirstPackage); // // Save the minimum core ID per package. @@ -274,9 +284,9 @@ CpuInitDataInitialize ( // Save the minimum thread ID per core. // FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core] = MIN ( - Location->Thread, - FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core] - ); + Location->Thread, + FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core] + ); } // @@ -293,13 +303,14 @@ CpuInitDataInitialize ( // Set First.Die/Tile/Module for each thread assuming: // single Die under each package, single Tile under each Die, single Module under each Tile // - CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die = 1; - CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile = 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die = 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile = 1; CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Module = 1; if (Location->Core == FirstCore[Location->Package]) { CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1; } + if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) { CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1; } @@ -318,14 +329,14 @@ CpuInitDataInitialize ( **/ VOID SupportedMaskOr ( - IN UINT8 *SupportedFeatureMask, - IN UINT8 *OrFeatureBitMask, - IN UINT32 BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN UINT8 *OrFeatureBitMask, + IN UINT32 BitMaskSize ) { - UINTN Index; - UINT8 *Data1; - UINT8 *Data2; + UINTN Index; + UINT8 *Data1; + UINT8 *Data2; Data1 = SupportedFeatureMask; Data2 = OrFeatureBitMask; @@ -344,14 +355,14 @@ SupportedMaskOr ( **/ VOID SupportedMaskAnd ( - IN UINT8 *SupportedFeatureMask, - IN CONST UINT8 *AndFeatureBitMask, - IN UINT32 BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN CONST UINT8 *AndFeatureBitMask, + IN UINT32 BitMaskSize ) { - UINTN Index; - UINT8 *Data1; - CONST UINT8 *Data2; + UINTN Index; + UINT8 *Data1; + CONST UINT8 *Data2; Data1 = SupportedFeatureMask; Data2 = AndFeatureBitMask; @@ -369,14 +380,14 @@ SupportedMaskAnd ( **/ VOID SupportedMaskCleanBit ( - IN UINT8 *SupportedFeatureMask, - IN UINT8 *AndFeatureBitMask, - IN UINT32 BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN UINT8 *AndFeatureBitMask, + IN UINT32 BitMaskSize ) { - UINTN Index; - UINT8 *Data1; - UINT8 *Data2; + UINTN Index; + UINT8 *Data1; + UINT8 *Data2; Data1 = SupportedFeatureMask; Data2 = AndFeatureBitMask; @@ -400,14 +411,14 @@ SupportedMaskCleanBit ( **/ BOOLEAN IsBitMaskMatch ( - IN UINT8 *SupportedFeatureMask, - IN UINT8 *ComparedFeatureBitMask, - IN UINT32 BitMaskSize + IN UINT8 *SupportedFeatureMask, + IN UINT8 *ComparedFeatureBitMask, + IN UINT32 BitMaskSize ) { - UINTN Index; - UINT8 *Data1; - UINT8 *Data2; + UINTN Index; + UINT8 *Data1; + UINT8 *Data2; Data1 = SupportedFeatureMask; Data2 = ComparedFeatureBitMask; @@ -416,6 +427,7 @@ IsBitMaskMatch ( return TRUE; } } + return FALSE; } @@ -427,18 +439,18 @@ IsBitMaskMatch ( VOID EFIAPI CollectProcessorData ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - UINTN ProcessorNumber; - CPU_FEATURES_ENTRY *CpuFeature; - REGISTER_CPU_FEATURE_INFORMATION *CpuInfo; - LIST_ENTRY *Entry; - CPU_FEATURES_DATA *CpuFeaturesData; + UINTN ProcessorNumber; + CPU_FEATURES_ENTRY *CpuFeature; + REGISTER_CPU_FEATURE_INFORMATION *CpuInfo; + LIST_ENTRY *Entry; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer; ProcessorNumber = GetProcessorIndex (CpuFeaturesData); - CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo; + CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo; // // collect processor information // @@ -462,6 +474,7 @@ CollectProcessorData ( CpuFeaturesData->BitMaskSize ); } + Entry = Entry->ForwardLink; } } @@ -475,15 +488,15 @@ CollectProcessorData ( **/ VOID DumpRegisterTableOnProcessor ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - CPU_FEATURES_DATA *CpuFeaturesData; - UINTN FeatureIndex; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead; - UINT32 DebugPrintErrorLevel; + CPU_FEATURES_DATA *CpuFeaturesData; + UINTN FeatureIndex; + CPU_REGISTER_TABLE *RegisterTable; + CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; + CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead; + UINT32 DebugPrintErrorLevel; DebugPrintErrorLevel = (ProcessorNumber == 0) ? DEBUG_INFO : DEBUG_VERBOSE; CpuFeaturesData = GetCpuFeaturesData (); @@ -493,71 +506,71 @@ DumpRegisterTableOnProcessor ( RegisterTable = &CpuFeaturesData->RegisterTable[ProcessorNumber]; DEBUG ((DebugPrintErrorLevel, "RegisterTable->TableLength = %d\n", RegisterTable->TableLength)); - RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; + RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry; for (FeatureIndex = 0; FeatureIndex < RegisterTable->TableLength; FeatureIndex++) { RegisterTableEntry = &RegisterTableEntryHead[FeatureIndex]; switch (RegisterTableEntry->RegisterType) { - case Msr: - DEBUG (( - DebugPrintErrorLevel, - "Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", - (UINT32) ProcessorNumber, - (UINT32) FeatureIndex, - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitLength, - RegisterTableEntry->Value - )); - break; - case ControlRegister: - DEBUG (( - DebugPrintErrorLevel, - "Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", - (UINT32) ProcessorNumber, - (UINT32) FeatureIndex, - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitLength, - RegisterTableEntry->Value - )); - break; - case MemoryMapped: - DEBUG (( - DebugPrintErrorLevel, - "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", - (UINT32) ProcessorNumber, - (UINT32) FeatureIndex, - RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitLength, - RegisterTableEntry->Value - )); - break; - case CacheControl: - DEBUG (( - DebugPrintErrorLevel, - "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", - (UINT32) ProcessorNumber, - (UINT32) FeatureIndex, - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitLength, - RegisterTableEntry->Value - )); - break; - case Semaphore: - DEBUG (( - DebugPrintErrorLevel, - "Processor: %04d: Index %04d, SEMAP: %s\r\n", - (UINT32) ProcessorNumber, - (UINT32) FeatureIndex, - mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] - )); - break; + case Msr: + DEBUG (( + DebugPrintErrorLevel, + "Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", + (UINT32)ProcessorNumber, + (UINT32)FeatureIndex, + RegisterTableEntry->Index, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitLength, + RegisterTableEntry->Value + )); + break; + case ControlRegister: + DEBUG (( + DebugPrintErrorLevel, + "Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", + (UINT32)ProcessorNumber, + (UINT32)FeatureIndex, + RegisterTableEntry->Index, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitLength, + RegisterTableEntry->Value + )); + break; + case MemoryMapped: + DEBUG (( + DebugPrintErrorLevel, + "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", + (UINT32)ProcessorNumber, + (UINT32)FeatureIndex, + RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitLength, + RegisterTableEntry->Value + )); + break; + case CacheControl: + DEBUG (( + DebugPrintErrorLevel, + "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", + (UINT32)ProcessorNumber, + (UINT32)FeatureIndex, + RegisterTableEntry->Index, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitLength, + RegisterTableEntry->Value + )); + break; + case Semaphore: + DEBUG (( + DebugPrintErrorLevel, + "Processor: %04d: Index %04d, SEMAP: %s\r\n", + (UINT32)ProcessorNumber, + (UINT32)FeatureIndex, + mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] + )); + break; - default: - break; + default: + break; } } } @@ -581,11 +594,11 @@ BiggestDep ( IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep ) { - CPU_FEATURE_DEPENDENCE_TYPE Bigger; + CPU_FEATURE_DEPENDENCE_TYPE Bigger; Bigger = MAX (BeforeDep, AfterDep); Bigger = MAX (Bigger, NoneNeibBeforeDep); - return MAX(Bigger, NoneNeibAfterDep); + return MAX (Bigger, NoneNeibAfterDep); } /** @@ -596,26 +609,26 @@ BiggestDep ( **/ VOID AnalysisProcessorFeatures ( - IN UINTN NumberOfCpus + IN UINTN NumberOfCpus ) { - EFI_STATUS Status; - UINTN ProcessorNumber; - CPU_FEATURES_ENTRY *CpuFeature; - CPU_FEATURES_ENTRY *CpuFeatureInOrder; - CPU_FEATURES_INIT_ORDER *CpuInitOrder; - REGISTER_CPU_FEATURE_INFORMATION *CpuInfo; - LIST_ENTRY *Entry; - CPU_FEATURES_DATA *CpuFeaturesData; - LIST_ENTRY *NextEntry; - CPU_FEATURES_ENTRY *NextCpuFeatureInOrder; - BOOLEAN Success; - CPU_FEATURE_DEPENDENCE_TYPE BeforeDep; - CPU_FEATURE_DEPENDENCE_TYPE AfterDep; - CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep; - CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep; - - CpuFeaturesData = GetCpuFeaturesData (); + EFI_STATUS Status; + UINTN ProcessorNumber; + CPU_FEATURES_ENTRY *CpuFeature; + CPU_FEATURES_ENTRY *CpuFeatureInOrder; + CPU_FEATURES_INIT_ORDER *CpuInitOrder; + REGISTER_CPU_FEATURE_INFORMATION *CpuInfo; + LIST_ENTRY *Entry; + CPU_FEATURES_DATA *CpuFeaturesData; + LIST_ENTRY *NextEntry; + CPU_FEATURES_ENTRY *NextCpuFeatureInOrder; + BOOLEAN Success; + CPU_FEATURE_DEPENDENCE_TYPE BeforeDep; + CPU_FEATURE_DEPENDENCE_TYPE AfterDep; + CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep; + CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep; + + CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData->CapabilityPcd = AllocatePool (CpuFeaturesData->BitMaskSize); ASSERT (CpuFeaturesData->CapabilityPcd != NULL); SetMem (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize, 0xFF); @@ -626,6 +639,7 @@ AnalysisProcessorFeatures ( // SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize); } + // // Calculate the last setting // @@ -637,28 +651,30 @@ AnalysisProcessorFeatures ( // Dump the last CPU feature list // DEBUG_CODE_BEGIN (); - DEBUG ((DEBUG_INFO, "Last CPU features list...\n")); - Entry = GetFirstNode (&CpuFeaturesData->FeatureList); - while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) { - CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry); - if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) { - if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) { - DEBUG ((DEBUG_INFO, "[Enable ] ")); - } else { - DEBUG ((DEBUG_INFO, "[Disable ] ")); - } + DEBUG ((DEBUG_INFO, "Last CPU features list...\n")); + Entry = GetFirstNode (&CpuFeaturesData->FeatureList); + while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) { + CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry); + if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) { + if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) { + DEBUG ((DEBUG_INFO, "[Enable ] ")); } else { - DEBUG ((DEBUG_INFO, "[Unsupport] ")); + DEBUG ((DEBUG_INFO, "[Disable ] ")); } - DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize); - Entry = Entry->ForwardLink; + } else { + DEBUG ((DEBUG_INFO, "[Unsupport] ")); } - DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n")); - DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize); - DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n")); - DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize); - DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n")); - DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize); + + DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize); + Entry = Entry->ForwardLink; + } + + DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n")); + DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize); + DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n")); + DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize); + DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n")); + DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize); DEBUG_CODE_END (); // @@ -669,7 +685,7 @@ AnalysisProcessorFeatures ( for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) { CpuInitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber]; - Entry = GetFirstNode (&CpuFeaturesData->FeatureList); + Entry = GetFirstNode (&CpuFeaturesData->FeatureList); while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) { // // Insert each feature into processor's order list @@ -680,13 +696,15 @@ AnalysisProcessorFeatures ( ASSERT (CpuFeatureInOrder != NULL); InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link); } + Entry = Entry->ForwardLink; } + // // Go through ordered feature list to initialize CPU features // CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo; - Entry = GetFirstNode (&CpuInitOrder->OrderList); + Entry = GetFirstNode (&CpuInitOrder->OrderList); while (!IsNull (&CpuInitOrder->OrderList, Entry)) { CpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (Entry); @@ -736,23 +754,24 @@ AnalysisProcessorFeatures ( // Check whether next feature has After type dependence with not neighborhood CPU // Features in former CPU features. // - NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope(NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList); + NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope (NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList); } else { BeforeDep = NoneDepType; AfterDep = NoneDepType; NoneNeibAfterDep = NoneDepType; } + // // Check whether current feature has Before type dependence with none neighborhood // CPU features in after Cpu features. // - NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope(CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList); + NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope (CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList); // // Get the biggest dependence and add semaphore for it. // PackageDepType > CoreDepType > ThreadDepType > NoneDepType. // - BeforeDep = BiggestDep(BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep); + BeforeDep = BiggestDep (BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep); if (BeforeDep > ThreadDepType) { CPU_REGISTER_TABLE_WRITE32 (ProcessorNumber, Semaphore, 0, BeforeDep); } @@ -783,7 +802,7 @@ AnalysisProcessorFeatures ( **/ VOID LibReleaseSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { InterlockedIncrement (Sem); @@ -801,7 +820,7 @@ LibReleaseSemaphore ( **/ VOID LibWaitForSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { UINT32 Value; @@ -827,42 +846,46 @@ LibWaitForSemaphore ( **/ UINTN ReadWriteCr ( - IN UINT32 CrIndex, - IN BOOLEAN Read, - IN OUT UINTN *CrValue + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue ) { switch (CrIndex) { - case 0: - if (Read) { - *CrValue = AsmReadCr0 (); - } else { - AsmWriteCr0 (*CrValue); - } - break; - case 2: - if (Read) { - *CrValue = AsmReadCr2 (); - } else { - AsmWriteCr2 (*CrValue); - } - break; - case 3: - if (Read) { - *CrValue = AsmReadCr3 (); - } else { - AsmWriteCr3 (*CrValue); - } - break; - case 4: - if (Read) { - *CrValue = AsmReadCr4 (); - } else { - AsmWriteCr4 (*CrValue); - } - break; - default: - return EFI_UNSUPPORTED;; + case 0: + if (Read) { + *CrValue = AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + + break; + case 2: + if (Read) { + *CrValue = AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + + break; + case 3: + if (Read) { + *CrValue = AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + + break; + case 4: + if (Read) { + *CrValue = AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + + break; + default: + return EFI_UNSUPPORTED; } return EFI_SUCCESS; @@ -880,10 +903,10 @@ ReadWriteCr ( **/ VOID ProgramProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable, - IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, - IN CPU_STATUS_INFORMATION *CpuStatus, - IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags + IN CPU_REGISTER_TABLE *RegisterTable, + IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, + IN CPU_STATUS_INFORMATION *CpuStatus, + IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags ) { CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; @@ -903,54 +926,25 @@ ProgramProcessorRegister ( // // Traverse Register Table of this logical processor // - RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; + RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry; for (Index = 0; Index < RegisterTable->TableLength; Index++) { - RegisterTableEntry = &RegisterTableEntryHead[Index]; // // Check the type of specified register // switch (RegisterTableEntry->RegisterType) { - // - // The specified register is Control Register - // - case ControlRegister: - Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); - if (EFI_ERROR (Status)) { - break; - } - if (RegisterTableEntry->TestThenWrite) { - CurrentValue = BitFieldRead64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 - ); - if (CurrentValue == RegisterTableEntry->Value) { + // + // The specified register is Control Register + // + case ControlRegister: + Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } - } - Value = (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); - break; - // - // The specified register is Model Specific Register - // - case Msr: - if (RegisterTableEntry->TestThenWrite) { - Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); - if (RegisterTableEntry->ValidBitLength >= 64) { - if (Value == RegisterTableEntry->Value) { - break; - } - } else { + if (RegisterTableEntry->TestThenWrite) { CurrentValue = BitFieldRead64 ( Value, RegisterTableEntry->ValidBitStart, @@ -960,153 +954,190 @@ ProgramProcessorRegister ( break; } } - } - if (RegisterTableEntry->ValidBitLength >= 64) { - // - // If length is not less than 64 bits, then directly write without reading - // - AsmWriteMsr64 ( - RegisterTableEntry->Index, - RegisterTableEntry->Value - ); - } else { - // - // Set the bit section according to bit start and length - // - AsmMsrBitFieldWrite64 ( - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - } - break; - // - // MemoryMapped operations - // - case MemoryMapped: - AcquireSpinLock (&CpuFlags->MemoryMappedLock); - MmioBitFieldWrite32 ( - (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - (UINT32)RegisterTableEntry->Value - ); - ReleaseSpinLock (&CpuFlags->MemoryMappedLock); - break; - // - // Enable or disable cache - // - case CacheControl: - // - // If value of the entry is 0, then disable cache. Otherwise, enable cache. - // - if (RegisterTableEntry->Value == 0) { - AsmDisableCache (); - } else { - AsmEnableCache (); - } - break; + Value = (UINTN)BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); + break; - case Semaphore: - // Semaphore works logic like below: // - // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]); - // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]); + // The specified register is Model Specific Register // - // All threads (T0...Tn) waits in P() line and continues running - // together. + case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >= 64) { + if (Value == RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue = BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 + ); + if (CurrentValue == RegisterTableEntry->Value) { + break; + } + } + } + + if (RegisterTableEntry->ValidBitLength >= 64) { + // + // If length is not less than 64 bits, then directly write without reading + // + AsmWriteMsr64 ( + RegisterTableEntry->Index, + RegisterTableEntry->Value + ); + } else { + // + // Set the bit section according to bit start and length + // + AsmMsrBitFieldWrite64 ( + RegisterTableEntry->Index, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + } + + break; // + // MemoryMapped operations // - // T0 T1 ... Tn + case MemoryMapped: + AcquireSpinLock (&CpuFlags->MemoryMappedLock); + MmioBitFieldWrite32 ( + (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + (UINT32)RegisterTableEntry->Value + ); + ReleaseSpinLock (&CpuFlags->MemoryMappedLock); + break; // - // V(0...n) V(0...n) ... V(0...n) - // n * P(0) n * P(1) ... n * P(n) + // Enable or disable cache // - switch (RegisterTableEntry->Value) { - case CoreDepType: - SemaphorePtr = CpuFlags->CoreSemaphoreCount; - ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore; - - CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core; + case CacheControl: // - // Get Offset info for the first thread in the core which current thread belongs to. + // If value of the entry is 0, then disable cache. Otherwise, enable cache. // - FirstThread = CurrentCore * CpuStatus->MaxThreadCount; - CurrentThread = FirstThread + ApLocation->Thread; - - // - // Different cores may have different valid threads in them. If driver maintail clearly - // thread index in different cores, the logic will be much complicated. - // Here driver just simply records the max thread number in all cores and use it as expect - // thread number for all cores. - // In below two steps logic, first current thread will Release semaphore for each thread - // in current core. Maybe some threads are not valid in this core, but driver don't - // care. Second, driver will let current thread wait semaphore for all valid threads in - // current core. Because only the valid threads will do release semaphore for this - // thread, driver here only need to wait the valid thread count. - // - - // - // First Notify ALL THREADs in current Core that this thread is ready. - // - for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) { - LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); - } - // - // Second, check whether all VALID THREADs (not all threads) in current core are ready. - // - for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) { - LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); + if (RegisterTableEntry->Value == 0) { + AsmDisableCache (); + } else { + AsmEnableCache (); } + break; - case PackageDepType: - SemaphorePtr = CpuFlags->PackageSemaphoreCount; - ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage; + case Semaphore: + // Semaphore works logic like below: // - // Get Offset info for the first thread in the package which current thread belongs to. + // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]); + // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]); // - FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount; + // All threads (T0...Tn) waits in P() line and continues running + // together. // - // Get the possible threads count for current package. // - CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread; - + // T0 T1 ... Tn // - // Different packages may have different valid threads in them. If driver maintail clearly - // thread index in different packages, the logic will be much complicated. - // Here driver just simply records the max thread number in all packages and use it as expect - // thread number for all packages. - // In below two steps logic, first current thread will Release semaphore for each thread - // in current package. Maybe some threads are not valid in this package, but driver don't - // care. Second, driver will let current thread wait semaphore for all valid threads in - // current package. Because only the valid threads will do release semaphore for this - // thread, driver here only need to wait the valid thread count. + // V(0...n) V(0...n) ... V(0...n) + // n * P(0) n * P(1) ... n * P(n) // + switch (RegisterTableEntry->Value) { + case CoreDepType: + SemaphorePtr = CpuFlags->CoreSemaphoreCount; + ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore; + + CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core; + // + // Get Offset info for the first thread in the core which current thread belongs to. + // + FirstThread = CurrentCore * CpuStatus->MaxThreadCount; + CurrentThread = FirstThread + ApLocation->Thread; + + // + // Different cores may have different valid threads in them. If driver maintail clearly + // thread index in different cores, the logic will be much complicated. + // Here driver just simply records the max thread number in all cores and use it as expect + // thread number for all cores. + // In below two steps logic, first current thread will Release semaphore for each thread + // in current core. Maybe some threads are not valid in this core, but driver don't + // care. Second, driver will let current thread wait semaphore for all valid threads in + // current core. Because only the valid threads will do release semaphore for this + // thread, driver here only need to wait the valid thread count. + // + + // + // First Notify ALL THREADs in current Core that this thread is ready. + // + for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) { + LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); + } + + // + // Second, check whether all VALID THREADs (not all threads) in current core are ready. + // + for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) { + LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); + } - // - // First Notify ALL THREADS in current package that this thread is ready. - // - for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) { - LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); - } - // - // Second, check whether VALID THREADS (not all threads) in current package are ready. - // - for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) { - LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); + break; + + case PackageDepType: + SemaphorePtr = CpuFlags->PackageSemaphoreCount; + ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage; + // + // Get Offset info for the first thread in the package which current thread belongs to. + // + FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount; + // + // Get the possible threads count for current package. + // + CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread; + + // + // Different packages may have different valid threads in them. If driver maintail clearly + // thread index in different packages, the logic will be much complicated. + // Here driver just simply records the max thread number in all packages and use it as expect + // thread number for all packages. + // In below two steps logic, first current thread will Release semaphore for each thread + // in current package. Maybe some threads are not valid in this package, but driver don't + // care. Second, driver will let current thread wait semaphore for all valid threads in + // current package. Because only the valid threads will do release semaphore for this + // thread, driver here only need to wait the valid thread count. + // + + // + // First Notify ALL THREADS in current package that this thread is ready. + // + for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) { + LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); + } + + // + // Second, check whether VALID THREADS (not all threads) in current package are ready. + // + for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) { + LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); + } + + break; + + default: + break; } + break; default: break; - } - break; - - default: - break; } } } @@ -1120,32 +1151,33 @@ ProgramProcessorRegister ( VOID EFIAPI SetProcessorRegister ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ) { - CPU_FEATURES_DATA *CpuFeaturesData; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE *RegisterTables; - UINT32 InitApicId; - UINTN ProcIndex; - UINTN Index; - ACPI_CPU_DATA *AcpiCpuData; + CPU_FEATURES_DATA *CpuFeaturesData; + CPU_REGISTER_TABLE *RegisterTable; + CPU_REGISTER_TABLE *RegisterTables; + UINT32 InitApicId; + UINTN ProcIndex; + UINTN Index; + ACPI_CPU_DATA *AcpiCpuData; - CpuFeaturesData = (CPU_FEATURES_DATA *) Buffer; - AcpiCpuData = CpuFeaturesData->AcpiCpuData; + CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer; + AcpiCpuData = CpuFeaturesData->AcpiCpuData; RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable; - InitApicId = GetInitialApicId (); + InitApicId = GetInitialApicId (); RegisterTable = NULL; - ProcIndex = (UINTN)-1; + ProcIndex = (UINTN)-1; for (Index = 0; Index < AcpiCpuData->NumberOfCpus; Index++) { if (RegisterTables[Index].InitialApicId == InitApicId) { RegisterTable = &RegisterTables[Index]; - ProcIndex = Index; + ProcIndex = Index; break; } } + ASSERT (RegisterTable != NULL); ProgramProcessorRegister ( @@ -1170,9 +1202,9 @@ CpuFeaturesDetect ( VOID ) { - CPU_FEATURES_DATA *CpuFeaturesData; + CPU_FEATURES_DATA *CpuFeaturesData; - CpuFeaturesData = GetCpuFeaturesData(); + CpuFeaturesData = GetCpuFeaturesData (); CpuInitDataInitialize (); diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c index e2e06e88e0..e635cade5d 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c @@ -13,7 +13,7 @@ #include "RegisterCpuFeatures.h" -CPU_FEATURES_DATA mCpuFeaturesData = {0}; +CPU_FEATURES_DATA mCpuFeaturesData = { 0 }; /** Worker function to get CPU_FEATURES_DATA pointer. @@ -38,17 +38,17 @@ GetMpService ( VOID ) { - EFI_STATUS Status; - MP_SERVICES MpService; + EFI_STATUS Status; + MP_SERVICES MpService; // // Get MP Services Protocol // Status = gBS->LocateProtocol ( - &gEfiMpServiceProtocolGuid, - NULL, - (VOID **)&MpService.Protocol - ); + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **)&MpService.Protocol + ); ASSERT_EFI_ERROR (Status); return MpService; @@ -63,15 +63,15 @@ GetMpService ( **/ UINTN GetProcessorIndex ( - IN CPU_FEATURES_DATA *CpuFeaturesData + IN CPU_FEATURES_DATA *CpuFeaturesData ) { - EFI_STATUS Status; - UINTN ProcessorIndex; - EFI_MP_SERVICES_PROTOCOL *MpServices; + EFI_STATUS Status; + UINTN ProcessorIndex; + EFI_MP_SERVICES_PROTOCOL *MpServices; MpServices = CpuFeaturesData->MpService.Protocol; - Status = MpServices->WhoAmI(MpServices, &ProcessorIndex); + Status = MpServices->WhoAmI (MpServices, &ProcessorIndex); ASSERT_EFI_ERROR (Status); return ProcessorIndex; } @@ -88,22 +88,22 @@ GetProcessorIndex ( **/ EFI_STATUS GetProcessorInformation ( - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ) { - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpServices; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - MpServices = CpuFeaturesData->MpService.Protocol; + MpServices = CpuFeaturesData->MpService.Protocol; Status = MpServices->GetProcessorInfo ( - MpServices, - ProcessorNumber, - ProcessorInfoBuffer - ); + MpServices, + ProcessorNumber, + ProcessorInfoBuffer + ); return Status; } @@ -117,29 +117,29 @@ GetProcessorInformation ( **/ VOID StartupAllAPsWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN EFI_EVENT MpEvent + IN EFI_AP_PROCEDURE Procedure, + IN EFI_EVENT MpEvent ) { - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpServices; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - MpServices = CpuFeaturesData->MpService.Protocol; + MpServices = CpuFeaturesData->MpService.Protocol; // // Wakeup all APs // Status = MpServices->StartupAllAPs ( - MpServices, - Procedure, - FALSE, - MpEvent, - 0, - CpuFeaturesData, - NULL - ); + MpServices, + Procedure, + FALSE, + MpEvent, + 0, + CpuFeaturesData, + NULL + ); ASSERT_EFI_ERROR (Status); } @@ -150,24 +150,24 @@ StartupAllAPsWorker ( **/ VOID SwitchNewBsp ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpServices; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - MpServices = CpuFeaturesData->MpService.Protocol; + MpServices = CpuFeaturesData->MpService.Protocol; // // Wakeup all APs // Status = MpServices->SwitchBSP ( - MpServices, - ProcessorNumber, - TRUE - ); + MpServices, + ProcessorNumber, + TRUE + ); ASSERT_EFI_ERROR (Status); } @@ -183,16 +183,16 @@ SwitchNewBsp ( **/ VOID GetNumberOfProcessor ( - OUT UINTN *NumberOfCpus, - OUT UINTN *NumberOfEnabledProcessors + OUT UINTN *NumberOfCpus, + OUT UINTN *NumberOfEnabledProcessors ) { - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpServices; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - MpServices = CpuFeaturesData->MpService.Protocol; + MpServices = CpuFeaturesData->MpService.Protocol; // // Get the number of CPUs @@ -219,14 +219,14 @@ CpuFeaturesInitialize ( VOID ) { - CPU_FEATURES_DATA *CpuFeaturesData; - UINTN OldBspNumber; - EFI_EVENT MpEvent; - EFI_STATUS Status; + CPU_FEATURES_DATA *CpuFeaturesData; + UINTN OldBspNumber; + EFI_EVENT MpEvent; + EFI_STATUS Status; CpuFeaturesData = GetCpuFeaturesData (); - OldBspNumber = GetProcessorIndex (CpuFeaturesData); + OldBspNumber = GetProcessorIndex (CpuFeaturesData); CpuFeaturesData->BspNumber = OldBspNumber; // @@ -263,6 +263,7 @@ CpuFeaturesInitialize ( do { Status = gBS->CheckEvent (MpEvent); } while (Status == EFI_NOT_READY); + ASSERT_EFI_ERROR (Status); } @@ -273,4 +274,3 @@ CpuFeaturesInitialize ( SwitchNewBsp (CpuFeaturesData->BspNumber); } } - diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c index 4e558e9fee..d4c528b3e9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c @@ -20,7 +20,7 @@ 0xa694c467, 0x697a, 0x446b, { 0xb9, 0x29, 0x5b, 0x14, 0xa0, 0xcf, 0x39, 0xf } \ } -EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID; +EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID; /** Worker function to get CPU_FEATURES_DATA pointer. @@ -32,16 +32,16 @@ GetCpuFeaturesData ( VOID ) { - CPU_FEATURES_DATA *CpuInitData; - EFI_HOB_GUID_TYPE *GuidHob; - VOID *DataInHob; - UINT64 Data64; + CPU_FEATURES_DATA *CpuInitData; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *DataInHob; + UINT64 Data64; CpuInitData = NULL; - GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid); + GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid); if (GuidHob != NULL) { - DataInHob = GET_GUID_HOB_DATA (GuidHob); - CpuInitData = (CPU_FEATURES_DATA *) (*(UINTN *) DataInHob); + DataInHob = GET_GUID_HOB_DATA (GuidHob); + CpuInitData = (CPU_FEATURES_DATA *)(*(UINTN *)DataInHob); ASSERT (CpuInitData != NULL); } else { CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA)); @@ -49,10 +49,10 @@ GetCpuFeaturesData ( // // Build location of CPU MP DATA buffer in HOB // - Data64 = (UINT64) (UINTN) CpuInitData; + Data64 = (UINT64)(UINTN)CpuInitData; BuildGuidDataHob ( &mRegisterCpuFeaturesHobGuid, - (VOID *) &Data64, + (VOID *)&Data64, sizeof (UINT64) ); } @@ -70,8 +70,8 @@ GetMpService ( VOID ) { - EFI_STATUS Status; - MP_SERVICES MpService; + EFI_STATUS Status; + MP_SERVICES MpService; // // Get MP Services2 Ppi @@ -95,12 +95,12 @@ GetMpService ( **/ UINTN GetProcessorIndex ( - IN CPU_FEATURES_DATA *CpuFeaturesData + IN CPU_FEATURES_DATA *CpuFeaturesData ) { - EFI_STATUS Status; - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - UINTN ProcessorIndex; + EFI_STATUS Status; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + UINTN ProcessorIndex; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; @@ -126,22 +126,22 @@ GetProcessorIndex ( **/ EFI_STATUS GetProcessorInformation ( - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ) { - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - EFI_STATUS Status; - CPU_FEATURES_DATA *CpuFeaturesData; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + EFI_STATUS Status; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; Status = CpuMp2Ppi->GetProcessorInfo ( - CpuMp2Ppi, - ProcessorNumber, - ProcessorInfoBuffer - ); + CpuMp2Ppi, + ProcessorNumber, + ProcessorInfoBuffer + ); return Status; } @@ -155,27 +155,27 @@ GetProcessorInformation ( **/ VOID StartupAllAPsWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN EFI_EVENT MpEvent + IN EFI_AP_PROCEDURE Procedure, + IN EFI_EVENT MpEvent ) { - EFI_STATUS Status; - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; // // Wakeup all APs for data collection. // Status = CpuMp2Ppi->StartupAllAPs ( - CpuMp2Ppi, - Procedure, - FALSE, - 0, - CpuFeaturesData - ); + CpuMp2Ppi, + Procedure, + FALSE, + 0, + CpuFeaturesData + ); ASSERT_EFI_ERROR (Status); } @@ -188,12 +188,12 @@ StartupAllAPsWorker ( **/ VOID StartupAllCPUsWorker ( - IN EFI_AP_PROCEDURE Procedure + IN EFI_AP_PROCEDURE Procedure ) { - EFI_STATUS Status; - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); @@ -201,12 +201,12 @@ StartupAllCPUsWorker ( // Get MP Services2 Ppi // CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; - Status = CpuMp2Ppi->StartupAllCPUs ( - CpuMp2Ppi, - Procedure, - 0, - CpuFeaturesData - ); + Status = CpuMp2Ppi->StartupAllCPUs ( + CpuMp2Ppi, + Procedure, + 0, + CpuFeaturesData + ); ASSERT_EFI_ERROR (Status); } @@ -217,24 +217,24 @@ StartupAllCPUsWorker ( **/ VOID SwitchNewBsp ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - EFI_STATUS Status; - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; // // Wakeup all APs for data collection. // Status = CpuMp2Ppi->SwitchBSP ( - CpuMp2Ppi, - ProcessorNumber, - TRUE - ); + CpuMp2Ppi, + ProcessorNumber, + TRUE + ); ASSERT_EFI_ERROR (Status); } @@ -250,25 +250,25 @@ SwitchNewBsp ( **/ VOID GetNumberOfProcessor ( - OUT UINTN *NumberOfCpus, - OUT UINTN *NumberOfEnabledProcessors + OUT UINTN *NumberOfCpus, + OUT UINTN *NumberOfEnabledProcessors ) { - EFI_STATUS Status; - EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; + CPU_FEATURES_DATA *CpuFeaturesData; CpuFeaturesData = GetCpuFeaturesData (); - CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; // // Get the number of CPUs // Status = CpuMp2Ppi->GetNumberOfProcessors ( - CpuMp2Ppi, - NumberOfCpus, - NumberOfEnabledProcessors - ); + CpuMp2Ppi, + NumberOfCpus, + NumberOfEnabledProcessors + ); ASSERT_EFI_ERROR (Status); } @@ -286,12 +286,12 @@ CpuFeaturesInitialize ( VOID ) { - CPU_FEATURES_DATA *CpuFeaturesData; - UINTN OldBspNumber; + CPU_FEATURES_DATA *CpuFeaturesData; + UINTN OldBspNumber; CpuFeaturesData = GetCpuFeaturesData (); - OldBspNumber = GetProcessorIndex (CpuFeaturesData); + OldBspNumber = GetProcessorIndex (CpuFeaturesData); CpuFeaturesData->BspNumber = OldBspNumber; // @@ -306,4 +306,3 @@ CpuFeaturesInitialize ( SwitchNewBsp (CpuFeaturesData->BspNumber); } } - diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h index e8a4aa644d..4a84954cac 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h @@ -27,66 +27,66 @@ #define CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'F', 'E', 'S') -#define CPU_FEATURE_NAME_SIZE 128 +#define CPU_FEATURE_NAME_SIZE 128 typedef struct { - REGISTER_CPU_FEATURE_INFORMATION CpuInfo; - UINT8 *FeaturesSupportedMask; - LIST_ENTRY OrderList; + REGISTER_CPU_FEATURE_INFORMATION CpuInfo; + UINT8 *FeaturesSupportedMask; + LIST_ENTRY OrderList; } CPU_FEATURES_INIT_ORDER; typedef struct { - UINT32 Signature; - LIST_ENTRY Link; - UINT8 *FeatureMask; - CHAR8 *FeatureName; - CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc; - CPU_FEATURE_SUPPORT SupportFunc; - CPU_FEATURE_INITIALIZE InitializeFunc; - UINT8 *ThreadBeforeFeatureBitMask; - UINT8 *ThreadAfterFeatureBitMask; - UINT8 *CoreBeforeFeatureBitMask; - UINT8 *CoreAfterFeatureBitMask; - UINT8 *PackageBeforeFeatureBitMask; - UINT8 *PackageAfterFeatureBitMask; - VOID *ConfigData; - BOOLEAN BeforeAll; - BOOLEAN AfterAll; + UINT32 Signature; + LIST_ENTRY Link; + UINT8 *FeatureMask; + CHAR8 *FeatureName; + CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc; + CPU_FEATURE_SUPPORT SupportFunc; + CPU_FEATURE_INITIALIZE InitializeFunc; + UINT8 *ThreadBeforeFeatureBitMask; + UINT8 *ThreadAfterFeatureBitMask; + UINT8 *CoreBeforeFeatureBitMask; + UINT8 *CoreAfterFeatureBitMask; + UINT8 *PackageBeforeFeatureBitMask; + UINT8 *PackageAfterFeatureBitMask; + VOID *ConfigData; + BOOLEAN BeforeAll; + BOOLEAN AfterAll; } CPU_FEATURES_ENTRY; // // Flags used when program the register. // typedef struct { - volatile UINTN MemoryMappedLock; // Spinlock used to program mmio - volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore. - volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore. + volatile UINTN MemoryMappedLock; // Spinlock used to program mmio + volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore. + volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore. } PROGRAM_CPU_REGISTER_FLAGS; typedef union { - EFI_MP_SERVICES_PROTOCOL *Protocol; - EDKII_PEI_MP_SERVICES2_PPI *Ppi; + EFI_MP_SERVICES_PROTOCOL *Protocol; + EDKII_PEI_MP_SERVICES2_PPI *Ppi; } MP_SERVICES; typedef struct { - UINTN FeaturesCount; - UINT32 BitMaskSize; - LIST_ENTRY FeatureList; + UINTN FeaturesCount; + UINT32 BitMaskSize; + LIST_ENTRY FeatureList; - CPU_FEATURES_INIT_ORDER *InitOrder; - UINT8 *CapabilityPcd; - UINT8 *SettingPcd; + CPU_FEATURES_INIT_ORDER *InitOrder; + UINT8 *CapabilityPcd; + UINT8 *SettingPcd; - UINT32 NumberOfCpus; - ACPI_CPU_DATA *AcpiCpuData; + UINT32 NumberOfCpus; + ACPI_CPU_DATA *AcpiCpuData; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE *PreSmmRegisterTable; - UINTN BspNumber; + CPU_REGISTER_TABLE *RegisterTable; + CPU_REGISTER_TABLE *PreSmmRegisterTable; + UINTN BspNumber; - PROGRAM_CPU_REGISTER_FLAGS CpuFlags; + PROGRAM_CPU_REGISTER_FLAGS CpuFlags; - MP_SERVICES MpService; + MP_SERVICES MpService; } CPU_FEATURES_DATA; #define CPU_FEATURE_ENTRY_FROM_LINK(a) \ @@ -116,7 +116,7 @@ GetCpuFeaturesData ( **/ UINTN GetProcessorIndex ( - IN CPU_FEATURES_DATA *CpuFeaturesData + IN CPU_FEATURES_DATA *CpuFeaturesData ); /** @@ -131,8 +131,8 @@ GetProcessorIndex ( **/ EFI_STATUS GetProcessorInformation ( - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ); /** @@ -145,8 +145,8 @@ GetProcessorInformation ( **/ VOID StartupAllAPsWorker ( - IN EFI_AP_PROCEDURE Procedure, - IN EFI_EVENT MpEvent + IN EFI_AP_PROCEDURE Procedure, + IN EFI_EVENT MpEvent ); /** @@ -161,8 +161,8 @@ StartupAllAPsWorker ( **/ VOID GetNumberOfProcessor ( - OUT UINTN *NumberOfCpus, - OUT UINTN *NumberOfEnabledProcessors + OUT UINTN *NumberOfCpus, + OUT UINTN *NumberOfEnabledProcessors ); /** @@ -172,7 +172,7 @@ GetNumberOfProcessor ( **/ VOID SwitchNewBsp ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ); /** @@ -184,8 +184,8 @@ SwitchNewBsp ( **/ VOID DumpCpuFeatureMask ( - IN UINT8 *FeatureMask, - IN UINT32 BitMaskSize + IN UINT8 *FeatureMask, + IN UINT32 BitMaskSize ); /** @@ -212,9 +212,9 @@ DumpCpuFeature ( **/ CPU_FEATURE_DEPENDENCE_TYPE DetectFeatureScope ( - IN CPU_FEATURES_ENTRY *CpuFeature, - IN BOOLEAN Before, - IN UINT8 *NextCpuFeatureMask + IN CPU_FEATURES_ENTRY *CpuFeature, + IN BOOLEAN Before, + IN UINT8 *NextCpuFeatureMask ); /** @@ -228,9 +228,9 @@ DetectFeatureScope ( **/ CPU_FEATURE_DEPENDENCE_TYPE DetectNoneNeighborhoodFeatureScope ( - IN CPU_FEATURES_ENTRY *CpuFeature, - IN BOOLEAN Before, - IN LIST_ENTRY *FeatureList + IN CPU_FEATURES_ENTRY *CpuFeature, + IN BOOLEAN Before, + IN LIST_ENTRY *FeatureList ); /** @@ -242,7 +242,7 @@ DetectNoneNeighborhoodFeatureScope ( VOID EFIAPI SetProcessorRegister ( - IN OUT VOID *Buffer + IN OUT VOID *Buffer ); /** diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index ffe34ffb48..0285aaf5c9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -17,17 +17,18 @@ **/ VOID DumpCpuFeatureMask ( - IN UINT8 *FeatureMask, - IN UINT32 BitMaskSize + IN UINT8 *FeatureMask, + IN UINT32 BitMaskSize ) { - UINTN Index; - UINT8 *Data8; + UINTN Index; + UINT8 *Data8; - Data8 = (UINT8 *) FeatureMask; + Data8 = (UINT8 *)FeatureMask; for (Index = 0; Index < BitMaskSize; Index++) { DEBUG ((DEBUG_INFO, " %02x ", *Data8++)); } + DEBUG ((DEBUG_INFO, "\n")); } @@ -44,7 +45,6 @@ DumpCpuFeature ( IN UINT32 BitMaskSize ) { - if (CpuFeature->FeatureName != NULL) { DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName)); } else { @@ -64,8 +64,8 @@ DumpCpuFeature ( **/ BOOLEAN IsBitMaskMatchCheck ( - IN UINT8 *FeatureMask, - IN UINT8 *DependentBitMask + IN UINT8 *FeatureMask, + IN UINT8 *DependentBitMask ) { UINTN Index; @@ -82,6 +82,7 @@ IsBitMaskMatchCheck ( return TRUE; } } + return FALSE; } @@ -98,14 +99,14 @@ IsBitMaskMatchCheck ( **/ BOOLEAN FindSpecifyFeature ( - IN LIST_ENTRY *FeatureList, - IN LIST_ENTRY *CurrentEntry, - IN BOOLEAN SearchFormer, - IN UINT8 *FeatureMask + IN LIST_ENTRY *FeatureList, + IN LIST_ENTRY *CurrentEntry, + IN BOOLEAN SearchFormer, + IN UINT8 *FeatureMask ) { - CPU_FEATURES_ENTRY *CpuFeature; - LIST_ENTRY *NextEntry; + CPU_FEATURES_ENTRY *CpuFeature; + LIST_ENTRY *NextEntry; // // Check whether exist the not neighborhood entry first. @@ -165,9 +166,9 @@ FindSpecifyFeature ( **/ CPU_FEATURE_DEPENDENCE_TYPE DetectFeatureScope ( - IN CPU_FEATURES_ENTRY *CpuFeature, - IN BOOLEAN Before, - IN UINT8 *NextCpuFeatureMask + IN CPU_FEATURES_ENTRY *CpuFeature, + IN BOOLEAN Before, + IN UINT8 *NextCpuFeatureMask ) { // @@ -185,17 +186,20 @@ DetectFeatureScope ( if (Before) { if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) + { return PackageDepType; } if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) + { return CoreDepType; } if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) + { return ThreadDepType; } @@ -203,17 +207,20 @@ DetectFeatureScope ( } if ((CpuFeature->PackageAfterFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) + { return PackageDepType; } if ((CpuFeature->CoreAfterFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) + { return CoreDepType; } if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) && - IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) { + IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) + { return ThreadDepType; } @@ -231,24 +238,27 @@ DetectFeatureScope ( **/ CPU_FEATURE_DEPENDENCE_TYPE DetectNoneNeighborhoodFeatureScope ( - IN CPU_FEATURES_ENTRY *CpuFeature, - IN BOOLEAN Before, - IN LIST_ENTRY *FeatureList + IN CPU_FEATURES_ENTRY *CpuFeature, + IN BOOLEAN Before, + IN LIST_ENTRY *FeatureList ) { if (Before) { if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) + { return PackageDepType; } if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) + { return CoreDepType; } if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) + { return ThreadDepType; } @@ -256,17 +266,20 @@ DetectNoneNeighborhoodFeatureScope ( } if ((CpuFeature->PackageAfterFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) + { return PackageDepType; } if ((CpuFeature->CoreAfterFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) + { return CoreDepType; } if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) && - FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) { + FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) + { return ThreadDepType; } @@ -294,17 +307,17 @@ DetectNoneNeighborhoodFeatureScope ( **/ BOOLEAN AdjustFeaturesDependence ( - IN OUT CPU_FEATURES_ENTRY *PreviousFeature, - IN OUT CPU_FEATURES_ENTRY *CurrentFeature, - IN CPU_FEATURES_ENTRY *FindFeature, - IN BOOLEAN Before + IN OUT CPU_FEATURES_ENTRY *PreviousFeature, + IN OUT CPU_FEATURES_ENTRY *CurrentFeature, + IN CPU_FEATURES_ENTRY *FindFeature, + IN BOOLEAN Before ) { - CPU_FEATURE_DEPENDENCE_TYPE PreDependType; - CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType; + CPU_FEATURE_DEPENDENCE_TYPE PreDependType; + CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType; - PreDependType = DetectFeatureScope(PreviousFeature, Before, FindFeature->FeatureMask); - CurrentDependType = DetectFeatureScope(CurrentFeature, Before, FindFeature->FeatureMask); + PreDependType = DetectFeatureScope (PreviousFeature, Before, FindFeature->FeatureMask); + CurrentDependType = DetectFeatureScope (CurrentFeature, Before, FindFeature->FeatureMask); // // If previous feature has no dependence with the find featue. @@ -336,16 +349,16 @@ AdjustFeaturesDependence ( **/ VOID AdjustEntry ( - IN LIST_ENTRY *FeatureList, - IN OUT LIST_ENTRY *FindEntry, - IN OUT LIST_ENTRY *CurrentEntry, - IN BOOLEAN Before + IN LIST_ENTRY *FeatureList, + IN OUT LIST_ENTRY *FindEntry, + IN OUT LIST_ENTRY *CurrentEntry, + IN BOOLEAN Before ) { - LIST_ENTRY *PreviousEntry; - CPU_FEATURES_ENTRY *PreviousFeature; - CPU_FEATURES_ENTRY *CurrentFeature; - CPU_FEATURES_ENTRY *FindFeature; + LIST_ENTRY *PreviousEntry; + CPU_FEATURES_ENTRY *PreviousFeature; + CPU_FEATURES_ENTRY *CurrentFeature; + CPU_FEATURES_ENTRY *FindFeature; // // For CPU feature which has core or package type dependence, later code need to insert @@ -363,11 +376,10 @@ AdjustEntry ( if (Before) { PreviousEntry = GetPreviousNode (FeatureList, FindEntry); } else { - PreviousEntry = GetNextNode (FeatureList, FindEntry); } - CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry); + CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry); RemoveEntryList (CurrentEntry); if (IsNull (FeatureList, PreviousEntry)) { @@ -407,7 +419,6 @@ AdjustEntry ( } } - /** Checks and adjusts current CPU features per dependency relationship. @@ -419,14 +430,14 @@ AdjustEntry ( **/ BOOLEAN InsertToBeforeEntry ( - IN LIST_ENTRY *FeatureList, - IN LIST_ENTRY *CurrentEntry, - IN UINT8 *FeatureMask + IN LIST_ENTRY *FeatureList, + IN LIST_ENTRY *CurrentEntry, + IN UINT8 *FeatureMask ) { - LIST_ENTRY *CheckEntry; - CPU_FEATURES_ENTRY *CheckFeature; - BOOLEAN Swapped; + LIST_ENTRY *CheckEntry; + CPU_FEATURES_ENTRY *CheckFeature; + BOOLEAN Swapped; Swapped = FALSE; @@ -441,6 +452,7 @@ InsertToBeforeEntry ( Swapped = TRUE; break; } + CheckEntry = CheckEntry->ForwardLink; } @@ -458,14 +470,14 @@ InsertToBeforeEntry ( **/ BOOLEAN InsertToAfterEntry ( - IN LIST_ENTRY *FeatureList, - IN LIST_ENTRY *CurrentEntry, - IN UINT8 *FeatureMask + IN LIST_ENTRY *FeatureList, + IN LIST_ENTRY *CurrentEntry, + IN UINT8 *FeatureMask ) { - LIST_ENTRY *CheckEntry; - CPU_FEATURES_ENTRY *CheckFeature; - BOOLEAN Swapped; + LIST_ENTRY *CheckEntry; + CPU_FEATURES_ENTRY *CheckFeature; + BOOLEAN Swapped; Swapped = FALSE; @@ -480,6 +492,7 @@ InsertToAfterEntry ( Swapped = TRUE; break; } + CheckEntry = CheckEntry->ForwardLink; } @@ -493,22 +506,22 @@ InsertToAfterEntry ( **/ VOID CheckCpuFeaturesDependency ( - IN LIST_ENTRY *FeatureList + IN LIST_ENTRY *FeatureList ) { - LIST_ENTRY *CurrentEntry; - CPU_FEATURES_ENTRY *CpuFeature; - LIST_ENTRY *CheckEntry; - CPU_FEATURES_ENTRY *CheckFeature; - BOOLEAN Swapped; - LIST_ENTRY *TempEntry; - LIST_ENTRY *NextEntry; + LIST_ENTRY *CurrentEntry; + CPU_FEATURES_ENTRY *CpuFeature; + LIST_ENTRY *CheckEntry; + CPU_FEATURES_ENTRY *CheckFeature; + BOOLEAN Swapped; + LIST_ENTRY *TempEntry; + LIST_ENTRY *NextEntry; CurrentEntry = GetFirstNode (FeatureList); while (!IsNull (FeatureList, CurrentEntry)) { - Swapped = FALSE; + Swapped = FALSE; CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry); - NextEntry = CurrentEntry->ForwardLink; + NextEntry = CurrentEntry->ForwardLink; if (CpuFeature->BeforeAll) { // // Check all features dispatched before this entry @@ -526,8 +539,10 @@ CheckCpuFeaturesDependency ( Swapped = TRUE; break; } + CheckEntry = CheckEntry->ForwardLink; } + if (Swapped) { CurrentEntry = NextEntry; continue; @@ -550,11 +565,13 @@ CheckCpuFeaturesDependency ( RemoveEntryList (CurrentEntry); InsertHeadList (CheckEntry, CurrentEntry); CurrentEntry = TempEntry; - Swapped = TRUE; + Swapped = TRUE; break; } + CheckEntry = CheckEntry->ForwardLink; } + if (Swapped) { CurrentEntry = NextEntry; continue; @@ -622,18 +639,18 @@ CheckCpuFeaturesDependency ( **/ RETURN_STATUS RegisterCpuFeatureWorker ( - IN CPU_FEATURES_DATA *CpuFeaturesData, - IN CPU_FEATURES_ENTRY *CpuFeature + IN CPU_FEATURES_DATA *CpuFeaturesData, + IN CPU_FEATURES_ENTRY *CpuFeature ) { - EFI_STATUS Status; - CPU_FEATURES_ENTRY *CpuFeatureEntry; - LIST_ENTRY *Entry; - BOOLEAN FeatureExist; + EFI_STATUS Status; + CPU_FEATURES_ENTRY *CpuFeatureEntry; + LIST_ENTRY *Entry; + BOOLEAN FeatureExist; - FeatureExist = FALSE; + FeatureExist = FALSE; CpuFeatureEntry = NULL; - Entry = GetFirstNode (&CpuFeaturesData->FeatureList); + Entry = GetFirstNode (&CpuFeaturesData->FeatureList); while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) { CpuFeatureEntry = CPU_FEATURE_ENTRY_FROM_LINK (Entry); if (CompareMem (CpuFeature->FeatureMask, CpuFeatureEntry->FeatureMask, CpuFeaturesData->BitMaskSize) == 0) { @@ -643,6 +660,7 @@ RegisterCpuFeatureWorker ( FeatureExist = TRUE; break; } + Entry = Entry->ForwardLink; } @@ -661,55 +679,71 @@ RegisterCpuFeatureWorker ( if (CpuFeature->GetConfigDataFunc != NULL) { CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc; } + if (CpuFeature->SupportFunc != NULL) { CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc; } + if (CpuFeature->InitializeFunc != NULL) { CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc; } + if (CpuFeature->FeatureName != NULL) { if (CpuFeatureEntry->FeatureName == NULL) { CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE); ASSERT (CpuFeatureEntry->FeatureName != NULL); } + Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName); ASSERT_EFI_ERROR (Status); FreePool (CpuFeature->FeatureName); } + if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask); } + CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask; } + if (CpuFeature->ThreadAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask); } + CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask; } + if (CpuFeature->CoreBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask); } + CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask; } + if (CpuFeature->CoreAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask); } + CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask; } + if (CpuFeature->PackageBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask); } + CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask; } + if (CpuFeature->PackageAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) { FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask); } + CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask; } @@ -719,6 +753,7 @@ RegisterCpuFeatureWorker ( FreePool (CpuFeature->FeatureMask); FreePool (CpuFeature); } + // // Verify CPU features dependency can change CPU feature order // @@ -735,12 +770,12 @@ RegisterCpuFeatureWorker ( **/ VOID SetCpuFeaturesBitMask ( - IN UINT8 **FeaturesBitMask, - IN UINT32 Feature, - IN UINTN BitMaskSize + IN UINT8 **FeaturesBitMask, + IN UINT32 Feature, + IN UINTN BitMaskSize ) { - UINT8 *CpuFeaturesBitMask; + UINT8 *CpuFeaturesBitMask; ASSERT (FeaturesBitMask != NULL); CpuFeaturesBitMask = *FeaturesBitMask; @@ -751,7 +786,7 @@ SetCpuFeaturesBitMask ( } CpuFeaturesBitMask += (Feature / 8); - *CpuFeaturesBitMask |= (UINT8) (1 << (Feature % 8)); + *CpuFeaturesBitMask |= (UINT8)(1 << (Feature % 8)); } /** @@ -803,27 +838,27 @@ SetCpuFeaturesBitMask ( RETURN_STATUS EFIAPI RegisterCpuFeature ( - IN CHAR8 *FeatureName OPTIONAL, - IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL, - IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL, - IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL, + IN CHAR8 *FeatureName OPTIONAL, + IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL, + IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL, + IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL, ... ) { - EFI_STATUS Status; - VA_LIST Marker; - UINT32 Feature; - CPU_FEATURES_ENTRY *CpuFeature; - UINT8 *FeatureMask; - UINT8 *ThreadBeforeFeatureBitMask; - UINT8 *ThreadAfterFeatureBitMask; - UINT8 *CoreBeforeFeatureBitMask; - UINT8 *CoreAfterFeatureBitMask; - UINT8 *PackageBeforeFeatureBitMask; - UINT8 *PackageAfterFeatureBitMask; - BOOLEAN BeforeAll; - BOOLEAN AfterAll; - CPU_FEATURES_DATA *CpuFeaturesData; + EFI_STATUS Status; + VA_LIST Marker; + UINT32 Feature; + CPU_FEATURES_ENTRY *CpuFeature; + UINT8 *FeatureMask; + UINT8 *ThreadBeforeFeatureBitMask; + UINT8 *ThreadAfterFeatureBitMask; + UINT8 *CoreBeforeFeatureBitMask; + UINT8 *CoreAfterFeatureBitMask; + UINT8 *PackageBeforeFeatureBitMask; + UINT8 *PackageAfterFeatureBitMask; + BOOLEAN BeforeAll; + BOOLEAN AfterAll; + CPU_FEATURES_DATA *CpuFeaturesData; FeatureMask = NULL; ThreadBeforeFeatureBitMask = NULL; @@ -832,8 +867,8 @@ RegisterCpuFeature ( CoreAfterFeatureBitMask = NULL; PackageBeforeFeatureBitMask = NULL; PackageAfterFeatureBitMask = NULL; - BeforeAll = FALSE; - AfterAll = FALSE; + BeforeAll = FALSE; + AfterAll = FALSE; CpuFeaturesData = GetCpuFeaturesData (); if (CpuFeaturesData->FeaturesCount == 0) { @@ -844,7 +879,7 @@ RegisterCpuFeature ( // ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesCapability)); ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesSupport)); - CpuFeaturesData->BitMaskSize = (UINT32) PcdGetSize (PcdCpuFeaturesSetting); + CpuFeaturesData->BitMaskSize = (UINT32)PcdGetSize (PcdCpuFeaturesSetting); } VA_START (Marker, InitializeFunc); @@ -853,19 +888,27 @@ RegisterCpuFeature ( // // It's invalid to require a feature is before AND after all other features. // - ASSERT ((Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)) - != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)); + ASSERT ( + (Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)) + != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL) + ); // // It's invalid to require feature A is before AND after before feature B, // either in thread level, core level or package level. // - ASSERT ((Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)) - != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)); - ASSERT ((Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)) - != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)); - ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)) - != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)); + ASSERT ( + (Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)) + != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER) + ); + ASSERT ( + (Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)) + != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER) + ); + ASSERT ( + (Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)) + != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER) + ); if (Feature < CPU_FEATURE_THREAD_BEFORE) { BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE; AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE; @@ -885,8 +928,10 @@ RegisterCpuFeature ( } else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) { SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize); } + Feature = VA_ARG (Marker, UINT32); } + VA_END (Marker); CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY)); @@ -905,7 +950,7 @@ RegisterCpuFeature ( CpuFeature->SupportFunc = SupportFunc; CpuFeature->InitializeFunc = InitializeFunc; if (FeatureName != NULL) { - CpuFeature->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE); + CpuFeature->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE); ASSERT (CpuFeature->FeatureName != NULL); Status = AsciiStrCpyS (CpuFeature->FeatureName, CPU_FEATURE_NAME_SIZE, FeatureName); ASSERT_EFI_ERROR (Status); @@ -927,18 +972,18 @@ GetAcpiCpuData ( VOID ) { - EFI_STATUS Status; - UINTN NumberOfCpus; - UINTN NumberOfEnabledProcessors; - ACPI_CPU_DATA *AcpiCpuData; - UINTN TableSize; - CPU_REGISTER_TABLE *RegisterTable; - UINTN Index; - EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; - - AcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress); + EFI_STATUS Status; + UINTN NumberOfCpus; + UINTN NumberOfEnabledProcessors; + ACPI_CPU_DATA *AcpiCpuData; + UINTN TableSize; + CPU_REGISTER_TABLE *RegisterTable; + UINTN Index; + EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; + + AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress); if (AcpiCpuData == NULL) { - AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA))); + AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA))); ASSERT (AcpiCpuData != NULL); ZeroMem (AcpiCpuData, sizeof (ACPI_CPU_DATA)); @@ -952,14 +997,15 @@ GetAcpiCpuData ( AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus; } - if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0 || - AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) { + if ((AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) || + (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0)) + { // // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs // - NumberOfCpus = AcpiCpuData->NumberOfCpus; - TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE); - RegisterTable = AllocatePages (EFI_SIZE_TO_PAGES (TableSize)); + NumberOfCpus = AcpiCpuData->NumberOfCpus; + TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE); + RegisterTable = AllocatePages (EFI_SIZE_TO_PAGES (TableSize)); ASSERT (RegisterTable != NULL); for (Index = 0; Index < NumberOfCpus; Index++) { @@ -976,9 +1022,11 @@ GetAcpiCpuData ( RegisterTable[NumberOfCpus + Index].AllocatedSize = 0; RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0; } + if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) { AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable; } + if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) { AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus); } @@ -995,14 +1043,14 @@ GetAcpiCpuData ( STATIC VOID EnlargeRegisterTable ( - IN OUT CPU_REGISTER_TABLE *RegisterTable + IN OUT CPU_REGISTER_TABLE *RegisterTable ) { EFI_PHYSICAL_ADDRESS Address; UINTN UsedPages; UsedPages = RegisterTable->AllocatedSize / EFI_PAGE_SIZE; - Address = (UINTN)AllocatePages (UsedPages + 1); + Address = (UINTN)AllocatePages (UsedPages + 1); ASSERT (Address != 0); // @@ -1011,8 +1059,8 @@ EnlargeRegisterTable ( // if (RegisterTable->AllocatedSize > 0) { CopyMem ( - (VOID *) (UINTN) Address, - (VOID *) (UINTN) RegisterTable->RegisterTableEntry, + (VOID *)(UINTN)Address, + (VOID *)(UINTN)RegisterTable->RegisterTableEntry, RegisterTable->AllocatedSize ); @@ -1045,27 +1093,27 @@ EnlargeRegisterTable ( **/ VOID CpuRegisterTableWriteWorker ( - IN BOOLEAN PreSmmFlag, - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT8 ValidBitStart, - IN UINT8 ValidBitLength, - IN UINT64 Value, - IN BOOLEAN TestThenWrite + IN BOOLEAN PreSmmFlag, + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value, + IN BOOLEAN TestThenWrite ) { - CPU_FEATURES_DATA *CpuFeaturesData; - ACPI_CPU_DATA *AcpiCpuData; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; + CPU_FEATURES_DATA *CpuFeaturesData; + ACPI_CPU_DATA *AcpiCpuData; + CPU_REGISTER_TABLE *RegisterTable; + CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; CpuFeaturesData = GetCpuFeaturesData (); if (CpuFeaturesData->RegisterTable == NULL) { AcpiCpuData = GetAcpiCpuData (); ASSERT ((AcpiCpuData != NULL) && (AcpiCpuData->CpuFeatureInitData.RegisterTable != 0)); - CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.RegisterTable; - CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable; + CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable; + CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable; } if (PreSmmFlag) { @@ -1081,10 +1129,10 @@ CpuRegisterTableWriteWorker ( // // Append entry in the register table. // - RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; + RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry; RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType; - RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index; - RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32) RShiftU64 (Index, 32); + RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32)Index; + RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32)RShiftU64 (Index, 32); RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength; RegisterTableEntry[RegisterTable->TableLength].Value = Value; @@ -1110,18 +1158,18 @@ CpuRegisterTableWriteWorker ( VOID EFIAPI CpuRegisterTableWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ) { - UINT8 Start; - UINT8 End; - UINT8 Length; + UINT8 Start; + UINT8 End; + UINT8 Length; - Start = (UINT8)LowBitSet64 (ValueMask); + Start = (UINT8)LowBitSet64 (ValueMask); End = (UINT8)HighBitSet64 (ValueMask); Length = End - Start + 1; CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE); @@ -1144,18 +1192,18 @@ CpuRegisterTableWrite ( VOID EFIAPI CpuRegisterTableTestThenWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ) { - UINT8 Start; - UINT8 End; - UINT8 Length; + UINT8 Start; + UINT8 End; + UINT8 Length; - Start = (UINT8)LowBitSet64 (ValueMask); + Start = (UINT8)LowBitSet64 (ValueMask); End = (UINT8)HighBitSet64 (ValueMask); Length = End - Start + 1; CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, TRUE); @@ -1178,18 +1226,18 @@ CpuRegisterTableTestThenWrite ( VOID EFIAPI PreSmmCpuRegisterTableWrite ( - IN UINTN ProcessorNumber, - IN REGISTER_TYPE RegisterType, - IN UINT64 Index, - IN UINT64 ValueMask, - IN UINT64 Value + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value ) { UINT8 Start; UINT8 End; UINT8 Length; - Start = (UINT8)LowBitSet64 (ValueMask); + Start = (UINT8)LowBitSet64 (ValueMask); End = (UINT8)HighBitSet64 (ValueMask); Length = End - Start + 1; CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE); @@ -1208,14 +1256,15 @@ PreSmmCpuRegisterTableWrite ( **/ BOOLEAN IsCpuFeatureSetInCpuPcd ( - IN UINT8 *CpuBitMask, - IN UINTN CpuBitMaskSize, - IN UINT32 Feature + IN UINT8 *CpuBitMask, + IN UINTN CpuBitMaskSize, + IN UINT32 Feature ) { if ((Feature >> 3) >= CpuBitMaskSize) { return FALSE; } + return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0); } @@ -1236,7 +1285,7 @@ IsCpuFeatureSetInCpuPcd ( BOOLEAN EFIAPI IsCpuFeatureSupported ( - IN UINT32 Feature + IN UINT32 Feature ) { return IsCpuFeatureSetInCpuPcd ( @@ -1260,7 +1309,7 @@ IsCpuFeatureSupported ( BOOLEAN EFIAPI IsCpuFeatureInSetting ( - IN UINT32 Feature + IN UINT32 Feature ) { return IsCpuFeatureSetInCpuPcd ( @@ -1280,11 +1329,11 @@ IsCpuFeatureInSetting ( VOID EFIAPI SwitchBspAfterFeaturesInitialize ( - IN UINTN ProcessorNumber + IN UINTN ProcessorNumber ) { - CPU_FEATURES_DATA *CpuFeaturesData; + CPU_FEATURES_DATA *CpuFeaturesData; - CpuFeaturesData = GetCpuFeaturesData (); + CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData->BspNumber = ProcessorNumber; } diff --git a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c index 8e2a420f80..e0149df044 100644 --- a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c +++ b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c @@ -27,10 +27,10 @@ InternalX86GetTimerFrequency ( VOID ) { - UINTN Divisor; + UINTN Divisor; GetApicTimerState (&Divisor, NULL, NULL); - return PcdGet32(PcdFSBClock) / (UINT32)Divisor; + return PcdGet32 (PcdFSBClock) / (UINT32)Divisor; } /** @@ -48,13 +48,13 @@ InternalX86GetTimerFrequency ( VOID EFIAPI InternalX86Delay ( - IN UINT32 Delay + IN UINT32 Delay ) { - INT32 Ticks; - UINT32 Times; - UINT32 InitCount; - UINT32 StartTick; + INT32 Ticks; + UINT32 Times; + UINT32 InitCount; + UINT32 StartTick; // // In case Delay is too larger, separate it into several small delay slot. @@ -65,13 +65,13 @@ InternalX86Delay ( // InitCount = GetApicTimerInitCount (); ASSERT (InitCount != 0); - Times = Delay / (InitCount / 2); - Delay = Delay % (InitCount / 2); + Times = Delay / (InitCount / 2); + Delay = Delay % (InitCount / 2); // // Get Start Tick and do delay // - StartTick = GetApicTimerCurrentCount (); + StartTick = GetApicTimerCurrentCount (); do { // // Wait until time out by Delay value @@ -111,7 +111,7 @@ InternalX86Delay ( UINTN EFIAPI MicroSecondDelay ( - IN UINTN MicroSeconds + IN UINTN MicroSeconds ) { InternalX86Delay ( @@ -139,7 +139,7 @@ MicroSecondDelay ( UINTN EFIAPI NanoSecondDelay ( - IN UINTN NanoSeconds + IN UINTN NanoSeconds ) { InternalX86Delay ( @@ -200,8 +200,8 @@ GetPerformanceCounter ( UINT64 EFIAPI GetPerformanceCounterProperties ( - OUT UINT64 *StartValue OPTIONAL, - OUT UINT64 *EndValue OPTIONAL + OUT UINT64 *StartValue OPTIONAL, + OUT UINT64 *EndValue OPTIONAL ) { if (StartValue != NULL) { @@ -212,7 +212,7 @@ GetPerformanceCounterProperties ( *EndValue = 0; } - return (UINT64) InternalX86GetTimerFrequency (); + return (UINT64)InternalX86GetTimerFrequency (); } /** @@ -229,7 +229,7 @@ GetPerformanceCounterProperties ( UINT64 EFIAPI GetTimeInNanoSecond ( - IN UINT64 Ticks + IN UINT64 Ticks ) { UINT64 Frequency; @@ -251,9 +251,9 @@ GetTimeInNanoSecond ( // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34, // i.e. highest bit set in Remainder should <= 33. // - Shift = MAX (0, HighBitSet64 (Remainder) - 33); - Remainder = RShiftU64 (Remainder, (UINTN) Shift); - Frequency = RShiftU64 (Frequency, (UINTN) Shift); + Shift = MAX (0, HighBitSet64 (Remainder) - 33); + Remainder = RShiftU64 (Remainder, (UINTN)Shift); + Frequency = RShiftU64 (Frequency, (UINTN)Shift); NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); return NanoSeconds; diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c index 24bd6d0a94..249cd40f9d 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c @@ -14,9 +14,9 @@ /// /// Page Table Entry /// -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_PS BIT7 +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_PS BIT7 /** @@ -28,14 +28,14 @@ **/ VOID StmGen4GPageTable ( - IN UINTN PageTableBase + IN UINTN PageTableBase ) { - UINTN Index; - UINT32 *Pte; - UINT32 Address; + UINTN Index; + UINT32 *Pte; + UINT32 Address; - Pte = (UINT32*)(UINTN)PageTableBase; + Pte = (UINT32 *)(UINTN)PageTableBase; Address = 0; for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) { @@ -63,7 +63,7 @@ StmGen4GPageTable ( UINT32 EFIAPI SmmStmExceptionHandler ( - IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context + IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context ) { // TBD - SmmStmExceptionHandler, record information diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index fa3a866ab6..78de7f8407 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -34,8 +34,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // MSRs required for configuration of SMM Code Access Check // -#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D -#define SMM_CODE_ACCESS_CHK_BIT BIT58 +#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D +#define SMM_CODE_ACCESS_CHK_BIT BIT58 // // Set default value to assume SMRR is not supported @@ -86,7 +86,7 @@ CpuFeaturesLibInitialization ( AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); FamilyId = (RegEax >> 8) & 0xf; ModelId = (RegEax >> 4) & 0xf; - if (FamilyId == 0x06 || FamilyId == 0x0f) { + if ((FamilyId == 0x06) || (FamilyId == 0x0f)) { ModelId = ModelId | ((RegEax >> 12) & 0xf0); } @@ -110,7 +110,7 @@ CpuFeaturesLibInitialization ( // SMRR Physical Base and SMM Physical Mask MSRs are not available. // if (FamilyId == 0x06) { - if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) { + if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) { mSmrrSupported = FALSE; } } @@ -123,7 +123,7 @@ CpuFeaturesLibInitialization ( // Processor Family MSRs // if (FamilyId == 0x06) { - if (ModelId == 0x17 || ModelId == 0x0f) { + if ((ModelId == 0x17) || (ModelId == 0x0f)) { mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE; mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK; } @@ -204,7 +204,7 @@ SmmCpuFeaturesInitializeProcessor ( // // Configure SMBASE. // - CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; // @@ -216,7 +216,7 @@ SmmCpuFeaturesInitializeProcessor ( // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A) // is set, then the MSR is locked and can not be modified. // - if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) { + if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) { FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL); if ((FeatureControl & BIT3) == 0) { if ((FeatureControl & BIT0) == 0) { @@ -242,7 +242,8 @@ SmmCpuFeaturesInitializeProcessor ( // if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) || - ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) { + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) + { // // Print message and halt if CPU is Monarch // @@ -263,7 +264,7 @@ SmmCpuFeaturesInitializeProcessor ( AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); FamilyId = (RegEax >> 8) & 0xf; ModelId = (RegEax >> 4) & 0xf; - if (FamilyId == 0x06 || FamilyId == 0x0f) { + if ((FamilyId == 0x06) || (FamilyId == 0x0f)) { ModelId = ModelId | ((RegEax >> 12) & 0xf0); } @@ -276,10 +277,11 @@ SmmCpuFeaturesInitializeProcessor ( // Intel(R) Core(TM) Processor Family MSRs. // if (FamilyId == 0x06) { - if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 || - ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F || - ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C || - ModelId == 0x8C) { + if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) || + (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) || + (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) || + (ModelId == 0x8C)) + { // // Check to see if the CPU supports the SMM Code Access Check feature // Do not access this MSR unless the CPU supports the SmmRegFeatureControl @@ -382,7 +384,7 @@ SmmCpuFeaturesDisableSmrr ( ) { if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID); + AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID); } } @@ -397,7 +399,7 @@ SmmCpuFeaturesReenableSmrr ( ) { if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID); + AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID); } } @@ -458,9 +460,10 @@ SmmCpuFeaturesIsSmmRegisterSupported ( IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) { return TRUE; } + return FALSE; } @@ -483,9 +486,10 @@ SmmCpuFeaturesGetSmmRegister ( IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) { return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); } + return 0; } @@ -508,7 +512,7 @@ SmmCpuFeaturesSetSmmRegister ( IN UINT64 Value ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) { AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); } } @@ -605,9 +609,8 @@ SmmCpuFeaturesCompleteSmmReadyToLock ( VOID * EFIAPI SmmCpuFeaturesAllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ) { return NULL; } - diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c index c92387625d..4e8f897f5e 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -24,21 +24,21 @@ #include "CpuFeaturesLib.h" #include "SmmStm.h" -#define TXT_EVTYPE_BASE 0x400 -#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) +#define TXT_EVTYPE_BASE 0x400 +#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) -#define RDWR_ACCS 3 -#define FULL_ACCS 7 +#define RDWR_ACCS 3 +#define FULL_ACCS 7 EFI_HANDLE mStmSmmCpuHandle = NULL; -BOOLEAN mLockLoadMonitor = FALSE; +BOOLEAN mLockLoadMonitor = FALSE; // // Template of STM_RSC_END structure for copying. // -GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = { - {END_OF_RESOURCES, sizeof (STM_RSC_END)}, +GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = { + { END_OF_RESOURCES, sizeof (STM_RSC_END) }, }; GLOBAL_REMOVE_IF_UNREFERENCED UINT8 *mStmResourcesPtr = NULL; @@ -52,7 +52,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mStmState = 0; // System Configuration Table pointing to STM Configuration Table // GLOBAL_REMOVE_IF_UNREFERENCED -EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = { +EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = { LoadMonitor, AddPiResource, DeletePiResource, @@ -60,10 +60,7 @@ EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = { GetMonitorState, }; - - - -#define CPUID1_EDX_XD_SUPPORT 0x100000 +#define CPUID1_EDX_XD_SUPPORT 0x100000 // // External global variables associated with SMI Handler Template @@ -146,10 +143,10 @@ SmmCpuFeaturesLibStmConstructor ( // // Retrieve MSEG location from MSEG SRAM HOB // - SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); + SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob); if (SmramDescriptor->PhysicalSize > 0) { - mMsegBase = (UINTN)SmramDescriptor->CpuStart; - mMsegSize = (UINTN)SmramDescriptor->PhysicalSize; + mMsegBase = (UINTN)SmramDescriptor->CpuStart; + mMsegSize = (UINTN)SmramDescriptor->PhysicalSize; } } else if (PcdGet32 (PcdCpuMsegSize) > 0) { // @@ -162,6 +159,7 @@ SmmCpuFeaturesLibStmConstructor ( DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize))); } } + if (mMsegBase > 0) { DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize)); } @@ -251,16 +249,16 @@ SmmCpuFeaturesInstallSmiHandler ( IN UINT32 Cr3 ) { - EFI_STATUS Status; - TXT_PROCESSOR_SMM_DESCRIPTOR *Psd; - VOID *Hob; - UINT32 RegEax; - UINT32 RegEdx; - EFI_PROCESSOR_INFORMATION ProcessorInfo; + EFI_STATUS Status; + TXT_PROCESSOR_SMM_DESCRIPTOR *Psd; + VOID *Hob; + UINT32 RegEax; + UINT32 RegEdx; + EFI_PROCESSOR_INFORMATION ProcessorInfo; CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof (gcStmPsd)); - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET); - Psd->SmmGdtPtr = GdtBase; + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET); + Psd->SmmGdtPtr = GdtBase; Psd->SmmGdtSize = (UINT32)GdtSize; // @@ -293,49 +291,49 @@ SmmCpuFeaturesInstallSmiHandler ( // // Set the value at the top of the CPU stack to the CPU Index // - *(UINTN*)(UINTN)gStmSmiStack = CpuIndex; + *(UINTN *)(UINTN)gStmSmiStack = CpuIndex; // // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), - (VOID*)gcStmSmiHandlerTemplate, + (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET), + (VOID *)gcStmSmiHandlerTemplate, gcStmSmiHandlerSize ); Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset; - Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN); + Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof (UINTN); Psd->SmmCr3 = Cr3; - DEBUG((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32(PcdCpuSmmStmExceptionStackSize))); - DEBUG((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize)))); - Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))); + DEBUG ((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32 (PcdCpuSmmStmExceptionStackSize))); + DEBUG ((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)))); + Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))); Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))); - Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource (); + Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource (); // // Get the APIC ID for the CPU specified by CpuIndex // Status = mSmmCpuFeaturesLibMpService->GetProcessorInfo ( - mSmmCpuFeaturesLibMpService, - CpuIndex, - &ProcessorInfo - ); + mSmmCpuFeaturesLibMpService, + CpuIndex, + &ProcessorInfo + ); ASSERT_EFI_ERROR (Status); Psd->LocalApicId = (UINT32)ProcessorInfo.ProcessorId; - Psd->AcpiRsdp = 0; + Psd->AcpiRsdp = 0; Hob = GetFirstHob (EFI_HOB_TYPE_CPU); if (Hob != NULL) { - Psd->PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; + Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; } else { AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000008) { AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - Psd->PhysicalAddressBits = (UINT8) RegEax; + Psd->PhysicalAddressBits = (UINT8)RegEax; } else { Psd->PhysicalAddressBits = 36; } @@ -385,6 +383,7 @@ SmmEndOfDxeEventNotify ( break; } } + if (Rsdp == NULL) { for (Index = 0; Index < gST->NumberOfTableEntries; Index++) { if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) { @@ -416,8 +415,8 @@ StmSmmConfigurationTableInit ( VOID ) { - EFI_STATUS Status; - VOID *Registration; + EFI_STATUS Status; + VOID *Registration; Status = gSmst->SmmInstallProtocolInterface ( &mStmSmmCpuHandle, @@ -468,19 +467,19 @@ GetMonitorState ( **/ BOOLEAN HandleSingleResource ( - IN STM_RSC *Resource, - IN STM_RSC *Record + IN STM_RSC *Resource, + IN STM_RSC *Record ) { - UINT64 ResourceLo; - UINT64 ResourceHi; - UINT64 RecordLo; - UINT64 RecordHi; + UINT64 ResourceLo; + UINT64 ResourceHi; + UINT64 RecordLo; + UINT64 RecordHi; ResourceLo = 0; ResourceHi = 0; - RecordLo = 0; - RecordHi = 0; + RecordLo = 0; + RecordHi = 0; // // Calling code is responsible for making sure that @@ -488,62 +487,69 @@ HandleSingleResource ( // thus we use just one of them as switch variable. // switch (Resource->Header.RscType) { - case MEM_RANGE: - case MMIO_RANGE: - ResourceLo = Resource->Mem.Base; - ResourceHi = Resource->Mem.Base + Resource->Mem.Length; - RecordLo = Record->Mem.Base; - RecordHi = Record->Mem.Base + Record->Mem.Length; - if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) { - if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { - Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes; - return TRUE; - } else { + case MEM_RANGE: + case MMIO_RANGE: + ResourceLo = Resource->Mem.Base; + ResourceHi = Resource->Mem.Base + Resource->Mem.Length; + RecordLo = Record->Mem.Base; + RecordHi = Record->Mem.Base + Record->Mem.Length; + if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes; + return TRUE; + } else { + return FALSE; + } + } + + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + ResourceLo = (UINT64)Resource->Io.Base; + ResourceHi = (UINT64)Resource->Io.Base + (UINT64)Resource->Io.Length; + RecordLo = (UINT64)Record->Io.Base; + RecordHi = (UINT64)Record->Io.Base + (UINT64)Record->Io.Length; + break; + case PCI_CFG_RANGE: + if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || + (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) + { return FALSE; } - } - break; - case IO_RANGE: - case TRAPPED_IO_RANGE: - ResourceLo = (UINT64) Resource->Io.Base; - ResourceHi = (UINT64) Resource->Io.Base + (UINT64) Resource->Io.Length; - RecordLo = (UINT64) Record->Io.Base; - RecordHi = (UINT64) Record->Io.Base + (UINT64) Record->Io.Length; - break; - case PCI_CFG_RANGE: - if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || - (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) { - return FALSE; - } - if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) { - return FALSE; - } - ResourceLo = (UINT64) Resource->PciCfg.Base; - ResourceHi = (UINT64) Resource->PciCfg.Base + (UINT64) Resource->PciCfg.Length; - RecordLo = (UINT64) Record->PciCfg.Base; - RecordHi = (UINT64) Record->PciCfg.Base + (UINT64) Record->PciCfg.Length; - if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { - if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { - Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; - return TRUE; - } else { + + if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof (STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) { return FALSE; } - } - break; - case MACHINE_SPECIFIC_REG: - // - // Special case - merge MSR masks in place. - // - if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { + + ResourceLo = (UINT64)Resource->PciCfg.Base; + ResourceHi = (UINT64)Resource->PciCfg.Base + (UINT64)Resource->PciCfg.Length; + RecordLo = (UINT64)Record->PciCfg.Base; + RecordHi = (UINT64)Record->PciCfg.Base + (UINT64)Record->PciCfg.Length; + if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; + return TRUE; + } else { + return FALSE; + } + } + + break; + case MACHINE_SPECIFIC_REG: + // + // Special case - merge MSR masks in place. + // + if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { + return FALSE; + } + + Record->Msr.ReadMask |= Resource->Msr.ReadMask; + Record->Msr.WriteMask |= Resource->Msr.WriteMask; + return TRUE; + default: return FALSE; - } - Record->Msr.ReadMask |= Resource->Msr.ReadMask; - Record->Msr.WriteMask |= Resource->Msr.WriteMask; - return TRUE; - default: - return FALSE; } + // // If resources are disjoint // @@ -557,6 +563,7 @@ HandleSingleResource ( if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) { return TRUE; } + // // Resources are overlapping. // Resource and record are merged. @@ -565,22 +572,22 @@ HandleSingleResource ( ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi; switch (Resource->Header.RscType) { - case MEM_RANGE: - case MMIO_RANGE: - Record->Mem.Base = ResourceLo; - Record->Mem.Length = ResourceHi - ResourceLo; - break; - case IO_RANGE: - case TRAPPED_IO_RANGE: - Record->Io.Base = (UINT16) ResourceLo; - Record->Io.Length = (UINT16) (ResourceHi - ResourceLo); - break; - case PCI_CFG_RANGE: - Record->PciCfg.Base = (UINT16) ResourceLo; - Record->PciCfg.Length = (UINT16) (ResourceHi - ResourceLo); - break; - default: - return FALSE; + case MEM_RANGE: + case MMIO_RANGE: + Record->Mem.Base = ResourceLo; + Record->Mem.Length = ResourceHi - ResourceLo; + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + Record->Io.Base = (UINT16)ResourceLo; + Record->Io.Length = (UINT16)(ResourceHi - ResourceLo); + break; + case PCI_CFG_RANGE: + Record->PciCfg.Base = (UINT16)ResourceLo; + Record->PciCfg.Length = (UINT16)(ResourceHi - ResourceLo); + break; + default: + return FALSE; } return TRUE; @@ -595,10 +602,10 @@ HandleSingleResource ( **/ VOID AddSingleResource ( - IN STM_RSC *Resource + IN STM_RSC *Resource ) { - STM_RSC *Record; + STM_RSC *Record; Record = (STM_RSC *)mStmResourcesPtr; @@ -606,6 +613,7 @@ AddSingleResource ( if (Record->Header.RscType == END_OF_RESOURCES) { break; } + // // Go to next record if resource and record types don't match. // @@ -613,12 +621,14 @@ AddSingleResource ( Record = (STM_RSC *)((UINTN)Record + Record->Header.Length); continue; } + // // Record is handled inside of procedure - don't adjust. // if (HandleSingleResource (Resource, Record)) { - return ; + return; } + Record = (STM_RSC *)((UINTN)Record + Record->Header.Length); } @@ -626,19 +636,19 @@ AddSingleResource ( // Add resource to the end of area. // CopyMem ( - mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode), + mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode), Resource, Resource->Header.Length ); CopyMem ( - mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length, + mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode) + Resource->Header.Length, &mRscEndNode, - sizeof(mRscEndNode) + sizeof (mRscEndNode) ); - mStmResourceSizeUsed += Resource->Header.Length; + mStmResourceSizeUsed += Resource->Header.Length; mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed; - return ; + return; } /** @@ -652,13 +662,13 @@ AddSingleResource ( **/ VOID AddResource ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ) { - UINT32 Count; - UINTN Index; - STM_RSC *Resource; + UINT32 Count; + UINTN Index; + STM_RSC *Resource; if (NumEntries == 0) { Count = 0xFFFFFFFF; @@ -670,12 +680,14 @@ AddResource ( for (Index = 0; Index < Count; Index++) { if (Resource->Header.RscType == END_OF_RESOURCES) { - return ; + return; } + AddSingleResource (Resource); Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); } - return ; + + return; } /** @@ -692,14 +704,14 @@ AddResource ( **/ BOOLEAN ValidateResource ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ) { - UINT32 Count; - UINTN Index; - STM_RSC *Resource; - UINTN SubIndex; + UINT32 Count; + UINTN Index; + STM_RSC *Resource; + UINTN SubIndex; // // If NumEntries == 0 make it very big. Scan will be terminated by @@ -724,21 +736,23 @@ ValidateResource ( switch (Resource->Header.RscType) { case END_OF_RESOURCES: if (Resource->Header.Length != sizeof (STM_RSC_END)) { - return FALSE; + return FALSE; } + // // If we are passed actual number of resources to add, // END_OF_RESOURCES structure between them is considered an // error. If NumEntries == 0 END_OF_RESOURCES is a termination. // if (NumEntries != 0) { - return FALSE; + return FALSE; } else { // // If NumEntries == 0 and list reached end - return success. // return TRUE; } + break; case MEM_RANGE: @@ -750,6 +764,7 @@ ValidateResource ( if (Resource->Mem.RWXAttributes > FULL_ACCS) { return FALSE; } + break; case IO_RANGE: @@ -761,35 +776,42 @@ ValidateResource ( if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) { return FALSE; } + break; case PCI_CFG_RANGE: DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction)); - if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { + if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof (STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { return FALSE; } + for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) { if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) { return FALSE; } } + if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) { return FALSE; } + break; case MACHINE_SPECIFIC_REG: if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) { return FALSE; } + break; - default : + default: DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType)); return FALSE; } + Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); } + return TRUE; } @@ -808,13 +830,13 @@ ValidateResource ( **/ UINTN GetResourceSize ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ) { - UINT32 Count; - UINTN Index; - STM_RSC *Resource; + UINT32 Count; + UINTN Index; + STM_RSC *Resource; Resource = ResourceList; @@ -837,6 +859,7 @@ GetResourceSize ( if (Resource->Header.RscType == END_OF_RESOURCES) { break; } + Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); } @@ -859,8 +882,8 @@ GetResourceSize ( EFI_STATUS EFIAPI AddPiResource ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ) { EFI_STATUS Status; @@ -884,7 +907,7 @@ AddPiResource ( // // First time allocation // - NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof(mRscEndNode))); + NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof (mRscEndNode))); DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize)); Status = gSmst->SmmAllocatePages ( AllocateAnyPages, @@ -899,11 +922,11 @@ AddPiResource ( // // Copy EndResource for initialization // - mStmResourcesPtr = (UINT8 *)(UINTN)NewResource; + mStmResourcesPtr = (UINT8 *)(UINTN)NewResource; mStmResourceTotalSize = NewResourceSize; - CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); - mStmResourceSizeUsed = sizeof(mRscEndNode); - mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode)); + mStmResourceSizeUsed = sizeof (mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode); // // Let SmmCore change resource ptr @@ -925,6 +948,7 @@ AddPiResource ( if (EFI_ERROR (Status)) { return Status; } + CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed); mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed; @@ -934,7 +958,7 @@ AddPiResource ( ); mStmResourceTotalSize = NewResourceSize; - mStmResourcesPtr = (UINT8 *)(UINTN)NewResource; + mStmResourcesPtr = (UINT8 *)(UINTN)NewResource; // // Let SmmCore change resource ptr @@ -966,8 +990,8 @@ AddPiResource ( EFI_STATUS EFIAPI DeletePiResource ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ) { if (ResourceList != NULL) { @@ -975,12 +999,13 @@ DeletePiResource ( ASSERT (FALSE); return EFI_UNSUPPORTED; } + // // Delete all // - CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); - mStmResourceSizeUsed = sizeof(mRscEndNode); - mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode)); + mStmResourceSizeUsed = sizeof (mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode); return EFI_SUCCESS; } @@ -1000,8 +1025,8 @@ DeletePiResource ( EFI_STATUS EFIAPI GetPiResource ( - OUT STM_RSC *ResourceList, - IN OUT UINT32 *ResourceSize + OUT STM_RSC *ResourceList, + IN OUT UINT32 *ResourceSize ) { if (*ResourceSize < mStmResourceSizeUsed) { @@ -1029,7 +1054,7 @@ EnableMsegMsr ( { MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl; - SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); + SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); SmmMonitorCtl.Bits.Valid = 1; AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, SmmMonitorCtl.Uint64); } @@ -1067,18 +1092,18 @@ GetVmcsSize ( **/ BOOLEAN StmCheckStmImage ( - IN EFI_PHYSICAL_ADDRESS StmImage, - IN UINTN StmImageSize + IN EFI_PHYSICAL_ADDRESS StmImage, + IN UINTN StmImageSize ) { - UINTN MinMsegSize; - STM_HEADER *StmHeader; - IA32_VMX_MISC_REGISTER VmxMiscMsr; + UINTN MinMsegSize; + STM_HEADER *StmHeader; + IA32_VMX_MISC_REGISTER VmxMiscMsr; // // Check to see if STM image is compatible with CPU // - StmHeader = (STM_HEADER *)(UINTN)StmImage; + StmHeader = (STM_HEADER *)(UINTN)StmImage; VmxMiscMsr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); if (StmHeader->HwStmHdr.MsegHeaderRevision != VmxMiscMsr.Bits.MsegRevisionIdentifier) { DEBUG ((DEBUG_ERROR, "STM Image not compatible with CPU\n")); @@ -1101,8 +1126,8 @@ StmCheckStmImage ( // // We will create page table, just in case that SINIT does not create it. // - if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6)) { - MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6); + if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6)) { + MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6); } } @@ -1133,8 +1158,8 @@ StmCheckStmImage ( **/ VOID StmLoadStmImage ( - IN EFI_PHYSICAL_ADDRESS StmImage, - IN UINTN StmImageSize + IN EFI_PHYSICAL_ADDRESS StmImage, + IN UINTN StmImageSize ) { MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl; @@ -1145,7 +1170,7 @@ StmLoadStmImage ( // Get MSEG base address from MSR_IA32_SMM_MONITOR_CTL // SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); - MsegBase = SmmMonitorCtl.Bits.MsegBase << 12; + MsegBase = SmmMonitorCtl.Bits.MsegBase << 12; // // Zero all of MSEG base address @@ -1181,8 +1206,8 @@ StmLoadStmImage ( EFI_STATUS EFIAPI LoadMonitor ( - IN EFI_PHYSICAL_ADDRESS StmImage, - IN UINTN StmImageSize + IN EFI_PHYSICAL_ADDRESS StmImage, + IN UINTN StmImageSize ) { MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl; @@ -1201,7 +1226,7 @@ LoadMonitor ( } // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence. - TpmMeasureAndLogData( + TpmMeasureAndLogData ( 0, // PcrIndex TXT_EVTYPE_STM_HASH, // EventType NULL, // EventLog @@ -1226,7 +1251,7 @@ LoadMonitor ( **/ VOID * -GetStmResource( +GetStmResource ( VOID ) { @@ -1241,19 +1266,19 @@ GetStmResource( **/ VOID NotifyStmResourceChange ( - VOID *StmResource + VOID *StmResource ) { UINTN Index; TXT_PROCESSOR_SMM_DESCRIPTOR *Psd; for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET); + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET); Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource; } - return ; -} + return; +} /** This is STM setup BIOS callback. @@ -1278,4 +1303,3 @@ SmmStmTeardown ( { mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED; } - diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h index da551cc4a6..597c3abf00 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h @@ -21,7 +21,7 @@ **/ VOID StmGen4GPageTable ( - IN UINTN PageTableBase + IN UINTN PageTableBase ); /** @@ -42,10 +42,9 @@ StmGen4GPageTable ( UINT32 EFIAPI SmmStmExceptionHandler ( - IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context + IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context ); - /** Get STM state. @@ -73,8 +72,8 @@ GetMonitorState ( EFI_STATUS EFIAPI LoadMonitor ( - IN EFI_PHYSICAL_ADDRESS StmImage, - IN UINTN StmImageSize + IN EFI_PHYSICAL_ADDRESS StmImage, + IN UINTN StmImageSize ); /** @@ -94,7 +93,7 @@ EFI_STATUS EFIAPI AddPiResource ( IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN UINT32 NumEntries OPTIONAL ); /** @@ -113,8 +112,8 @@ AddPiResource ( EFI_STATUS EFIAPI DeletePiResource ( - IN STM_RSC *ResourceList, - IN UINT32 NumEntries OPTIONAL + IN STM_RSC *ResourceList, + IN UINT32 NumEntries OPTIONAL ); /** @@ -133,8 +132,8 @@ DeletePiResource ( EFI_STATUS EFIAPI GetPiResource ( - OUT STM_RSC *ResourceList, - IN OUT UINT32 *ResourceSize + OUT STM_RSC *ResourceList, + IN OUT UINT32 *ResourceSize ); /** @@ -153,7 +152,7 @@ StmSmmConfigurationTableInit ( **/ VOID NotifyStmResourceChange ( - IN VOID *StmResource + IN VOID *StmResource ); /** @@ -174,6 +173,6 @@ GetStmResource ( VOID EFIAPI SmmCpuFeaturesLibStmSmiEntryFixupAddress ( - ); + ); #endif diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c index c8a3f58e0c..00ab9bd0cd 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c @@ -14,9 +14,9 @@ /// /// Page Table Entry /// -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_PS BIT7 +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_PS BIT7 /** @@ -28,22 +28,22 @@ **/ VOID StmGen4GPageTable ( - IN UINTN PageTableBase + IN UINTN PageTableBase ) { - UINTN Index; - UINTN SubIndex; - UINT64 *Pde; - UINT64 *Pte; - UINT64 *Pml4; + UINTN Index; + UINTN SubIndex; + UINT64 *Pde; + UINT64 *Pte; + UINT64 *Pml4; - Pml4 = (UINT64*)(UINTN)PageTableBase; + Pml4 = (UINT64 *)(UINTN)PageTableBase; PageTableBase += SIZE_4KB; - *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; + *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; - Pde = (UINT64*)(UINTN)PageTableBase; + Pde = (UINT64 *)(UINTN)PageTableBase; PageTableBase += SIZE_4KB; - Pte = (UINT64 *)(UINTN)PageTableBase; + Pte = (UINT64 *)(UINTN)PageTableBase; for (Index = 0; Index < 4; Index++) { *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P; @@ -75,7 +75,7 @@ StmGen4GPageTable ( UINT32 EFIAPI SmmStmExceptionHandler ( - IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context + IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context ) { // TBD - SmmStmExceptionHandler, record information diff --git a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c index 6c2010dc0a..085a03e52a 100644 --- a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c +++ b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c @@ -69,7 +69,7 @@ ClearTopLevelSmiStatus ( EFI_STATUS EFIAPI PlatformSmmBspElection ( - OUT BOOLEAN *IsBsp + OUT BOOLEAN *IsBsp ) { return EFI_NOT_READY; @@ -92,10 +92,10 @@ PlatformSmmBspElection ( EFI_STATUS EFIAPI GetPlatformPageTableAttribute ( - IN UINT64 Address, - IN OUT SMM_PAGE_SIZE_TYPE *PageSize, - IN OUT UINTN *NumOfPages, - IN OUT UINTN *PageAttribute + IN UINT64 Address, + IN OUT SMM_PAGE_SIZE_TYPE *PageSize, + IN OUT UINTN *NumOfPages, + IN OUT UINTN *PageAttribute ) { return EFI_UNSUPPORTED; diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c index 89b065cb3f..d661d85974 100644 --- a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c @@ -35,15 +35,15 @@ UINT64 EFIAPI VmgExit ( - IN OUT GHCB *Ghcb, - IN UINT64 ExitCode, - IN UINT64 ExitInfo1, - IN UINT64 ExitInfo2 + IN OUT GHCB *Ghcb, + IN UINT64 ExitCode, + IN UINT64 ExitInfo1, + IN UINT64 ExitInfo2 ) { GHCB_EVENT_INJECTION Event; - Event.Uint64 = 0; + Event.Uint64 = 0; Event.Elements.Vector = GP_EXCEPTION; Event.Elements.Type = GHCB_EVENT_INJECTION_TYPE_EXCEPTION; Event.Elements.Valid = 1; @@ -65,8 +65,8 @@ VmgExit ( VOID EFIAPI VmgInit ( - IN OUT GHCB *Ghcb, - IN OUT BOOLEAN *InterruptState + IN OUT GHCB *Ghcb, + IN OUT BOOLEAN *InterruptState ) { } @@ -85,8 +85,8 @@ VmgInit ( VOID EFIAPI VmgDone ( - IN OUT GHCB *Ghcb, - IN BOOLEAN InterruptState + IN OUT GHCB *Ghcb, + IN BOOLEAN InterruptState ) { } @@ -104,8 +104,8 @@ VmgDone ( VOID EFIAPI VmgSetOffsetValid ( - IN OUT GHCB *Ghcb, - IN GHCB_REGISTER Offset + IN OUT GHCB *Ghcb, + IN GHCB_REGISTER Offset ) { } @@ -126,8 +126,8 @@ VmgSetOffsetValid ( BOOLEAN EFIAPI VmgIsOffsetValid ( - IN GHCB *Ghcb, - IN GHCB_REGISTER Offset + IN GHCB *Ghcb, + IN GHCB_REGISTER Offset ) { return FALSE; diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c index e9e2464be7..8bd0612c7b 100644 --- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c +++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c @@ -86,14 +86,14 @@ typedef struct { } EFI_SMM_SYSTEM_TABLE2_64; typedef struct { - EFI_GUID VendorGuid; - UINT64 VendorTable; + EFI_GUID VendorGuid; + UINT64 VendorTable; } EFI_CONFIGURATION_TABLE64; #endif #if defined (MDE_CPU_X64) -typedef EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2_64; -typedef EFI_CONFIGURATION_TABLE EFI_CONFIGURATION_TABLE64; +typedef EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2_64; +typedef EFI_CONFIGURATION_TABLE EFI_CONFIGURATION_TABLE64; #endif /** @@ -113,14 +113,14 @@ typedef EFI_CONFIGURATION_TABLE EFI_CONFIGURATION_TABLE64; EFI_STATUS EFIAPI Communicate ( - IN CONST EFI_PEI_SMM_COMMUNICATION_PPI *This, - IN OUT VOID *CommBuffer, - IN OUT UINTN *CommSize + IN CONST EFI_PEI_SMM_COMMUNICATION_PPI *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize ); -EFI_PEI_SMM_COMMUNICATION_PPI mSmmCommunicationPpi = { Communicate }; +EFI_PEI_SMM_COMMUNICATION_PPI mSmmCommunicationPpi = { Communicate }; -EFI_PEI_PPI_DESCRIPTOR mPpiList = { +EFI_PEI_PPI_DESCRIPTOR mPpiList = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiPeiSmmCommunicationPpiGuid, &mSmmCommunicationPpi @@ -136,8 +136,8 @@ GetCommunicationContext ( VOID ) { - EFI_HOB_GUID_TYPE *GuidHob; - EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; GuidHob = GetFirstGuidHob (&gEfiPeiSmmCommunicationPpiGuid); ASSERT (GuidHob != NULL); @@ -154,20 +154,20 @@ GetCommunicationContext ( **/ VOID SetCommunicationContext ( - IN EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext + IN EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext ) { - EFI_PEI_HOB_POINTERS Hob; - UINTN BufferSize; + EFI_PEI_HOB_POINTERS Hob; + UINTN BufferSize; BufferSize = sizeof (*SmmCommunicationContext); - Hob.Raw = BuildGuidHob ( - &gEfiPeiSmmCommunicationPpiGuid, - BufferSize - ); + Hob.Raw = BuildGuidHob ( + &gEfiPeiSmmCommunicationPpiGuid, + BufferSize + ); ASSERT (Hob.Raw); - CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof(*SmmCommunicationContext)); + CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof (*SmmCommunicationContext)); } /** @@ -181,18 +181,18 @@ SetCommunicationContext ( **/ VOID * InternalSmstGetVendorTableByGuid ( - IN UINT64 Signature, - IN EFI_SMM_SYSTEM_TABLE2 *Smst, - IN EFI_GUID *VendorGuid + IN UINT64 Signature, + IN EFI_SMM_SYSTEM_TABLE2 *Smst, + IN EFI_GUID *VendorGuid ) { - EFI_CONFIGURATION_TABLE *SmmConfigurationTable; - UINTN NumberOfTableEntries; - UINTN Index; - EFI_SMM_SYSTEM_TABLE2_64 *Smst64; - EFI_CONFIGURATION_TABLE64 *SmmConfigurationTable64; + EFI_CONFIGURATION_TABLE *SmmConfigurationTable; + UINTN NumberOfTableEntries; + UINTN Index; + EFI_SMM_SYSTEM_TABLE2_64 *Smst64; + EFI_CONFIGURATION_TABLE64 *SmmConfigurationTable64; - if ((sizeof(UINTN) == sizeof(UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) { + if ((sizeof (UINTN) == sizeof (UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) { // // 32 PEI + 64 DXE // @@ -200,23 +200,25 @@ InternalSmstGetVendorTableByGuid ( DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst64->SmmConfigurationTable)); DEBUG ((DEBUG_INFO, "InitCommunicationContext - NumberOfTableEntries: %x\n", Smst64->NumberOfTableEntries)); SmmConfigurationTable64 = (EFI_CONFIGURATION_TABLE64 *)(UINTN)Smst64->SmmConfigurationTable; - NumberOfTableEntries = (UINTN)Smst64->NumberOfTableEntries; + NumberOfTableEntries = (UINTN)Smst64->NumberOfTableEntries; for (Index = 0; Index < NumberOfTableEntries; Index++) { if (CompareGuid (&SmmConfigurationTable64[Index].VendorGuid, VendorGuid)) { return (VOID *)(UINTN)SmmConfigurationTable64[Index].VendorTable; } } + return NULL; } else { DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst->SmmConfigurationTable)); DEBUG ((DEBUG_INFO, "InitCommunicationContext - NumberOfTableEntries: %x\n", Smst->NumberOfTableEntries)); SmmConfigurationTable = Smst->SmmConfigurationTable; - NumberOfTableEntries = Smst->NumberOfTableEntries; + NumberOfTableEntries = Smst->NumberOfTableEntries; for (Index = 0; Index < NumberOfTableEntries; Index++) { if (CompareGuid (&SmmConfigurationTable[Index].VendorGuid, VendorGuid)) { return (VOID *)SmmConfigurationTable[Index].VendorTable; } } + return NULL; } } @@ -229,14 +231,14 @@ InitCommunicationContext ( VOID ) { - EFI_SMRAM_DESCRIPTOR *SmramDescriptor; - SMM_S3_RESUME_STATE *SmmS3ResumeState; - VOID *GuidHob; - EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; + EFI_SMRAM_DESCRIPTOR *SmramDescriptor; + SMM_S3_RESUME_STATE *SmmS3ResumeState; + VOID *GuidHob; + EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid); ASSERT (GuidHob != NULL); - SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); + SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob); SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart; DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmS3ResumeState: %x\n", SmmS3ResumeState)); @@ -251,7 +253,7 @@ InitCommunicationContext ( SetCommunicationContext (SmmCommunicationContext); - return ; + return; } /** @@ -271,17 +273,17 @@ InitCommunicationContext ( EFI_STATUS EFIAPI Communicate ( - IN CONST EFI_PEI_SMM_COMMUNICATION_PPI *This, - IN OUT VOID *CommBuffer, - IN OUT UINTN *CommSize + IN CONST EFI_PEI_SMM_COMMUNICATION_PPI *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize ) { - EFI_STATUS Status; - PEI_SMM_CONTROL_PPI *SmmControl; - PEI_SMM_ACCESS_PPI *SmmAccess; - UINT8 SmiCommand; - UINTN Size; - EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; + EFI_STATUS Status; + PEI_SMM_CONTROL_PPI *SmmControl; + PEI_SMM_ACCESS_PPI *SmmAccess; + UINT8 SmiCommand; + UINTN Size; + EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext; DEBUG ((DEBUG_INFO, "PiSmmCommunicationPei Communicate Enter\n")); @@ -333,15 +335,15 @@ Communicate ( // Send command // SmiCommand = (UINT8)SmmCommunicationContext->SwSmiNumber; - Size = sizeof(SmiCommand); - Status = SmmControl->Trigger ( - (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), - SmmControl, - (INT8 *)&SmiCommand, - &Size, - FALSE, - 0 - ); + Size = sizeof (SmiCommand); + Status = SmmControl->Trigger ( + (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), + SmmControl, + (INT8 *)&SmiCommand, + &Size, + FALSE, + 0 + ); ASSERT_EFI_ERROR (Status); // @@ -366,14 +368,14 @@ Communicate ( EFI_STATUS EFIAPI PiSmmCommunicationPeiEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; - PEI_SMM_ACCESS_PPI *SmmAccess; - EFI_BOOT_MODE BootMode; - UINTN Index; + EFI_STATUS Status; + PEI_SMM_ACCESS_PPI *SmmAccess; + EFI_BOOT_MODE BootMode; + UINTN Index; BootMode = GetBootModeHob (); if (BootMode != BOOT_ON_S3_RESUME) { diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h index cf1c57eeff..c51c012ebc 100644 --- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h +++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h @@ -11,12 +11,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack(push, 1) -#define SMM_COMMUNICATION_SIGNATURE SIGNATURE_32 ('S','M','M','C') +#define SMM_COMMUNICATION_SIGNATURE SIGNATURE_32 ('S','M','M','C') typedef struct { - UINT32 Signature; - UINT32 SwSmiNumber; - EFI_PHYSICAL_ADDRESS BufferPtrAddress; + UINT32 Signature; + UINT32 SwSmiNumber; + EFI_PHYSICAL_ADDRESS BufferPtrAddress; } EFI_SMM_COMMUNICATION_CONTEXT; #pragma pack(pop) diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c index 4fdea359d8..2e76ade769 100644 --- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c +++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c @@ -39,7 +39,7 @@ SetCommunicationContext ( gSmst, &gEfiPeiSmmCommunicationPpiGuid, &mSmmCommunicationContext, - sizeof(mSmmCommunicationContext) + sizeof (mSmmCommunicationContext) ); ASSERT_EFI_ERROR (Status); } @@ -66,14 +66,14 @@ PiSmmCommunicationHandler ( IN OUT UINTN *CommBufferSize OPTIONAL ) { - UINTN CommSize; - EFI_STATUS Status; - EFI_SMM_COMMUNICATE_HEADER *CommunicateHeader; - EFI_PHYSICAL_ADDRESS *BufferPtrAddress; + UINTN CommSize; + EFI_STATUS Status; + EFI_SMM_COMMUNICATE_HEADER *CommunicateHeader; + EFI_PHYSICAL_ADDRESS *BufferPtrAddress; DEBUG ((DEBUG_INFO, "PiSmmCommunicationHandler Enter\n")); - BufferPtrAddress = (EFI_PHYSICAL_ADDRESS *)(UINTN)mSmmCommunicationContext.BufferPtrAddress; + BufferPtrAddress = (EFI_PHYSICAL_ADDRESS *)(UINTN)mSmmCommunicationContext.BufferPtrAddress; CommunicateHeader = (EFI_SMM_COMMUNICATE_HEADER *)(UINTN)*BufferPtrAddress; DEBUG ((DEBUG_INFO, "PiSmmCommunicationHandler CommunicateHeader - %x\n", CommunicateHeader)); if (CommunicateHeader == NULL) { @@ -122,28 +122,28 @@ Done: @return Allocated address for output. **/ -VOID* +VOID * AllocateAcpiNvsMemoryBelow4G ( - IN UINTN Size + IN UINTN Size ) { UINTN Pages; EFI_PHYSICAL_ADDRESS Address; EFI_STATUS Status; - VOID* Buffer; + VOID *Buffer; - Pages = EFI_SIZE_TO_PAGES (Size); + Pages = EFI_SIZE_TO_PAGES (Size); Address = 0xffffffff; - Status = gBS->AllocatePages ( - AllocateMaxAddress, - EfiACPIMemoryNVS, - Pages, - &Address - ); + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); ASSERT_EFI_ERROR (Status); - Buffer = (VOID *) (UINTN) Address; + Buffer = (VOID *)(UINTN)Address; ZeroMem (Buffer, Size); return Buffer; @@ -165,11 +165,11 @@ PiSmmCommunicationSmmEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - EFI_SMM_SW_DISPATCH2_PROTOCOL *SmmSwDispatch2; - EFI_SMM_SW_REGISTER_CONTEXT SmmSwDispatchContext; - EFI_HANDLE DispatchHandle; - EFI_PHYSICAL_ADDRESS *BufferPtrAddress; + EFI_STATUS Status; + EFI_SMM_SW_DISPATCH2_PROTOCOL *SmmSwDispatch2; + EFI_SMM_SW_REGISTER_CONTEXT SmmSwDispatchContext; + EFI_HANDLE DispatchHandle; + EFI_PHYSICAL_ADDRESS *BufferPtrAddress; // // Register software SMI handler @@ -182,24 +182,24 @@ PiSmmCommunicationSmmEntryPoint ( ASSERT_EFI_ERROR (Status); SmmSwDispatchContext.SwSmiInputValue = (UINTN)-1; - Status = SmmSwDispatch2->Register ( - SmmSwDispatch2, - PiSmmCommunicationHandler, - &SmmSwDispatchContext, - &DispatchHandle - ); + Status = SmmSwDispatch2->Register ( + SmmSwDispatch2, + PiSmmCommunicationHandler, + &SmmSwDispatchContext, + &DispatchHandle + ); ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_INFO, "SmmCommunication SwSmi: %x\n", (UINTN)SmmSwDispatchContext.SwSmiInputValue)); - BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof(EFI_PHYSICAL_ADDRESS)); + BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof (EFI_PHYSICAL_ADDRESS)); ASSERT (BufferPtrAddress != NULL); DEBUG ((DEBUG_INFO, "SmmCommunication BufferPtrAddress: 0x%016lx, BufferPtr: 0x%016lx\n", (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress, *BufferPtrAddress)); // // Save context // - mSmmCommunicationContext.SwSmiNumber = (UINT32)SmmSwDispatchContext.SwSmiInputValue; + mSmmCommunicationContext.SwSmiNumber = (UINT32)SmmSwDispatchContext.SwSmiInputValue; mSmmCommunicationContext.BufferPtrAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress; SetCommunicationContext (); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 0d723336e4..9b45c442c9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -10,42 +10,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack(1) typedef struct { - UINTN Lock; - VOID *StackStart; - UINTN StackSize; - VOID *ApFunction; - IA32_DESCRIPTOR GdtrProfile; - IA32_DESCRIPTOR IdtrProfile; - UINT32 BufferStart; - UINT32 Cr3; - UINTN InitializeFloatingPointUnitsAddress; + UINTN Lock; + VOID *StackStart; + UINTN StackSize; + VOID *ApFunction; + IA32_DESCRIPTOR GdtrProfile; + IA32_DESCRIPTOR IdtrProfile; + UINT32 BufferStart; + UINT32 Cr3; + UINTN InitializeFloatingPointUnitsAddress; } MP_CPU_EXCHANGE_INFO; #pragma pack() typedef struct { - UINT8 *RendezvousFunnelAddress; - UINTN PModeEntryOffset; - UINTN FlatJumpOffset; - UINTN Size; - UINTN LModeEntryOffset; - UINTN LongJumpOffset; + UINT8 *RendezvousFunnelAddress; + UINTN PModeEntryOffset; + UINTN FlatJumpOffset; + UINTN Size; + UINTN LModeEntryOffset; + UINTN LongJumpOffset; } MP_ASSEMBLY_ADDRESS_MAP; // // Flags used when program the register. // typedef struct { - volatile UINTN MemoryMappedLock; // Spinlock used to program mmio - volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program + volatile UINTN MemoryMappedLock; // Spinlock used to program mmio + volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program // core level semaphore. - volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program + volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program // package level semaphore. } PROGRAM_CPU_REGISTER_FLAGS; // // Signal that SMM BASE relocation is complete. // -volatile BOOLEAN mInitApsAfterSmmBaseReloc; +volatile BOOLEAN mInitApsAfterSmmBaseReloc; /** Get starting address and size of the rendezvous entry for APs. @@ -56,38 +56,38 @@ volatile BOOLEAN mInitApsAfterSmmBaseReloc; VOID * EFIAPI AsmGetAddressMap ( - MP_ASSEMBLY_ADDRESS_MAP *AddressMap + MP_ASSEMBLY_ADDRESS_MAP *AddressMap ); -#define LEGACY_REGION_SIZE (2 * 0x1000) -#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE) +#define LEGACY_REGION_SIZE (2 * 0x1000) +#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE) -PROGRAM_CPU_REGISTER_FLAGS mCpuFlags; -ACPI_CPU_DATA mAcpiCpuData; -volatile UINT32 mNumberToFinish; -MP_CPU_EXCHANGE_INFO *mExchangeInfo; -BOOLEAN mRestoreSmmConfigurationInS3 = FALSE; +PROGRAM_CPU_REGISTER_FLAGS mCpuFlags; +ACPI_CPU_DATA mAcpiCpuData; +volatile UINT32 mNumberToFinish; +MP_CPU_EXCHANGE_INFO *mExchangeInfo; +BOOLEAN mRestoreSmmConfigurationInS3 = FALSE; // // S3 boot flag // -BOOLEAN mSmmS3Flag = FALSE; +BOOLEAN mSmmS3Flag = FALSE; // // Pointer to structure used during S3 Resume // -SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL; +SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL; -BOOLEAN mAcpiS3Enable = TRUE; +BOOLEAN mAcpiS3Enable = TRUE; -UINT8 *mApHltLoopCode = NULL; -UINT8 mApHltLoopCodeTemplate[] = { - 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4] - 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax] - 0xFA, // cli - 0xF4, // hlt - 0xEB, 0xFC // jmp $-2 - }; +UINT8 *mApHltLoopCode = NULL; +UINT8 mApHltLoopCodeTemplate[] = { + 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4] + 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax] + 0xFA, // cli + 0xF4, // hlt + 0xEB, 0xFC // jmp $-2 +}; /** Sync up the MTRR values for all processors. @@ -97,8 +97,9 @@ UINT8 mApHltLoopCodeTemplate[] = { VOID EFIAPI LoadMtrrData ( - EFI_PHYSICAL_ADDRESS MtrrTable + EFI_PHYSICAL_ADDRESS MtrrTable ) + /*++ Routine Description: @@ -112,9 +113,9 @@ Returns: --*/ { - MTRR_SETTINGS *MtrrSettings; + MTRR_SETTINGS *MtrrSettings; - MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable; + MtrrSettings = (MTRR_SETTINGS *)(UINTN)MtrrTable; MtrrSetAllMtrrs (MtrrSettings); } @@ -126,7 +127,7 @@ Returns: **/ VOID S3ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { InterlockedIncrement (Sem); @@ -144,7 +145,7 @@ S3ReleaseSemaphore ( **/ VOID S3WaitForSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { UINT32 Value; @@ -170,42 +171,46 @@ S3WaitForSemaphore ( **/ UINTN ReadWriteCr ( - IN UINT32 CrIndex, - IN BOOLEAN Read, - IN OUT UINTN *CrValue + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue ) { switch (CrIndex) { - case 0: - if (Read) { - *CrValue = AsmReadCr0 (); - } else { - AsmWriteCr0 (*CrValue); - } - break; - case 2: - if (Read) { - *CrValue = AsmReadCr2 (); - } else { - AsmWriteCr2 (*CrValue); - } - break; - case 3: - if (Read) { - *CrValue = AsmReadCr3 (); - } else { - AsmWriteCr3 (*CrValue); - } - break; - case 4: - if (Read) { - *CrValue = AsmReadCr4 (); - } else { - AsmWriteCr4 (*CrValue); - } - break; - default: - return EFI_UNSUPPORTED;; + case 0: + if (Read) { + *CrValue = AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + + break; + case 2: + if (Read) { + *CrValue = AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + + break; + case 3: + if (Read) { + *CrValue = AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + + break; + case 4: + if (Read) { + *CrValue = AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + + break; + default: + return EFI_UNSUPPORTED; } return EFI_SUCCESS; @@ -223,10 +228,10 @@ ReadWriteCr ( **/ VOID ProgramProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable, - IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, - IN CPU_STATUS_INFORMATION *CpuStatus, - IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags + IN CPU_REGISTER_TABLE *RegisterTable, + IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, + IN CPU_STATUS_INFORMATION *CpuStatus, + IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags ) { CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; @@ -246,53 +251,25 @@ ProgramProcessorRegister ( // // Traverse Register Table of this logical processor // - RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; + RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry; for (Index = 0; Index < RegisterTable->TableLength; Index++) { - RegisterTableEntry = &RegisterTableEntryHead[Index]; // // Check the type of specified register // switch (RegisterTableEntry->RegisterType) { - // - // The specified register is Control Register - // - case ControlRegister: - Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); - if (EFI_ERROR (Status)) { - break; - } - if (RegisterTableEntry->TestThenWrite) { - CurrentValue = BitFieldRead64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 - ); - if (CurrentValue == RegisterTableEntry->Value) { + // + // The specified register is Control Register + // + case ControlRegister: + Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } - } - Value = (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); - break; - // - // The specified register is Model Specific Register - // - case Msr: - if (RegisterTableEntry->TestThenWrite) { - Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); - if (RegisterTableEntry->ValidBitLength >= 64) { - if (Value == RegisterTableEntry->Value) { - break; - } - } else { + + if (RegisterTableEntry->TestThenWrite) { CurrentValue = BitFieldRead64 ( Value, RegisterTableEntry->ValidBitStart, @@ -302,164 +279,200 @@ ProgramProcessorRegister ( break; } } - } + Value = (UINTN)BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); + break; // - // If this function is called to restore register setting after INIT signal, - // there is no need to restore MSRs in register table. + // The specified register is Model Specific Register // - if (RegisterTableEntry->ValidBitLength >= 64) { - // - // If length is not less than 64 bits, then directly write without reading - // - AsmWriteMsr64 ( - RegisterTableEntry->Index, - RegisterTableEntry->Value - ); - } else { + case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >= 64) { + if (Value == RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue = BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1 + ); + if (CurrentValue == RegisterTableEntry->Value) { + break; + } + } + } + // - // Set the bit section according to bit start and length + // If this function is called to restore register setting after INIT signal, + // there is no need to restore MSRs in register table. // - AsmMsrBitFieldWrite64 ( - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - } - break; - // - // MemoryMapped operations - // - case MemoryMapped: - AcquireSpinLock (&CpuFlags->MemoryMappedLock); - MmioBitFieldWrite32 ( - (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, - (UINT32)RegisterTableEntry->Value - ); - ReleaseSpinLock (&CpuFlags->MemoryMappedLock); - break; - // - // Enable or disable cache - // - case CacheControl: - // - // If value of the entry is 0, then disable cache. Otherwise, enable cache. - // - if (RegisterTableEntry->Value == 0) { - AsmDisableCache (); - } else { - AsmEnableCache (); - } - break; + if (RegisterTableEntry->ValidBitLength >= 64) { + // + // If length is not less than 64 bits, then directly write without reading + // + AsmWriteMsr64 ( + RegisterTableEntry->Index, + RegisterTableEntry->Value + ); + } else { + // + // Set the bit section according to bit start and length + // + AsmMsrBitFieldWrite64 ( + RegisterTableEntry->Index, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + } - case Semaphore: - // Semaphore works logic like below: - // - // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]); - // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]); - // - // All threads (T0...Tn) waits in P() line and continues running - // together. + break; // + // MemoryMapped operations // - // T0 T1 ... Tn + case MemoryMapped: + AcquireSpinLock (&CpuFlags->MemoryMappedLock); + MmioBitFieldWrite32 ( + (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, + (UINT32)RegisterTableEntry->Value + ); + ReleaseSpinLock (&CpuFlags->MemoryMappedLock); + break; // - // V(0...n) V(0...n) ... V(0...n) - // n * P(0) n * P(1) ... n * P(n) + // Enable or disable cache // - ASSERT ( - (ApLocation != NULL) && - (CpuStatus->ThreadCountPerPackage != 0) && - (CpuStatus->ThreadCountPerCore != 0) && - (CpuFlags->CoreSemaphoreCount != NULL) && - (CpuFlags->PackageSemaphoreCount != NULL) - ); - switch (RegisterTableEntry->Value) { - case CoreDepType: - SemaphorePtr = CpuFlags->CoreSemaphoreCount; - ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore; - - CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core; - // - // Get Offset info for the first thread in the core which current thread belongs to. + case CacheControl: // - FirstThread = CurrentCore * CpuStatus->MaxThreadCount; - CurrentThread = FirstThread + ApLocation->Thread; - - // - // Different cores may have different valid threads in them. If driver maintail clearly - // thread index in different cores, the logic will be much complicated. - // Here driver just simply records the max thread number in all cores and use it as expect - // thread number for all cores. - // In below two steps logic, first current thread will Release semaphore for each thread - // in current core. Maybe some threads are not valid in this core, but driver don't - // care. Second, driver will let current thread wait semaphore for all valid threads in - // current core. Because only the valid threads will do release semaphore for this - // thread, driver here only need to wait the valid thread count. - // - + // If value of the entry is 0, then disable cache. Otherwise, enable cache. // - // First Notify ALL THREADs in current Core that this thread is ready. - // - for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) { - S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); - } - // - // Second, check whether all VALID THREADs (not all threads) in current core are ready. - // - for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) { - S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); + if (RegisterTableEntry->Value == 0) { + AsmDisableCache (); + } else { + AsmEnableCache (); } + break; - case PackageDepType: - SemaphorePtr = CpuFlags->PackageSemaphoreCount; - ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage; + case Semaphore: + // Semaphore works logic like below: // - // Get Offset info for the first thread in the package which current thread belongs to. + // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]); + // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]); // - FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount; + // All threads (T0...Tn) waits in P() line and continues running + // together. // - // Get the possible threads count for current package. // - CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread; - + // T0 T1 ... Tn // - // Different packages may have different valid threads in them. If driver maintail clearly - // thread index in different packages, the logic will be much complicated. - // Here driver just simply records the max thread number in all packages and use it as expect - // thread number for all packages. - // In below two steps logic, first current thread will Release semaphore for each thread - // in current package. Maybe some threads are not valid in this package, but driver don't - // care. Second, driver will let current thread wait semaphore for all valid threads in - // current package. Because only the valid threads will do release semaphore for this - // thread, driver here only need to wait the valid thread count. + // V(0...n) V(0...n) ... V(0...n) + // n * P(0) n * P(1) ... n * P(n) // + ASSERT ( + (ApLocation != NULL) && + (CpuStatus->ThreadCountPerPackage != 0) && + (CpuStatus->ThreadCountPerCore != 0) && + (CpuFlags->CoreSemaphoreCount != NULL) && + (CpuFlags->PackageSemaphoreCount != NULL) + ); + switch (RegisterTableEntry->Value) { + case CoreDepType: + SemaphorePtr = CpuFlags->CoreSemaphoreCount; + ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore; + + CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core; + // + // Get Offset info for the first thread in the core which current thread belongs to. + // + FirstThread = CurrentCore * CpuStatus->MaxThreadCount; + CurrentThread = FirstThread + ApLocation->Thread; + + // + // Different cores may have different valid threads in them. If driver maintail clearly + // thread index in different cores, the logic will be much complicated. + // Here driver just simply records the max thread number in all cores and use it as expect + // thread number for all cores. + // In below two steps logic, first current thread will Release semaphore for each thread + // in current core. Maybe some threads are not valid in this core, but driver don't + // care. Second, driver will let current thread wait semaphore for all valid threads in + // current core. Because only the valid threads will do release semaphore for this + // thread, driver here only need to wait the valid thread count. + // + + // + // First Notify ALL THREADs in current Core that this thread is ready. + // + for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) { + S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); + } + + // + // Second, check whether all VALID THREADs (not all threads) in current core are ready. + // + for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) { + S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); + } - // - // First Notify ALL THREADS in current package that this thread is ready. - // - for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) { - S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); - } - // - // Second, check whether VALID THREADS (not all threads) in current package are ready. - // - for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) { - S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); + break; + + case PackageDepType: + SemaphorePtr = CpuFlags->PackageSemaphoreCount; + ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage; + // + // Get Offset info for the first thread in the package which current thread belongs to. + // + FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount; + // + // Get the possible threads count for current package. + // + CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread; + + // + // Different packages may have different valid threads in them. If driver maintail clearly + // thread index in different packages, the logic will be much complicated. + // Here driver just simply records the max thread number in all packages and use it as expect + // thread number for all packages. + // In below two steps logic, first current thread will Release semaphore for each thread + // in current package. Maybe some threads are not valid in this package, but driver don't + // care. Second, driver will let current thread wait semaphore for all valid threads in + // current package. Because only the valid threads will do release semaphore for this + // thread, driver here only need to wait the valid thread count. + // + + // + // First Notify ALL THREADS in current package that this thread is ready. + // + for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) { + S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); + } + + // + // Second, check whether VALID THREADS (not all threads) in current package are ready. + // + for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) { + S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); + } + + break; + + default: + break; } + break; default: break; - } - break; - - default: - break; } } } @@ -473,15 +486,15 @@ ProgramProcessorRegister ( **/ VOID SetRegister ( - IN BOOLEAN PreSmmRegisterTable + IN BOOLEAN PreSmmRegisterTable ) { - CPU_FEATURE_INIT_DATA *FeatureInitData; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE *RegisterTables; - UINT32 InitApicId; - UINTN ProcIndex; - UINTN Index; + CPU_FEATURE_INIT_DATA *FeatureInitData; + CPU_REGISTER_TABLE *RegisterTable; + CPU_REGISTER_TABLE *RegisterTables; + UINT32 InitApicId; + UINTN ProcIndex; + UINTN Index; FeatureInitData = &mAcpiCpuData.CpuFeatureInitData; @@ -490,20 +503,22 @@ SetRegister ( } else { RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable; } + if (RegisterTables == NULL) { return; } - InitApicId = GetInitialApicId (); + InitApicId = GetInitialApicId (); RegisterTable = NULL; - ProcIndex = (UINTN)-1; + ProcIndex = (UINTN)-1; for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { if (RegisterTables[Index].InitialApicId == InitApicId) { RegisterTable = &RegisterTables[Index]; - ProcIndex = Index; + ProcIndex = Index; break; } } + ASSERT (RegisterTable != NULL); if (FeatureInitData->ApLocation != 0) { @@ -531,8 +546,8 @@ InitializeAp ( VOID ) { - UINTN TopOfStack; - UINT8 Stack[128]; + UINTN TopOfStack; + UINT8 Stack[128]; LoadMtrrData (mAcpiCpuData.MtrrTable); @@ -558,9 +573,9 @@ InitializeAp ( // // Place AP into the safe code, count down the number with lock mechanism in the safe code. // - TopOfStack = (UINTN) Stack + sizeof (Stack); - TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1); - CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate)); + TopOfStack = (UINTN)Stack + sizeof (Stack); + TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1); + CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate)); TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish); } @@ -576,8 +591,8 @@ PrepareApStartupVector ( EFI_PHYSICAL_ADDRESS WorkingBuffer ) { - EFI_PHYSICAL_ADDRESS StartupVector; - MP_ASSEMBLY_ADDRESS_MAP AddressMap; + EFI_PHYSICAL_ADDRESS StartupVector; + MP_ASSEMBLY_ADDRESS_MAP AddressMap; // // Get the address map of startup code for AP, @@ -592,25 +607,25 @@ PrepareApStartupVector ( // Copy AP startup code to startup vector, and then redirect the long jump // instructions for mode switching. // - CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size); - *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset); + CopyMem ((VOID *)(UINTN)StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size); + *(UINT32 *)(UINTN)(StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32)(StartupVector + AddressMap.PModeEntryOffset); if (AddressMap.LongJumpOffset != 0) { - *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset); + *(UINT32 *)(UINTN)(StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32)(StartupVector + AddressMap.LModeEntryOffset); } // // Get the start address of exchange data between BSP and AP. // - mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size); - ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO)); + mExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)(StartupVector + AddressMap.Size); + ZeroMem ((VOID *)mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO)); - CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR)); - CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR)); + CopyMem ((VOID *)(UINTN)&mExchangeInfo->GdtrProfile, (VOID *)(UINTN)mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR)); + CopyMem ((VOID *)(UINTN)&mExchangeInfo->IdtrProfile, (VOID *)(UINTN)mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR)); - mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress; - mExchangeInfo->StackSize = mAcpiCpuData.StackSize; - mExchangeInfo->BufferStart = (UINT32) StartupVector; - mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ()); + mExchangeInfo->StackStart = (VOID *)(UINTN)mAcpiCpuData.StackAddress; + mExchangeInfo->StackSize = mAcpiCpuData.StackSize; + mExchangeInfo->BufferStart = (UINT32)StartupVector; + mExchangeInfo->Cr3 = (UINT32)(AsmReadCr3 ()); mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits; } @@ -639,8 +654,9 @@ InitializeCpuBeforeRebase ( } else { ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus); } - mNumberToFinish = (UINT32)(mNumberOfCpus - 1); - mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp; + + mNumberToFinish = (UINT32)(mNumberOfCpus - 1); + mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp; // // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots. @@ -674,6 +690,7 @@ InitializeCpuAfterRebase ( } else { ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus); } + mNumberToFinish = (UINT32)(mNumberOfCpus - 1); // @@ -745,11 +762,11 @@ SmmRestoreCpu ( VOID ) { - SMM_S3_RESUME_STATE *SmmS3ResumeState; - IA32_DESCRIPTOR Ia32Idtr; - IA32_DESCRIPTOR X64Idtr; - IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER]; - EFI_STATUS Status; + SMM_S3_RESUME_STATE *SmmS3ResumeState; + IA32_DESCRIPTOR Ia32Idtr; + IA32_DESCRIPTOR X64Idtr; + IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER]; + EFI_STATUS Status; DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n")); @@ -770,15 +787,15 @@ SmmRestoreCpu ( // // Save the IA32 IDT Descriptor // - AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); + AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr); // // Setup X64 IDT table // ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32); - X64Idtr.Base = (UINTN) IdtEntryTable; - X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1); - AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr); + X64Idtr.Base = (UINTN)IdtEntryTable; + X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1); + AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr); // // Setup the default exception handler @@ -822,11 +839,11 @@ SmmRestoreCpu ( // mRestoreSmmConfigurationInS3 = TRUE; - DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); + DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); // // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase @@ -854,7 +871,7 @@ SmmRestoreCpu ( // // Restore IA32 IDT table // - AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); + AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr); AsmDisablePaging64 ( SmmS3ResumeState->ReturnCs, (UINT32)SmmS3ResumeState->ReturnEntryPoint, @@ -882,11 +899,11 @@ InitSmmS3ResumeState ( IN UINT32 Cr3 ) { - VOID *GuidHob; - EFI_SMRAM_DESCRIPTOR *SmramDescriptor; - SMM_S3_RESUME_STATE *SmmS3ResumeState; - EFI_PHYSICAL_ADDRESS Address; - EFI_STATUS Status; + VOID *GuidHob; + EFI_SMRAM_DESCRIPTOR *SmramDescriptor; + SMM_S3_RESUME_STATE *SmmS3ResumeState; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; if (!mAcpiS3Enable) { return; @@ -899,10 +916,10 @@ InitSmmS3ResumeState ( "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n", __FUNCTION__, &gEfiAcpiVariableGuid - )); + )); CpuDeadLoop (); } else { - SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); + SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob); DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor)); DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart)); @@ -910,7 +927,7 @@ InitSmmS3ResumeState ( SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart; ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE)); - mSmmS3ResumeState = SmmS3ResumeState; + mSmmS3ResumeState = SmmS3ResumeState; SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst; SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu; @@ -928,6 +945,7 @@ InitSmmS3ResumeState ( if (sizeof (UINTN) == sizeof (UINT64)) { SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64; } + if (sizeof (UINTN) == sizeof (UINT32)) { SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32; } @@ -950,7 +968,7 @@ InitSmmS3ResumeState ( &Address ); ASSERT_EFI_ERROR (Status); - mApHltLoopCode = (UINT8 *) (UINTN) Address; + mApHltLoopCode = (UINT8 *)(UINTN)Address; } /** @@ -963,22 +981,22 @@ InitSmmS3ResumeState ( **/ VOID CopyRegisterTable ( - IN CPU_REGISTER_TABLE *DestinationRegisterTableList, - IN CPU_REGISTER_TABLE *SourceRegisterTableList, - IN UINT32 NumberOfCpus + IN CPU_REGISTER_TABLE *DestinationRegisterTableList, + IN CPU_REGISTER_TABLE *SourceRegisterTableList, + IN UINT32 NumberOfCpus ) { - UINTN Index; - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; + UINTN Index; + CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE)); for (Index = 0; Index < NumberOfCpus; Index++) { if (DestinationRegisterTableList[Index].TableLength != 0) { DestinationRegisterTableList[Index].AllocatedSize = DestinationRegisterTableList[Index].TableLength * sizeof (CPU_REGISTER_TABLE_ENTRY); - RegisterTableEntry = AllocateCopyPool ( - DestinationRegisterTableList[Index].AllocatedSize, - (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry - ); + RegisterTableEntry = AllocateCopyPool ( + DestinationRegisterTableList[Index].AllocatedSize, + (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry + ); ASSERT (RegisterTableEntry != NULL); DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry; } @@ -996,11 +1014,11 @@ CopyRegisterTable ( **/ BOOLEAN IsRegisterTableEmpty ( - IN CPU_REGISTER_TABLE *RegisterTable, - IN UINT32 NumberOfCpus + IN CPU_REGISTER_TABLE *RegisterTable, + IN UINT32 NumberOfCpus ) { - UINTN Index; + UINTN Index; if (RegisterTable != NULL) { for (Index = 0; Index < NumberOfCpus; Index++) { @@ -1022,11 +1040,11 @@ IsRegisterTableEmpty ( **/ VOID CopyCpuFeatureInitDatatoSmram ( - IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst, - IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc + IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst, + IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc ) { - CPU_STATUS_INFORMATION *CpuStatus; + CPU_STATUS_INFORMATION *CpuStatus; if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) { CpuFeatureInitDataDst->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE)); @@ -1055,25 +1073,25 @@ CopyCpuFeatureInitDatatoSmram ( if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage != 0) { CpuStatus->ThreadCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool ( - sizeof (UINT32) * CpuStatus->PackageCount, - (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage - ); + sizeof (UINT32) * CpuStatus->PackageCount, + (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage + ); ASSERT (CpuStatus->ThreadCountPerPackage != 0); } if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore != 0) { CpuStatus->ThreadCountPerCore = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool ( - sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount), - (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore - ); + sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount), + (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore + ); ASSERT (CpuStatus->ThreadCountPerCore != 0); } if (CpuFeatureInitDataSrc->ApLocation != 0) { CpuFeatureInitDataDst->ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool ( - mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION), - (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation - ); + mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION), + (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation + ); ASSERT (CpuFeatureInitDataDst->ApLocation != 0); } } @@ -1087,13 +1105,13 @@ GetAcpiCpuData ( VOID ) { - ACPI_CPU_DATA *AcpiCpuData; - IA32_DESCRIPTOR *Gdtr; - IA32_DESCRIPTOR *Idtr; - VOID *GdtForAp; - VOID *IdtForAp; - VOID *MachineCheckHandlerForAp; - CPU_STATUS_INFORMATION *CpuStatus; + ACPI_CPU_DATA *AcpiCpuData; + IA32_DESCRIPTOR *Gdtr; + IA32_DESCRIPTOR *Idtr; + VOID *GdtForAp; + VOID *IdtForAp; + VOID *MachineCheckHandlerForAp; + CPU_STATUS_INFORMATION *CpuStatus; if (!mAcpiS3Enable) { return; @@ -1140,15 +1158,15 @@ GetAcpiCpuData ( GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize); ASSERT (GdtForAp != NULL); - IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1)); - MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1)); + IdtForAp = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1)); + MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1)); CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize); - Gdtr->Base = (UINTN)GdtForAp; - Idtr->Base = (UINTN)IdtForAp; + Gdtr->Base = (UINTN)GdtForAp; + Idtr->Base = (UINTN)IdtForAp; mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp; ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA)); @@ -1175,7 +1193,7 @@ GetAcpiCpuData ( ); ASSERT (mCpuFlags.PackageSemaphoreCount != NULL); - InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock); + InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock); } } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c index c9138a531a..5d624f8e9e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c @@ -38,15 +38,15 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = { EFI_STATUS EFIAPI SmmGetProcessorInfo ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ) { // // Check parameter // - if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) { + if ((ProcessorNumber >= mMaxNumberOfCpus) || (ProcessorInfoBuffer == NULL)) { return EFI_INVALID_PARAMETER; } @@ -75,8 +75,8 @@ SmmGetProcessorInfo ( EFI_STATUS EFIAPI SmmSwitchBsp ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - IN UINTN ProcessorNumber + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + IN UINTN ProcessorNumber ) { // @@ -90,8 +90,9 @@ SmmSwitchBsp ( return EFI_NOT_FOUND; } - if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone || - gSmst->CurrentlyExecutingCpu == ProcessorNumber) { + if ((gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) || + (gSmst->CurrentlyExecutingCpu == ProcessorNumber)) + { return EFI_UNSUPPORTED; } @@ -132,7 +133,7 @@ SmmAddProcessor ( // // Check parameter // - if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) { + if ((ProcessorNumber == NULL) || (ProcessorId == INVALID_APIC_ID)) { return EFI_INVALID_PARAMETER; } @@ -151,10 +152,11 @@ SmmAddProcessor ( // of the APIC ID to SMBASE. // for (Index = 0; Index < mMaxNumberOfCpus; Index++) { - if (mCpuHotPlugData.ApicId[Index] == ProcessorId && - gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) { + if ((mCpuHotPlugData.ApicId[Index] == ProcessorId) && + (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID)) + { gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId; - gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; + gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; GetProcessorLocationByApicId ( (UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package, @@ -162,7 +164,7 @@ SmmAddProcessor ( &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread ); - *ProcessorNumber = Index; + *ProcessorNumber = Index; gSmmCpuPrivate->Operation[Index] = SmmCpuAdd; return EFI_SUCCESS; } @@ -197,8 +199,9 @@ SmmRemoveProcessor ( // // Check parameter // - if (ProcessorNumber >= mMaxNumberOfCpus || - gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) { + if ((ProcessorNumber >= mMaxNumberOfCpus) || + (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID)) + { return EFI_INVALID_PARAMETER; } @@ -214,7 +217,7 @@ SmmRemoveProcessor ( } gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId = INVALID_APIC_ID; - mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID; + mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID; // // Removal of the processor from the CPU list is pending until all SMI handlers are finished @@ -237,12 +240,12 @@ SmmRemoveProcessor ( EFI_STATUS EFIAPI SmmWhoAmI ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - OUT UINTN *ProcessorNumber + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + OUT UINTN *ProcessorNumber ) { - UINTN Index; - UINT64 ApicId; + UINTN Index; + UINT64 ApicId; // // Check parameter @@ -259,6 +262,7 @@ SmmWhoAmI ( return EFI_SUCCESS; } } + // // This should not happen // @@ -276,15 +280,15 @@ SmmCpuUpdate ( VOID ) { - UINTN Index; + UINTN Index; // // Handle pending BSP switch operations // for (Index = 0; Index < mMaxNumberOfCpus; Index++) { if (gSmmCpuPrivate->Operation[Index] == SmmCpuSwitchBsp) { - gSmmCpuPrivate->Operation[Index] = SmmCpuNone; - mSmmMpSyncData->SwitchBsp = TRUE; + gSmmCpuPrivate->Operation[Index] = SmmCpuNone; + mSmmMpSyncData->SwitchBsp = TRUE; mSmmMpSyncData->CandidateBsp[Index] = TRUE; } } @@ -330,10 +334,10 @@ SmmCpuUpdate ( EFI_STATUS EFIAPI SmmRegisterExceptionHandler ( - IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, - IN EFI_EXCEPTION_TYPE ExceptionType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ) + IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE ExceptionType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) { return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler); } @@ -352,7 +356,7 @@ InitializeSmmCpuServices ( IN EFI_HANDLE Handle ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = gSmst->SmmInstallProtocolInterface ( &Handle, @@ -363,4 +367,3 @@ InitializeSmmCpuServices ( ASSERT_EFI_ERROR (Status); return Status; } - diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h index 98b0feb42c..8847dbb851 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h @@ -38,9 +38,9 @@ typedef enum { EFI_STATUS EFIAPI SmmGetProcessorInfo ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - IN UINTN ProcessorNumber, - OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer ); /** @@ -57,8 +57,8 @@ SmmGetProcessorInfo ( EFI_STATUS EFIAPI SmmSwitchBsp ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - IN UINTN ProcessorNumber + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + IN UINTN ProcessorNumber ); /** @@ -115,8 +115,8 @@ SmmRemoveProcessor ( EFI_STATUS EFIAPI SmmWhoAmI ( - IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, - OUT UINTN *ProcessorNumber + IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, + OUT UINTN *ProcessorNumber ); /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c index 9c8e2d15ac..8ec8790c05 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -36,13 +36,13 @@ EnableCet ( **/ VOID GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL + OUT UINTN *Base, + OUT BOOLEAN *FiveLevels OPTIONAL ) { *Base = ((mInternalCr3 == 0) ? - (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) : - mInternalCr3); + (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) : + mInternalCr3); if (FiveLevels != NULL) { *FiveLevels = FALSE; } @@ -59,9 +59,9 @@ SmmInitPageTable ( VOID ) { - UINTN PageFaultHandlerHookAddress; - IA32_IDT_GATE_DESCRIPTOR *IdtEntry; - EFI_STATUS Status; + UINTN PageFaultHandlerHookAddress; + IA32_IDT_GATE_DESCRIPTOR *IdtEntry; + EFI_STATUS Status; // // Initialize spin lock @@ -72,18 +72,19 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmProfileEnable) || HEAP_GUARD_NONSTOP_MODE || - NULL_DETECTION_NONSTOP_MODE) { + NULL_DETECTION_NONSTOP_MODE) + { // // Set own Page Fault entry instead of the default one, because SMM Profile // feature depends on IRET instruction to do Single Step // PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile; - IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base; - IdtEntry += EXCEPT_IA32_PAGE_FAULT; - IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; - IdtEntry->Bits.Reserved_0 = 0; - IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; - IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16); + IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; + IdtEntry += EXCEPT_IA32_PAGE_FAULT; + IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; + IdtEntry->Bits.Reserved_0 = 0; + IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; + IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16); } else { // // Register SMM Page Fault Handler @@ -98,6 +99,7 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmStackGuard)) { InitializeIDTSmmStackGuard (); } + return Gen4GPageTable (TRUE); } @@ -124,13 +126,13 @@ SmiDefaultPFHandler ( VOID EFIAPI SmiPFHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { - UINTN PFAddress; - UINTN GuardPageAddress; - UINTN CpuIndex; + UINTN PFAddress; + UINTN GuardPageAddress; + UINTN CpuIndex; ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT); @@ -143,25 +145,27 @@ SmiPFHandler ( // or SMM page protection violation. // if ((PFAddress >= mCpuHotPlugData.SmrrBase) && - (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) { + (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) + { DumpCpuContext (InterruptType, SystemContext); - CpuIndex = GetCpuIndex (); + CpuIndex = GetCpuIndex (); GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize); if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && (PFAddress >= GuardPageAddress) && - (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) { + (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) + { DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n")); } else { if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) { DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp); - ); + ); } else { DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip); - ); + ); } if (HEAP_GUARD_NONSTOP_MODE) { @@ -169,6 +173,7 @@ SmiPFHandler ( goto Exit; } } + CpuDeadLoop (); goto Exit; } @@ -177,13 +182,14 @@ SmiPFHandler ( // If a page fault occurs in non-SMRAM range. // if ((PFAddress < mCpuHotPlugData.SmrrBase) || - (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { + (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) + { if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) { DumpCpuContext (InterruptType, SystemContext); DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp); - ); + ); CpuDeadLoop (); goto Exit; } @@ -191,13 +197,14 @@ SmiPFHandler ( // // If NULL pointer was just accessed // - if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 && - (PFAddress < EFI_PAGE_SIZE)) { + if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) && + (PFAddress < EFI_PAGE_SIZE)) + { DumpCpuContext (InterruptType, SystemContext); DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n")); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip); - ); + ); if (NULL_DETECTION_NONSTOP_MODE) { GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData); @@ -213,7 +220,7 @@ SmiPFHandler ( DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip); - ); + ); CpuDeadLoop (); goto Exit; } @@ -241,15 +248,15 @@ SetPageTableAttributes ( VOID ) { - UINTN Index2; - UINTN Index3; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINTN PageTableBase; - BOOLEAN IsSplitted; - BOOLEAN PageTableSplitted; - BOOLEAN CetEnabled; + UINTN Index2; + UINTN Index3; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINTN PageTableBase; + BOOLEAN IsSplitted; + BOOLEAN PageTableSplitted; + BOOLEAN CetEnabled; // // Don't mark page table to read-only if heap guard is enabled. @@ -259,7 +266,7 @@ SetPageTableAttributes ( // if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) { DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n")); - return ; + return; } // @@ -267,7 +274,7 @@ SetPageTableAttributes ( // if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n")); - return ; + return; } DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n")); @@ -276,14 +283,15 @@ SetPageTableAttributes ( // Disable write protection, because we need mark page table to be write protected. // We need *write* page table memory, to mark itself to be *read only*. // - CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; + CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; if (CetEnabled) { // // CET must be disabled if WP is disabled. // - DisableCet(); + DisableCet (); } - AsmWriteCr0 (AsmReadCr0() & ~CR0_WP); + + AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); do { DEBUG ((DEBUG_INFO, "Start...\n")); @@ -304,15 +312,17 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); - for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) { + for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { // 2M continue; } + L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable == NULL) { continue; } + SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); } @@ -322,15 +332,15 @@ SetPageTableAttributes ( // // Enable write protection, after page table updated. // - AsmWriteCr0 (AsmReadCr0() | CR0_WP); + AsmWriteCr0 (AsmReadCr0 () | CR0_WP); if (CetEnabled) { // // re-enable CET. // - EnableCet(); + EnableCet (); } - return ; + return; } /** @@ -343,7 +353,7 @@ SaveCr2 ( OUT UINTN *Cr2 ) { - return ; + return; } /** @@ -356,7 +366,7 @@ RestoreCr2 ( IN UINTN Cr2 ) { - return ; + return; } /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c index 31ee067ad6..a9fcc89dda 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c @@ -32,7 +32,7 @@ SemaphoreHook ( mRebasedFlag = RebasedFlag; - CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c index ef277349d4..6c48a53f67 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" -extern UINT64 gTaskGateDescriptor; +extern UINT64 gTaskGateDescriptor; -EFI_PHYSICAL_ADDRESS mGdtBuffer; -UINTN mGdtBufferSize; +EFI_PHYSICAL_ADDRESS mGdtBuffer; +UINTN mGdtBufferSize; -extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; +extern BOOLEAN mCetSupported; +extern UINTN mSmmShadowStackSize; -X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; -X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; -UINT32 mCetPl0Ssp; -UINT32 mCetInterruptSsp; +X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; +X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; +UINT32 mCetPl0Ssp; +UINT32 mCetInterruptSsp; /** Initialize IDT for SMM Stack Guard. @@ -38,8 +38,8 @@ InitializeIDTSmmStackGuard ( // is a Task Gate Descriptor so that when a Page Fault Exception occurs, // the processors can use a known good stack in case stack is ran out. // - IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; - IdtGate += EXCEPT_IA32_PAGE_FAULT; + IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; + IdtGate += EXCEPT_IA32_PAGE_FAULT; IdtGate->Uint64 = gTaskGateDescriptor; } @@ -58,13 +58,13 @@ InitGdt ( OUT UINTN *GdtStepSize ) { - UINTN Index; - IA32_SEGMENT_DESCRIPTOR *GdtDescriptor; - UINTN TssBase; - UINTN GdtTssTableSize; - UINT8 *GdtTssTables; - UINTN GdtTableStepSize; - UINTN InterruptShadowStack; + UINTN Index; + IA32_SEGMENT_DESCRIPTOR *GdtDescriptor; + UINTN TssBase; + UINTN GdtTssTableSize; + UINT8 *GdtTssTables; + UINTN GdtTableStepSize; + UINTN InterruptShadowStack; if (FeaturePcdGet (PcdCpuSmmStackGuard)) { // @@ -79,46 +79,46 @@ InitGdt ( gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR)); GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE + 7) & ~7; // 8 bytes aligned - mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; + mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; // // IA32 Stack Guard need use task switch to switch stack that need // write GDT and TSS, so AllocateCodePages() could not be used here // as code pages will be set to RO. // - GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); + GdtTssTables = (UINT8 *)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); ASSERT (GdtTssTables != NULL); - mGdtBuffer = (UINTN)GdtTssTables; + mGdtBuffer = (UINTN)GdtTssTables; GdtTableStepSize = GdtTssTableSize; for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { - CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE); + CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE); // // Fixup TSS descriptors // - TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1); - GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2; - GdtDescriptor->Bits.BaseLow = (UINT16)TssBase; - GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16); + TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1); + GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2; + GdtDescriptor->Bits.BaseLow = (UINT16)TssBase; + GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16); GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24); TssBase += TSS_SIZE; GdtDescriptor++; - GdtDescriptor->Bits.BaseLow = (UINT16)TssBase; - GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16); + GdtDescriptor->Bits.BaseLow = (UINT16)TssBase; + GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16); GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24); // // Fixup TSS segments // // ESP as known good stack // - *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize; + *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize; *(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3; // // Setup ShadowStack for stack switch // if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { - InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index); + InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index); *(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack; } } @@ -127,14 +127,14 @@ InitGdt ( // Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory. // GdtTssTableSize = gcSmiGdtr.Limit + 1; - mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; - GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); + mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; + GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); ASSERT (GdtTssTables != NULL); - mGdtBuffer = (UINTN)GdtTssTables; + mGdtBuffer = (UINTN)GdtTssTables; GdtTableStepSize = GdtTssTableSize; for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { - CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1); + CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1); } } @@ -181,24 +181,24 @@ InitShadowStack ( IN VOID *ShadowStack ) { - UINTN SmmShadowStackSize; + UINTN SmmShadowStackSize; if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize))); if (FeaturePcdGet (PcdCpuSmmStackGuard)) { SmmShadowStackSize += EFI_PAGES_TO_SIZE (2); } - mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64)); + + mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64)); PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4); DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp)); DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack)); DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize)); if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64)); + mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64)); PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp)); } } } - diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c index e83031fc01..bba4a6f058 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c @@ -20,7 +20,7 @@ InitSmmS3Cr3 ( { mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE); - return ; + return; } /** @@ -49,11 +49,11 @@ InitPagesForPFHandler ( **/ VOID RestorePageTableAbove4G ( - UINT64 *PageTable, - UINT64 PFAddress, - UINTN CpuIndex, - UINTN ErrorCode, - BOOLEAN *IsValidPFAddress + UINT64 *PageTable, + UINT64 PFAddress, + UINTN CpuIndex, + UINTN ErrorCode, + BOOLEAN *IsValidPFAddress ) { } @@ -67,7 +67,7 @@ RestorePageTableAbove4G ( **/ VOID ClearTrapFlag ( - IN OUT EFI_SYSTEM_CONTEXT SystemContext + IN OUT EFI_SYSTEM_CONTEXT SystemContext ) { SystemContext.SystemContextIa32->Eflags &= (UINTN) ~BIT8; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h index 533e8561b2..6c95f2bb19 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h @@ -12,42 +12,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack (1) typedef struct _MSR_DS_AREA_STRUCT { - UINT32 BTSBufferBase; - UINT32 BTSIndex; - UINT32 BTSAbsoluteMaximum; - UINT32 BTSInterruptThreshold; - UINT32 PEBSBufferBase; - UINT32 PEBSIndex; - UINT32 PEBSAbsoluteMaximum; - UINT32 PEBSInterruptThreshold; - UINT32 PEBSCounterReset[4]; - UINT32 Reserved; + UINT32 BTSBufferBase; + UINT32 BTSIndex; + UINT32 BTSAbsoluteMaximum; + UINT32 BTSInterruptThreshold; + UINT32 PEBSBufferBase; + UINT32 PEBSIndex; + UINT32 PEBSAbsoluteMaximum; + UINT32 PEBSInterruptThreshold; + UINT32 PEBSCounterReset[4]; + UINT32 Reserved; } MSR_DS_AREA_STRUCT; typedef struct _BRANCH_TRACE_RECORD { - UINT32 LastBranchFrom; - UINT32 LastBranchTo; - UINT32 Rsvd0 : 4; - UINT32 BranchPredicted : 1; - UINT32 Rsvd1 : 27; + UINT32 LastBranchFrom; + UINT32 LastBranchTo; + UINT32 Rsvd0 : 4; + UINT32 BranchPredicted : 1; + UINT32 Rsvd1 : 27; } BRANCH_TRACE_RECORD; typedef struct _PEBS_RECORD { - UINT32 Eflags; - UINT32 LinearIP; - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; - UINT32 Esi; - UINT32 Edi; - UINT32 Ebp; - UINT32 Esp; + UINT32 Eflags; + UINT32 LinearIP; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + UINT32 Esi; + UINT32 Edi; + UINT32 Ebp; + UINT32 Esp; } PEBS_RECORD; #pragma pack () -#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB) +#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB) /** Update page table to map the memory correctly in order to make the instruction @@ -63,11 +63,11 @@ typedef struct _PEBS_RECORD { **/ VOID RestorePageTableAbove4G ( - UINT64 *PageTable, - UINT64 PFAddress, - UINTN CpuIndex, - UINTN ErrorCode, - BOOLEAN *IsValidPFAddress + UINT64 *PageTable, + UINT64 PFAddress, + UINTN CpuIndex, + UINTN ErrorCode, + BOOLEAN *IsValidPFAddress ); /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 48f9c330b8..882dee4fe2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -13,18 +13,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE) // -MTRR_SETTINGS gSmiMtrrs; -UINT64 gPhyMask; -SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL; -UINTN mSmmMpSyncDataSize; -SMM_CPU_SEMAPHORES mSmmCpuSemaphores; -UINTN mSemaphoreSize; -SPIN_LOCK *mPFLock = NULL; -SMM_CPU_SYNC_MODE mCpuSmmSyncMode; -BOOLEAN mMachineCheckSupported = FALSE; -MM_COMPLETION mSmmStartupThisApToken; - -extern UINTN mSmmShadowStackSize; +MTRR_SETTINGS gSmiMtrrs; +UINT64 gPhyMask; +SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL; +UINTN mSmmMpSyncDataSize; +SMM_CPU_SEMAPHORES mSmmCpuSemaphores; +UINTN mSemaphoreSize; +SPIN_LOCK *mPFLock = NULL; +SMM_CPU_SYNC_MODE mCpuSmmSyncMode; +BOOLEAN mMachineCheckSupported = FALSE; +MM_COMPLETION mSmmStartupThisApToken; + +extern UINTN mSmmShadowStackSize; /** Performs an atomic compare exchange operation to get semaphore. @@ -38,27 +38,29 @@ extern UINTN mSmmShadowStackSize; **/ UINT32 WaitForSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { - UINT32 Value; + UINT32 Value; - for (;;) { + for ( ; ;) { Value = *Sem; - if (Value != 0 && - InterlockedCompareExchange32 ( - (UINT32*)Sem, - Value, - Value - 1 - ) == Value) { + if ((Value != 0) && + (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value - 1 + ) == Value)) + { break; } + CpuPause (); } + return Value - 1; } - /** Performs an atomic compare exchange operation to release semaphore. The compare exchange operation must be performed using @@ -71,19 +73,20 @@ WaitForSemaphore ( **/ UINT32 ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { - UINT32 Value; + UINT32 Value; do { Value = *Sem; } while (Value + 1 != 0 && InterlockedCompareExchange32 ( - (UINT32*)Sem, + (UINT32 *)Sem, Value, Value + 1 ) != Value); + return Value + 1; } @@ -99,17 +102,19 @@ ReleaseSemaphore ( **/ UINT32 LockdownSemaphore ( - IN OUT volatile UINT32 *Sem + IN OUT volatile UINT32 *Sem ) { - UINT32 Value; + UINT32 Value; do { Value = *Sem; } while (InterlockedCompareExchange32 ( - (UINT32*)Sem, - Value, (UINT32)-1 + (UINT32 *)Sem, + Value, + (UINT32)-1 ) != Value); + return Value; } @@ -121,10 +126,10 @@ LockdownSemaphore ( **/ VOID WaitForAllAPs ( - IN UINTN NumberOfAPs + IN UINTN NumberOfAPs ) { - UINTN BspIndex; + UINTN BspIndex; BspIndex = mSmmMpSyncData->BspIndex; while (NumberOfAPs-- > 0) { @@ -142,7 +147,7 @@ ReleaseAllAPs ( VOID ) { - UINTN Index; + UINTN Index; for (Index = 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { @@ -165,9 +170,9 @@ AllCpusInSmmWithExceptions ( SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions ) { - UINTN Index; - SMM_CPU_DATA_BLOCK *CpuData; - EFI_PROCESSOR_INFORMATION *ProcessorInfo; + UINTN Index; + SMM_CPU_DATA_BLOCK *CpuData; + EFI_PROCESSOR_INFORMATION *ProcessorInfo; ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus); @@ -175,24 +180,26 @@ AllCpusInSmmWithExceptions ( return TRUE; } - CpuData = mSmmMpSyncData->CpuData; + CpuData = mSmmMpSyncData->CpuData; ProcessorInfo = gSmmCpuPrivate->ProcessorInfo; for (Index = 0; Index < mMaxNumberOfCpus; Index++) { - if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) { - if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) { + if (!(*(CpuData[Index].Present)) && (ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) { + if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0)) { continue; } - if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) { + + if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0)) { continue; } - if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) { + + if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0)) { continue; } + return FALSE; } } - return TRUE; } @@ -223,7 +230,7 @@ IsLmceOsEnabled ( } McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); - return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN == 1); + return (BOOLEAN)(McgExtCtrl.Bits.LMCE_EN == 1); } /** @@ -241,10 +248,10 @@ IsLmceSignaled ( VOID ) { - MSR_IA32_MCG_STATUS_REGISTER McgStatus; + MSR_IA32_MCG_STATUS_REGISTER McgStatus; McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); - return (BOOLEAN) (McgStatus.Bits.LMCE_S == 1); + return (BOOLEAN)(McgStatus.Bits.LMCE_S == 1); } /** @@ -257,10 +264,10 @@ SmmWaitForApArrival ( VOID ) { - UINT64 Timer; - UINTN Index; - BOOLEAN LmceEn; - BOOLEAN LmceSignal; + UINT64 Timer; + UINTN Index; + BOOLEAN LmceEn; + BOOLEAN LmceSignal; ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus); @@ -268,7 +275,7 @@ SmmWaitForApArrival ( LmceSignal = FALSE; if (mMachineCheckSupported) { LmceEn = IsLmceOsEnabled (); - LmceSignal = IsLmceSignaled(); + LmceSignal = IsLmceSignaled (); } // @@ -287,8 +294,9 @@ SmmWaitForApArrival ( // for (Timer = StartSyncTimer (); !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) && - !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED ); - ) { + !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED); + ) + { CpuPause (); } @@ -313,7 +321,7 @@ SmmWaitForApArrival ( // Send SMI IPIs to bring outside processors in // for (Index = 0; Index < mMaxNumberOfCpus; Index++) { - if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) { + if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) { SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId); } } @@ -323,8 +331,9 @@ SmmWaitForApArrival ( // for (Timer = StartSyncTimer (); !IsSyncTimerTimeout (Timer) && - !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED ); - ) { + !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED); + ) + { CpuPause (); } } @@ -332,7 +341,6 @@ SmmWaitForApArrival ( return; } - /** Replace OS MTRR's with SMI MTRR's. @@ -341,7 +349,7 @@ SmmWaitForApArrival ( **/ VOID ReplaceOSMtrrs ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { SmmCpuFeaturesDisableSmrr (); @@ -363,25 +371,25 @@ ReplaceOSMtrrs ( **/ BOOLEAN WaitForAllAPsNotBusy ( - IN BOOLEAN BlockMode + IN BOOLEAN BlockMode ) { - UINTN Index; + UINTN Index; for (Index = 0; Index < mMaxNumberOfCpus; Index++) { // // Ignore BSP and APs which not call in SMM. // - if (!IsPresentAp(Index)) { + if (!IsPresentAp (Index)) { continue; } if (BlockMode) { - AcquireSpinLock(mSmmMpSyncData->CpuData[Index].Busy); - ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy); + AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy); + ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy); } else { if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) { - ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy); + ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy); } else { return FALSE; } @@ -402,11 +410,11 @@ WaitForAllAPsNotBusy ( **/ BOOLEAN IsPresentAp ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { return ((CpuIndex != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) && - *(mSmmMpSyncData->CpuData[CpuIndex].Present)); + *(mSmmMpSyncData->CpuData[CpuIndex].Present)); } /** @@ -417,10 +425,10 @@ IsPresentAp ( **/ VOID ReleaseToken ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { - PROCEDURE_TOKEN *Token; + PROCEDURE_TOKEN *Token; Token = mSmmMpSyncData->CpuData[CpuIndex].Token; @@ -455,15 +463,15 @@ ResetTokens ( **/ VOID BSPHandler ( - IN UINTN CpuIndex, - IN SMM_CPU_SYNC_MODE SyncMode + IN UINTN CpuIndex, + IN SMM_CPU_SYNC_MODE SyncMode ) { - UINTN Index; - MTRR_SETTINGS Mtrrs; - UINTN ApCount; - BOOLEAN ClearTopLevelSmiResult; - UINTN PresentCount; + UINTN Index; + MTRR_SETTINGS Mtrrs; + UINTN ApCount; + BOOLEAN ClearTopLevelSmiResult; + UINTN PresentCount; ASSERT (CpuIndex == mSmmMpSyncData->BspIndex); ApCount = 0; @@ -488,7 +496,7 @@ BSPHandler ( // we cleared it after SMI handlers are run, we would miss the SMI that // occurs after SMI handlers are done and before SMI status bit is cleared. // - ClearTopLevelSmiResult = ClearTopLevelSmiStatus(); + ClearTopLevelSmiResult = ClearTopLevelSmiStatus (); ASSERT (ClearTopLevelSmiResult == TRUE); // @@ -499,25 +507,24 @@ BSPHandler ( // // If Traditional Sync Mode or need to configure MTRRs: gather all available APs. // - if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) { - + if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for APs to arrive // - SmmWaitForApArrival(); + SmmWaitForApArrival (); // // Lock the counter down and retrieve the number of APs // *mSmmMpSyncData->AllCpusInSync = TRUE; - ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1; + ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1; // // Wait for all APs to get ready for programming MTRRs // WaitForAllAPs (ApCount); - if (SmmCpuFeaturesNeedConfigureMtrrs()) { + if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal all APs it's time for backup MTRRs // @@ -531,7 +538,7 @@ BSPHandler ( // We do the backup first and then set MTRR to avoid race condition for threads // in the same core. // - MtrrGetAllMtrrs(&Mtrrs); + MtrrGetAllMtrrs (&Mtrrs); // // Wait for all APs to complete their MTRR saving @@ -587,13 +594,12 @@ BSPHandler ( // make those APs to exit SMI synchronously. APs which arrive later will be excluded and // will run through freely. // - if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) { - + if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Lock the counter down and retrieve the number of APs // *mSmmMpSyncData->AllCpusInSync = TRUE; - ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1; + ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1; // // Make sure all APs have their Present flag set // @@ -601,9 +607,10 @@ BSPHandler ( PresentCount = 0; for (Index = 0; Index < mMaxNumberOfCpus; Index++) { if (*(mSmmMpSyncData->CpuData[Index].Present)) { - PresentCount ++; + PresentCount++; } } + if (PresentCount > ApCount) { break; } @@ -621,7 +628,7 @@ BSPHandler ( // WaitForAllAPs (ApCount); - if (SmmCpuFeaturesNeedConfigureMtrrs()) { + if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal APs to restore MTRRs // @@ -631,7 +638,7 @@ BSPHandler ( // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); - MtrrSetAllMtrrs(&Mtrrs); + MtrrSetAllMtrrs (&Mtrrs); // // Wait for all APs to complete MTRR programming @@ -681,7 +688,7 @@ BSPHandler ( // // Allow APs to check in from this point on // - *mSmmMpSyncData->Counter = 0; + *mSmmMpSyncData->Counter = 0; *mSmmMpSyncData->AllCpusInSync = FALSE; } @@ -695,15 +702,15 @@ BSPHandler ( **/ VOID APHandler ( - IN UINTN CpuIndex, - IN BOOLEAN ValidSmi, - IN SMM_CPU_SYNC_MODE SyncMode + IN UINTN CpuIndex, + IN BOOLEAN ValidSmi, + IN SMM_CPU_SYNC_MODE SyncMode ) { - UINT64 Timer; - UINTN BspIndex; - MTRR_SETTINGS Mtrrs; - EFI_STATUS ProcedureStatus; + UINT64 Timer; + UINTN BspIndex; + MTRR_SETTINGS Mtrrs; + EFI_STATUS ProcedureStatus; // // Timeout BSP @@ -711,7 +718,8 @@ APHandler ( for (Timer = StartSyncTimer (); !IsSyncTimerTimeout (Timer) && !(*mSmmMpSyncData->InsideSmm); - ) { + ) + { CpuPause (); } @@ -737,7 +745,8 @@ APHandler ( for (Timer = StartSyncTimer (); !IsSyncTimerTimeout (Timer) && !(*mSmmMpSyncData->InsideSmm); - ) { + ) + { CpuPause (); } @@ -768,14 +777,14 @@ APHandler ( // *(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE; - if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) { + if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP of arrival at this point // ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); } - if (SmmCpuFeaturesNeedConfigureMtrrs()) { + if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // @@ -784,7 +793,7 @@ APHandler ( // // Backup OS MTRRs // - MtrrGetAllMtrrs(&Mtrrs); + MtrrGetAllMtrrs (&Mtrrs); // // Signal BSP the completion of this AP @@ -830,9 +839,9 @@ APHandler ( // // Invoke the scheduled procedure // - ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure) ( - (VOID*)mSmmMpSyncData->CpuData[CpuIndex].Parameter - ); + ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure)( + (VOID *)mSmmMpSyncData->CpuData[CpuIndex].Parameter + ); if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus; } @@ -847,7 +856,7 @@ APHandler ( ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } - if (SmmCpuFeaturesNeedConfigureMtrrs()) { + if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // @@ -862,7 +871,7 @@ APHandler ( // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); - MtrrSetAllMtrrs(&Mtrrs); + MtrrSetAllMtrrs (&Mtrrs); } // @@ -884,7 +893,6 @@ APHandler ( // Notify BSP the readiness of this AP to exit SMM // ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); - } /** @@ -896,7 +904,7 @@ APHandler ( **/ UINT32 Gen4GPageTable ( - IN BOOLEAN Is32BitPageTable + IN BOOLEAN Is32BitPageTable ) { VOID *PageTable; @@ -911,9 +919,9 @@ Gen4GPageTable ( UINTN PageIndex; UINTN PageAddress; - Low2MBoundary = 0; + Low2MBoundary = 0; High2MBoundary = 0; - PagesNeeded = 0; + PagesNeeded = 0; if (FeaturePcdGet (PcdCpuSmmStackGuard)) { // // Add one more page for known good stack, then find the lower 2MB aligned address. @@ -924,8 +932,9 @@ Gen4GPageTable ( // then find the lower 2MB aligned address. // High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1); - PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1; + PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1; } + // // Allocate the page table // @@ -933,7 +942,7 @@ Gen4GPageTable ( ASSERT (PageTable != NULL); PageTable = (VOID *)((UINTN)PageTable); - Pte = (UINT64*)PageTable; + Pte = (UINT64 *)PageTable; // // Zero out all page table entries first @@ -945,8 +954,9 @@ Gen4GPageTable ( // for (Index = 0; Index < 4; Index++) { Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask | - (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS); + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS); } + Pte += EFI_PAGE_SIZE / sizeof (*Pte); // @@ -956,17 +966,17 @@ Gen4GPageTable ( Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS; } - Pdpte = (UINT64*)PageTable; + Pdpte = (UINT64 *)PageTable; if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5); + Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5); GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE; for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) { - Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); + Pte = (UINT64 *)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; // // Fill in Page Table Entries // - Pte = (UINT64*)Pages; + Pte = (UINT64 *)Pages; PageAddress = PageIndex; for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { if (PageAddress == GuardPage) { @@ -981,17 +991,19 @@ Gen4GPageTable ( } else { Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } - PageAddress+= EFI_PAGE_SIZE; + + PageAddress += EFI_PAGE_SIZE; } + Pages += EFI_PAGE_SIZE; } } if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) { - Pte = (UINT64*)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); + Pte = (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); if ((Pte[0] & IA32_PG_PS) == 0) { // 4K-page entries are already mapped. Just hide the first one anyway. - Pte = (UINT64*)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); + Pte = (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0 } else { // Create 4K-page entries @@ -1000,12 +1012,12 @@ Gen4GPageTable ( Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS); - Pte = (UINT64*)Pages; + Pte = (UINT64 *)Pages; PageAddress = 0; - Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left + Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { PageAddress += EFI_PAGE_SIZE; - Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS; + Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } } } @@ -1024,11 +1036,11 @@ Gen4GPageTable ( **/ BOOLEAN IsTokenInUse ( - IN SPIN_LOCK *Token + IN SPIN_LOCK *Token ) { - LIST_ENTRY *Link; - PROCEDURE_TOKEN *ProcToken; + LIST_ENTRY *Link; + PROCEDURE_TOKEN *ProcToken; if (Token == NULL) { return FALSE; @@ -1061,12 +1073,12 @@ AllocateTokenBuffer ( VOID ) { - UINTN SpinLockSize; - UINT32 TokenCountPerChunk; - UINTN Index; - SPIN_LOCK *SpinLock; - UINT8 *SpinLockBuffer; - PROCEDURE_TOKEN *ProcTokens; + UINTN SpinLockSize; + UINT32 TokenCountPerChunk; + UINTN Index; + SPIN_LOCK *SpinLock; + UINT8 *SpinLockBuffer; + PROCEDURE_TOKEN *ProcTokens; SpinLockSize = GetSpinLockProperties (); @@ -1076,6 +1088,7 @@ AllocateTokenBuffer ( DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n")); CpuDeadLoop (); } + DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk)); // @@ -1113,7 +1126,7 @@ AllocateTokenBuffer ( **/ PROCEDURE_TOKEN * GetFreeToken ( - IN UINT32 RunningApsCount + IN UINT32 RunningApsCount ) { PROCEDURE_TOKEN *NewToken; @@ -1125,7 +1138,8 @@ GetFreeToken ( if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) { gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer (); } - NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken); + + NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken); gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken); NewToken->RunningApCount = RunningApsCount; @@ -1148,7 +1162,7 @@ GetFreeToken ( **/ EFI_STATUS IsApReady ( - IN SPIN_LOCK *Token + IN SPIN_LOCK *Token ) { if (AcquireSpinLockOrFail (Token)) { @@ -1196,42 +1210,50 @@ IsApReady ( **/ EFI_STATUS InternalSmmStartupThisAp ( - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL, - IN MM_COMPLETION *Token, - IN UINTN TimeoutInMicroseconds, - IN OUT EFI_STATUS *CpuStatus + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL, + IN MM_COMPLETION *Token, + IN UINTN TimeoutInMicroseconds, + IN OUT EFI_STATUS *CpuStatus ) { - PROCEDURE_TOKEN *ProcToken; + PROCEDURE_TOKEN *ProcToken; if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) { - DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus)); + DEBUG ((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus)); return EFI_INVALID_PARAMETER; } + if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) { - DEBUG((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex)); + DEBUG ((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex)); return EFI_INVALID_PARAMETER; } + if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) { return EFI_INVALID_PARAMETER; } + if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) { if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) { - DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex)); + DEBUG ((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex)); } + return EFI_INVALID_PARAMETER; } + if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) { if (!FeaturePcdGet (PcdCpuHotPlugSupport)) { - DEBUG((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex)); + DEBUG ((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex)); } + return EFI_INVALID_PARAMETER; } + if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) { return EFI_INVALID_PARAMETER; } + if (Procedure == NULL) { return EFI_INVALID_PARAMETER; } @@ -1257,12 +1279,13 @@ InternalSmmStartupThisAp ( // 2. Get a free token from the token buffer. // 3. Call ReleaseToken() in APHandler(). // - ProcToken = GetFreeToken (1); + ProcToken = GetFreeToken (1); mSmmMpSyncData->CpuData[CpuIndex].Token = ProcToken; - *Token = (MM_COMPLETION)ProcToken->SpinLock; + *Token = (MM_COMPLETION)ProcToken->SpinLock; } } - mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus; + + mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY; } @@ -1309,20 +1332,21 @@ InternalSmmStartupThisAp ( **/ EFI_STATUS InternalSmmStartupAllAPs ( - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ) { - UINTN Index; - UINTN CpuCount; - PROCEDURE_TOKEN *ProcToken; + UINTN Index; + UINTN CpuCount; + PROCEDURE_TOKEN *ProcToken; if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) { return EFI_INVALID_PARAMETER; } + if (Procedure == NULL) { return EFI_INVALID_PARAMETER; } @@ -1330,25 +1354,27 @@ InternalSmmStartupAllAPs ( CpuCount = 0; for (Index = 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { - CpuCount ++; + CpuCount++; if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) { return EFI_INVALID_PARAMETER; } - if (!AcquireSpinLockOrFail(mSmmMpSyncData->CpuData[Index].Busy)) { + if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) { return EFI_NOT_READY; } + ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy); } } + if (CpuCount == 0) { return EFI_NOT_STARTED; } if (Token != NULL) { ProcToken = GetFreeToken ((UINT32)mMaxNumberOfCpus); - *Token = (MM_COMPLETION)ProcToken->SpinLock; + *Token = (MM_COMPLETION)ProcToken->SpinLock; } else { ProcToken = NULL; } @@ -1368,13 +1394,14 @@ InternalSmmStartupAllAPs ( for (Index = 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { - mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2) Procedure; + mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2)Procedure; mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments; if (ProcToken != NULL) { - mSmmMpSyncData->CpuData[Index].Token = ProcToken; + mSmmMpSyncData->CpuData[Index].Token = ProcToken; } + if (CPUStatus != NULL) { - mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index]; + mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index]; if (mSmmMpSyncData->CpuData[Index].Status != NULL) { *mSmmMpSyncData->CpuData[Index].Status = EFI_NOT_READY; } @@ -1426,10 +1453,10 @@ InternalSmmStartupAllAPs ( EFI_STATUS EFIAPI ProcedureWrapper ( - IN VOID *Buffer + IN VOID *Buffer ) { - PROCEDURE_WRAPPER *Wrapper; + PROCEDURE_WRAPPER *Wrapper; Wrapper = Buffer; Wrapper->Procedure (Wrapper->ProcedureArgument); @@ -1454,14 +1481,14 @@ ProcedureWrapper ( EFI_STATUS EFIAPI SmmBlockingStartupThisAp ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL ) { PROCEDURE_WRAPPER Wrapper; - Wrapper.Procedure = Procedure; + Wrapper.Procedure = Procedure; Wrapper.ProcedureArgument = ProcArguments; // @@ -1487,25 +1514,25 @@ SmmBlockingStartupThisAp ( EFI_STATUS EFIAPI SmmStartupThisAp ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL ) { - gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure = Procedure; + gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure = Procedure; gSmmCpuPrivate->ApWrapperFunc[CpuIndex].ProcedureArgument = ProcArguments; // // Use wrapper function to convert EFI_AP_PROCEDURE to EFI_AP_PROCEDURE2. // return InternalSmmStartupThisAp ( - ProcedureWrapper, - CpuIndex, - &gSmmCpuPrivate->ApWrapperFunc[CpuIndex], - FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken, - 0, - NULL - ); + ProcedureWrapper, + CpuIndex, + &gSmmCpuPrivate->ApWrapperFunc[CpuIndex], + FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken, + 0, + NULL + ); } /** @@ -1524,10 +1551,10 @@ CpuSmmDebugEntry ( IN UINTN CpuIndex ) { - SMRAM_SAVE_STATE_MAP *CpuSaveState; + SMRAM_SAVE_STATE_MAP *CpuSaveState; if (FeaturePcdGet (PcdCpuSmmDebug)) { - ASSERT(CpuIndex < mMaxNumberOfCpus); + ASSERT (CpuIndex < mMaxNumberOfCpus); CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex]; if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { AsmWriteDr6 (CpuSaveState->x86._DR6); @@ -1554,10 +1581,10 @@ CpuSmmDebugExit ( IN UINTN CpuIndex ) { - SMRAM_SAVE_STATE_MAP *CpuSaveState; + SMRAM_SAVE_STATE_MAP *CpuSaveState; if (FeaturePcdGet (PcdCpuSmmDebug)) { - ASSERT(CpuIndex < mMaxNumberOfCpus); + ASSERT (CpuIndex < mMaxNumberOfCpus); CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex]; if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 (); @@ -1578,17 +1605,17 @@ CpuSmmDebugExit ( VOID EFIAPI SmiRendezvous ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { - EFI_STATUS Status; - BOOLEAN ValidSmi; - BOOLEAN IsBsp; - BOOLEAN BspInProgress; - UINTN Index; - UINTN Cr2; + EFI_STATUS Status; + BOOLEAN ValidSmi; + BOOLEAN IsBsp; + BOOLEAN BspInProgress; + UINTN Index; + UINTN Cr2; - ASSERT(CpuIndex < mMaxNumberOfCpus); + ASSERT (CpuIndex < mMaxNumberOfCpus); // // Save Cr2 because Page Fault exception in SMM may override its value, @@ -1612,7 +1639,7 @@ SmiRendezvous ( // // Determine if this is a valid SMI // - ValidSmi = PlatformValidSmi(); + ValidSmi = PlatformValidSmi (); // // Determine if BSP has been already in progress. Note this must be checked after @@ -1644,9 +1671,9 @@ SmiRendezvous ( while (*mSmmMpSyncData->AllCpusInSync) { CpuPause (); } + goto Exit; } else { - // // The BUSY lock is initialized to Released state. // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call. @@ -1693,7 +1720,7 @@ SmiRendezvous ( // Platform hook fails to determine, use default BSP election method // InterlockedCompareExchange32 ( - (UINT32*)&mSmmMpSyncData->BspIndex, + (UINT32 *)&mSmmMpSyncData->BspIndex, (UINT32)-1, (UINT32)CpuIndex ); @@ -1705,7 +1732,6 @@ SmiRendezvous ( // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP // if (mSmmMpSyncData->BspIndex == CpuIndex) { - // // Clear last request for SwitchBsp. // @@ -1774,45 +1800,45 @@ InitializeSmmCpuSemaphores ( VOID ) { - UINTN ProcessorCount; - UINTN TotalSize; - UINTN GlobalSemaphoresSize; - UINTN CpuSemaphoresSize; - UINTN SemaphoreSize; - UINTN Pages; - UINTN *SemaphoreBlock; - UINTN SemaphoreAddr; - - SemaphoreSize = GetSpinLockProperties (); - ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; + UINTN ProcessorCount; + UINTN TotalSize; + UINTN GlobalSemaphoresSize; + UINTN CpuSemaphoresSize; + UINTN SemaphoreSize; + UINTN Pages; + UINTN *SemaphoreBlock; + UINTN SemaphoreAddr; + + SemaphoreSize = GetSpinLockProperties (); + ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize; CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize; - TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize; - DEBUG((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize)); - DEBUG((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize)); - Pages = EFI_SIZE_TO_PAGES (TotalSize); + TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize; + DEBUG ((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize)); + DEBUG ((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize)); + Pages = EFI_SIZE_TO_PAGES (TotalSize); SemaphoreBlock = AllocatePages (Pages); ASSERT (SemaphoreBlock != NULL); ZeroMem (SemaphoreBlock, TotalSize); - SemaphoreAddr = (UINTN)SemaphoreBlock; + SemaphoreAddr = (UINTN)SemaphoreBlock; mSmmCpuSemaphores.SemaphoreGlobal.Counter = (UINT32 *)SemaphoreAddr; - SemaphoreAddr += SemaphoreSize; + SemaphoreAddr += SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm = (BOOLEAN *)SemaphoreAddr; - SemaphoreAddr += SemaphoreSize; + SemaphoreAddr += SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync = (BOOLEAN *)SemaphoreAddr; - SemaphoreAddr += SemaphoreSize; + SemaphoreAddr += SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.PFLock = (SPIN_LOCK *)SemaphoreAddr; - SemaphoreAddr += SemaphoreSize; + SemaphoreAddr += SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock - = (SPIN_LOCK *)SemaphoreAddr; + = (SPIN_LOCK *)SemaphoreAddr; SemaphoreAddr += SemaphoreSize; - SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize; + SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize; mSmmCpuSemaphores.SemaphoreCpu.Busy = (SPIN_LOCK *)SemaphoreAddr; - SemaphoreAddr += ProcessorCount * SemaphoreSize; + SemaphoreAddr += ProcessorCount * SemaphoreSize; mSmmCpuSemaphores.SemaphoreCpu.Run = (UINT32 *)SemaphoreAddr; - SemaphoreAddr += ProcessorCount * SemaphoreSize; + SemaphoreAddr += ProcessorCount * SemaphoreSize; mSmmCpuSemaphores.SemaphoreCpu.Present = (BOOLEAN *)SemaphoreAddr; mPFLock = mSmmCpuSemaphores.SemaphoreGlobal.PFLock; @@ -1831,7 +1857,7 @@ InitializeMpSyncData ( VOID ) { - UINTN CpuIndex; + UINTN CpuIndex; if (mSmmMpSyncData != NULL) { // @@ -1839,7 +1865,7 @@ InitializeMpSyncData ( // CpuData array of SMM_CPU_DATA_BLOCK and one CandidateBsp array of BOOLEAN. // ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize); - mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA)); + mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA)); mSmmMpSyncData->CandidateBsp = (BOOLEAN *)(mSmmMpSyncData->CpuData + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) { // @@ -1847,21 +1873,24 @@ InitializeMpSyncData ( // mSmmMpSyncData->BspIndex = (UINT32)-1; } + mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode; mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter; mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm; mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync; - ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL && - mSmmMpSyncData->AllCpusInSync != NULL); + ASSERT ( + mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL && + mSmmMpSyncData->AllCpusInSync != NULL + ); *mSmmMpSyncData->Counter = 0; *mSmmMpSyncData->InsideSmm = FALSE; *mSmmMpSyncData->AllCpusInSync = FALSE; - for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex ++) { - mSmmMpSyncData->CpuData[CpuIndex].Busy = + for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) { + mSmmMpSyncData->CpuData[CpuIndex].Busy = (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex); - mSmmMpSyncData->CpuData[CpuIndex].Run = + mSmmMpSyncData->CpuData[CpuIndex].Run = (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreSize * CpuIndex); mSmmMpSyncData->CpuData[CpuIndex].Present = (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemaphoreSize * CpuIndex); @@ -1882,9 +1911,9 @@ InitializeMpSyncData ( **/ UINT32 InitializeMpServiceData ( - IN VOID *Stacks, - IN UINTN StackSize, - IN UINTN ShadowStackSize + IN VOID *Stacks, + IN UINTN StackSize, + IN UINTN ShadowStackSize ) { UINT32 Cr3; @@ -1911,7 +1940,7 @@ InitializeMpServiceData ( // mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) + (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; - mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize)); + mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA *)AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize)); ASSERT (mSmmMpSyncData != NULL); mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode); InitializeMpSyncData (); @@ -1926,7 +1955,8 @@ InitializeMpServiceData ( } else { VirPhyAddressSize.Bits.PhysicalAddressBits = 36; } - gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; + + gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; // // Clear the low 12 bits // @@ -1946,7 +1976,7 @@ InitializeMpServiceData ( InstallSmiHandler ( Index, (UINT32)mCpuHotPlugData.SmBase[Index], - (VOID*)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index), + (VOID *)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index), StackSize, (UINTN)(GdtTssTables + GdtTableStepSize * Index), gcSmiGdtr.Limit + 1, @@ -2009,13 +2039,14 @@ RegisterSmmEntry ( **/ EFI_STATUS RegisterStartupProcedure ( - IN EFI_AP_PROCEDURE Procedure, - IN OUT VOID *ProcedureArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN OUT VOID *ProcedureArguments OPTIONAL ) { - if (Procedure == NULL && ProcedureArguments != NULL) { + if ((Procedure == NULL) && (ProcedureArguments != NULL)) { return EFI_INVALID_PARAMETER; } + if (mSmmMpSyncData == NULL) { return EFI_NOT_READY; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index fbf45d6525..40aabeda72 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -21,7 +21,9 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { NULL, // Pointer to Operation array NULL, // Pointer to CpuSaveStateSize array NULL, // Pointer to CpuSaveState array - { {0} }, // SmmReservedSmramRegion + { + { 0 } + }, // SmmReservedSmramRegion { SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp 0, // SmmCoreEntryContext.CurrentlyExecutingCpu @@ -35,10 +37,10 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry }, NULL, // pointer to Ap Wrapper Func array - {NULL, NULL}, // List_Entry for Tokens. + { NULL, NULL }, // List_Entry for Tokens. }; -CPU_HOT_PLUG_DATA mCpuHotPlugData = { +CPU_HOT_PLUG_DATA mCpuHotPlugData = { CPU_HOT_PLUG_DATA_REVISION_1, // Revision 0, // Array Length of SmBase and APIC ID NULL, // Pointer to APIC ID array @@ -67,7 +69,7 @@ EFI_HANDLE mSmmCpuHandle = NULL; /// /// SMM CPU Protocol instance /// -EFI_SMM_CPU_PROTOCOL mSmmCpu = { +EFI_SMM_CPU_PROTOCOL mSmmCpu = { SmmReadSaveState, SmmWriteSaveState }; @@ -75,60 +77,60 @@ EFI_SMM_CPU_PROTOCOL mSmmCpu = { /// /// SMM Memory Attribute Protocol instance /// -EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = { +EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = { EdkiiSmmGetMemoryAttributes, EdkiiSmmSetMemoryAttributes, EdkiiSmmClearMemoryAttributes }; -EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; +EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; // // SMM stack information // -UINTN mSmmStackArrayBase; -UINTN mSmmStackArrayEnd; -UINTN mSmmStackSize; +UINTN mSmmStackArrayBase; +UINTN mSmmStackArrayEnd; +UINTN mSmmStackSize; -UINTN mSmmShadowStackSize; -BOOLEAN mCetSupported = TRUE; +UINTN mSmmShadowStackSize; +BOOLEAN mCetSupported = TRUE; -UINTN mMaxNumberOfCpus = 1; -UINTN mNumberOfCpus = 1; +UINTN mMaxNumberOfCpus = 1; +UINTN mNumberOfCpus = 1; // // SMM ready to lock flag // -BOOLEAN mSmmReadyToLock = FALSE; +BOOLEAN mSmmReadyToLock = FALSE; // // Global used to cache PCD for SMM Code Access Check enable // -BOOLEAN mSmmCodeAccessCheckEnable = FALSE; +BOOLEAN mSmmCodeAccessCheckEnable = FALSE; // // Global copy of the PcdPteMemoryEncryptionAddressOrMask // -UINT64 mAddressEncMask = 0; +UINT64 mAddressEncMask = 0; // // Spin lock used to serialize setting of SMM Code Access Check feature // -SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; +SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; // // Saved SMM ranges information // -EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; -UINTN mSmmCpuSmramRangeCount; +EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; +UINTN mSmmCpuSmramRangeCount; -UINT8 mPhysicalAddressBits; +UINT8 mPhysicalAddressBits; // // Control register contents saved for SMM S3 resume state initialization. // -UINT32 mSmmCr0; -UINT32 mSmmCr4; +UINT32 mSmmCr0; +UINT32 mSmmCr4; /** Initialize IDT to setup exception handlers for SMM. @@ -139,19 +141,19 @@ InitializeSmmIdt ( VOID ) { - EFI_STATUS Status; - BOOLEAN InterruptState; - IA32_DESCRIPTOR DxeIdtr; + EFI_STATUS Status; + BOOLEAN InterruptState; + IA32_DESCRIPTOR DxeIdtr; // // There are 32 (not 255) entries in it since only processor // generated exceptions will be handled. // - gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; + gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; // // Allocate page aligned IDT, because it might be set as read only. // - gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1)); + gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1)); ASSERT (gcSmiIdtr.Base != 0); ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1); @@ -173,7 +175,7 @@ InitializeSmmIdt ( // // Restore DXE IDT table and CPU interrupt // - AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr); + AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr); SetInterruptState (InterruptState); } @@ -185,19 +187,19 @@ InitializeSmmIdt ( **/ VOID DumpModuleInfoByIp ( - IN UINTN CallerIpAddress + IN UINTN CallerIpAddress ) { - UINTN Pe32Data; - VOID *PdbPointer; + UINTN Pe32Data; + VOID *PdbPointer; // // Find Image Base // Pe32Data = PeCoffSearchImageBase (CallerIpAddress); if (Pe32Data != 0) { - DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress)); - PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); + DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress)); + PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data); if (PdbPointer != NULL) { DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer)); } @@ -221,11 +223,11 @@ DumpModuleInfoByIp ( EFI_STATUS EFIAPI SmmReadSaveState ( - IN CONST EFI_SMM_CPU_PROTOCOL *This, - IN UINTN Width, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN CpuIndex, - OUT VOID *Buffer + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + OUT VOID *Buffer ) { EFI_STATUS Status; @@ -236,6 +238,7 @@ SmmReadSaveState ( if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { return EFI_INVALID_PARAMETER; } + // // The SpeculationBarrier() call here is to ensure the above check for the // CpuIndex has been completed before the execution of subsequent codes. @@ -252,6 +255,7 @@ SmmReadSaveState ( if (Width != sizeof (UINT64)) { return EFI_INVALID_PARAMETER; } + // // If the processor is in SMM at the time the SMI occurred, // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer. @@ -273,6 +277,7 @@ SmmReadSaveState ( if (Status == EFI_UNSUPPORTED) { Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer); } + return Status; } @@ -293,11 +298,11 @@ SmmReadSaveState ( EFI_STATUS EFIAPI SmmWriteSaveState ( - IN CONST EFI_SMM_CPU_PROTOCOL *This, - IN UINTN Width, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN CpuIndex, - IN CONST VOID *Buffer + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + IN CONST VOID *Buffer ) { EFI_STATUS Status; @@ -324,10 +329,10 @@ SmmWriteSaveState ( if (Status == EFI_UNSUPPORTED) { Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer); } + return Status; } - /** C function for SMI handler. To change all processor's SMMBase Register. @@ -338,8 +343,8 @@ SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; // // Update SMM IDT entries' code segment and load IDT @@ -384,6 +389,7 @@ SmmInitHandler ( return; } } + ASSERT (FALSE); } @@ -427,7 +433,7 @@ SmmRelocateBases ( gcSmiInitGdtr.Base = gcSmiGdtr.Base; gcSmiInitGdtr.Limit = gcSmiGdtr.Limit; - U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); + U8Ptr = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); // @@ -459,7 +465,8 @@ SmmRelocateBases ( // // Wait for this AP to finish its 1st SMI // - while (!mRebased[Index]); + while (!mRebased[Index]) { + } } else { // // BSP will be Relocated later @@ -477,7 +484,8 @@ SmmRelocateBases ( // // Wait for the BSP to finish its 1st SMI // - while (!mRebased[BspIndex]); + while (!mRebased[BspIndex]) { + } // // Restore contents at address 0x38000 @@ -537,24 +545,24 @@ PiCpuSmmEntry ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpServices; - UINTN NumberOfEnabledProcessors; - UINTN Index; - VOID *Buffer; - UINTN BufferPages; - UINTN TileCodeSize; - UINTN TileDataSize; - UINTN TileSize; - UINT8 *Stacks; - VOID *Registration; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - UINTN FamilyId; - UINTN ModelId; - UINT32 Cr3; + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices; + UINTN NumberOfEnabledProcessors; + UINTN Index; + VOID *Buffer; + UINTN BufferPages; + UINTN TileCodeSize; + UINTN TileDataSize; + UINTN TileSize; + UINT8 *Stacks; + VOID *Registration; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + UINT32 Cr3; // // Initialize address fixup @@ -598,10 +606,10 @@ PiCpuSmmEntry ( // A constant BSP index makes no sense because it may be hot removed. // DEBUG_CODE_BEGIN (); - if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection)); + } - ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection)); - } DEBUG_CODE_END (); // @@ -625,6 +633,7 @@ PiCpuSmmEntry ( } else { mMaxNumberOfCpus = mNumberOfCpus; } + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus; // @@ -702,8 +711,8 @@ PiCpuSmmEntry ( // AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); FamilyId = (RegEax >> 8) & 0xf; - ModelId = (RegEax >> 4) & 0xf; - if (FamilyId == 0x06 || FamilyId == 0x0f) { + ModelId = (RegEax >> 4) & 0xf; + if ((FamilyId == 0x06) || (FamilyId == 0x0f)) { ModelId = ModelId | ((RegEax >> 12) & 0xf0); } @@ -712,6 +721,7 @@ PiCpuSmmEntry ( if (RegEax >= CPUID_EXTENDED_CPU_SIG) { AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); } + // // Determine the mode of the CPU at the time an SMI occurs // Intel(R) 64 and IA-32 Architectures Software Developer's Manual @@ -721,8 +731,9 @@ PiCpuSmmEntry ( if ((RegEdx & BIT29) != 0) { mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; } + if (FamilyId == 0x06) { - if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) { + if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) { mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; } } @@ -739,17 +750,18 @@ PiCpuSmmEntry ( mCetSupported = FALSE; PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); } + if (mCetSupported) { AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL); DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx)); AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL); DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); - AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL); + AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL); DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); } } else { mCetSupported = FALSE; - PatchInstructionX86(mPatchCetSupported, mCetSupported, 1); + PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); } } else { mCetSupported = FALSE; @@ -762,11 +774,11 @@ PiCpuSmmEntry ( // This size is rounded up to nearest power of 2. // TileCodeSize = GetSmiHandlerSize (); - TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB); + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); - TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); - TileSize = TileDataSize + TileCodeSize - 1; - TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); + TileSize = TileDataSize + TileCodeSize - 1; + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); // @@ -796,8 +808,9 @@ PiCpuSmmEntry ( } else { Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); } + ASSERT (Buffer != NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages))); + DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. @@ -832,17 +845,19 @@ PiCpuSmmEntry ( // size for each CPU in the platform // for (Index = 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; - gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP); + mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP); gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); - gSmmCpuPrivate->Operation[Index] = SmmCpuNone; + gSmmCpuPrivate->Operation[Index] = SmmCpuNone; if (Index < mNumberOfCpus) { Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]); ASSERT_EFI_ERROR (Status); mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId; - DEBUG ((DEBUG_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n", + DEBUG (( + DEBUG_INFO, + "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n", Index, (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId, mCpuHotPlugData.SmBase[Index], @@ -851,7 +866,7 @@ PiCpuSmmEntry ( )); } else { gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID; - mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID; + mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID; } } @@ -916,10 +931,10 @@ PiCpuSmmEntry ( } } - Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize))); + Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize))); ASSERT (Stacks != NULL); mSmmStackArrayBase = (UINTN)Stacks; - mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1; + mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1; DEBUG ((DEBUG_INFO, "Stacks - 0x%x\n", Stacks)); DEBUG ((DEBUG_INFO, "mSmmStackSize - 0x%x\n", mSmmStackSize)); @@ -933,7 +948,7 @@ PiCpuSmmEntry ( // PatchInstructionX86 ( gPatchSmmInitStack, - (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)), + (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)), sizeof (UINTN) ); @@ -977,8 +992,8 @@ PiCpuSmmEntry ( if (FeaturePcdGet (PcdCpuSmmStackGuard)) { SetNotPresentPage ( Cr3, - (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE(1) + (mSmmStackSize + mSmmShadowStackSize) * Index, - EFI_PAGES_TO_SIZE(1) + (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index, + EFI_PAGES_TO_SIZE (1) ); } } @@ -997,7 +1012,8 @@ PiCpuSmmEntry ( // Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces ( &gSmmCpuPrivate->SmmCpuHandle, - &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration, + &gEfiSmmConfigurationProtocolGuid, + &gSmmCpuPrivate->SmmConfiguration, NULL ); ASSERT_EFI_ERROR (Status); @@ -1087,17 +1103,17 @@ PiCpuSmmEntry ( **/ VOID FindSmramInfo ( - OUT UINT32 *SmrrBase, - OUT UINT32 *SmrrSize + OUT UINT32 *SmrrBase, + OUT UINT32 *SmrrSize ) { - EFI_STATUS Status; - UINTN Size; - EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; - EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; - UINTN Index; - UINT64 MaxSize; - BOOLEAN Found; + EFI_STATUS Status; + UINTN Size; + EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; + EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; + UINTN Index; + UINT64 MaxSize; + BOOLEAN Found; // // Get SMM Access Protocol @@ -1108,7 +1124,7 @@ FindSmramInfo ( // // Get SMRAM information // - Size = 0; + Size = 0; Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); ASSERT (Status == EFI_BUFFER_TOO_SMALL); @@ -1135,7 +1151,7 @@ FindSmramInfo ( if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) { if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) { if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) { - MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize; + MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize; CurrentSmramRange = &mSmmCpuSmramRanges[Index]; } } @@ -1150,14 +1166,15 @@ FindSmramInfo ( do { Found = FALSE; for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { - if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase && - *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) { + if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) && + (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))) + { *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart; *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); - Found = TRUE; - } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) { + Found = TRUE; + } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) { *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); - Found = TRUE; + Found = TRUE; } } } while (Found); @@ -1272,6 +1289,7 @@ ConfigSmmCodeAccessCheck ( // continue; } + // // Acquire Config SMM Code Access Check spin lock. The AP will release the // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). @@ -1316,7 +1334,7 @@ ConfigSmmCodeAccessCheck ( **/ VOID * AllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ) { VOID *Buffer; @@ -1325,6 +1343,7 @@ AllocatePageTableMemory ( if (Buffer != NULL) { return Buffer; } + return AllocatePages (Pages); } @@ -1337,7 +1356,7 @@ AllocatePageTableMemory ( **/ VOID * AllocateCodePages ( - IN UINTN Pages + IN UINTN Pages ) { EFI_STATUS Status; @@ -1351,7 +1370,8 @@ AllocateCodePages ( if (EFI_ERROR (Status)) { return NULL; } - return (VOID *) (UINTN) Memory; + + return (VOID *)(UINTN)Memory; } /** @@ -1366,8 +1386,8 @@ AllocateCodePages ( **/ VOID * AllocateAlignedCodePages ( - IN UINTN Pages, - IN UINTN Alignment + IN UINTN Pages, + IN UINTN Alignment ) { EFI_STATUS Status; @@ -1385,23 +1405,25 @@ AllocateAlignedCodePages ( if (Pages == 0) { return NULL; } + if (Alignment > EFI_PAGE_SIZE) { // // Calculate the total number of pages since alignment is larger than page size. // - AlignmentMask = Alignment - 1; - RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment); + AlignmentMask = Alignment - 1; + RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment); // // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow. // ASSERT (RealPages > Pages); - Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory); + Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory); if (EFI_ERROR (Status)) { return NULL; } - AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask; - UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory); + + AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask; + UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory); if (UnalignedPages > 0) { // // Free first unaligned page(s). @@ -1409,6 +1431,7 @@ AllocateAlignedCodePages ( Status = gSmst->SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } + Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages = RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { @@ -1426,9 +1449,11 @@ AllocateAlignedCodePages ( if (EFI_ERROR (Status)) { return NULL; } - AlignedMemory = (UINTN) Memory; + + AlignedMemory = (UINTN)Memory; } - return (VOID *) AlignedMemory; + + return (VOID *)AlignedMemory; } /** @@ -1447,6 +1472,7 @@ PerformRemainingTasks ( if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { SmmProfileStart (); } + // // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable. // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index fc9b748948..26d07c5b5e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -74,69 +74,69 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef union { struct { // enable shadow stacks - UINT32 SH_STK_ENP:1; + UINT32 SH_STK_ENP : 1; // enable the WRSS{D,Q}W instructions. - UINT32 WR_SHSTK_EN:1; + UINT32 WR_SHSTK_EN : 1; // enable tracking of indirect call/jmp targets to be ENDBRANCH instruction. - UINT32 ENDBR_EN:1; + UINT32 ENDBR_EN : 1; // enable legacy compatibility treatment for indirect call/jmp tracking. - UINT32 LEG_IW_EN:1; + UINT32 LEG_IW_EN : 1; // enable use of no-track prefix on indirect call/jmp. - UINT32 NO_TRACK_EN:1; + UINT32 NO_TRACK_EN : 1; // disable suppression of CET indirect branch tracking on legacy compatibility. - UINT32 SUPPRESS_DIS:1; - UINT32 RSVD:4; + UINT32 SUPPRESS_DIS : 1; + UINT32 RSVD : 4; // indirect branch tracking is suppressed. // This bit can be written to 1 only if TRACKER is written as IDLE. - UINT32 SUPPRESS:1; + UINT32 SUPPRESS : 1; // Value of the endbranch state machine // Values: IDLE (0), WAIT_FOR_ENDBRANCH(1). - UINT32 TRACKER:1; + UINT32 TRACKER : 1; // linear address of a bitmap in memory indicating valid // pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled // and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on // parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are // reserved and must be 0. This value is extended by 12 bits at the low end to form the base address // (this automatically aligns the address on a 4-Kbyte boundary). - UINT32 EB_LEG_BITMAP_BASE_low:12; - UINT32 EB_LEG_BITMAP_BASE_high:32; + UINT32 EB_LEG_BITMAP_BASE_low : 12; + UINT32 EB_LEG_BITMAP_BASE_high : 32; } Bits; - UINT64 Uint64; + UINT64 Uint64; } MSR_IA32_CET; // // MSRs required for configuration of SMM Code Access Check // -#define EFI_MSR_SMM_MCA_CAP 0x17D -#define SMM_CODE_ACCESS_CHK_BIT BIT58 +#define EFI_MSR_SMM_MCA_CAP 0x17D +#define SMM_CODE_ACCESS_CHK_BIT BIT58 -#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0 -#define SMM_CODE_CHK_EN_BIT BIT2 +#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0 +#define SMM_CODE_CHK_EN_BIT BIT2 /// /// Page Table Entry /// -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_U BIT2 -#define IA32_PG_WT BIT3 -#define IA32_PG_CD BIT4 -#define IA32_PG_A BIT5 -#define IA32_PG_D BIT6 -#define IA32_PG_PS BIT7 -#define IA32_PG_PAT_2M BIT12 -#define IA32_PG_PAT_4K IA32_PG_PS -#define IA32_PG_PMNT BIT62 -#define IA32_PG_NX BIT63 - -#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P) +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_U BIT2 +#define IA32_PG_WT BIT3 +#define IA32_PG_CD BIT4 +#define IA32_PG_A BIT5 +#define IA32_PG_D BIT6 +#define IA32_PG_PS BIT7 +#define IA32_PG_PAT_2M BIT12 +#define IA32_PG_PAT_4K IA32_PG_PS +#define IA32_PG_PMNT BIT62 +#define IA32_PG_NX BIT63 + +#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P) // // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE // X64 PAE PDPTE does not have such restriction // -#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P) +#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P) -#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS) +#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS) #define PAGING_4K_MASK 0xFFF #define PAGING_2M_MASK 0x1FFFFF @@ -144,11 +144,11 @@ typedef union { #define PAGING_PAE_INDEX_MASK 0x1FF -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull -#define SMRR_MAX_ADDRESS BASE_4GB +#define SMRR_MAX_ADDRESS BASE_4GB typedef enum { PageNone, @@ -158,28 +158,28 @@ typedef enum { } PAGE_ATTRIBUTE; typedef struct { - PAGE_ATTRIBUTE Attribute; - UINT64 Length; - UINT64 AddressMask; + PAGE_ATTRIBUTE Attribute; + UINT64 Length; + UINT64 AddressMask; } PAGE_ATTRIBUTE_TABLE; // // Size of Task-State Segment defined in IA32 Manual // -#define TSS_SIZE 104 -#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP -#define TSS_X64_IST1_OFFSET 36 -#define TSS_IA32_CR3_OFFSET 28 -#define TSS_IA32_ESP_OFFSET 56 -#define TSS_IA32_SSP_OFFSET 104 +#define TSS_SIZE 104 +#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP +#define TSS_X64_IST1_OFFSET 36 +#define TSS_IA32_CR3_OFFSET 28 +#define TSS_IA32_ESP_OFFSET 56 +#define TSS_IA32_SSP_OFFSET 104 -#define CR0_WP BIT16 +#define CR0_WP BIT16 // // Code select value // -#define PROTECT_MODE_CODE_SEGMENT 0x08 -#define LONG_MODE_CODE_SEGMENT 0x38 +#define PROTECT_MODE_CODE_SEGMENT 0x08 +#define LONG_MODE_CODE_SEGMENT 0x38 // // The size 0x20 must be bigger than @@ -189,31 +189,31 @@ typedef struct { // #define BACK_BUF_SIZE 0x20 -#define EXCEPTION_VECTOR_NUMBER 0x20 +#define EXCEPTION_VECTOR_NUMBER 0x20 -#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL +#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL -typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS; -#define ARRIVAL_EXCEPTION_BLOCKED 0x1 -#define ARRIVAL_EXCEPTION_DELAYED 0x2 -#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4 +typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS; +#define ARRIVAL_EXCEPTION_BLOCKED 0x1 +#define ARRIVAL_EXCEPTION_DELAYED 0x2 +#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4 // // Wrapper used to convert EFI_AP_PROCEDURE2 and EFI_AP_PROCEDURE. // typedef struct { - EFI_AP_PROCEDURE Procedure; - VOID *ProcedureArgument; + EFI_AP_PROCEDURE Procedure; + VOID *ProcedureArgument; } PROCEDURE_WRAPPER; #define PROCEDURE_TOKEN_SIGNATURE SIGNATURE_32 ('P', 'R', 'T', 'S') typedef struct { - UINTN Signature; - LIST_ENTRY Link; + UINTN Signature; + LIST_ENTRY Link; - SPIN_LOCK *SpinLock; - volatile UINT32 RunningApCount; + SPIN_LOCK *SpinLock; + volatile UINT32 RunningApCount; } PROCEDURE_TOKEN; #define PROCEDURE_TOKEN_FROM_LINK(a) CR (a, PROCEDURE_TOKEN, Link, PROCEDURE_TOKEN_SIGNATURE) @@ -221,10 +221,10 @@ typedef struct { #define TOKEN_BUFFER_SIGNATURE SIGNATURE_32 ('T', 'K', 'B', 'S') typedef struct { - UINTN Signature; - LIST_ENTRY Link; + UINTN Signature; + LIST_ENTRY Link; - UINT8 *Buffer; + UINT8 *Buffer; } TOKEN_BUFFER; #define TOKEN_BUFFER_FROM_LINK(a) CR (a, TOKEN_BUFFER, Link, TOKEN_BUFFER_SIGNATURE) @@ -237,33 +237,33 @@ typedef struct { #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u') typedef struct { - UINTN Signature; + UINTN Signature; - EFI_HANDLE SmmCpuHandle; + EFI_HANDLE SmmCpuHandle; - EFI_PROCESSOR_INFORMATION *ProcessorInfo; - SMM_CPU_OPERATION *Operation; - UINTN *CpuSaveStateSize; - VOID **CpuSaveState; + EFI_PROCESSOR_INFORMATION *ProcessorInfo; + SMM_CPU_OPERATION *Operation; + UINTN *CpuSaveStateSize; + VOID **CpuSaveState; - EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1]; - EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext; - EFI_SMM_ENTRY_POINT SmmCoreEntry; + EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1]; + EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext; + EFI_SMM_ENTRY_POINT SmmCoreEntry; - EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration; + EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration; - PROCEDURE_WRAPPER *ApWrapperFunc; - LIST_ENTRY TokenList; - LIST_ENTRY *FirstFreeToken; + PROCEDURE_WRAPPER *ApWrapperFunc; + LIST_ENTRY TokenList; + LIST_ENTRY *FirstFreeToken; } SMM_CPU_PRIVATE_DATA; extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate; -extern CPU_HOT_PLUG_DATA mCpuHotPlugData; -extern UINTN mMaxNumberOfCpus; -extern UINTN mNumberOfCpus; -extern EFI_SMM_CPU_PROTOCOL mSmmCpu; -extern EFI_MM_MP_PROTOCOL mSmmMp; -extern UINTN mInternalCr3; +extern CPU_HOT_PLUG_DATA mCpuHotPlugData; +extern UINTN mMaxNumberOfCpus; +extern UINTN mNumberOfCpus; +extern EFI_SMM_CPU_PROTOCOL mSmmCpu; +extern EFI_MM_MP_PROTOCOL mSmmMp; +extern UINTN mInternalCr3; /// /// The mode of the CPU at the time an SMI occurs @@ -291,11 +291,11 @@ extern UINT8 mSmmSaveStateRegisterLma; EFI_STATUS EFIAPI SmmReadSaveState ( - IN CONST EFI_SMM_CPU_PROTOCOL *This, - IN UINTN Width, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN CpuIndex, - OUT VOID *Buffer + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + OUT VOID *Buffer ); /** @@ -315,11 +315,11 @@ SmmReadSaveState ( EFI_STATUS EFIAPI SmmWriteSaveState ( - IN CONST EFI_SMM_CPU_PROTOCOL *This, - IN UINTN Width, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN CpuIndex, - IN CONST VOID *Buffer + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + IN CONST VOID *Buffer ); /** @@ -376,16 +376,16 @@ WriteSaveStateRegister ( IN CONST VOID *Buffer ); -extern CONST UINT8 gcSmmInitTemplate[]; -extern CONST UINT16 gcSmmInitSize; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; -extern UINT32 mSmmCr0; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; -extern UINT32 mSmmCr4; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack; -X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported; -extern BOOLEAN mCetSupported; +extern CONST UINT8 gcSmmInitTemplate[]; +extern CONST UINT16 gcSmmInitSize; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; +extern UINT32 mSmmCr0; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; +extern UINT32 mSmmCr4; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack; +X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported; +extern BOOLEAN mCetSupported; /** Semaphore operation for all processor relocate SMMBase. @@ -400,13 +400,13 @@ SmmRelocationSemaphoreComplete ( /// The type of SMM CPU Information /// typedef struct { - SPIN_LOCK *Busy; - volatile EFI_AP_PROCEDURE2 Procedure; - volatile VOID *Parameter; - volatile UINT32 *Run; - volatile BOOLEAN *Present; - PROCEDURE_TOKEN *Token; - EFI_STATUS *Status; + SPIN_LOCK *Busy; + volatile EFI_AP_PROCEDURE2 Procedure; + volatile VOID *Parameter; + volatile UINT32 *Run; + volatile BOOLEAN *Present; + PROCEDURE_TOKEN *Token; + EFI_STATUS *Status; } SMM_CPU_DATA_BLOCK; typedef enum { @@ -432,56 +432,56 @@ typedef struct { VOID *StartupProcArgs; } SMM_DISPATCHER_MP_SYNC_DATA; -#define SMM_PSD_OFFSET 0xfb00 +#define SMM_PSD_OFFSET 0xfb00 /// /// All global semaphores' pointer /// typedef struct { - volatile UINT32 *Counter; - volatile BOOLEAN *InsideSmm; - volatile BOOLEAN *AllCpusInSync; - SPIN_LOCK *PFLock; - SPIN_LOCK *CodeAccessCheckLock; + volatile UINT32 *Counter; + volatile BOOLEAN *InsideSmm; + volatile BOOLEAN *AllCpusInSync; + SPIN_LOCK *PFLock; + SPIN_LOCK *CodeAccessCheckLock; } SMM_CPU_SEMAPHORE_GLOBAL; /// /// All semaphores for each processor /// typedef struct { - SPIN_LOCK *Busy; - volatile UINT32 *Run; - volatile BOOLEAN *Present; - SPIN_LOCK *Token; + SPIN_LOCK *Busy; + volatile UINT32 *Run; + volatile BOOLEAN *Present; + SPIN_LOCK *Token; } SMM_CPU_SEMAPHORE_CPU; /// /// All semaphores' information /// typedef struct { - SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal; - SMM_CPU_SEMAPHORE_CPU SemaphoreCpu; + SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal; + SMM_CPU_SEMAPHORE_CPU SemaphoreCpu; } SMM_CPU_SEMAPHORES; -extern IA32_DESCRIPTOR gcSmiGdtr; -extern EFI_PHYSICAL_ADDRESS mGdtBuffer; -extern UINTN mGdtBufferSize; -extern IA32_DESCRIPTOR gcSmiIdtr; -extern VOID *gcSmiIdtrPtr; -extern UINT64 gPhyMask; -extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData; -extern UINTN mSmmStackArrayBase; -extern UINTN mSmmStackArrayEnd; -extern UINTN mSmmStackSize; -extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService; -extern IA32_DESCRIPTOR gcSmiInitGdtr; -extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores; -extern UINTN mSemaphoreSize; -extern SPIN_LOCK *mPFLock; -extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; -extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; -extern UINTN mSmmCpuSmramRangeCount; -extern UINT8 mPhysicalAddressBits; +extern IA32_DESCRIPTOR gcSmiGdtr; +extern EFI_PHYSICAL_ADDRESS mGdtBuffer; +extern UINTN mGdtBufferSize; +extern IA32_DESCRIPTOR gcSmiIdtr; +extern VOID *gcSmiIdtrPtr; +extern UINT64 gPhyMask; +extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData; +extern UINTN mSmmStackArrayBase; +extern UINTN mSmmStackArrayEnd; +extern UINTN mSmmStackSize; +extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService; +extern IA32_DESCRIPTOR gcSmiInitGdtr; +extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores; +extern UINTN mSemaphoreSize; +extern SPIN_LOCK *mPFLock; +extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; +extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; +extern UINTN mSmmCpuSmramRangeCount; +extern UINT8 mPhysicalAddressBits; // // Copy of the PcdPteMemoryEncryptionAddressOrMask @@ -497,10 +497,9 @@ extern UINT64 mAddressEncMask; **/ UINT32 Gen4GPageTable ( - IN BOOLEAN Is32BitPageTable + IN BOOLEAN Is32BitPageTable ); - /** Initialize global data for MP synchronization. @@ -511,9 +510,9 @@ Gen4GPageTable ( **/ UINT32 InitializeMpServiceData ( - IN VOID *Stacks, - IN UINTN StackSize, - IN UINTN ShadowStackSize + IN VOID *Stacks, + IN UINTN StackSize, + IN UINTN ShadowStackSize ); /** @@ -544,7 +543,7 @@ StartSyncTimer ( BOOLEAN EFIAPI IsSyncTimerTimeout ( - IN UINT64 Timer + IN UINT64 Timer ); /** @@ -567,8 +566,8 @@ InitializeIDTSmmStackGuard ( VOID EFIAPI InitializeIdtIst ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN UINT8 Ist + IN EFI_EXCEPTION_TYPE ExceptionType, + IN UINT8 Ist ); /** @@ -631,9 +630,9 @@ SmmInitPageTable ( EFI_STATUS EFIAPI SmmStartupThisAp ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL ); /** @@ -653,9 +652,9 @@ SmmStartupThisAp ( EFI_STATUS EFIAPI SmmBlockingStartupThisAp ( - IN EFI_AP_PROCEDURE Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL ); /** @@ -683,9 +682,9 @@ SmmBlockingStartupThisAp ( EFI_STATUS EFIAPI SmmSetMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); /** @@ -713,9 +712,9 @@ SmmSetMemoryAttributes ( EFI_STATUS EFIAPI SmmClearMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); /** @@ -738,8 +737,8 @@ InitializeMpSyncData ( **/ VOID FindSmramInfo ( - OUT UINT32 *SmrrBase, - OUT UINT32 *SmrrSize + OUT UINT32 *SmrrBase, + OUT UINT32 *SmrrSize ); /** @@ -765,8 +764,8 @@ SmmRelocateBases ( VOID EFIAPI SmiPFHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ); /** @@ -795,7 +794,7 @@ PerformPreTasks ( **/ VOID InitMsrSpinLockByIndex ( - IN UINT32 MsrIndex + IN UINT32 MsrIndex ); /** @@ -908,7 +907,7 @@ InstallSmiHandler ( **/ VOID DumpModuleInfoByIp ( - IN UINTN CallerIpAddress + IN UINTN CallerIpAddress ); /** @@ -964,8 +963,8 @@ SetPageTableAttributes ( **/ VOID GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL + OUT UINTN *Base, + OUT BOOLEAN *FiveLevels OPTIONAL ); /** @@ -994,10 +993,10 @@ GetPageTable ( EFI_STATUS EFIAPI SmmSetMemoryAttributesEx ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *IsSplitted OPTIONAL ); /** @@ -1026,10 +1025,10 @@ SmmSetMemoryAttributesEx ( EFI_STATUS EFIAPI SmmClearMemoryAttributesEx ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *IsSplitted OPTIONAL ); /** @@ -1049,7 +1048,7 @@ SmmClearMemoryAttributesEx ( **/ VOID * AllocatePageTableMemory ( - IN UINTN Pages + IN UINTN Pages ); /** @@ -1061,7 +1060,7 @@ AllocatePageTableMemory ( **/ VOID * AllocateCodePages ( - IN UINTN Pages + IN UINTN Pages ); /** @@ -1076,16 +1075,15 @@ AllocateCodePages ( **/ VOID * AllocateAlignedCodePages ( - IN UINTN Pages, - IN UINTN Alignment + IN UINTN Pages, + IN UINTN Alignment ); - // // S3 related global variable and function prototype. // -extern BOOLEAN mSmmS3Flag; +extern BOOLEAN mSmmS3Flag; /** Initialize SMM S3 resume state structure used during S3 Resume. @@ -1151,9 +1149,9 @@ TransferApToSafeState ( **/ EFI_STATUS SetShadowStack ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length + IN UINTN Cr3, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length ); /** @@ -1167,9 +1165,9 @@ SetShadowStack ( **/ EFI_STATUS SetNotPresentPage ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length + IN UINTN Cr3, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length ); /** @@ -1210,10 +1208,10 @@ InitShadowStack ( EFI_STATUS EFIAPI EdkiiSmmSetMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); /** @@ -1242,10 +1240,10 @@ EdkiiSmmSetMemoryAttributes ( EFI_STATUS EFIAPI EdkiiSmmClearMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); /** @@ -1272,10 +1270,10 @@ EdkiiSmmClearMemoryAttributes ( EFI_STATUS EFIAPI EdkiiSmmGetMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 *Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 *Attributes ); /** @@ -1285,7 +1283,7 @@ EdkiiSmmGetMemoryAttributes ( VOID EFIAPI PiSmmCpuSmmInitFixupAddress ( - ); + ); /** This function fixes up the address of the global variable or function @@ -1294,7 +1292,7 @@ PiSmmCpuSmmInitFixupAddress ( VOID EFIAPI PiSmmCpuSmiEntryFixupAddress ( - ); + ); /** This function reads CR2 register when on-demand paging is enabled @@ -1355,12 +1353,12 @@ RestoreCr2 ( **/ EFI_STATUS InternalSmmStartupThisAp ( - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN CpuIndex, - IN OUT VOID *ProcArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN UINTN TimeoutInMicroseconds, - IN OUT EFI_STATUS *CpuStatus + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN CpuIndex, + IN OUT VOID *ProcArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN UINTN TimeoutInMicroseconds, + IN OUT EFI_STATUS *CpuStatus ); /** @@ -1374,7 +1372,7 @@ InternalSmmStartupThisAp ( **/ BOOLEAN IsTokenInUse ( - IN SPIN_LOCK *Token + IN SPIN_LOCK *Token ); /** @@ -1405,7 +1403,7 @@ IsApReady ( **/ BOOLEAN IsPresentAp ( - IN UINTN CpuIndex + IN UINTN CpuIndex ); /** @@ -1439,11 +1437,11 @@ IsPresentAp ( **/ EFI_STATUS InternalSmmStartupAllAPs ( - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ); /** @@ -1466,8 +1464,8 @@ InternalSmmStartupAllAPs ( **/ EFI_STATUS RegisterStartupProcedure ( - IN EFI_AP_PROCEDURE Procedure, - IN OUT VOID *ProcedureArguments OPTIONAL + IN EFI_AP_PROCEDURE Procedure, + IN OUT VOID *ProcedureArguments OPTIONAL ); /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 12dde85cf1..1f7cc15727 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -17,19 +17,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PREVIOUS_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \ ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) - (Size))) -EFI_MEMORY_DESCRIPTOR *mUefiMemoryMap; -UINTN mUefiMemoryMapSize; -UINTN mUefiDescriptorSize; +EFI_MEMORY_DESCRIPTOR *mUefiMemoryMap; +UINTN mUefiMemoryMapSize; +UINTN mUefiDescriptorSize; -EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mGcdMemSpace = NULL; -UINTN mGcdMemNumberOfDesc = 0; +EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mGcdMemSpace = NULL; +UINTN mGcdMemNumberOfDesc = 0; EFI_MEMORY_ATTRIBUTES_TABLE *mUefiMemoryAttributesTable = NULL; -PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { - {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, - {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, - {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, +PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { + { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 }, + { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 }, + { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, }; UINTN mInternalCr3; @@ -43,7 +43,7 @@ UINTN mInternalCr3; **/ VOID SetPageTableBase ( - IN UINTN Cr3 + IN UINTN Cr3 ) { mInternalCr3 = Cr3; @@ -62,11 +62,13 @@ PageAttributeToLength ( ) { UINTN Index; - for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) { + + for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) { if (PageAttribute == mPageAttributeTable[Index].Attribute) { return (UINTN)mPageAttributeTable[Index].Length; } } + return 0; } @@ -83,11 +85,13 @@ PageAttributeToMask ( ) { UINTN Index; - for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) { + + for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) { if (PageAttribute == mPageAttributeTable[Index].Attribute) { return (UINTN)mPageAttributeTable[Index].AddressMask; } } + return 0; } @@ -101,22 +105,22 @@ PageAttributeToMask ( **/ VOID * GetPageTableEntry ( - IN PHYSICAL_ADDRESS Address, - OUT PAGE_ATTRIBUTE *PageAttribute + IN PHYSICAL_ADDRESS Address, + OUT PAGE_ATTRIBUTE *PageAttribute ) { - UINTN Index1; - UINTN Index2; - UINTN Index3; - UINTN Index4; - UINTN Index5; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINT64 *L4PageTable; - UINT64 *L5PageTable; - UINTN PageTableBase; - BOOLEAN Enable5LevelPaging; + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINTN Index5; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + UINT64 *L5PageTable; + UINTN PageTableBase; + BOOLEAN Enable5LevelPaging; GetPageTable (&PageTableBase, &Enable5LevelPaging); @@ -126,7 +130,7 @@ GetPageTableEntry ( Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; - if (sizeof(UINTN) == sizeof(UINT64)) { + if (sizeof (UINTN) == sizeof (UINT64)) { if (Enable5LevelPaging) { L5PageTable = (UINT64 *)PageTableBase; if (L5PageTable[Index5] == 0) { @@ -138,6 +142,7 @@ GetPageTableEntry ( } else { L4PageTable = (UINT64 *)PageTableBase; } + if (L4PageTable[Index4] == 0) { *PageAttribute = PageNone; return NULL; @@ -147,10 +152,12 @@ GetPageTableEntry ( } else { L3PageTable = (UINT64 *)PageTableBase; } + if (L3PageTable[Index3] == 0) { *PageAttribute = PageNone; return NULL; } + if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { // 1G *PageAttribute = Page1G; @@ -162,6 +169,7 @@ GetPageTableEntry ( *PageAttribute = PageNone; return NULL; } + if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { // 2M *PageAttribute = Page2M; @@ -174,6 +182,7 @@ GetPageTableEntry ( *PageAttribute = PageNone; return NULL; } + *PageAttribute = Page4K; return &L1PageTable[Index1]; } @@ -187,20 +196,24 @@ GetPageTableEntry ( **/ UINT64 GetAttributesFromPageEntry ( - IN UINT64 *PageEntry + IN UINT64 *PageEntry ) { UINT64 Attributes; + Attributes = 0; if ((*PageEntry & IA32_PG_P) == 0) { Attributes |= EFI_MEMORY_RP; } + if ((*PageEntry & IA32_PG_RW) == 0) { Attributes |= EFI_MEMORY_RO; } + if ((*PageEntry & IA32_PG_NX) != 0) { Attributes |= EFI_MEMORY_XP; } + return Attributes; } @@ -214,17 +227,17 @@ GetAttributesFromPageEntry ( **/ VOID ConvertPageEntryAttribute ( - IN UINT64 *PageEntry, - IN UINT64 Attributes, - IN BOOLEAN IsSet, - OUT BOOLEAN *IsModified + IN UINT64 *PageEntry, + IN UINT64 Attributes, + IN BOOLEAN IsSet, + OUT BOOLEAN *IsModified ) { UINT64 CurrentPageEntry; UINT64 NewPageEntry; CurrentPageEntry = *PageEntry; - NewPageEntry = CurrentPageEntry; + NewPageEntry = CurrentPageEntry; if ((Attributes & EFI_MEMORY_RP) != 0) { if (IsSet) { NewPageEntry &= ~(UINT64)IA32_PG_P; @@ -232,6 +245,7 @@ ConvertPageEntryAttribute ( NewPageEntry |= IA32_PG_P; } } + if ((Attributes & EFI_MEMORY_RO) != 0) { if (IsSet) { NewPageEntry &= ~(UINT64)IA32_PG_RW; @@ -250,6 +264,7 @@ ConvertPageEntryAttribute ( NewPageEntry |= IA32_PG_RW; } } + if ((Attributes & EFI_MEMORY_XP) != 0) { if (mXdSupported) { if (IsSet) { @@ -259,6 +274,7 @@ ConvertPageEntryAttribute ( } } } + *PageEntry = NewPageEntry; if (CurrentPageEntry != NewPageEntry) { *IsModified = TRUE; @@ -281,13 +297,13 @@ ConvertPageEntryAttribute ( **/ PAGE_ATTRIBUTE NeedSplitPage ( - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute ) { - UINT64 PageEntryLength; + UINT64 PageEntryLength; PageEntryLength = PageAttributeToLength (PageAttribute); @@ -315,14 +331,14 @@ NeedSplitPage ( **/ RETURN_STATUS SplitPage ( - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute, - IN PAGE_ATTRIBUTE SplitAttribute + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute, + IN PAGE_ATTRIBUTE SplitAttribute ) { - UINT64 BaseAddress; - UINT64 *NewPageEntry; - UINTN Index; + UINT64 BaseAddress; + UINT64 *NewPageEntry; + UINTN Index; ASSERT (PageAttribute == Page2M || PageAttribute == Page1G); @@ -337,10 +353,12 @@ SplitPage ( if (NewPageEntry == NULL) { return RETURN_OUT_OF_RESOURCES; } + BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64; - for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { @@ -352,16 +370,18 @@ SplitPage ( // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table. // ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K); - if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) { + if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) { NewPageEntry = AllocatePageTableMemory (1); DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); if (NewPageEntry == NULL) { return RETURN_OUT_OF_RESOURCES; } + BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64; - for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { @@ -401,21 +421,21 @@ SplitPage ( RETURN_STATUS EFIAPI ConvertMemoryPageAttributes ( - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN BOOLEAN IsSet, - OUT BOOLEAN *IsSplitted OPTIONAL, - OUT BOOLEAN *IsModified OPTIONAL + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN BOOLEAN IsSet, + OUT BOOLEAN *IsSplitted OPTIONAL, + OUT BOOLEAN *IsModified OPTIONAL ) { - UINT64 *PageEntry; - PAGE_ATTRIBUTE PageAttribute; - UINTN PageEntryLength; - PAGE_ATTRIBUTE SplitAttribute; - RETURN_STATUS Status; - BOOLEAN IsEntryModified; - EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress; + UINT64 *PageEntry; + PAGE_ATTRIBUTE PageAttribute; + UINTN PageEntryLength; + PAGE_ATTRIBUTE SplitAttribute; + RETURN_STATUS Status; + BOOLEAN IsEntryModified; + EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress; ASSERT (Attributes != 0); ASSERT ((Attributes & ~EFI_MEMORY_ATTRIBUTE_MASK) == 0); @@ -431,18 +451,21 @@ ConvertMemoryPageAttributes ( if (BaseAddress > MaximumSupportMemAddress) { return RETURN_UNSUPPORTED; } + if (Length > MaximumSupportMemAddress) { return RETURN_UNSUPPORTED; } + if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) { return RETURN_UNSUPPORTED; } -// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); + // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); if (IsSplitted != NULL) { *IsSplitted = FALSE; } + if (IsModified != NULL) { *IsModified = FALSE; } @@ -455,8 +478,9 @@ ConvertMemoryPageAttributes ( if (PageEntry == NULL) { return RETURN_UNSUPPORTED; } + PageEntryLength = PageAttributeToLength (PageAttribute); - SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); + SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); if (SplitAttribute == PageNone) { ConvertPageEntryAttribute (PageEntry, Attributes, IsSet, &IsEntryModified); if (IsEntryModified) { @@ -464,22 +488,26 @@ ConvertMemoryPageAttributes ( *IsModified = TRUE; } } + // // Convert success, move to next // BaseAddress += PageEntryLength; - Length -= PageEntryLength; + Length -= PageEntryLength; } else { Status = SplitPage (PageEntry, PageAttribute, SplitAttribute); if (RETURN_ERROR (Status)) { return RETURN_UNSUPPORTED; } + if (IsSplitted != NULL) { *IsSplitted = TRUE; } + if (IsModified != NULL) { *IsModified = TRUE; } + // // Just split current page // Convert success in next around @@ -512,7 +540,7 @@ FlushTlbForAll ( VOID ) { - UINTN Index; + UINTN Index; FlushTlbOnCurrentProcessor (NULL); @@ -551,22 +579,22 @@ FlushTlbForAll ( EFI_STATUS EFIAPI SmmSetMemoryAttributesEx ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *IsSplitted OPTIONAL ) { EFI_STATUS Status; BOOLEAN IsModified; Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { if (IsModified) { // // Flush TLB as last step // - FlushTlbForAll(); + FlushTlbForAll (); } } @@ -599,22 +627,22 @@ SmmSetMemoryAttributesEx ( EFI_STATUS EFIAPI SmmClearMemoryAttributesEx ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *IsSplitted OPTIONAL ) { EFI_STATUS Status; BOOLEAN IsModified; Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { if (IsModified) { // // Flush TLB as last step // - FlushTlbForAll(); + FlushTlbForAll (); } } @@ -646,9 +674,9 @@ SmmClearMemoryAttributesEx ( EFI_STATUS EFIAPI SmmSetMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { return SmmSetMemoryAttributesEx (BaseAddress, Length, Attributes, NULL); @@ -679,9 +707,9 @@ SmmSetMemoryAttributes ( EFI_STATUS EFIAPI SmmClearMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { return SmmClearMemoryAttributesEx (BaseAddress, Length, Attributes, NULL); @@ -698,9 +726,9 @@ SmmClearMemoryAttributes ( **/ EFI_STATUS SetShadowStack ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length + IN UINTN Cr3, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length ) { EFI_STATUS Status; @@ -725,9 +753,9 @@ SetShadowStack ( **/ EFI_STATUS SetNotPresentPage ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length + IN UINTN Cr3, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length ) { EFI_STATUS Status; @@ -759,7 +787,7 @@ SmmGetSystemConfigurationTable ( OUT VOID **Table ) { - UINTN Index; + UINTN Index; ASSERT (TableGuid != NULL); ASSERT (Table != NULL); @@ -789,11 +817,11 @@ PatchSmmSaveStateMap ( UINTN TileSize; TileCodeSize = GetSmiHandlerSize (); - TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB); + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); - TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); - TileSize = TileDataSize + TileCodeSize - 1; - TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); + TileSize = TileDataSize + TileCodeSize - 1; + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n")); for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) { @@ -863,8 +891,8 @@ PatchGdtIdtMap ( VOID ) { - EFI_PHYSICAL_ADDRESS BaseAddress; - UINTN Size; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINTN Size; // // GDT @@ -872,7 +900,7 @@ PatchGdtIdtMap ( DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n")); BaseAddress = mGdtBuffer; - Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB); + Size = ALIGN_VALUE (mGdtBufferSize, SIZE_4KB); // // The range should have been set to RO // if it is allocated with EfiRuntimeServicesCode. @@ -889,7 +917,7 @@ PatchGdtIdtMap ( DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n")); BaseAddress = gcSmiIdtr.Base; - Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB); + Size = ALIGN_VALUE (gcSmiIdtr.Limit + 1, SIZE_4KB); // // The range should have been set to RO // if it is allocated with EfiRuntimeServicesCode. @@ -909,17 +937,17 @@ SetMemMapAttributes ( VOID ) { - EFI_MEMORY_DESCRIPTOR *MemoryMap; - EFI_MEMORY_DESCRIPTOR *MemoryMapStart; - UINTN MemoryMapEntryCount; - UINTN DescriptorSize; - UINTN Index; - EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + EFI_MEMORY_DESCRIPTOR *MemoryMapStart; + UINTN MemoryMapEntryCount; + UINTN DescriptorSize; + UINTN Index; + EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); if (MemoryAttributesTable == NULL) { DEBUG ((DEBUG_INFO, "MemoryAttributesTable - NULL\n")); - return ; + return; } DEBUG ((DEBUG_INFO, "MemoryAttributesTable:\n")); @@ -928,9 +956,9 @@ SetMemMapAttributes ( DEBUG ((DEBUG_INFO, " DescriptorSize - 0x%08x\n", MemoryAttributesTable->DescriptorSize)); MemoryMapEntryCount = MemoryAttributesTable->NumberOfEntries; - DescriptorSize = MemoryAttributesTable->DescriptorSize; - MemoryMapStart = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1); - MemoryMap = MemoryMapStart; + DescriptorSize = MemoryAttributesTable->DescriptorSize; + MemoryMapStart = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1); + MemoryMap = MemoryMapStart; for (Index = 0; Index < MemoryMapEntryCount; Index++) { DEBUG ((DEBUG_INFO, "Entry (0x%x)\n", MemoryMap)); DEBUG ((DEBUG_INFO, " Type - 0x%x\n", MemoryMap->Type)); @@ -938,42 +966,43 @@ SetMemMapAttributes ( DEBUG ((DEBUG_INFO, " VirtualStart - 0x%016lx\n", MemoryMap->VirtualStart)); DEBUG ((DEBUG_INFO, " NumberOfPages - 0x%016lx\n", MemoryMap->NumberOfPages)); DEBUG ((DEBUG_INFO, " Attribute - 0x%016lx\n", MemoryMap->Attribute)); - MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize); + MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize); } MemoryMap = MemoryMapStart; for (Index = 0; Index < MemoryMapEntryCount; Index++) { DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", MemoryMap->PhysicalStart, MemoryMap->NumberOfPages)); switch (MemoryMap->Type) { - case EfiRuntimeServicesCode: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_RO - ); - break; - case EfiRuntimeServicesData: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_XP - ); - break; - default: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_XP - ); - break; + case EfiRuntimeServicesCode: + SmmSetMemoryAttributes ( + MemoryMap->PhysicalStart, + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), + EFI_MEMORY_RO + ); + break; + case EfiRuntimeServicesData: + SmmSetMemoryAttributes ( + MemoryMap->PhysicalStart, + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), + EFI_MEMORY_XP + ); + break; + default: + SmmSetMemoryAttributes ( + MemoryMap->PhysicalStart, + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), + EFI_MEMORY_XP + ); + break; } - MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize); + + MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize); } PatchSmmSaveStateMap (); PatchGdtIdtMap (); - return ; + return; } /** @@ -992,27 +1021,27 @@ SortMemoryMap ( IN UINTN DescriptorSize ) { - EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; - EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry; - EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; - EFI_MEMORY_DESCRIPTOR TempMemoryMap; + EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; + EFI_MEMORY_DESCRIPTOR TempMemoryMap; - MemoryMapEntry = MemoryMap; + MemoryMapEntry = MemoryMap; NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); - MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + MemoryMapSize); + MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize); while (MemoryMapEntry < MemoryMapEnd) { while (NextMemoryMapEntry < MemoryMapEnd) { if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) { - CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); - CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); - CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof(EFI_MEMORY_DESCRIPTOR)); + CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof (EFI_MEMORY_DESCRIPTOR)); } NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize); } - MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); - NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); } } @@ -1034,16 +1063,16 @@ IsUefiPageNotPresent ( ) { switch (MemoryMap->Type) { - case EfiLoaderCode: - case EfiLoaderData: - case EfiBootServicesCode: - case EfiBootServicesData: - case EfiConventionalMemory: - case EfiUnusableMemory: - case EfiACPIReclaimMemory: - return TRUE; - default: - return FALSE; + case EfiLoaderCode: + case EfiLoaderData: + case EfiBootServicesCode: + case EfiBootServicesData: + case EfiConventionalMemory: + case EfiUnusableMemory: + case EfiACPIReclaimMemory: + return TRUE; + default: + return FALSE; } } @@ -1069,24 +1098,25 @@ MergeMemoryMapForNotPresentEntry ( IN UINTN DescriptorSize ) { - EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; - EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; - UINT64 MemoryBlockLength; - EFI_MEMORY_DESCRIPTOR *NewMemoryMapEntry; - EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; + UINT64 MemoryBlockLength; + EFI_MEMORY_DESCRIPTOR *NewMemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry; - MemoryMapEntry = MemoryMap; + MemoryMapEntry = MemoryMap; NewMemoryMapEntry = MemoryMap; - MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + *MemoryMapSize); + MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + *MemoryMapSize); while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) { - CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); + CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); do { - MemoryBlockLength = (UINT64) (EFI_PAGES_TO_SIZE((UINTN)MemoryMapEntry->NumberOfPages)); + MemoryBlockLength = (UINT64)(EFI_PAGES_TO_SIZE ((UINTN)MemoryMapEntry->NumberOfPages)); if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) && - IsUefiPageNotPresent(MemoryMapEntry) && IsUefiPageNotPresent(NextMemoryMapEntry) && - ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) { + IsUefiPageNotPresent (MemoryMapEntry) && IsUefiPageNotPresent (NextMemoryMapEntry) && + ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) + { MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages; if (NewMemoryMapEntry != MemoryMapEntry) { NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages; @@ -1100,13 +1130,13 @@ MergeMemoryMapForNotPresentEntry ( } } while (TRUE); - MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); NewMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NewMemoryMapEntry, DescriptorSize); } *MemoryMapSize = (UINTN)NewMemoryMapEntry - (UINTN)MemoryMap; - return ; + return; } /** @@ -1124,15 +1154,16 @@ GetGcdMemoryMap ( Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap); if (EFI_ERROR (Status)) { - return ; + return; } mGcdMemNumberOfDesc = 0; for (Index = 0; Index < NumberOfDescriptors; Index++) { - if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved && - (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == - (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED) - ) { + if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) && + ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == + (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)) + ) + { mGcdMemNumberOfDesc++; } } @@ -1142,19 +1173,20 @@ GetGcdMemoryMap ( if (mGcdMemSpace == NULL) { mGcdMemNumberOfDesc = 0; gBS->FreePool (MemSpaceMap); - return ; + return; } mGcdMemNumberOfDesc = 0; for (Index = 0; Index < NumberOfDescriptors; Index++) { - if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved && - (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == - (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED) - ) { + if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) && + ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == + (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)) + ) + { CopyMem ( &mGcdMemSpace[mGcdMemNumberOfDesc], &MemSpaceMap[Index], - sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR) + sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR) ); mGcdMemNumberOfDesc++; } @@ -1177,7 +1209,7 @@ GetUefiMemoryAttributesTable ( Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) { - MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; + MemoryAttributesTableSize = sizeof (EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; mUefiMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable); ASSERT (mUefiMemoryAttributesTable != NULL); } @@ -1191,30 +1223,30 @@ GetUefiMemoryMap ( VOID ) { - EFI_STATUS Status; - UINTN MapKey; - UINT32 DescriptorVersion; - EFI_MEMORY_DESCRIPTOR *MemoryMap; - UINTN UefiMemoryMapSize; + EFI_STATUS Status; + UINTN MapKey; + UINT32 DescriptorVersion; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN UefiMemoryMapSize; DEBUG ((DEBUG_INFO, "GetUefiMemoryMap\n")); UefiMemoryMapSize = 0; - MemoryMap = NULL; - Status = gBS->GetMemoryMap ( - &UefiMemoryMapSize, - MemoryMap, - &MapKey, - &mUefiDescriptorSize, - &DescriptorVersion - ); + MemoryMap = NULL; + Status = gBS->GetMemoryMap ( + &UefiMemoryMapSize, + MemoryMap, + &MapKey, + &mUefiDescriptorSize, + &DescriptorVersion + ); ASSERT (Status == EFI_BUFFER_TOO_SMALL); do { Status = gBS->AllocatePool (EfiBootServicesData, UefiMemoryMapSize, (VOID **)&MemoryMap); ASSERT (MemoryMap != NULL); if (MemoryMap == NULL) { - return ; + return; } Status = gBS->GetMemoryMap ( @@ -1231,14 +1263,14 @@ GetUefiMemoryMap ( } while (Status == EFI_BUFFER_TOO_SMALL); if (MemoryMap == NULL) { - return ; + return; } SortMemoryMap (MemoryMap, UefiMemoryMapSize, mUefiDescriptorSize); MergeMemoryMapForNotPresentEntry (MemoryMap, &UefiMemoryMapSize, mUefiDescriptorSize); mUefiMemoryMapSize = UefiMemoryMapSize; - mUefiMemoryMap = AllocateCopyPool (UefiMemoryMapSize, MemoryMap); + mUefiMemoryMap = AllocateCopyPool (UefiMemoryMapSize, MemoryMap); ASSERT (mUefiMemoryMap != NULL); gBS->FreePool (MemoryMap); @@ -1266,35 +1298,37 @@ SetUefiMemMapAttributes ( VOID ) { - EFI_STATUS Status; - EFI_MEMORY_DESCRIPTOR *MemoryMap; - UINTN MemoryMapEntryCount; - UINTN Index; - EFI_MEMORY_DESCRIPTOR *Entry; + EFI_STATUS Status; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN MemoryMapEntryCount; + UINTN Index; + EFI_MEMORY_DESCRIPTOR *Entry; DEBUG ((DEBUG_INFO, "SetUefiMemMapAttributes\n")); if (mUefiMemoryMap != NULL) { MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize; - MemoryMap = mUefiMemoryMap; + MemoryMap = mUefiMemoryMap; for (Index = 0; Index < MemoryMapEntryCount; Index++) { - if (IsUefiPageNotPresent(MemoryMap)) { + if (IsUefiPageNotPresent (MemoryMap)) { Status = SmmSetMemoryAttributes ( MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), EFI_MEMORY_RP ); DEBUG (( DEBUG_INFO, "UefiMemory protection: 0x%lx - 0x%lx %r\n", MemoryMap->PhysicalStart, - MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), + MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), Status )); } - MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize); + + MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize); } } + // // Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress(). // @@ -1318,6 +1352,7 @@ SetUefiMemMapAttributes ( )); } } + // // Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress(). // @@ -1328,25 +1363,27 @@ SetUefiMemMapAttributes ( if (mUefiMemoryAttributesTable != NULL) { Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1); for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) { - if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) { + if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) { if ((Entry->Attribute & EFI_MEMORY_RO) != 0) { Status = SmmSetMemoryAttributes ( Entry->PhysicalStart, - EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages), + EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages), EFI_MEMORY_RP ); DEBUG (( DEBUG_INFO, "UefiMemoryAttribute protection: 0x%lx - 0x%lx %r\n", Entry->PhysicalStart, - Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages), + Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages), Status )); } } + Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize); } } + // // Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress(). // @@ -1365,29 +1402,32 @@ IsSmmCommBufferForbiddenAddress ( IN UINT64 Address ) { - EFI_MEMORY_DESCRIPTOR *MemoryMap; - UINTN MemoryMapEntryCount; - UINTN Index; - EFI_MEMORY_DESCRIPTOR *Entry; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN MemoryMapEntryCount; + UINTN Index; + EFI_MEMORY_DESCRIPTOR *Entry; if (mUefiMemoryMap != NULL) { - MemoryMap = mUefiMemoryMap; + MemoryMap = mUefiMemoryMap; MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize; for (Index = 0; Index < MemoryMapEntryCount; Index++) { if (IsUefiPageNotPresent (MemoryMap)) { if ((Address >= MemoryMap->PhysicalStart) && - (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages)) ) { + (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages))) + { return TRUE; } } - MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize); + + MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize); } } if (mGcdMemSpace != NULL) { for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) { if ((Address >= mGcdMemSpace[Index].BaseAddress) && - (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length) ) { + (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length)) + { return TRUE; } } @@ -1396,17 +1436,20 @@ IsSmmCommBufferForbiddenAddress ( if (mUefiMemoryAttributesTable != NULL) { Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1); for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) { - if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) { + if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) { if ((Entry->Attribute & EFI_MEMORY_RO) != 0) { if ((Address >= Entry->PhysicalStart) && - (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) { + (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) + { return TRUE; } + Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize); } } } } + return FALSE; } @@ -1436,10 +1479,10 @@ IsSmmCommBufferForbiddenAddress ( EFI_STATUS EFIAPI EdkiiSmmSetMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { return SmmSetMemoryAttributes (BaseAddress, Length, Attributes); @@ -1471,10 +1514,10 @@ EdkiiSmmSetMemoryAttributes ( EFI_STATUS EFIAPI EdkiiSmmClearMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ) { return SmmClearMemoryAttributes (BaseAddress, Length, Attributes); @@ -1504,10 +1547,10 @@ EdkiiSmmClearMemoryAttributes ( EFI_STATUS EFIAPI EdkiiSmmGetMemoryAttributes ( - IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - OUT UINT64 *Attributes + IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + OUT UINT64 *Attributes ) { EFI_PHYSICAL_ADDRESS Address; @@ -1516,17 +1559,16 @@ EdkiiSmmGetMemoryAttributes ( PAGE_ATTRIBUTE PageAttr; INT64 Size; - if (Length < SIZE_4KB || Attributes == NULL) { + if ((Length < SIZE_4KB) || (Attributes == NULL)) { return EFI_INVALID_PARAMETER; } - Size = (INT64)Length; + Size = (INT64)Length; MemAttr = (UINT64)-1; do { - PageEntry = GetPageTableEntry (BaseAddress, &PageAttr); - if (PageEntry == NULL || PageAttr == PageNone) { + if ((PageEntry == NULL) || (PageAttr == PageNone)) { return EFI_UNSUPPORTED; } @@ -1535,35 +1577,34 @@ EdkiiSmmGetMemoryAttributes ( // share the same attribute. Return EFI_NO_MAPPING if not. // *Attributes = GetAttributesFromPageEntry (PageEntry); - if (MemAttr != (UINT64)-1 && *Attributes != MemAttr) { + if ((MemAttr != (UINT64)-1) && (*Attributes != MemAttr)) { return EFI_NO_MAPPING; } switch (PageAttr) { - case Page4K: - Address = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64; - Size -= (SIZE_4KB - (BaseAddress - Address)); - BaseAddress += (SIZE_4KB - (BaseAddress - Address)); - break; - - case Page2M: - Address = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64; - Size -= SIZE_2MB - (BaseAddress - Address); - BaseAddress += SIZE_2MB - (BaseAddress - Address); - break; - - case Page1G: - Address = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64; - Size -= SIZE_1GB - (BaseAddress - Address); - BaseAddress += SIZE_1GB - (BaseAddress - Address); - break; + case Page4K: + Address = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64; + Size -= (SIZE_4KB - (BaseAddress - Address)); + BaseAddress += (SIZE_4KB - (BaseAddress - Address)); + break; - default: - return EFI_UNSUPPORTED; + case Page2M: + Address = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64; + Size -= SIZE_2MB - (BaseAddress - Address); + BaseAddress += SIZE_2MB - (BaseAddress - Address); + break; + + case Page1G: + Address = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64; + Size -= SIZE_1GB - (BaseAddress - Address); + BaseAddress += SIZE_1GB - (BaseAddress - Address); + break; + + default: + return EFI_UNSUPPORTED; } MemAttr = *Attributes; - } while (Size > 0); return EFI_SUCCESS; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c index 9b2b191e03..6cc5f016ca 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent /// /// SMM MP Protocol instance /// -EFI_MM_MP_PROTOCOL mSmmMp = { +EFI_MM_MP_PROTOCOL mSmmMp = { EFI_MM_MP_PROTOCOL_REVISION, 0, SmmMpGetNumberOfProcessors, @@ -37,8 +37,8 @@ EFI_MM_MP_PROTOCOL mSmmMp = { EFI_STATUS EFIAPI SmmMpGetNumberOfProcessors ( - IN CONST EFI_MM_MP_PROTOCOL *This, - OUT UINTN *NumberOfProcessors + IN CONST EFI_MM_MP_PROTOCOL *This, + OUT UINTN *NumberOfProcessors ) { if (NumberOfProcessors == NULL) { @@ -114,23 +114,23 @@ SmmMpGetNumberOfProcessors ( EFI_STATUS EFIAPI SmmMpDispatchProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN CpuNumber, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN CpuNumber, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ) { return InternalSmmStartupThisAp ( - Procedure, - CpuNumber, - ProcedureArguments, - Token, - TimeoutInMicroseconds, - CPUStatus - ); + Procedure, + CpuNumber, + ProcedureArguments, + Token, + TimeoutInMicroseconds, + CPUStatus + ); } /** @@ -202,21 +202,21 @@ SmmMpDispatchProcedure ( EFI_STATUS EFIAPI SmmMpBroadcastProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ) { - return InternalSmmStartupAllAPs( - Procedure, - TimeoutInMicroseconds, - ProcedureArguments, - Token, - CPUStatus - ); + return InternalSmmStartupAllAPs ( + Procedure, + TimeoutInMicroseconds, + ProcedureArguments, + Token, + CPUStatus + ); } /** @@ -286,8 +286,8 @@ SmmMpSetStartupProcedure ( EFI_STATUS EFIAPI SmmMpCheckForProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN MM_COMPLETION Token + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token ) { if (Token == NULL) { @@ -329,11 +329,11 @@ SmmMpCheckForProcedure ( EFI_STATUS EFIAPI SmmMpWaitForProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN MM_COMPLETION Token + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token ) { - EFI_STATUS Status; + EFI_STATUS Status; do { Status = SmmMpCheckForProcedure (This, Token); @@ -341,4 +341,3 @@ SmmMpWaitForProcedure ( return Status; } - diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h index b95ed8c6f8..e2dac6c7d4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h @@ -27,11 +27,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_STATUS EFIAPI SmmMpGetNumberOfProcessors ( - IN CONST EFI_MM_MP_PROTOCOL *This, - OUT UINTN *NumberOfProcessors + IN CONST EFI_MM_MP_PROTOCOL *This, + OUT UINTN *NumberOfProcessors ); - /** This service allows the caller to invoke a procedure one of the application processors (AP). This function uses an optional token parameter to support blocking and non-blocking modes. If the token @@ -96,13 +95,13 @@ SmmMpGetNumberOfProcessors ( EFI_STATUS EFIAPI SmmMpDispatchProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN CpuNumber, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN CpuNumber, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ); /** @@ -174,15 +173,14 @@ SmmMpDispatchProcedure ( EFI_STATUS EFIAPI SmmMpBroadcastProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN EFI_AP_PROCEDURE2 Procedure, - IN UINTN TimeoutInMicroseconds, - IN OUT VOID *ProcedureArguments OPTIONAL, - IN OUT MM_COMPLETION *Token, - IN OUT EFI_STATUS *CPUStatus + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus ); - /** This service allows the caller to set a startup procedure that will be executed when an AP powers up from a state where core configuration and context is lost. The procedure is execution has the @@ -246,8 +244,8 @@ SmmMpSetStartupProcedure ( EFI_STATUS EFIAPI SmmMpCheckForProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN MM_COMPLETION Token + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token ); /** @@ -278,8 +276,8 @@ SmmMpCheckForProcedure ( EFI_STATUS EFIAPI SmmMpWaitForProcedure ( - IN CONST EFI_MM_MP_PROTOCOL *This, - IN MM_COMPLETION Token + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token ); #endif diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index c3f9794b95..c1efda7126 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -11,80 +11,84 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" #include "SmmProfileInternal.h" -UINT32 mSmmProfileCr3; +UINT32 mSmmProfileCr3; -SMM_PROFILE_HEADER *mSmmProfileBase; -MSR_DS_AREA_STRUCT *mMsrDsAreaBase; +SMM_PROFILE_HEADER *mSmmProfileBase; +MSR_DS_AREA_STRUCT *mMsrDsAreaBase; // // The buffer to store SMM profile data. // -UINTN mSmmProfileSize; +UINTN mSmmProfileSize; // // The buffer to enable branch trace store. // -UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE; +UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE; // // The flag indicates if execute-disable is supported by processor. // -BOOLEAN mXdSupported = TRUE; +BOOLEAN mXdSupported = TRUE; // // The flag indicates if execute-disable is enabled on processor. // -BOOLEAN mXdEnabled = FALSE; +BOOLEAN mXdEnabled = FALSE; // // The flag indicates if BTS is supported by processor. // -BOOLEAN mBtsSupported = TRUE; +BOOLEAN mBtsSupported = TRUE; // // The flag indicates if SMM profile starts to record data. // -BOOLEAN mSmmProfileStart = FALSE; +BOOLEAN mSmmProfileStart = FALSE; // // The flag indicates if #DB will be setup in #PF handler. // -BOOLEAN mSetupDebugTrap = FALSE; +BOOLEAN mSetupDebugTrap = FALSE; // // Record the page fault exception count for one instruction execution. // -UINTN *mPFEntryCount; +UINTN *mPFEntryCount; -UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; +UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT]; -MSR_DS_AREA_STRUCT **mMsrDsArea; -BRANCH_TRACE_RECORD **mMsrBTSRecord; -UINTN mBTSRecordNumber; -PEBS_RECORD **mMsrPEBSRecord; +MSR_DS_AREA_STRUCT **mMsrDsArea; +BRANCH_TRACE_RECORD **mMsrBTSRecord; +UINTN mBTSRecordNumber; +PEBS_RECORD **mMsrPEBSRecord; // // These memory ranges are always present, they does not generate the access type of page fault exception, // but they possibly generate instruction fetch type of page fault exception. // -MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL; -UINTN mProtectionMemRangeCount = 0; +MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL; +UINTN mProtectionMemRangeCount = 0; // // Some predefined memory ranges. // -MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = { +MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = { // // SMRAM range (to be fixed in runtime). // It is always present and instruction fetches are allowed. // - {{0x00000000, 0x00000000},TRUE,FALSE}, + { + { 0x00000000, 0x00000000 }, TRUE, FALSE + }, // // SMM profile data range( to be fixed in runtime). // It is always present and instruction fetches are not allowed. // - {{0x00000000, 0x00000000},TRUE,TRUE}, + { + { 0x00000000, 0x00000000 }, TRUE, TRUE + }, // // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime). @@ -105,13 +109,13 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = { // // These memory ranges are mapped by 4KB-page instead of 2MB-page. // -MEMORY_RANGE *mSplitMemRange = NULL; -UINTN mSplitMemRangeCount = 0; +MEMORY_RANGE *mSplitMemRange = NULL; +UINTN mSplitMemRangeCount = 0; // // SMI command port. // -UINT32 mSmiCommandPort; +UINT32 mSmiCommandPort; /** Disable branch trace store. @@ -146,8 +150,8 @@ GetCpuIndex ( VOID ) { - UINTN Index; - UINT32 ApicId; + UINTN Index; + UINT32 ApicId; ApicId = GetApicId (); @@ -156,6 +160,7 @@ GetCpuIndex ( return Index; } } + ASSERT (FALSE); return 0; } @@ -169,8 +174,8 @@ GetCpuIndex ( **/ UINT64 GetSourceFromDestinationOnBts ( - UINTN CpuIndex, - UINT64 DestinationIP + UINTN CpuIndex, + UINT64 DestinationIP ) { BRANCH_TRACE_RECORD *CurrentBTSRecord; @@ -186,8 +191,9 @@ GetSourceFromDestinationOnBts ( // Underflow // CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1); - CurrentBTSRecord --; + CurrentBTSRecord--; } + if (CurrentBTSRecord->LastBranchTo == DestinationIP) { // // Good! find 1st one, then find 2nd one. @@ -204,6 +210,7 @@ GetSourceFromDestinationOnBts ( return CurrentBTSRecord->LastBranchFrom; } } + CurrentBTSRecord--; } @@ -221,8 +228,8 @@ GetSourceFromDestinationOnBts ( VOID EFIAPI DebugExceptionHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { UINTN CpuIndex; @@ -230,9 +237,11 @@ DebugExceptionHandler ( if (!mSmmProfileStart && !HEAP_GUARD_NONSTOP_MODE && - !NULL_DETECTION_NONSTOP_MODE) { + !NULL_DETECTION_NONSTOP_MODE) + { return; } + CpuIndex = GetCpuIndex (); // @@ -268,7 +277,7 @@ DebugExceptionHandler ( **/ BOOLEAN IsInSmmRanges ( - IN EFI_PHYSICAL_ADDRESS Address + IN EFI_PHYSICAL_ADDRESS Address ) { UINTN Index; @@ -276,12 +285,15 @@ IsInSmmRanges ( if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { return TRUE; } + for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { - if (Address >= mSmmCpuSmramRanges[Index].CpuStart && - Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) { + if ((Address >= mSmmCpuSmramRanges[Index].CpuStart) && + (Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) + { return TRUE; } } + return FALSE; } @@ -294,8 +306,8 @@ IsInSmmRanges ( **/ BOOLEAN IsAddressValid ( - IN EFI_PHYSICAL_ADDRESS Address, - IN BOOLEAN *Nx + IN EFI_PHYSICAL_ADDRESS Address, + IN BOOLEAN *Nx ) { UINTN Index; @@ -310,14 +322,15 @@ IsAddressValid ( return mProtectionMemRange[Index].Present; } } + *Nx = TRUE; return FALSE; - } else { *Nx = TRUE; if (IsInSmmRanges (Address)) { *Nx = FALSE; } + return TRUE; } } @@ -330,7 +343,7 @@ IsAddressValid ( **/ BOOLEAN IsAddressSplit ( - IN EFI_PHYSICAL_ADDRESS Address + IN EFI_PHYSICAL_ADDRESS Address ) { UINTN Index; @@ -349,12 +362,13 @@ IsAddressSplit ( if ((mCpuHotPlugData.SmrrBase - Address) < BASE_2MB) { return TRUE; } - } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) { + } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) { if ((Address - (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) < BASE_2MB) { return TRUE; } } } + // // Return default // @@ -393,9 +407,9 @@ InitProtectedMemRange ( // Get MMIO ranges from GCD and add them into protected memory ranges. // gDS->GetMemorySpaceMap ( - &NumberOfDescriptors, - &MemorySpaceMap - ); + &NumberOfDescriptors, + &MemorySpaceMap + ); for (Index = 0; Index < NumberOfDescriptors; Index++) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) { NumberOfAddedDescriptors++; @@ -403,8 +417,8 @@ InitProtectedMemRange ( } if (NumberOfAddedDescriptors != 0) { - TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate); - mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize); + TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate); + mProtectionMemRange = (MEMORY_PROTECTION_RANGE *)AllocateZeroPool (TotalSize); ASSERT (mProtectionMemRange != NULL); mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE); @@ -416,8 +430,8 @@ InitProtectedMemRange ( // // Create split ranges which come from protected ranges. // - TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE); - mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize); + TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE); + mSplitMemRange = (MEMORY_RANGE *)AllocateZeroPool (TotalSize); ASSERT (mSplitMemRange != NULL); // @@ -425,13 +439,15 @@ InitProtectedMemRange ( // NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE); for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { - if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base && - mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) { + if ((mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base) && + (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top)) + { // // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz // break; } + mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart; mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize; mProtectionMemRange[NumberOfProtectRange].Present = TRUE; @@ -446,6 +462,7 @@ InitProtectedMemRange ( if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) { continue; } + mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress; mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length; mProtectionMemRange[NumberOfProtectRange].Present = TRUE; @@ -479,7 +496,8 @@ InitProtectedMemRange ( Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1); Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1); if ((Top2MBAlignedAddress > Base2MBAlignedAddress) && - ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) { + ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) + { // // There is an range which could be mapped by 2MB-page. // @@ -493,6 +511,7 @@ InitProtectedMemRange ( mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1); NumberOfSpliteRange++; } + if (Low4KBPageSize != 0) { // // Add not 2MB-aligned range to be mapped by 4KB-page. @@ -519,6 +538,7 @@ InitProtectedMemRange ( DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base)); DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top)); } + for (Index = 0; Index < mSplitMemRangeCount; Index++) { DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base)); DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top)); @@ -534,64 +554,65 @@ InitPaging ( VOID ) { - UINT64 Pml5Entry; - UINT64 Pml4Entry; - UINT64 *Pml5; - UINT64 *Pml4; - UINT64 *Pdpt; - UINT64 *Pd; - UINT64 *Pt; - UINTN Address; - UINTN Pml5Index; - UINTN Pml4Index; - UINTN PdptIndex; - UINTN PdIndex; - UINTN PtIndex; - UINTN NumberOfPdptEntries; - UINTN NumberOfPml4Entries; - UINTN NumberOfPml5Entries; - UINTN SizeOfMemorySpace; - BOOLEAN Nx; - IA32_CR4 Cr4; - BOOLEAN Enable5LevelPaging; - - Cr4.UintN = AsmReadCr4 (); - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); + UINT64 Pml5Entry; + UINT64 Pml4Entry; + UINT64 *Pml5; + UINT64 *Pml4; + UINT64 *Pdpt; + UINT64 *Pd; + UINT64 *Pt; + UINTN Address; + UINTN Pml5Index; + UINTN Pml4Index; + UINTN PdptIndex; + UINTN PdIndex; + UINTN PtIndex; + UINTN NumberOfPdptEntries; + UINTN NumberOfPml4Entries; + UINTN NumberOfPml5Entries; + UINTN SizeOfMemorySpace; + BOOLEAN Nx; + IA32_CR4 Cr4; + BOOLEAN Enable5LevelPaging; + + Cr4.UintN = AsmReadCr4 (); + Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); if (sizeof (UINTN) == sizeof (UINT64)) { if (!Enable5LevelPaging) { - Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P; - Pml5 = &Pml5Entry; + Pml5Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P; + Pml5 = &Pml5Entry; } else { - Pml5 = (UINT64*) (UINTN) mSmmProfileCr3; + Pml5 = (UINT64 *)(UINTN)mSmmProfileCr3; } + SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1; // // Calculate the table entries of PML4E and PDPTE. // NumberOfPml5Entries = 1; if (SizeOfMemorySpace > 48) { - NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48); - SizeOfMemorySpace = 48; + NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48); + SizeOfMemorySpace = 48; } NumberOfPml4Entries = 1; if (SizeOfMemorySpace > 39) { - NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39); - SizeOfMemorySpace = 39; + NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39); + SizeOfMemorySpace = 39; } NumberOfPdptEntries = 1; ASSERT (SizeOfMemorySpace > 30); - NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30); + NumberOfPdptEntries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 30); } else { - Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P; - Pml4 = &Pml4Entry; - Pml5Entry = (UINTN) Pml4 | IA32_PG_P; - Pml5 = &Pml5Entry; - NumberOfPml5Entries = 1; - NumberOfPml4Entries = 1; - NumberOfPdptEntries = 4; + Pml4Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P; + Pml4 = &Pml4Entry; + Pml5Entry = (UINTN)Pml4 | IA32_PG_P; + Pml5 = &Pml5Entry; + NumberOfPml5Entries = 1; + NumberOfPml4Entries = 1; + NumberOfPdptEntries = 4; } // @@ -604,7 +625,8 @@ InitPaging ( // continue; } - Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); + + Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { if ((Pml4[Pml4Index] & IA32_PG_P) == 0) { // @@ -612,6 +634,7 @@ InitPaging ( // continue; } + Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) { if ((*Pdpt & IA32_PG_P) == 0) { @@ -620,16 +643,19 @@ InitPaging ( // continue; } + if ((*Pdpt & IA32_PG_PS) != 0) { // // This is 1G entry, skip it // continue; } + Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); if (Pd == 0) { continue; } + for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) { if ((*Pd & IA32_PG_P) == 0) { // @@ -637,13 +663,14 @@ InitPaging ( // continue; } - Address = (UINTN) LShiftU64 ( - LShiftU64 ( - LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, - 9 - ) + PdIndex, - 21 - ); + + Address = (UINTN)LShiftU64 ( + LShiftU64 ( + LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, + 9 + ) + PdIndex, + 21 + ); // // If it is 2M page, check IsAddressSplit() @@ -658,9 +685,10 @@ InitPaging ( ASSERT (Pt != NULL); // Split it - for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) { + for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++) { Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS); } // end for PT + *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } // end if IsAddressSplit } // end for PD @@ -679,7 +707,8 @@ InitPaging ( // continue; } - Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); + + Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { if ((Pml4[Pml4Index] & IA32_PG_P) == 0) { // @@ -687,6 +716,7 @@ InitPaging ( // continue; } + Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) { if ((*Pdpt & IA32_PG_P) == 0) { @@ -695,6 +725,7 @@ InitPaging ( // continue; } + if ((*Pdpt & IA32_PG_PS) != 0) { // // This is 1G entry, set NX bit and skip it @@ -702,12 +733,15 @@ InitPaging ( if (mXdSupported) { *Pdpt = *Pdpt | IA32_PG_NX; } + continue; } + Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); if (Pd == 0) { continue; } + for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) { if ((*Pd & IA32_PG_P) == 0) { // @@ -715,13 +749,14 @@ InitPaging ( // continue; } - Address = (UINTN) LShiftU64 ( - LShiftU64 ( - LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, - 9 - ) + PdIndex, - 21 - ); + + Address = (UINTN)LShiftU64 ( + LShiftU64 ( + LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, + 9 + ) + PdIndex, + 21 + ); if ((*Pd & IA32_PG_PS) != 0) { // 2MB page @@ -732,6 +767,7 @@ InitPaging ( // *Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); } + if (Nx && mXdSupported) { *Pd = *Pd | IA32_PG_NX; } @@ -741,13 +777,16 @@ InitPaging ( if (Pt == 0) { continue; } - for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) { + + for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++, Pt++) { if (!IsAddressValid (Address, &Nx)) { *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); } + if (Nx && mXdSupported) { *Pt = *Pt | IA32_PG_NX; } + Address += SIZE_4KB; } // end for PT } // end if PS @@ -766,7 +805,7 @@ InitPaging ( // mXdEnabled = TRUE; - return ; + return; } /** @@ -778,11 +817,11 @@ GetSmiCommandPort ( VOID ) { - EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt; + EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt; - Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) EfiLocateFirstAcpiTable ( - EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE - ); + Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)EfiLocateFirstAcpiTable ( + EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE + ); ASSERT (Fadt != NULL); mSmiCommandPort = Fadt->SmiCmd; @@ -830,7 +869,7 @@ InitSmmProfileCallBack ( SMM_PROFILE_NAME, &gEfiCallerIdGuid, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - sizeof(mSmmProfileBase), + sizeof (mSmmProfileBase), &mSmmProfileBase ); @@ -856,20 +895,22 @@ InitSmmProfileInternal ( VOID ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Base; - VOID *Registration; - UINTN Index; - UINTN MsrDsAreaSizePerCpu; - UINTN TotalSize; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Base; + VOID *Registration; + UINTN Index; + UINTN MsrDsAreaSizePerCpu; + UINTN TotalSize; mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus); ASSERT (mPFEntryCount != NULL); - mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool ( - sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus); + mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool ( + sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus + ); ASSERT (mLastPFEntryValue != NULL); mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool ( - sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus); + sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus + ); ASSERT (mLastPFEntryPointer != NULL); // @@ -885,7 +926,7 @@ InitSmmProfileInternal ( TotalSize = mSmmProfileSize; } - Base = 0xFFFFFFFF; + Base = 0xFFFFFFFF; Status = gBS->AllocatePages ( AllocateMaxAddress, EfiReservedMemoryType, @@ -900,8 +941,8 @@ InitSmmProfileInternal ( // Initialize SMM profile data header. // mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER); - mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY)); - mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY)); + mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof (SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY)); + mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof (SMM_PROFILE_ENTRY)); mSmmProfileBase->CurDataEntries = 0; mSmmProfileBase->CurDataSize = 0; mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase; @@ -917,22 +958,22 @@ InitSmmProfileInternal ( mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * mMaxNumberOfCpus); ASSERT (mMsrPEBSRecord != NULL); - mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize); + mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize); MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus; - mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD); + mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof (MSR_DS_AREA_STRUCT)) / sizeof (BRANCH_TRACE_RECORD); for (Index = 0; Index < mMaxNumberOfCpus; Index++) { mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index); - mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT)); - mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER); + mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof (MSR_DS_AREA_STRUCT)); + mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER); - mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index]; - mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase; - mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1; - mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1; + mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index]; + mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase; + mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof (BRANCH_TRACE_RECORD) + 1; + mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1; mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index]; mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase; - mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1; + mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof (PEBS_RECORD) + 1; mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1; } } @@ -967,7 +1008,7 @@ InitSmmProfileInternal ( ); ASSERT_EFI_ERROR (Status); - return ; + return; } /** @@ -1056,12 +1097,13 @@ ActivateSingleStepDB ( VOID ) { - UINTN Dr6; + UINTN Dr6; Dr6 = AsmReadDr6 (); if ((Dr6 & DR6_SINGLE_STEP) != 0) { return; } + Dr6 |= DR6_SINGLE_STEP; AsmWriteDr6 (Dr6); } @@ -1079,8 +1121,9 @@ ActivateLBR ( DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL); if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) { - return ; + return; } + DebugCtl |= MSR_DEBUG_CTL_LBR; AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl); } @@ -1093,14 +1136,14 @@ ActivateLBR ( **/ VOID ActivateBTS ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { UINT64 DebugCtl; DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL); if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) { - return ; + return; } AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]); @@ -1131,7 +1174,7 @@ SmmProfileRecordSmiNum ( **/ VOID ActivateSmmProfile ( - IN UINTN CpuIndex + IN UINTN CpuIndex ) { // @@ -1173,7 +1216,8 @@ InitSmmProfile ( // if (!FeaturePcdGet (PcdCpuSmmProfileEnable) && !HEAP_GUARD_NONSTOP_MODE && - !NULL_DETECTION_NONSTOP_MODE) { + !NULL_DETECTION_NONSTOP_MODE) + { return; } @@ -1206,19 +1250,19 @@ InitSmmProfile ( **/ VOID RestorePageTableBelow4G ( - UINT64 *PageTable, - UINT64 PFAddress, - UINTN CpuIndex, - UINTN ErrorCode + UINT64 *PageTable, + UINT64 PFAddress, + UINTN CpuIndex, + UINTN ErrorCode ) { - UINTN PTIndex; - UINTN PFIndex; - IA32_CR4 Cr4; - BOOLEAN Enable5LevelPaging; + UINTN PTIndex; + UINTN PFIndex; + IA32_CR4 Cr4; + BOOLEAN Enable5LevelPaging; - Cr4.UintN = AsmReadCr4 (); - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); + Cr4.UintN = AsmReadCr4 (); + Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); // // PML5 @@ -1226,16 +1270,16 @@ RestorePageTableBelow4G ( if (Enable5LevelPaging) { PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56); ASSERT (PageTable[PTIndex] != 0); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); } // // PML4 // - if (sizeof(UINT64) == sizeof(UINTN)) { + if (sizeof (UINT64) == sizeof (UINTN)) { PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47); ASSERT (PageTable[PTIndex] != 0); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); } // @@ -1243,7 +1287,7 @@ RestorePageTableBelow4G ( // PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38); ASSERT (PageTable[PTIndex] != 0); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); // // PD @@ -1261,7 +1305,7 @@ RestorePageTableBelow4G ( // ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT); if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) { - PFIndex = mPFEntryCount[CpuIndex]; + PFIndex = mPFEntryCount[CpuIndex]; mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex]; mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex]; mPFEntryCount[CpuIndex]++; @@ -1270,7 +1314,7 @@ RestorePageTableBelow4G ( // // Set new entry // - PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)); + PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)); PageTable[PTIndex] |= (UINT64)IA32_PG_PS; PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS; if ((ErrorCode & IA32_PF_EC_ID) != 0) { @@ -1281,7 +1325,7 @@ RestorePageTableBelow4G ( // Small page // ASSERT (PageTable[PTIndex] != 0); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); // // 4K PTE @@ -1295,7 +1339,7 @@ RestorePageTableBelow4G ( // ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT); if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) { - PFIndex = mPFEntryCount[CpuIndex]; + PFIndex = mPFEntryCount[CpuIndex]; mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex]; mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex]; mPFEntryCount[CpuIndex]++; @@ -1304,7 +1348,7 @@ RestorePageTableBelow4G ( // // Set new entry // - PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1)); + PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1)); PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS; if ((ErrorCode & IA32_PF_EC_ID) != 0) { PageTable[PTIndex] &= ~IA32_PG_NX; @@ -1320,18 +1364,18 @@ RestorePageTableBelow4G ( **/ VOID GuardPagePFHandler ( - UINTN ErrorCode + UINTN ErrorCode ) { - UINT64 *PageTable; - UINT64 PFAddress; - UINT64 RestoreAddress; - UINTN RestorePageNumber; - UINTN CpuIndex; + UINT64 *PageTable; + UINT64 PFAddress; + UINT64 RestoreAddress; + UINTN RestorePageNumber; + UINTN CpuIndex; - PageTable = (UINT64 *)AsmReadCr3 (); - PFAddress = AsmReadCr2 (); - CpuIndex = GetCpuIndex (); + PageTable = (UINT64 *)AsmReadCr3 (); + PFAddress = AsmReadCr2 (); + CpuIndex = GetCpuIndex (); // // Memory operation cross pages, like "rep mov" instruction, will cause @@ -1339,7 +1383,7 @@ GuardPagePFHandler ( // that current page and the page followed are both in PRESENT state. // RestorePageNumber = 2; - RestoreAddress = PFAddress; + RestoreAddress = PFAddress; while (RestorePageNumber > 0) { RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode); RestoreAddress += EFI_PAGE_SIZE; @@ -1361,25 +1405,25 @@ GuardPagePFHandler ( **/ VOID SmmProfilePFHandler ( - UINTN Rip, - UINTN ErrorCode + UINTN Rip, + UINTN ErrorCode ) { - UINT64 *PageTable; - UINT64 PFAddress; - UINT64 RestoreAddress; - UINTN RestorePageNumber; - UINTN CpuIndex; - UINTN Index; - UINT64 InstructionAddress; - UINTN MaxEntryNumber; - UINTN CurrentEntryNumber; - BOOLEAN IsValidPFAddress; - SMM_PROFILE_ENTRY *SmmProfileEntry; - UINT64 SmiCommand; - EFI_STATUS Status; - UINT8 SoftSmiValue; - EFI_SMM_SAVE_STATE_IO_INFO IoInfo; + UINT64 *PageTable; + UINT64 PFAddress; + UINT64 RestoreAddress; + UINTN RestorePageNumber; + UINTN CpuIndex; + UINTN Index; + UINT64 InstructionAddress; + UINTN MaxEntryNumber; + UINTN CurrentEntryNumber; + BOOLEAN IsValidPFAddress; + SMM_PROFILE_ENTRY *SmmProfileEntry; + UINT64 SmiCommand; + EFI_STATUS Status; + UINT8 SoftSmiValue; + EFI_SMM_SAVE_STATE_IO_INFO IoInfo; if (!mSmmProfileStart) { // @@ -1393,10 +1437,10 @@ SmmProfilePFHandler ( DisableBTS (); } - IsValidPFAddress = FALSE; - PageTable = (UINT64 *)AsmReadCr3 (); - PFAddress = AsmReadCr2 (); - CpuIndex = GetCpuIndex (); + IsValidPFAddress = FALSE; + PageTable = (UINT64 *)AsmReadCr3 (); + PFAddress = AsmReadCr2 (); + CpuIndex = GetCpuIndex (); // // Memory operation cross pages, like "rep mov" instruction, will cause @@ -1404,20 +1448,21 @@ SmmProfilePFHandler ( // that current page and the page followed are both in PRESENT state. // RestorePageNumber = 2; - RestoreAddress = PFAddress; + RestoreAddress = PFAddress; while (RestorePageNumber > 0) { if (RestoreAddress <= 0xFFFFFFFF) { RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode); } else { RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress); } + RestoreAddress += EFI_PAGE_SIZE; RestorePageNumber--; } if (!IsValidPFAddress) { InstructionAddress = Rip; - if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) { + if (((ErrorCode & IA32_PF_EC_ID) != 0) && (mBtsSupported)) { // // If it is instruction fetch failure, get the correct IP from BTS. // @@ -1434,18 +1479,19 @@ SmmProfilePFHandler ( // // Indicate it is not software SMI // - SmiCommand = 0xFFFFFFFFFFFFFFFFULL; + SmiCommand = 0xFFFFFFFFFFFFFFFFULL; for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { - Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo); + Status = SmmReadSaveState (&mSmmCpu, sizeof (IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo); if (EFI_ERROR (Status)) { continue; } + if (IoInfo.IoPort == mSmiCommandPort) { // // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port. // SoftSmiValue = IoRead8 (mSmiCommandPort); - SmiCommand = (UINT64)SoftSmiValue; + SmiCommand = (UINT64)SoftSmiValue; break; } } @@ -1454,24 +1500,27 @@ SmmProfilePFHandler ( // // Check if there is already a same entry in profile data. // - for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) { + for (Index = 0; Index < (UINTN)mSmmProfileBase->CurDataEntries; Index++) { if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) && (SmmProfileEntry[Index].Address == PFAddress) && (SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) && (SmmProfileEntry[Index].Instruction == InstructionAddress) && - (SmmProfileEntry[Index].SmiCmd == SmiCommand)) { + (SmmProfileEntry[Index].SmiCmd == SmiCommand)) + { // // Same record exist, need not save again. // break; } } + if (Index == mSmmProfileBase->CurDataEntries) { - CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries; - MaxEntryNumber = (UINTN) mSmmProfileBase->MaxDataEntries; + CurrentEntryNumber = (UINTN)mSmmProfileBase->CurDataEntries; + MaxEntryNumber = (UINTN)mSmmProfileBase->MaxDataEntries; if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) { CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber; } + if (CurrentEntryNumber < MaxEntryNumber) { // // Log the new entry @@ -1491,6 +1540,7 @@ SmmProfilePFHandler ( } } } + // // Flush TLB // @@ -1511,7 +1561,7 @@ InitIdtr ( VOID ) { - EFI_STATUS Status; + EFI_STATUS Status; Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h index 484d81eb00..1a82ac05ce 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h @@ -23,7 +23,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ VOID ActivateSmmProfile ( - IN UINTN CpuIndex + IN UINTN CpuIndex ); /** @@ -55,8 +55,8 @@ SmmProfileRecordSmiNum ( **/ VOID SmmProfilePFHandler ( - UINTN Rip, - UINTN ErrorCode + UINTN Rip, + UINTN ErrorCode ); /** @@ -80,7 +80,6 @@ PageFaultIdtHandlerSmmProfile ( VOID ); - /** Check if feature is supported by a processor. @@ -116,20 +115,20 @@ GetCpuIndex ( **/ VOID GuardPagePFHandler ( - UINTN ErrorCode + UINTN ErrorCode ); // // The flag indicates if execute-disable is supported by processor. // -extern BOOLEAN mXdSupported; +extern BOOLEAN mXdSupported; // // The flag indicates if execute-disable is enabled on processor. // -extern BOOLEAN mXdEnabled; +extern BOOLEAN mXdEnabled; // // The flag indicates if #DB will be setup in #PF handler. // -extern BOOLEAN mSetupDebugTrap; +extern BOOLEAN mSetupDebugTrap; #endif // _SMM_PROFILE_H_ diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h index 993360a8a8..0e60509e20 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -22,41 +22,41 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Configure the SMM_PROFILE DTS region size // -#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M +#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M -#define MAX_PF_PAGE_COUNT 0x2 +#define MAX_PF_PAGE_COUNT 0x2 -#define PEBS_RECORD_NUMBER 0x2 +#define PEBS_RECORD_NUMBER 0x2 -#define MAX_PF_ENTRY_COUNT 10 +#define MAX_PF_ENTRY_COUNT 10 // // This MACRO just enable unit test for the profile // Please disable it. // -#define IA32_PF_EC_ID (1u << 4) +#define IA32_PF_EC_ID (1u << 4) -#define SMM_PROFILE_NAME L"SmmProfileData" +#define SMM_PROFILE_NAME L"SmmProfileData" // // CPU generic definition // -#define CPUID1_EDX_XD_SUPPORT 0x100000 -#define MSR_EFER 0xc0000080 -#define MSR_EFER_XD 0x800 +#define CPUID1_EDX_XD_SUPPORT 0x100000 +#define MSR_EFER 0xc0000080 +#define MSR_EFER_XD 0x800 -#define CPUID1_EDX_BTS_AVAILABLE 0x200000 +#define CPUID1_EDX_BTS_AVAILABLE 0x200000 -#define DR6_SINGLE_STEP 0x4000 -#define RFLAG_TF 0x100 +#define DR6_SINGLE_STEP 0x4000 +#define RFLAG_TF 0x100 -#define MSR_DEBUG_CTL 0x1D9 -#define MSR_DEBUG_CTL_LBR 0x1 -#define MSR_DEBUG_CTL_TR 0x40 -#define MSR_DEBUG_CTL_BTS 0x80 -#define MSR_DEBUG_CTL_BTINT 0x100 -#define MSR_DS_AREA 0x600 +#define MSR_DEBUG_CTL 0x1D9 +#define MSR_DEBUG_CTL_LBR 0x1 +#define MSR_DEBUG_CTL_TR 0x40 +#define MSR_DEBUG_CTL_BTS 0x80 +#define MSR_DEBUG_CTL_BTINT 0x100 +#define MSR_DS_AREA 0x600 #define HEAP_GUARD_NONSTOP_MODE \ ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6) @@ -65,45 +65,45 @@ SPDX-License-Identifier: BSD-2-Clause-Patent ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6) typedef struct { - EFI_PHYSICAL_ADDRESS Base; - EFI_PHYSICAL_ADDRESS Top; + EFI_PHYSICAL_ADDRESS Base; + EFI_PHYSICAL_ADDRESS Top; } MEMORY_RANGE; typedef struct { - MEMORY_RANGE Range; - BOOLEAN Present; - BOOLEAN Nx; + MEMORY_RANGE Range; + BOOLEAN Present; + BOOLEAN Nx; } MEMORY_PROTECTION_RANGE; typedef struct { - UINT64 HeaderSize; - UINT64 MaxDataEntries; - UINT64 MaxDataSize; - UINT64 CurDataEntries; - UINT64 CurDataSize; - UINT64 TsegStart; - UINT64 TsegSize; - UINT64 NumSmis; - UINT64 NumCpus; + UINT64 HeaderSize; + UINT64 MaxDataEntries; + UINT64 MaxDataSize; + UINT64 CurDataEntries; + UINT64 CurDataSize; + UINT64 TsegStart; + UINT64 TsegSize; + UINT64 NumSmis; + UINT64 NumCpus; } SMM_PROFILE_HEADER; typedef struct { - UINT64 SmiNum; - UINT64 CpuNum; - UINT64 ApicId; - UINT64 ErrorCode; - UINT64 Instruction; - UINT64 Address; - UINT64 SmiCmd; + UINT64 SmiNum; + UINT64 CpuNum; + UINT64 ApicId; + UINT64 ErrorCode; + UINT64 Instruction; + UINT64 Address; + UINT64 SmiCmd; } SMM_PROFILE_ENTRY; -extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; -extern UINTN gSmiExceptionHandlers[]; -extern BOOLEAN mXdSupported; -X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; -X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; -extern UINTN *mPFEntryCount; -extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; +extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; +extern UINTN gSmiExceptionHandlers[]; +extern BOOLEAN mXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; +extern UINTN *mPFEntryCount; +extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT]; // @@ -127,7 +127,7 @@ InitIdtr ( **/ BOOLEAN IsAddressSplit ( - IN EFI_PHYSICAL_ADDRESS Address + IN EFI_PHYSICAL_ADDRESS Address ); /** @@ -139,8 +139,8 @@ IsAddressSplit ( **/ BOOLEAN IsAddressValid ( - IN EFI_PHYSICAL_ADDRESS Address, - IN BOOLEAN *Nx + IN EFI_PHYSICAL_ADDRESS Address, + IN BOOLEAN *Nx ); /** @@ -161,7 +161,7 @@ SmiDefaultPFHandler ( **/ VOID ClearTrapFlag ( - IN OUT EFI_SYSTEM_CONTEXT SystemContext + IN OUT EFI_SYSTEM_CONTEXT SystemContext ); #endif // _SMM_PROFILE_H_ diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index 518978c1d9..c8ddc6083d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -18,53 +18,53 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" typedef struct { - UINT64 Signature; // Offset 0x00 - UINT16 Reserved1; // Offset 0x08 - UINT16 Reserved2; // Offset 0x0A - UINT16 Reserved3; // Offset 0x0C - UINT16 SmmCs; // Offset 0x0E - UINT16 SmmDs; // Offset 0x10 - UINT16 SmmSs; // Offset 0x12 - UINT16 SmmOtherSegment; // Offset 0x14 - UINT16 Reserved4; // Offset 0x16 - UINT64 Reserved5; // Offset 0x18 - UINT64 Reserved6; // Offset 0x20 - UINT64 Reserved7; // Offset 0x28 - UINT64 SmmGdtPtr; // Offset 0x30 - UINT32 SmmGdtSize; // Offset 0x38 - UINT32 Reserved8; // Offset 0x3C - UINT64 Reserved9; // Offset 0x40 - UINT64 Reserved10; // Offset 0x48 - UINT16 Reserved11; // Offset 0x50 - UINT16 Reserved12; // Offset 0x52 - UINT32 Reserved13; // Offset 0x54 - UINT64 Reserved14; // Offset 0x58 + UINT64 Signature; // Offset 0x00 + UINT16 Reserved1; // Offset 0x08 + UINT16 Reserved2; // Offset 0x0A + UINT16 Reserved3; // Offset 0x0C + UINT16 SmmCs; // Offset 0x0E + UINT16 SmmDs; // Offset 0x10 + UINT16 SmmSs; // Offset 0x12 + UINT16 SmmOtherSegment; // Offset 0x14 + UINT16 Reserved4; // Offset 0x16 + UINT64 Reserved5; // Offset 0x18 + UINT64 Reserved6; // Offset 0x20 + UINT64 Reserved7; // Offset 0x28 + UINT64 SmmGdtPtr; // Offset 0x30 + UINT32 SmmGdtSize; // Offset 0x38 + UINT32 Reserved8; // Offset 0x3C + UINT64 Reserved9; // Offset 0x40 + UINT64 Reserved10; // Offset 0x48 + UINT16 Reserved11; // Offset 0x50 + UINT16 Reserved12; // Offset 0x52 + UINT32 Reserved13; // Offset 0x54 + UINT64 Reserved14; // Offset 0x58 } PROCESSOR_SMM_DESCRIPTOR; -extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd; +extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd; // // EFER register LMA bit // -#define LMA BIT10 +#define LMA BIT10 /// /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// -#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) +#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) /// /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE /// -#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } /// /// Structure used to describe a range of registers /// typedef struct { - EFI_SMM_SAVE_STATE_REGISTER Start; - EFI_SMM_SAVE_STATE_REGISTER End; - UINTN Length; + EFI_SMM_SAVE_STATE_REGISTER Start; + EFI_SMM_SAVE_STATE_REGISTER End; + UINTN Length; } CPU_SMM_SAVE_STATE_REGISTER_RANGE; /// @@ -72,36 +72,36 @@ typedef struct { /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value /// -#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 -#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 -#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 -#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 +#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 +#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 typedef struct { - UINT8 Width32; - UINT8 Width64; - UINT16 Offset32; - UINT16 Offset64Lo; - UINT16 Offset64Hi; - BOOLEAN Writeable; + UINT8 Width32; + UINT8 Width64; + UINT16 Offset32; + UINT16 Offset64Lo; + UINT16 Offset64Hi; + BOOLEAN Writeable; } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; /// /// Structure used to build a lookup table for the IOMisc width information /// typedef struct { - UINT8 Width; - EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; + UINT8 Width; + EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; } CPU_SMM_SAVE_STATE_IO_WIDTH; /// /// Variables from SMI Handler /// -X86_ASSEMBLY_PATCH_LABEL gPatchSmbase; -X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack; -X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3; -extern volatile UINT8 gcSmiHandlerTemplate[]; -extern CONST UINT16 gcSmiHandlerSize; +X86_ASSEMBLY_PATCH_LABEL gPatchSmbase; +X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack; +X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3; +extern volatile UINT8 gcSmiHandlerTemplate[]; +extern CONST UINT16 gcSmiHandlerSize; // // Variables used by SMI Handler @@ -112,76 +112,76 @@ IA32_DESCRIPTOR gSmiHandlerIdtr; /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// -CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = { +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = { SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP), SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4), - { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } + { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0} }; /// /// Lookup table used to retrieve the widths and offsets associated with each /// supported EFI_SMM_SAVE_STATE_REGISTER value /// -CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = { - {0, 0, 0, 0, 0, FALSE}, // Reserved +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = { + { 0, 0, 0, 0, 0, FALSE }, // Reserved // // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol. // - {4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1 - {4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2 - {4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3 + { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1 + { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2 + { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3 // // CPU Save State registers defined in PI SMM CPU Protocol. // - {0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 - {0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 - {0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 - {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 - {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 - {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 - {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 - - {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 - {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 - {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 - {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 - {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 - {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 - {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 - {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 - {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 - {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 - {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 - {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 - {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40 - {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 - {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 - {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 - {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 - {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 - {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 - - {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 - {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 - {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 - {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 + { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 + { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 + { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 + { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 + { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 + { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 + { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 + + { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 + { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 + { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 + { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 + { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 + { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 + { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 + { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40 + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 + + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 + { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 }; /// /// Lookup table for the IOMisc width information /// -CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = { +CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = { { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0 { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1 { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2 @@ -195,7 +195,7 @@ CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = { /// /// Lookup table for the IOMisc type information /// -CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = { +CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = { EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0 EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1 EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2 @@ -237,11 +237,13 @@ GetRegisterIndex ( UINTN Offset; for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) { - if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) { + if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) { return Register - mSmmCpuRegisterRanges[Index].Start + Offset; } + Offset += mSmmCpuRegisterRanges[Index].Length; } + return 0; } @@ -265,10 +267,10 @@ GetRegisterIndex ( **/ EFI_STATUS ReadSaveStateRegisterByIndex ( - IN UINTN CpuIndex, - IN UINTN RegisterIndex, - IN UINTN Width, - OUT VOID *Buffer + IN UINTN CpuIndex, + IN UINTN RegisterIndex, + IN UINTN Width, + OUT VOID *Buffer ) { SMRAM_SAVE_STATE_MAP *CpuSaveState; @@ -297,8 +299,8 @@ ReadSaveStateRegisterByIndex ( // // Write return buffer // - ASSERT(CpuSaveState != NULL); - CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width); + ASSERT (CpuSaveState != NULL); + CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width); } else { // // If 64-bit mode width is zero, then the specified register can not be accessed @@ -317,14 +319,15 @@ ReadSaveStateRegisterByIndex ( // // Write at most 4 of the lower bytes of the return buffer // - CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width)); + CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width)); if (Width > 4) { // // Write at most 4 of the upper bytes of the return buffer // - CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); + CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); } } + return EFI_SUCCESS; } @@ -382,7 +385,7 @@ ReadSaveStateRegister ( // // Get SMM Revision ID // - ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId); + ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId); // // See if the CPU supports the IOMisc register in the save state @@ -394,7 +397,7 @@ ReadSaveStateRegister ( // // Get the IOMisc register value // - ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32); + ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32); // // Check for the SMI_FLAG in IOMisc @@ -407,14 +410,15 @@ ReadSaveStateRegister ( // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS. // if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) && - (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) { + (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) + { return EFI_NOT_FOUND; } // // Compute index for the I/O Length and I/O Type lookup tables // - if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) { + if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) { return EFI_NOT_FOUND; } @@ -429,14 +433,14 @@ ReadSaveStateRegister ( // Zero the IoInfo structure that will be returned in Buffer // IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; - ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO)); + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); // // Use lookup tables to help fill in all the fields of the IoInfo structure // - IoInfo->IoPort = (UINT16)IoMisc.Bits.Port; + IoInfo->IoPort = (UINT16)IoMisc.Bits.Port; IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth; - IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type]; + IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type]; ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData); return EFI_SUCCESS; } @@ -525,11 +529,12 @@ WriteSaveStateRegister ( if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { return EFI_INVALID_PARAMETER; } + // // Write SMM State register // ASSERT (CpuSaveState != NULL); - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); } else { // // If 64-bit mode width is zero, then the specified register can not be accessed @@ -548,14 +553,15 @@ WriteSaveStateRegister ( // // Write at most 4 of the lower bytes of SMM State register // - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width)); + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width)); if (Width > 4) { // // Write at most 4 of the upper bytes of SMM State register // - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); } } + return EFI_SUCCESS; } @@ -600,7 +606,7 @@ HookReturnFromSmm ( if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { OriginalInstructionPointer = (UINT64)CpuState->x86._EIP; - CpuState->x86._EIP = (UINT32)NewInstructionPointer; + CpuState->x86._EIP = (UINT32)NewInstructionPointer; // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. @@ -615,6 +621,7 @@ HookReturnFromSmm ( } else { CpuState->x64._RIP = (UINT32)NewInstructionPointer; } + // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. @@ -623,6 +630,7 @@ HookReturnFromSmm ( CpuState->x64.AutoHALTRestart &= ~BIT0; } } + return OriginalInstructionPointer; } @@ -644,6 +652,7 @@ GetSmiHandlerSize ( if (Size != 0) { return Size; } + return gcSmiHandlerSize; } @@ -693,7 +702,7 @@ InstallSmiHandler ( // Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); - Psd->SmmGdtPtr = (UINT64)GdtBase; + Psd->SmmGdtPtr = (UINT64)GdtBase; Psd->SmmGdtSize = (UINT32)GdtSize; if (SmmCpuFeaturesGetSmiHandlerSize () != 0) { @@ -729,14 +738,14 @@ InstallSmiHandler ( // // Set the value at the top of the CPU stack to the CPU Index // - *(UINTN*)(UINTN)CpuSmiStack = CpuIndex; + *(UINTN *)(UINTN)CpuSmiStack = CpuIndex; // // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), - (VOID*)gcSmiHandlerTemplate, + (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET), + (VOID *)gcSmiHandlerTemplate, gcSmiHandlerSize ); } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c index 096ab323bb..0c070c5736 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c @@ -8,11 +8,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" -UINT64 mTimeoutTicker = 0; +UINT64 mTimeoutTicker = 0; // // Number of counts in a roll-over cycle of the performance counter. // -UINT64 mCycle = 0; +UINT64 mCycle = 0; // // Flag to indicate the performance counter is count-up or count-down. // @@ -33,15 +33,15 @@ InitializeSmmTimer ( TimerFrequency = GetPerformanceCounterProperties (&Start, &End); mTimeoutTicker = DivU64x32 ( - MultU64x64(TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)), + MultU64x64 (TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)), 1000 * 1000 ); if (End < Start) { mCountDown = TRUE; - mCycle = Start - End; + mCycle = Start - End; } else { mCountDown = FALSE; - mCycle = End - Start; + mCycle = End - Start; } } @@ -58,7 +58,6 @@ StartSyncTimer ( return GetPerformanceCounter (); } - /** Check if the SMM AP Sync timer is timeout. @@ -68,7 +67,7 @@ StartSyncTimer ( BOOLEAN EFIAPI IsSyncTimerTimeout ( - IN UINT64 Timer + IN UINT64 Timer ) { UINT64 CurrentTimer; @@ -106,5 +105,5 @@ IsSyncTimerTimeout ( } } - return (BOOLEAN) (Delta >= mTimeoutTicker); + return (BOOLEAN)(Delta >= mTimeoutTicker); } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 211a78b1c4..538394f239 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -10,16 +10,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" -#define PAGE_TABLE_PAGES 8 -#define ACC_MAX_BIT BIT3 +#define PAGE_TABLE_PAGES 8 +#define ACC_MAX_BIT BIT3 -extern UINTN mSmmShadowStackSize; +extern UINTN mSmmShadowStackSize; -LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); -BOOLEAN m1GPageTableSupport = FALSE; -BOOLEAN mCpuSmmRestrictedMemoryAccess; -BOOLEAN m5LevelPagingNeeded; -X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded; +LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); +BOOLEAN m1GPageTableSupport = FALSE; +BOOLEAN mCpuSmmRestrictedMemoryAccess; +BOOLEAN m5LevelPagingNeeded; +X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded; /** Disable CET. @@ -51,8 +51,8 @@ Is1GPageSupport ( VOID ) { - UINT32 RegEax; - UINT32 RegEdx; + UINT32 RegEax; + UINT32 RegEdx; AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000001) { @@ -61,6 +61,7 @@ Is1GPageSupport ( return TRUE; } } + return FALSE; } @@ -78,9 +79,9 @@ Is5LevelPagingNeeded ( VOID ) { - CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx; - UINT32 MaxExtendedFunctionId; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx; + UINT32 MaxExtendedFunctionId; AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL); if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) { @@ -88,14 +89,20 @@ Is5LevelPagingNeeded ( } else { VirPhyAddressSize.Bits.PhysicalAddressBits = 36; } + AsmCpuidEx ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, NULL, &ExtFeatureEcx.Uint32, NULL + NULL, + NULL, + &ExtFeatureEcx.Uint32, + NULL ); DEBUG (( - DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n", - VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage + DEBUG_INFO, + "PhysicalAddressBits = %d, 5LPageTable = %d.\n", + VirPhyAddressSize.Bits.PhysicalAddressBits, + ExtFeatureEcx.Bits.FiveLevelPage )); if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) { @@ -114,18 +121,19 @@ Is5LevelPagingNeeded ( **/ VOID GetPageTable ( - OUT UINTN *Base, - OUT BOOLEAN *FiveLevels OPTIONAL + OUT UINTN *Base, + OUT BOOLEAN *FiveLevels OPTIONAL ) { - IA32_CR4 Cr4; + IA32_CR4 Cr4; if (mInternalCr3 == 0) { *Base = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; if (FiveLevels != NULL) { - Cr4.UintN = AsmReadCr4 (); + Cr4.UintN = AsmReadCr4 (); *FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1); } + return; } @@ -146,8 +154,8 @@ GetPageTable ( **/ VOID SetSubEntriesNum ( - IN OUT UINT64 *Entry, - IN UINT64 SubEntryNum + IN OUT UINT64 *Entry, + IN UINT64 SubEntryNum ) { // @@ -167,7 +175,7 @@ SetSubEntriesNum ( **/ UINT64 GetSubEntriesNum ( - IN UINT64 *Entry + IN UINT64 *Entry ) { // @@ -186,25 +194,26 @@ CalculateMaximumSupportAddress ( VOID ) { - UINT32 RegEax; - UINT8 PhysicalAddressBits; - VOID *Hob; + UINT32 RegEax; + UINT8 PhysicalAddressBits; + VOID *Hob; // // Get physical address bits supported. // Hob = GetFirstHob (EFI_HOB_TYPE_CPU); if (Hob != NULL) { - PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; + PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; } else { AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000008) { AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits = (UINT8) RegEax; + PhysicalAddressBits = (UINT8)RegEax; } else { PhysicalAddressBits = 36; } } + return PhysicalAddressBits; } @@ -216,54 +225,54 @@ CalculateMaximumSupportAddress ( **/ VOID SetStaticPageTable ( - IN UINTN PageTable, - IN UINT8 PhysicalAddressBits + IN UINTN PageTable, + IN UINT8 PhysicalAddressBits ) { - UINT64 PageAddress; - UINTN NumberOfPml5EntriesNeeded; - UINTN NumberOfPml4EntriesNeeded; - UINTN NumberOfPdpEntriesNeeded; - UINTN IndexOfPml5Entries; - UINTN IndexOfPml4Entries; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT64 *PageMapLevel5Entry; - UINT64 *PageMapLevel4Entry; - UINT64 *PageMap; - UINT64 *PageDirectoryPointerEntry; - UINT64 *PageDirectory1GEntry; - UINT64 *PageDirectoryEntry; + UINT64 PageAddress; + UINTN NumberOfPml5EntriesNeeded; + UINTN NumberOfPml4EntriesNeeded; + UINTN NumberOfPdpEntriesNeeded; + UINTN IndexOfPml5Entries; + UINTN IndexOfPml4Entries; + UINTN IndexOfPdpEntries; + UINTN IndexOfPageDirectoryEntries; + UINT64 *PageMapLevel5Entry; + UINT64 *PageMapLevel4Entry; + UINT64 *PageMap; + UINT64 *PageDirectoryPointerEntry; + UINT64 *PageDirectory1GEntry; + UINT64 *PageDirectoryEntry; // // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses // when 5-Level Paging is disabled. // ASSERT (PhysicalAddressBits <= 52); - if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { + if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) { PhysicalAddressBits = 48; } NumberOfPml5EntriesNeeded = 1; if (PhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48); - PhysicalAddressBits = 48; + NumberOfPml5EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 48); + PhysicalAddressBits = 48; } NumberOfPml4EntriesNeeded = 1; if (PhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39); - PhysicalAddressBits = 39; + NumberOfPml4EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 39); + PhysicalAddressBits = 39; } NumberOfPdpEntriesNeeded = 1; ASSERT (PhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30); + NumberOfPdpEntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 30); // // By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // - PageMap = (VOID *) PageTable; + PageMap = (VOID *)PageTable; PageMapLevel4Entry = PageMap; PageMapLevel5Entry = NULL; @@ -273,22 +282,24 @@ SetStaticPageTable ( // PageMapLevel5Entry = PageMap; } - PageAddress = 0; + + PageAddress = 0; for ( IndexOfPml5Entries = 0 - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded - ; IndexOfPml5Entries++, PageMapLevel5Entry++) { + ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded + ; IndexOfPml5Entries++, PageMapLevel5Entry++) + { // // Each PML5 entry points to a page of PML4 entires. // So lets allocate space for them and fill them in in the IndexOfPml4Entries loop. // When 5-Level Paging is disabled, below allocation happens only once. // if (m5LevelPagingNeeded) { - PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask); + PageMapLevel4Entry = (UINT64 *)((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask); if (PageMapLevel4Entry == NULL) { PageMapLevel4Entry = AllocatePageTableMemory (1); - ASSERT(PageMapLevel4Entry != NULL); - ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE(1)); + ASSERT (PageMapLevel4Entry != NULL); + ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1)); *PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } @@ -298,11 +309,11 @@ SetStaticPageTable ( // // Each PML4 entry points to a page of Page Directory Pointer entries. // - PageDirectoryPointerEntry = (UINT64 *) ((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask); + PageDirectoryPointerEntry = (UINT64 *)((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask); if (PageDirectoryPointerEntry == NULL) { PageDirectoryPointerEntry = AllocatePageTableMemory (1); - ASSERT(PageDirectoryPointerEntry != NULL); - ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1)); + ASSERT (PageDirectoryPointerEntry != NULL); + ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1)); *PageMapLevel4Entry = (UINT64)(UINTN)PageDirectoryPointerEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } @@ -310,12 +321,13 @@ SetStaticPageTable ( if (m1GPageTableSupport) { PageDirectory1GEntry = PageDirectoryPointerEntry; for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) { - if (IndexOfPml4Entries == 0 && IndexOfPageDirectoryEntries < 4) { + if ((IndexOfPml4Entries == 0) && (IndexOfPageDirectoryEntries < 4)) { // // Skip the < 4G entries // continue; } + // // Fill in the Page Directory entries // @@ -324,21 +336,22 @@ SetStaticPageTable ( } else { PageAddress = BASE_4GB; for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) { - if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) { + if ((IndexOfPml4Entries == 0) && (IndexOfPdpEntries < 4)) { // // Skip the < 4G entries // continue; } + // // Each Directory Pointer entries points to a page of Page Directory entires. // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop. // - PageDirectoryEntry = (UINT64 *) ((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask); + PageDirectoryEntry = (UINT64 *)((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask); if (PageDirectoryEntry == NULL) { PageDirectoryEntry = AllocatePageTableMemory (1); - ASSERT(PageDirectoryEntry != NULL); - ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE(1)); + ASSERT (PageDirectoryEntry != NULL); + ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1)); // // Fill in a Page Directory Pointer Entries @@ -369,15 +382,15 @@ SmmInitPageTable ( VOID ) { - EFI_PHYSICAL_ADDRESS Pages; - UINT64 *PTEntry; - LIST_ENTRY *FreePage; - UINTN Index; - UINTN PageFaultHandlerHookAddress; - IA32_IDT_GATE_DESCRIPTOR *IdtEntry; - EFI_STATUS Status; - UINT64 *Pml4Entry; - UINT64 *Pml5Entry; + EFI_PHYSICAL_ADDRESS Pages; + UINT64 *PTEntry; + LIST_ENTRY *FreePage; + UINTN Index; + UINTN PageFaultHandlerHookAddress; + IA32_IDT_GATE_DESCRIPTOR *IdtEntry; + EFI_STATUS Status; + UINT64 *Pml4Entry; + UINT64 *Pml5Entry; // // Initialize spin lock @@ -401,7 +414,7 @@ SmmInitPageTable ( // // Set IA32_PG_PMNT bit to mask this entry // - PTEntry = (UINT64*)(UINTN)Pages; + PTEntry = (UINT64 *)(UINTN)Pages; for (Index = 0; Index < 4; Index++) { PTEntry[Index] |= IA32_PG_PMNT; } @@ -409,7 +422,7 @@ SmmInitPageTable ( // // Fill Page-Table-Level4 (PML4) entry // - Pml4Entry = (UINT64*)AllocatePageTableMemory (1); + Pml4Entry = (UINT64 *)AllocatePageTableMemory (1); ASSERT (Pml4Entry != NULL); *Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); @@ -424,9 +437,9 @@ SmmInitPageTable ( // // Fill PML5 entry // - Pml5Entry = (UINT64*)AllocatePageTableMemory (1); + Pml5Entry = (UINT64 *)AllocatePageTableMemory (1); ASSERT (Pml5Entry != NULL); - *Pml5Entry = (UINTN) Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; + *Pml5Entry = (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); // // Set sub-entries number @@ -445,7 +458,7 @@ SmmInitPageTable ( // // Add pages to page pool // - FreePage = (LIST_ENTRY*)AllocatePageTableMemory (PAGE_TABLE_PAGES); + FreePage = (LIST_ENTRY *)AllocatePageTableMemory (PAGE_TABLE_PAGES); ASSERT (FreePage != NULL); for (Index = 0; Index < PAGE_TABLE_PAGES; Index++) { InsertTailList (&mPagePool, FreePage); @@ -455,20 +468,21 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmProfileEnable) || HEAP_GUARD_NONSTOP_MODE || - NULL_DETECTION_NONSTOP_MODE) { + NULL_DETECTION_NONSTOP_MODE) + { // // Set own Page Fault entry instead of the default one, because SMM Profile // feature depends on IRET instruction to do Single Step // PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile; - IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base; - IdtEntry += EXCEPT_IA32_PAGE_FAULT; - IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; - IdtEntry->Bits.Reserved_0 = 0; - IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; - IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16); - IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32); - IdtEntry->Bits.Reserved_1 = 0; + IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; + IdtEntry += EXCEPT_IA32_PAGE_FAULT; + IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; + IdtEntry->Bits.Reserved_0 = 0; + IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; + IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16); + IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32); + IdtEntry->Bits.Reserved_1 = 0; } else { // // Register Smm Page Fault Handler @@ -509,8 +523,8 @@ SmmInitPageTable ( **/ VOID SetAccNum ( - IN OUT UINT64 *Entry, - IN UINT64 Acc + IN OUT UINT64 *Entry, + IN UINT64 Acc ) { // @@ -529,7 +543,7 @@ SetAccNum ( **/ UINT64 GetAccNum ( - IN UINT64 *Entry + IN UINT64 *Entry ) { // @@ -548,10 +562,10 @@ GetAccNum ( **/ UINT64 GetAndUpdateAccNum ( - IN OUT UINT64 *Entry + IN OUT UINT64 *Entry ) { - UINT64 Acc; + UINT64 Acc; Acc = GetAccNum (Entry); if ((*Entry & IA32_PG_A) != 0) { @@ -570,6 +584,7 @@ GetAndUpdateAccNum ( SetAccNum (Entry, Acc - 1); } } + return Acc; } @@ -587,84 +602,86 @@ ReclaimPages ( VOID ) { - UINT64 Pml5Entry; - UINT64 *Pml5; - UINT64 *Pml4; - UINT64 *Pdpt; - UINT64 *Pdt; - UINTN Pml5Index; - UINTN Pml4Index; - UINTN PdptIndex; - UINTN PdtIndex; - UINTN MinPml5; - UINTN MinPml4; - UINTN MinPdpt; - UINTN MinPdt; - UINT64 MinAcc; - UINT64 Acc; - UINT64 SubEntriesNum; - BOOLEAN PML4EIgnore; - BOOLEAN PDPTEIgnore; - UINT64 *ReleasePageAddress; - IA32_CR4 Cr4; - BOOLEAN Enable5LevelPaging; - UINT64 PFAddress; - UINT64 PFAddressPml5Index; - UINT64 PFAddressPml4Index; - UINT64 PFAddressPdptIndex; - UINT64 PFAddressPdtIndex; - - Pml4 = NULL; - Pdpt = NULL; - Pdt = NULL; - MinAcc = (UINT64)-1; - MinPml4 = (UINTN)-1; - MinPml5 = (UINTN)-1; - MinPdpt = (UINTN)-1; - MinPdt = (UINTN)-1; - Acc = 0; + UINT64 Pml5Entry; + UINT64 *Pml5; + UINT64 *Pml4; + UINT64 *Pdpt; + UINT64 *Pdt; + UINTN Pml5Index; + UINTN Pml4Index; + UINTN PdptIndex; + UINTN PdtIndex; + UINTN MinPml5; + UINTN MinPml4; + UINTN MinPdpt; + UINTN MinPdt; + UINT64 MinAcc; + UINT64 Acc; + UINT64 SubEntriesNum; + BOOLEAN PML4EIgnore; + BOOLEAN PDPTEIgnore; + UINT64 *ReleasePageAddress; + IA32_CR4 Cr4; + BOOLEAN Enable5LevelPaging; + UINT64 PFAddress; + UINT64 PFAddressPml5Index; + UINT64 PFAddressPml4Index; + UINT64 PFAddressPdptIndex; + UINT64 PFAddressPdtIndex; + + Pml4 = NULL; + Pdpt = NULL; + Pdt = NULL; + MinAcc = (UINT64)-1; + MinPml4 = (UINTN)-1; + MinPml5 = (UINTN)-1; + MinPdpt = (UINTN)-1; + MinPdt = (UINTN)-1; + Acc = 0; ReleasePageAddress = 0; - PFAddress = AsmReadCr2 (); + PFAddress = AsmReadCr2 (); PFAddressPml5Index = BitFieldRead64 (PFAddress, 48, 48 + 8); PFAddressPml4Index = BitFieldRead64 (PFAddress, 39, 39 + 8); PFAddressPdptIndex = BitFieldRead64 (PFAddress, 30, 30 + 8); - PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8); + PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8); - Cr4.UintN = AsmReadCr4 (); - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); - Pml5 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask); + Cr4.UintN = AsmReadCr4 (); + Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); + Pml5 = (UINT64 *)(UINTN)(AsmReadCr3 () & gPhyMask); if (!Enable5LevelPaging) { // // Create one fake PML5 entry for 4-Level Paging // so that the page table parsing logic only handles 5-Level page structure. // - Pml5Entry = (UINTN) Pml5 | IA32_PG_P; - Pml5 = &Pml5Entry; + Pml5Entry = (UINTN)Pml5 | IA32_PG_P; + Pml5 = &Pml5Entry; } // // First, find the leaf entry has the smallest access record value // for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) { - if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) { + if (((Pml5[Pml5Index] & IA32_PG_P) == 0) || ((Pml5[Pml5Index] & IA32_PG_PMNT) != 0)) { // // If the PML5 entry is not present or is masked, skip it // continue; } - Pml4 = (UINT64*)(UINTN)(Pml5[Pml5Index] & gPhyMask); + + Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & gPhyMask); for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) { - if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) { + if (((Pml4[Pml4Index] & IA32_PG_P) == 0) || ((Pml4[Pml4Index] & IA32_PG_PMNT) != 0)) { // // If the PML4 entry is not present or is masked, skip it // continue; } - Pdpt = (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask); + + Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask); PML4EIgnore = FALSE; for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) { - if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) { + if (((Pdpt[PdptIndex] & IA32_PG_P) == 0) || ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0)) { // // If the PDPT entry is not present or is masked, skip it // @@ -674,18 +691,20 @@ ReclaimPages ( // PML4EIgnore = TRUE; } + continue; } + if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) { // // It's not 1-GByte pages entry, it should be a PDPT entry, // we will not check PML4 entry more // PML4EIgnore = TRUE; - Pdt = (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask); + Pdt = (UINT64 *)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask); PDPTEIgnore = FALSE; - for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtIndex++) { - if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) { + for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof (*Pdt); PdtIndex++) { + if (((Pdt[PdtIndex] & IA32_PG_P) == 0) || ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0)) { // // If the PD entry is not present or is masked, skip it // @@ -695,79 +714,86 @@ ReclaimPages ( // PDPTEIgnore = TRUE; } + continue; } + if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) { // // It's not 2 MByte page table entry, it should be PD entry // we will find the entry has the smallest access record value // PDPTEIgnore = TRUE; - if (PdtIndex != PFAddressPdtIndex || PdptIndex != PFAddressPdptIndex || - Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) { + if ((PdtIndex != PFAddressPdtIndex) || (PdptIndex != PFAddressPdptIndex) || + (Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) + { Acc = GetAndUpdateAccNum (Pdt + PdtIndex); if (Acc < MinAcc) { // // If the PD entry has the smallest access record value, // save the Page address to be released // - MinAcc = Acc; - MinPml5 = Pml5Index; - MinPml4 = Pml4Index; - MinPdpt = PdptIndex; - MinPdt = PdtIndex; + MinAcc = Acc; + MinPml5 = Pml5Index; + MinPml4 = Pml4Index; + MinPdpt = PdptIndex; + MinPdt = PdtIndex; ReleasePageAddress = Pdt + PdtIndex; } } } } + if (!PDPTEIgnore) { // // If this PDPT entry has no PDT entries pointer to 4 KByte pages, // it should only has the entries point to 2 MByte Pages // - if (PdptIndex != PFAddressPdptIndex || Pml4Index != PFAddressPml4Index || - Pml5Index != PFAddressPml5Index) { + if ((PdptIndex != PFAddressPdptIndex) || (Pml4Index != PFAddressPml4Index) || + (Pml5Index != PFAddressPml5Index)) + { Acc = GetAndUpdateAccNum (Pdpt + PdptIndex); if (Acc < MinAcc) { // // If the PDPT entry has the smallest access record value, // save the Page address to be released // - MinAcc = Acc; - MinPml5 = Pml5Index; - MinPml4 = Pml4Index; - MinPdpt = PdptIndex; - MinPdt = (UINTN)-1; + MinAcc = Acc; + MinPml5 = Pml5Index; + MinPml4 = Pml4Index; + MinPdpt = PdptIndex; + MinPdt = (UINTN)-1; ReleasePageAddress = Pdpt + PdptIndex; } } } } } + if (!PML4EIgnore) { // // If PML4 entry has no the PDPT entry pointer to 2 MByte pages, // it should only has the entries point to 1 GByte Pages // - if (Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) { + if ((Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) { Acc = GetAndUpdateAccNum (Pml4 + Pml4Index); if (Acc < MinAcc) { // // If the PML4 entry has the smallest access record value, // save the Page address to be released // - MinAcc = Acc; - MinPml5 = Pml5Index; - MinPml4 = Pml4Index; - MinPdpt = (UINTN)-1; - MinPdt = (UINTN)-1; + MinAcc = Acc; + MinPml5 = Pml5Index; + MinPml4 = Pml4Index; + MinPdpt = (UINTN)-1; + MinPdt = (UINTN)-1; ReleasePageAddress = Pml4 + Pml4Index; } } } } } + // // Make sure one PML4/PDPT/PD entry is selected // @@ -776,7 +802,7 @@ ReclaimPages ( // // Secondly, insert the page pointed by this entry into page pool and clear this entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask)); *ReleasePageAddress = 0; // @@ -788,16 +814,17 @@ ReclaimPages ( // // If 4 KByte Page Table is released, check the PDPT entry // - Pml4 = (UINT64 *) (UINTN) (Pml5[MinPml5] & gPhyMask); - Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask); - SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt); - if (SubEntriesNum == 0 && - (MinPdpt != PFAddressPdptIndex || MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) { + Pml4 = (UINT64 *)(UINTN)(Pml5[MinPml5] & gPhyMask); + Pdpt = (UINT64 *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask); + SubEntriesNum = GetSubEntriesNum (Pdpt + MinPdpt); + if ((SubEntriesNum == 0) && + ((MinPdpt != PFAddressPdptIndex) || (MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) + { // // Release the empty Page Directory table if there was no more 4 KByte Page Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask)); Pdpt[MinPdpt] = 0; // // Go on checking the PML4 table @@ -805,33 +832,37 @@ ReclaimPages ( MinPdt = (UINTN)-1; continue; } + // // Update the sub-entries filed in PDPT entry and exit // SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF); break; } + if (MinPdpt != (UINTN)-1) { // // One 2MB Page Table is released or Page Directory table is released, check the PML4 entry // SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4); - if (SubEntriesNum == 0 && (MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) { + if ((SubEntriesNum == 0) && ((MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) { // // Release the empty PML4 table if there was no more 1G KByte Page Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask)); Pml4[MinPml4] = 0; - MinPdpt = (UINTN)-1; + MinPdpt = (UINTN)-1; continue; } + // // Update the sub-entries filed in PML4 entry and exit // SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF); break; } + // // PLM4 table has been released before, exit it // @@ -850,7 +881,7 @@ AllocPage ( VOID ) { - UINT64 RetVal; + UINT64 RetVal; if (IsListEmpty (&mPagePool)) { // @@ -867,7 +898,7 @@ AllocPage ( // // Clean this page and return // - ZeroMem ((VOID*)(UINTN)RetVal, EFI_PAGE_SIZE); + ZeroMem ((VOID *)(UINTN)RetVal, EFI_PAGE_SIZE); return RetVal; } @@ -880,78 +911,81 @@ SmiDefaultPFHandler ( VOID ) { - UINT64 *PageTable; - UINT64 *PageTableTop; - UINT64 PFAddress; - UINTN StartBit; - UINTN EndBit; - UINT64 PTIndex; - UINTN Index; - SMM_PAGE_SIZE_TYPE PageSize; - UINTN NumOfPages; - UINTN PageAttribute; - EFI_STATUS Status; - UINT64 *UpperEntry; - BOOLEAN Enable5LevelPaging; - IA32_CR4 Cr4; + UINT64 *PageTable; + UINT64 *PageTableTop; + UINT64 PFAddress; + UINTN StartBit; + UINTN EndBit; + UINT64 PTIndex; + UINTN Index; + SMM_PAGE_SIZE_TYPE PageSize; + UINTN NumOfPages; + UINTN PageAttribute; + EFI_STATUS Status; + UINT64 *UpperEntry; + BOOLEAN Enable5LevelPaging; + IA32_CR4 Cr4; // // Set default SMM page attribute // - PageSize = SmmPageSize2M; - NumOfPages = 1; + PageSize = SmmPageSize2M; + NumOfPages = 1; PageAttribute = 0; - EndBit = 0; - PageTableTop = (UINT64*)(AsmReadCr3 () & gPhyMask); - PFAddress = AsmReadCr2 (); + EndBit = 0; + PageTableTop = (UINT64 *)(AsmReadCr3 () & gPhyMask); + PFAddress = AsmReadCr2 (); - Cr4.UintN = AsmReadCr4 (); - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 != 0); + Cr4.UintN = AsmReadCr4 (); + Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 != 0); Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute); // // If platform not support page table attribute, set default SMM page attribute // if (Status != EFI_SUCCESS) { - PageSize = SmmPageSize2M; - NumOfPages = 1; + PageSize = SmmPageSize2M; + NumOfPages = 1; PageAttribute = 0; } + if (PageSize >= MaxSmmPageSizeType) { PageSize = SmmPageSize2M; } + if (NumOfPages > 512) { NumOfPages = 512; } switch (PageSize) { - case SmmPageSize4K: - // - // BIT12 to BIT20 is Page Table index - // - EndBit = 12; - break; - case SmmPageSize2M: - // - // BIT21 to BIT29 is Page Directory index - // - EndBit = 21; - PageAttribute |= (UINTN)IA32_PG_PS; - break; - case SmmPageSize1G: - if (!m1GPageTableSupport) { - DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!")); + case SmmPageSize4K: + // + // BIT12 to BIT20 is Page Table index + // + EndBit = 12; + break; + case SmmPageSize2M: + // + // BIT21 to BIT29 is Page Directory index + // + EndBit = 21; + PageAttribute |= (UINTN)IA32_PG_PS; + break; + case SmmPageSize1G: + if (!m1GPageTableSupport) { + DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!")); + ASSERT (FALSE); + } + + // + // BIT30 to BIT38 is Page Directory Pointer Table index + // + EndBit = 30; + PageAttribute |= (UINTN)IA32_PG_PS; + break; + default: ASSERT (FALSE); - } - // - // BIT30 to BIT38 is Page Directory Pointer Table index - // - EndBit = 30; - PageAttribute |= (UINTN)IA32_PG_PS; - break; - default: - ASSERT (FALSE); } // @@ -977,13 +1011,14 @@ SmiDefaultPFHandler ( // UpperEntry = PageTable + PTIndex; } + // // BIT9 to BIT11 of entry is used to save access record, // initialize value is 7 // PageTable[PTIndex] |= (UINT64)IA32_PG_A; SetAccNum (PageTable + PTIndex, 7); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask); } PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8); @@ -996,6 +1031,7 @@ SmiDefaultPFHandler ( DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n")); ASSERT (FALSE); } + // // Fill the new entry // @@ -1004,6 +1040,7 @@ SmiDefaultPFHandler ( if (UpperEntry != NULL) { SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF); } + // // Get the next page address if we need to create more page tables // @@ -1022,14 +1059,14 @@ SmiDefaultPFHandler ( VOID EFIAPI SmiPFHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_SYSTEM_CONTEXT SystemContext + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ) { - UINTN PFAddress; - UINTN GuardPageAddress; - UINTN ShadowStackGuardPageAddress; - UINTN CpuIndex; + UINTN PFAddress; + UINTN GuardPageAddress; + UINTN ShadowStackGuardPageAddress; + UINTN CpuIndex; ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT); @@ -1049,31 +1086,34 @@ SmiPFHandler ( // or SMM page protection violation. // if ((PFAddress >= mCpuHotPlugData.SmrrBase) && - (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) { + (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) + { DumpCpuContext (InterruptType, SystemContext); - CpuIndex = GetCpuIndex (); - GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize)); + CpuIndex = GetCpuIndex (); + GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize)); ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize)); if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && (PFAddress >= GuardPageAddress) && - (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) { + (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) + { DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n")); } else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && - (mSmmShadowStackSize > 0) && - (PFAddress >= ShadowStackGuardPageAddress) && - (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) { + (mSmmShadowStackSize > 0) && + (PFAddress >= ShadowStackGuardPageAddress) && + (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) + { DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n")); } else { if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) { DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%lx)\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp); - ); + ); } else { DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%lx)\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip); - ); + ); } if (HEAP_GUARD_NONSTOP_MODE) { @@ -1081,6 +1121,7 @@ SmiPFHandler ( goto Exit; } } + CpuDeadLoop (); goto Exit; } @@ -1089,13 +1130,14 @@ SmiPFHandler ( // If a page fault occurs in non-SMRAM range. // if ((PFAddress < mCpuHotPlugData.SmrrBase) || - (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { + (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) + { if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) { DumpCpuContext (InterruptType, SystemContext); DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp); - ); + ); CpuDeadLoop (); goto Exit; } @@ -1103,13 +1145,14 @@ SmiPFHandler ( // // If NULL pointer was just accessed // - if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 && - (PFAddress < EFI_PAGE_SIZE)) { + if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) && + (PFAddress < EFI_PAGE_SIZE)) + { DumpCpuContext (InterruptType, SystemContext); DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n")); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip); - ); + ); if (NULL_DETECTION_NONSTOP_MODE) { GuardPagePFHandler (SystemContext.SystemContextX64->ExceptionData); @@ -1125,7 +1168,7 @@ SmiPFHandler ( DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress)); DEBUG_CODE ( DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip); - ); + ); CpuDeadLoop (); goto Exit; } @@ -1152,20 +1195,20 @@ SetPageTableAttributes ( VOID ) { - UINTN Index2; - UINTN Index3; - UINTN Index4; - UINTN Index5; - UINT64 *L1PageTable; - UINT64 *L2PageTable; - UINT64 *L3PageTable; - UINT64 *L4PageTable; - UINT64 *L5PageTable; - UINTN PageTableBase; - BOOLEAN IsSplitted; - BOOLEAN PageTableSplitted; - BOOLEAN CetEnabled; - BOOLEAN Enable5LevelPaging; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINTN Index5; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + UINT64 *L5PageTable; + UINTN PageTableBase; + BOOLEAN IsSplitted; + BOOLEAN PageTableSplitted; + BOOLEAN CetEnabled; + BOOLEAN Enable5LevelPaging; // // Don't mark page table memory as read-only if @@ -1177,18 +1220,21 @@ SetPageTableAttributes ( // if (!mCpuSmmRestrictedMemoryAccess || ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) || - FeaturePcdGet (PcdCpuSmmProfileEnable)) { + FeaturePcdGet (PcdCpuSmmProfileEnable)) + { // // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time. // - ASSERT (!(mCpuSmmRestrictedMemoryAccess && - (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)); + ASSERT ( + !(mCpuSmmRestrictedMemoryAccess && + (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) + ); // // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time. // ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable))); - return ; + return; } DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n")); @@ -1197,19 +1243,20 @@ SetPageTableAttributes ( // Disable write protection, because we need mark page table to be write protected. // We need *write* page table memory, to mark itself to be *read only*. // - CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; + CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; if (CetEnabled) { // // CET must be disabled if WP is disabled. // - DisableCet(); + DisableCet (); } - AsmWriteCr0 (AsmReadCr0() & ~CR0_WP); + + AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); do { DEBUG ((DEBUG_INFO, "Start...\n")); PageTableSplitted = FALSE; - L5PageTable = NULL; + L5PageTable = NULL; GetPageTable (&PageTableBase, &Enable5LevelPaging); @@ -1219,7 +1266,7 @@ SetPageTableAttributes ( PageTableSplitted = (PageTableSplitted || IsSplitted); } - for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) { + for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof (UINT64) : 1); Index5++) { if (Enable5LevelPaging) { L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L4PageTable == NULL) { @@ -1228,10 +1275,11 @@ SetPageTableAttributes ( } else { L4PageTable = (UINT64 *)PageTableBase; } + SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); - for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { + for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) { L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L3PageTable == NULL) { continue; @@ -1240,11 +1288,12 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); - for (Index3 = 0; Index3 < SIZE_4KB/sizeof(UINT64); Index3++) { + for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) { if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { // 1G continue; } + L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable == NULL) { continue; @@ -1253,15 +1302,17 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); - for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) { + for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { // 2M continue; } + L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable == NULL) { continue; } + SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted); } @@ -1273,15 +1324,15 @@ SetPageTableAttributes ( // // Enable write protection, after page table updated. // - AsmWriteCr0 (AsmReadCr0() | CR0_WP); + AsmWriteCr0 (AsmReadCr0 () | CR0_WP); if (CetEnabled) { // // re-enable CET. // - EnableCet(); + EnableCet (); } - return ; + return; } /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c index 8c9de1fdae..dafbc3390e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c @@ -9,8 +9,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" -X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32; -X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32; +X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32; UINTN mSmmRelocationOriginalAddress; volatile BOOLEAN *mRebasedFlag; @@ -42,14 +42,14 @@ SemaphoreHook ( SMRAM_SAVE_STATE_MAP *CpuState; UINTN TempValue; - mRebasedFlag = RebasedFlag; + mRebasedFlag = RebasedFlag; PatchInstructionX86 ( gPatchRebasedFlagAddr32, (UINT32)(UINTN)mRebasedFlag, 4 ); - CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); mSmmRelocationOriginalAddress = HookReturnFromSmm ( CpuIndex, CpuState, diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index ce7afce6d4..00a284c369 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h" -EFI_PHYSICAL_ADDRESS mGdtBuffer; -UINTN mGdtBufferSize; +EFI_PHYSICAL_ADDRESS mGdtBuffer; +UINTN mGdtBufferSize; -extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; +extern BOOLEAN mCetSupported; +extern UINTN mSmmShadowStackSize; -X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; -X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; -X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable; -UINT32 mCetPl0Ssp; -UINT32 mCetInterruptSsp; -UINT32 mCetInterruptSspTable; +X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; +X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; +X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable; +UINT32 mCetPl0Ssp; +UINT32 mCetInterruptSsp; +UINT32 mCetInterruptSspTable; UINTN mSmmInterruptSspTables; @@ -33,14 +33,14 @@ UINTN mSmmInterruptSspTables; VOID EFIAPI InitializeIdtIst ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN UINT8 Ist + IN EFI_EXCEPTION_TYPE ExceptionType, + IN UINT8 Ist ) { IA32_IDT_GATE_DESCRIPTOR *IdtGate; - IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; - IdtGate += ExceptionType; + IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; + IdtGate += ExceptionType; IdtGate->Bits.Reserved_0 = Ist; } @@ -59,34 +59,34 @@ InitGdt ( OUT UINTN *GdtStepSize ) { - UINTN Index; - IA32_SEGMENT_DESCRIPTOR *GdtDescriptor; - UINTN TssBase; - UINTN GdtTssTableSize; - UINT8 *GdtTssTables; - UINTN GdtTableStepSize; + UINTN Index; + IA32_SEGMENT_DESCRIPTOR *GdtDescriptor; + UINTN TssBase; + UINTN GdtTssTableSize; + UINT8 *GdtTssTables; + UINTN GdtTableStepSize; // // For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention // on each SMI entry. // GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned - mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; - GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); + mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; + GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); ASSERT (GdtTssTables != NULL); - mGdtBuffer = (UINTN)GdtTssTables; + mGdtBuffer = (UINTN)GdtTssTables; GdtTableStepSize = GdtTssTableSize; for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { - CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE); + CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE); // // Fixup TSS descriptors // - TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1); - GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2; - GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase; - GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16); + TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1); + GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2; + GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase; + GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16); GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24); if ((FeaturePcdGet (PcdCpuSmmStackGuard)) || ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported)) { @@ -118,15 +118,17 @@ GetProtectedModeCS ( AsmReadGdtr (&GdtrDesc); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); - GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base; for (Index = 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L == 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) { + if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) { break; } } + GdtEntry++; } + ASSERT (Index != GdtEntryCount); return Index * 8; } @@ -171,9 +173,9 @@ InitShadowStack ( IN VOID *ShadowStack ) { - UINTN SmmShadowStackSize; - UINT64 *InterruptSspTable; - UINT32 InterruptSsp; + UINTN SmmShadowStackSize; + UINT64 *InterruptSspTable; + UINT32 InterruptSsp; if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize))); @@ -188,14 +190,15 @@ InitShadowStack ( // SmmShadowStackSize += EFI_PAGES_TO_SIZE (1); } - mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64)); + + mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64)); PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4); DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp)); DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack)); DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize)); if (mSmmInterruptSspTables == 0) { - mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); + mSmmInterruptSspTables = (UINTN)AllocateZeroPool (sizeof (UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); ASSERT (mSmmInterruptSspTables != 0); DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables)); } @@ -209,17 +212,16 @@ InitShadowStack ( // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime. // According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned. // - InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - (sizeof(UINT64) * 4)) & ~0x1f); - *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2; - mCetInterruptSsp = InterruptSsp - sizeof(UINT64); + InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - (sizeof (UINT64) * 4)) & ~0x1f); + *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof (UINT64) * 4) | 0x2; + mCetInterruptSsp = InterruptSsp - sizeof (UINT64); - mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex); - InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable; - InterruptSspTable[1] = mCetInterruptSsp; + mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof (UINT64) * 8 * CpuIndex); + InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable; + InterruptSspTable[1] = mCetInterruptSsp; PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable, 4); DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp)); DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable)); } } - diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c index 63bae5a913..cb7a691745 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -14,17 +14,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Current page index. // -UINTN mPFPageIndex; +UINTN mPFPageIndex; // // Pool for dynamically creating page table in page fault handler. // -UINT64 mPFPageBuffer; +UINT64 mPFPageBuffer; // // Store the uplink information for each page being used. // -UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT]; +UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT]; /** Create SMM page table for S3 path. @@ -35,8 +35,8 @@ InitSmmS3Cr3 ( VOID ) { - EFI_PHYSICAL_ADDRESS Pages; - UINT64 *PTEntry; + EFI_PHYSICAL_ADDRESS Pages; + UINT64 *PTEntry; // // Generate PAE page table for the first 4GB memory space @@ -46,7 +46,7 @@ InitSmmS3Cr3 ( // // Fill Page-Table-Level4 (PML4) entry // - PTEntry = (UINT64*)AllocatePageTableMemory (1); + PTEntry = (UINT64 *)AllocatePageTableMemory (1); ASSERT (PTEntry != NULL); *PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); @@ -56,7 +56,7 @@ InitSmmS3Cr3 ( // mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry; - return ; + return; } /** @@ -68,7 +68,7 @@ InitPagesForPFHandler ( VOID ) { - VOID *Address; + VOID *Address; // // Pre-Allocate memory for page fault handler @@ -77,9 +77,9 @@ InitPagesForPFHandler ( Address = AllocatePages (MAX_PF_PAGE_COUNT); ASSERT (Address != NULL); - mPFPageBuffer = (UINT64)(UINTN) Address; - mPFPageIndex = 0; - ZeroMem ((VOID *) (UINTN) mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT); + mPFPageBuffer = (UINT64)(UINTN)Address; + mPFPageIndex = 0; + ZeroMem ((VOID *)(UINTN)mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT); ZeroMem (mPFPageUplink, sizeof (mPFPageUplink)); return; @@ -93,16 +93,16 @@ InitPagesForPFHandler ( **/ VOID AcquirePage ( - UINT64 *Uplink + UINT64 *Uplink ) { - UINT64 Address; + UINT64 Address; // // Get the buffer // Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex); - ZeroMem ((VOID *) (UINTN) Address, EFI_PAGE_SIZE); + ZeroMem ((VOID *)(UINTN)Address, EFI_PAGE_SIZE); // // Cut the previous uplink if it exists and wasn't overwritten @@ -114,7 +114,7 @@ AcquirePage ( // // Link & Record the current uplink // - *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS; + *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS; mPFPageUplink[mPFPageIndex] = Uplink; mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT; @@ -134,26 +134,26 @@ AcquirePage ( **/ VOID RestorePageTableAbove4G ( - UINT64 *PageTable, - UINT64 PFAddress, - UINTN CpuIndex, - UINTN ErrorCode, - BOOLEAN *IsValidPFAddress + UINT64 *PageTable, + UINT64 PFAddress, + UINTN CpuIndex, + UINTN ErrorCode, + BOOLEAN *IsValidPFAddress ) { - UINTN PTIndex; - UINT64 Address; - BOOLEAN Nx; - BOOLEAN Existed; - UINTN Index; - UINTN PFIndex; - IA32_CR4 Cr4; - BOOLEAN Enable5LevelPaging; + UINTN PTIndex; + UINT64 Address; + BOOLEAN Nx; + BOOLEAN Existed; + UINTN Index; + UINTN PFIndex; + IA32_CR4 Cr4; + BOOLEAN Enable5LevelPaging; ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL)); - Cr4.UintN = AsmReadCr4 (); - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); + Cr4.UintN = AsmReadCr4 (); + Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); // // If page fault address is 4GB above. @@ -164,26 +164,28 @@ RestorePageTableAbove4G ( // If it exists in page table but page fault is generated, // there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range. // - Existed = FALSE; - PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK); - PTIndex = 0; + Existed = FALSE; + PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK); + PTIndex = 0; if (Enable5LevelPaging) { PTIndex = BitFieldRead64 (PFAddress, 48, 56); } + if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) { // PML5E if (Enable5LevelPaging) { - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); } + PTIndex = BitFieldRead64 (PFAddress, 39, 47); if ((PageTable[PTIndex] & IA32_PG_P) != 0) { // PML4E - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); - PTIndex = BitFieldRead64 (PFAddress, 30, 38); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PTIndex = BitFieldRead64 (PFAddress, 30, 38); if ((PageTable[PTIndex] & IA32_PG_P) != 0) { // PDPTE - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); - PTIndex = BitFieldRead64 (PFAddress, 21, 29); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PTIndex = BitFieldRead64 (PFAddress, 21, 29); // PD if ((PageTable[PTIndex] & IA32_PG_PS) != 0) { // @@ -197,7 +199,7 @@ RestorePageTableAbove4G ( // // 4KB page // - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK); if (PageTable != 0) { // // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB. @@ -217,7 +219,6 @@ RestorePageTableAbove4G ( // If page entry does not existed in page table at all, create a new entry. // if (!Existed) { - if (IsAddressValid (PFAddress, &Nx)) { // // If page fault address above 4GB is in protected range but it causes a page fault exception, @@ -234,19 +235,20 @@ RestorePageTableAbove4G ( // // Find the page table entry created just now. // - PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK); PFAddress = AsmReadCr2 (); // PML5E if (Enable5LevelPaging) { - PTIndex = BitFieldRead64 (PFAddress, 48, 56); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PTIndex = BitFieldRead64 (PFAddress, 48, 56); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); } + // PML4E - PTIndex = BitFieldRead64 (PFAddress, 39, 47); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PTIndex = BitFieldRead64 (PFAddress, 39, 47); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); // PDPTE - PTIndex = BitFieldRead64 (PFAddress, 30, 38); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PTIndex = BitFieldRead64 (PFAddress, 30, 38); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); // PD PTIndex = BitFieldRead64 (PFAddress, 21, 29); Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK; @@ -257,18 +259,21 @@ RestorePageTableAbove4G ( AcquirePage (&PageTable[PTIndex]); // PTE - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); + PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); for (Index = 0; Index < 512; Index++) { PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS; if (!IsAddressValid (Address, &Nx)) { PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); } + if (Nx && mXdSupported) { PageTable[Index] = PageTable[Index] | IA32_PG_NX; } + if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) { PTIndex = Index; } + Address += SIZE_4KB; } // end for PT } else { @@ -281,6 +286,7 @@ RestorePageTableAbove4G ( // PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); } + // // Set XD bit to 1 // @@ -297,7 +303,7 @@ RestorePageTableAbove4G ( // ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT); if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) { - PFIndex = mPFEntryCount[CpuIndex]; + PFIndex = mPFEntryCount[CpuIndex]; mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex]; mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex]; mPFEntryCount[CpuIndex]++; @@ -326,7 +332,7 @@ RestorePageTableAbove4G ( **/ VOID ClearTrapFlag ( - IN OUT EFI_SYSTEM_CONTEXT SystemContext + IN OUT EFI_SYSTEM_CONTEXT SystemContext ) { SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h index a857f587eb..80205c9b3e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h @@ -12,50 +12,50 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack (1) typedef struct _MSR_DS_AREA_STRUCT { - UINT64 BTSBufferBase; - UINT64 BTSIndex; - UINT64 BTSAbsoluteMaximum; - UINT64 BTSInterruptThreshold; - UINT64 PEBSBufferBase; - UINT64 PEBSIndex; - UINT64 PEBSAbsoluteMaximum; - UINT64 PEBSInterruptThreshold; - UINT64 PEBSCounterReset[2]; - UINT64 Reserved; + UINT64 BTSBufferBase; + UINT64 BTSIndex; + UINT64 BTSAbsoluteMaximum; + UINT64 BTSInterruptThreshold; + UINT64 PEBSBufferBase; + UINT64 PEBSIndex; + UINT64 PEBSAbsoluteMaximum; + UINT64 PEBSInterruptThreshold; + UINT64 PEBSCounterReset[2]; + UINT64 Reserved; } MSR_DS_AREA_STRUCT; typedef struct _BRANCH_TRACE_RECORD { - UINT64 LastBranchFrom; - UINT64 LastBranchTo; - UINT64 Rsvd0 : 4; - UINT64 BranchPredicted : 1; - UINT64 Rsvd1 : 59; + UINT64 LastBranchFrom; + UINT64 LastBranchTo; + UINT64 Rsvd0 : 4; + UINT64 BranchPredicted : 1; + UINT64 Rsvd1 : 59; } BRANCH_TRACE_RECORD; typedef struct _PEBS_RECORD { - UINT64 Rflags; - UINT64 LinearIP; - UINT64 Rax; - UINT64 Rbx; - UINT64 Rcx; - UINT64 Rdx; - UINT64 Rsi; - UINT64 Rdi; - UINT64 Rbp; - UINT64 Rsp; - UINT64 R8; - UINT64 R9; - UINT64 R10; - UINT64 R11; - UINT64 R12; - UINT64 R13; - UINT64 R14; - UINT64 R15; + UINT64 Rflags; + UINT64 LinearIP; + UINT64 Rax; + UINT64 Rbx; + UINT64 Rcx; + UINT64 Rdx; + UINT64 Rsi; + UINT64 Rdi; + UINT64 Rbp; + UINT64 Rsp; + UINT64 R8; + UINT64 R9; + UINT64 R10; + UINT64 R11; + UINT64 R12; + UINT64 R13; + UINT64 R14; + UINT64 R15; } PEBS_RECORD; #pragma pack () -#define PHYSICAL_ADDRESS_MASK ((1ull << 52) - SIZE_4KB) +#define PHYSICAL_ADDRESS_MASK ((1ull << 52) - SIZE_4KB) /** Update page table to map the memory correctly in order to make the instruction @@ -71,11 +71,11 @@ typedef struct _PEBS_RECORD { **/ VOID RestorePageTableAbove4G ( - UINT64 *PageTable, - UINT64 PFAddress, - UINTN CpuIndex, - UINTN ErrorCode, - BOOLEAN *IsValidPFAddress + UINT64 *PageTable, + UINT64 PFAddress, + UINTN CpuIndex, + UINTN ErrorCode, + BOOLEAN *IsValidPFAddress ); /** diff --git a/UefiCpuPkg/SecCore/FindPeiCore.c b/UefiCpuPkg/SecCore/FindPeiCore.c index ee063a1020..97adb68138 100644 --- a/UefiCpuPkg/SecCore/FindPeiCore.c +++ b/UefiCpuPkg/SecCore/FindPeiCore.c @@ -21,35 +21,34 @@ EFI_STATUS EFIAPI FindImageBase ( - IN EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumePtr, - IN EFI_FV_FILETYPE FileType, - OUT EFI_PHYSICAL_ADDRESS *CoreImageBase + IN EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumePtr, + IN EFI_FV_FILETYPE FileType, + OUT EFI_PHYSICAL_ADDRESS *CoreImageBase ) { - EFI_PHYSICAL_ADDRESS CurrentAddress; - EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; - EFI_FFS_FILE_HEADER *File; - UINT32 Size; - EFI_PHYSICAL_ADDRESS EndOfFile; - EFI_COMMON_SECTION_HEADER *Section; - EFI_PHYSICAL_ADDRESS EndOfSection; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; *CoreImageBase = 0; - CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) FirmwareVolumePtr; + CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)FirmwareVolumePtr; EndOfFirmwareVolume = CurrentAddress + FirmwareVolumePtr->FvLength; // // Loop through the FFS files in the Boot Firmware Volume // for (EndOfFile = CurrentAddress + FirmwareVolumePtr->HeaderLength; ; ) { - CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL; if (CurrentAddress > EndOfFirmwareVolume) { return EFI_NOT_FOUND; } - File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress; + File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; if (IS_FFS_FILE2 (File)) { Size = FFS_FILE2_SIZE (File); if (Size <= 0x00FFFFFF) { @@ -78,13 +77,14 @@ FindImageBase ( // Loop through the FFS file sections within the FFS file // if (IS_FFS_FILE2 (File)) { - EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2)); + EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)((UINT8 *)File + sizeof (EFI_FFS_FILE_HEADER2)); } else { - EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER)); + EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)((UINT8 *)File + sizeof (EFI_FFS_FILE_HEADER)); } - for (;;) { + + for ( ; ;) { CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL; - Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress; + Section = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress; if (IS_SECTION2 (Section)) { Size = SECTION2_SIZE (Section); @@ -106,14 +106,15 @@ FindImageBase ( // // Look for executable sections // - if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) { + if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) { if (File->Type == FileType) { if (IS_SECTION2 (Section)) { - *CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2)); + *CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2)); } else { - *CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER)); + *CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER)); } } + break; } } @@ -141,15 +142,15 @@ FindImageBase ( VOID EFIAPI FindAndReportEntryPoints ( - IN EFI_FIRMWARE_VOLUME_HEADER *SecCoreFirmwareVolumePtr, - IN EFI_FIRMWARE_VOLUME_HEADER *PeiCoreFirmwareVolumePtr, - OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + IN EFI_FIRMWARE_VOLUME_HEADER *SecCoreFirmwareVolumePtr, + IN EFI_FIRMWARE_VOLUME_HEADER *PeiCoreFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS SecCoreImageBase; - EFI_PHYSICAL_ADDRESS PeiCoreImageBase; - PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS SecCoreImageBase; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; // // Find SEC Core image base @@ -157,12 +158,12 @@ FindAndReportEntryPoints ( Status = FindImageBase (SecCoreFirmwareVolumePtr, EFI_FV_FILETYPE_SECURITY_CORE, &SecCoreImageBase); ASSERT_EFI_ERROR (Status); - ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT)); + ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT)); // // Report SEC Core debug information when remote debug is enabled // ImageContext.ImageAddress = SecCoreImageBase; - ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress); + ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress); PeCoffLoaderRelocateImageExtraAction (&ImageContext); // @@ -175,13 +176,13 @@ FindAndReportEntryPoints ( // Report PEI Core debug information when remote debug is enabled // ImageContext.ImageAddress = PeiCoreImageBase; - ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress); + ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress); PeCoffLoaderRelocateImageExtraAction (&ImageContext); // // Find PEI Core entry point // - Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint); + Status = PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (VOID **)PeiCoreEntryPoint); if (EFI_ERROR (Status)) { *PeiCoreEntryPoint = 0; } diff --git a/UefiCpuPkg/SecCore/SecBist.c b/UefiCpuPkg/SecCore/SecBist.c index 440140f565..cd2e340171 100644 --- a/UefiCpuPkg/SecCore/SecBist.c +++ b/UefiCpuPkg/SecCore/SecBist.c @@ -8,21 +8,21 @@ #include "SecMain.h" -EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformation = { +EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformation = { SecPlatformInformationBist }; -EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation = { +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiSecPlatformInformationPpiGuid, &mSecPlatformInformation }; -EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2 = { +EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2 = { SecPlatformInformation2Bist }; -EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2 = { +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2 = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiSecPlatformInformation2PpiGuid, &mSecPlatformInformation2 @@ -40,13 +40,13 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2 = { **/ EFI_STATUS GetBistFromHob ( - IN OUT UINT64 *StructureSize, - IN OUT VOID *StructureBuffer + IN OUT UINT64 *StructureSize, + IN OUT VOID *StructureBuffer ) { - EFI_HOB_GUID_TYPE *GuidHob; - VOID *DataInHob; - UINTN DataSize; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *DataInHob; + UINTN DataSize; GuidHob = GetFirstGuidHob (&gEfiCallerIdGuid); if (GuidHob == NULL) { @@ -60,12 +60,12 @@ GetBistFromHob ( // // return the information from BistHob // - if ((*StructureSize) < (UINT64) DataSize) { - *StructureSize = (UINT64) DataSize; + if ((*StructureSize) < (UINT64)DataSize) { + *StructureSize = (UINT64)DataSize; return EFI_BUFFER_TOO_SMALL; } - *StructureSize = (UINT64) DataSize; + *StructureSize = (UINT64)DataSize; CopyMem (StructureBuffer, DataInHob, DataSize); return EFI_SUCCESS; } @@ -84,9 +84,9 @@ GetBistFromHob ( EFI_STATUS EFIAPI SecPlatformInformationBist ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ) { return GetBistFromHob (StructureSize, PlatformInformationRecord); @@ -107,9 +107,9 @@ SecPlatformInformationBist ( EFI_STATUS EFIAPI SecPlatformInformation2Bist ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 ) { return GetBistFromHob (StructureSize, PlatformInformationRecord2); @@ -133,11 +133,11 @@ SecPlatformInformation2Bist ( **/ EFI_STATUS GetBistInfoFromPpi ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN CONST EFI_GUID *Guid, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, - OUT VOID **BistInformationData, - OUT UINT64 *BistInformationSize OPTIONAL + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_GUID *Guid, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, + OUT VOID **BistInformationData, + OUT UINT64 *BistInformationSize OPTIONAL ) { EFI_STATUS Status; @@ -161,15 +161,15 @@ GetBistInfoFromPpi ( // InformationSize = 0; SecPlatformInformation2 = NULL; - Status = SecPlatformInformation2Ppi->PlatformInformation2 ( - PeiServices, - &InformationSize, - SecPlatformInformation2 - ); + Status = SecPlatformInformation2Ppi->PlatformInformation2 ( + PeiServices, + &InformationSize, + SecPlatformInformation2 + ); if (Status == EFI_BUFFER_TOO_SMALL) { Status = PeiServicesAllocatePool ( - (UINTN) InformationSize, - (VOID **) &SecPlatformInformation2 + (UINTN)InformationSize, + (VOID **)&SecPlatformInformation2 ); if (Status == EFI_SUCCESS) { // @@ -185,6 +185,7 @@ GetBistInfoFromPpi ( if (BistInformationSize != NULL) { *BistInformationSize = InformationSize; } + return EFI_SUCCESS; } } @@ -203,25 +204,25 @@ RepublishSecPlatformInformationPpi ( VOID ) { - EFI_STATUS Status; - CONST EFI_PEI_SERVICES **PeiServices; - UINT64 BistInformationSize; - VOID *BistInformationData; - EFI_PEI_PPI_DESCRIPTOR *SecInformationDescriptor; + EFI_STATUS Status; + CONST EFI_PEI_SERVICES **PeiServices; + UINT64 BistInformationSize; + VOID *BistInformationData; + EFI_PEI_PPI_DESCRIPTOR *SecInformationDescriptor; PeiServices = GetPeiServicesTablePointer (); - Status = GetBistInfoFromPpi ( - PeiServices, - &gEfiSecPlatformInformation2PpiGuid, - &SecInformationDescriptor, - &BistInformationData, - &BistInformationSize - ); + Status = GetBistInfoFromPpi ( + PeiServices, + &gEfiSecPlatformInformation2PpiGuid, + &SecInformationDescriptor, + &BistInformationData, + &BistInformationSize + ); if (Status == EFI_SUCCESS) { BuildGuidDataHob ( &gEfiCallerIdGuid, BistInformationData, - (UINTN) BistInformationSize + (UINTN)BistInformationSize ); // // The old SecPlatformInformation2 data is on temporary memory. @@ -232,7 +233,9 @@ RepublishSecPlatformInformationPpi ( SecInformationDescriptor, &mPeiSecPlatformInformation2 ); - } if (Status == EFI_NOT_FOUND) { + } + + if (Status == EFI_NOT_FOUND) { Status = GetBistInfoFromPpi ( PeiServices, &gEfiSecPlatformInformationPpiGuid, @@ -244,7 +247,7 @@ RepublishSecPlatformInformationPpi ( BuildGuidDataHob ( &gEfiCallerIdGuid, BistInformationData, - (UINTN) BistInformationSize + (UINTN)BistInformationSize ); // // The old SecPlatformInformation data is on temporary memory. @@ -260,5 +263,5 @@ RepublishSecPlatformInformationPpi ( } } - ASSERT_EFI_ERROR(Status); + ASSERT_EFI_ERROR (Status); } diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 2416c4ce56..a7526be9dd 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -8,20 +8,20 @@ #include "SecMain.h" -EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = { +EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = { SecTemporaryRamDone }; EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPpi = { SecPlatformInformation }; -EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = { +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = { { // // SecPerformance PPI notify descriptor. // EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, &gPeiSecPerformancePpiGuid, - (VOID *) (UINTN) SecPerformancePpiCallBack + (VOID *)(UINTN)SecPerformancePpiCallBack }, { EFI_PEI_PPI_DESCRIPTOR_PPI, @@ -47,12 +47,12 @@ MigrateGdt ( VOID ) { - EFI_STATUS Status; - UINTN GdtBufferSize; - IA32_DESCRIPTOR Gdtr; - VOID *GdtBuffer; + EFI_STATUS Status; + UINTN GdtBufferSize; + IA32_DESCRIPTOR Gdtr; + VOID *GdtBuffer; - AsmReadGdtr ((IA32_DESCRIPTOR *) &Gdtr); + AsmReadGdtr ((IA32_DESCRIPTOR *)&Gdtr); GdtBufferSize = sizeof (IA32_SEGMENT_DESCRIPTOR) -1 + Gdtr.Limit + 1; Status = PeiServicesAllocatePool ( @@ -65,8 +65,8 @@ MigrateGdt ( } GdtBuffer = ALIGN_POINTER (GdtBuffer, sizeof (IA32_SEGMENT_DESCRIPTOR)); - CopyMem (GdtBuffer, (VOID *) Gdtr.Base, Gdtr.Limit + 1); - Gdtr.Base = (UINTN) GdtBuffer; + CopyMem (GdtBuffer, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base = (UINTN)GdtBuffer; AsmWriteGdtr (&Gdtr); return EFI_SUCCESS; @@ -90,8 +90,8 @@ UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL; VOID NORETURN EFIAPI -SecStartupPhase2( - IN VOID *Context +SecStartupPhase2 ( + IN VOID *Context ); /** @@ -114,18 +114,18 @@ SecPerformancePpiCallBack ( IN VOID *Ppi ) { - EFI_STATUS Status; - PEI_SEC_PERFORMANCE_PPI *SecPerf; - FIRMWARE_SEC_PERFORMANCE Performance; + EFI_STATUS Status; + PEI_SEC_PERFORMANCE_PPI *SecPerf; + FIRMWARE_SEC_PERFORMANCE Performance; - SecPerf = (PEI_SEC_PERFORMANCE_PPI *) Ppi; - Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **) PeiServices, SecPerf, &Performance); + SecPerf = (PEI_SEC_PERFORMANCE_PPI *)Ppi; + Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **)PeiServices, SecPerf, &Performance); if (!EFI_ERROR (Status)) { BuildGuidDataHob ( &gEfiFirmwarePerformanceGuid, &Performance, sizeof (FIRMWARE_SEC_PERFORMANCE) - ); + ); DEBUG ((DEBUG_INFO, "FPDT: SEC Performance Hob ResetEnd = %ld\n", Performance.ResetEnd)); } @@ -147,17 +147,17 @@ VOID NORETURN EFIAPI SecStartup ( - IN UINT32 SizeOfRam, - IN UINT32 TempRamBase, - IN VOID *BootFirmwareVolume + IN UINT32 SizeOfRam, + IN UINT32 TempRamBase, + IN VOID *BootFirmwareVolume ) { - EFI_SEC_PEI_HAND_OFF SecCoreData; - IA32_DESCRIPTOR IdtDescriptor; - SEC_IDT_TABLE IdtTableInStack; - UINT32 Index; - UINT32 PeiStackSize; - EFI_STATUS Status; + EFI_SEC_PEI_HAND_OFF SecCoreData; + IA32_DESCRIPTOR IdtDescriptor; + SEC_IDT_TABLE IdtTableInStack; + UINT32 Index; + UINT32 PeiStackSize; + EFI_STATUS Status; // // Report Status Code to indicate entering SEC core @@ -201,11 +201,11 @@ SecStartup ( // |-------------------|----> TempRamBase IdtTableInStack.PeiService = 0; - for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { - CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64)); + for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) { + CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&mIdtEntryTemplate, sizeof (UINT64)); } - IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable; + IdtDescriptor.Base = (UINTN)&IdtTableInStack.IdtTable; IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1); AsmWriteIdtr (&IdtDescriptor); @@ -219,14 +219,14 @@ SecStartup ( // // Update the base address and length of Pei temporary memory // - SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF); + SecCoreData.DataSize = (UINT16)sizeof (EFI_SEC_PEI_HAND_OFF); SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume; - SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *) BootFirmwareVolume)->FvLength; - SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase; + SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength; + SecCoreData.TemporaryRamBase = (VOID *)(UINTN)TempRamBase; SecCoreData.TemporaryRamSize = SizeOfRam; SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize; - SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize); + SecCoreData.StackBase = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize); SecCoreData.StackSize = PeiStackSize; // @@ -253,18 +253,18 @@ SecStartup ( VOID NORETURN EFIAPI -SecStartupPhase2( - IN VOID *Context +SecStartupPhase2 ( + IN VOID *Context ) { - EFI_SEC_PEI_HAND_OFF *SecCoreData; - EFI_PEI_PPI_DESCRIPTOR *PpiList; - UINT32 Index; - EFI_PEI_PPI_DESCRIPTOR *AllSecPpiList; - EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_SEC_PEI_HAND_OFF *SecCoreData; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINT32 Index; + EFI_PEI_PPI_DESCRIPTOR *AllSecPpiList; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; PeiCoreEntryPoint = NULL; - SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context; + SecCoreData = (EFI_SEC_PEI_HAND_OFF *)Context; // // Perform platform specific initialization before entering PeiCore. @@ -278,14 +278,15 @@ SecStartupPhase2( Index = 0; do { if (CompareGuid (PpiList[Index].Guid, &gEfiPeiCoreFvLocationPpiGuid) && - (((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation != 0) - ) { + (((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation != 0) + ) + { // // In this case, SecCore is in BFV but PeiCore is in another FV reported by PPI. // FindAndReportEntryPoints ( - (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, - (EFI_FIRMWARE_VOLUME_HEADER *) ((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation, + (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase, + (EFI_FIRMWARE_VOLUME_HEADER *)((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation, &PeiCoreEntryPoint ); if (PeiCoreEntryPoint != NULL) { @@ -299,6 +300,7 @@ SecStartupPhase2( } } while ((PpiList[Index++].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST); } + // // If EFI_PEI_CORE_FV_LOCATION_PPI not found, try to locate PeiCore from BFV. // @@ -307,8 +309,8 @@ SecStartupPhase2( // Both SecCore and PeiCore are in BFV. // FindAndReportEntryPoints ( - (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, - (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, + (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase, + (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint ); if (PeiCoreEntryPoint == NULL) { @@ -317,13 +319,13 @@ SecStartupPhase2( } if (PpiList != NULL) { - AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase; + AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase; // // Remove the terminal flag from the terminal PPI // CopyMem (AllSecPpiList, mPeiSecPlatformInformationPpi, sizeof (mPeiSecPlatformInformationPpi)); - Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1; + Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1; AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST); // @@ -339,7 +341,7 @@ SecStartupPhase2( // // Add the terminal PPI // - CopyMem (&AllSecPpiList[Index ++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR)); + CopyMem (&AllSecPpiList[Index++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR)); // // Set PpiList to the total PPI @@ -350,13 +352,13 @@ SecStartupPhase2( // Adjust PEI TEMP RAM Range. // ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); - SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); + SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR); // // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement // will be built based on them in PEI phase. // - SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07); + SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07); SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07; } else { // @@ -370,7 +372,7 @@ SecStartupPhase2( "%a() Stack Base: 0x%p, Stack Size: 0x%x\n", __FUNCTION__, SecCoreData->StackBase, - (UINT32) SecCoreData->StackSize + (UINT32)SecCoreData->StackSize )); // @@ -385,7 +387,7 @@ SecStartupPhase2( // Transfer the control to the PEI core // ASSERT (PeiCoreEntryPoint != NULL); - (*PeiCoreEntryPoint) (SecCoreData, PpiList); + (*PeiCoreEntryPoint)(SecCoreData, PpiList); // // Should not come here. @@ -407,12 +409,12 @@ SecTemporaryRamDone ( VOID ) { - EFI_STATUS Status; - EFI_STATUS Status2; - UINTN Index; - BOOLEAN State; - EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; - REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi; + EFI_STATUS Status; + EFI_STATUS Status2; + UINTN Index; + BOOLEAN State; + EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; + REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi; // // Republish Sec Platform Information(2) PPI @@ -427,7 +429,7 @@ SecTemporaryRamDone ( &gRepublishSecPpiPpiGuid, Index, &PeiPpiDescriptor, - (VOID **) &RepublishSecPpiPpi + (VOID **)&RepublishSecPpiPpi ); if (!EFI_ERROR (Status)) { DEBUG ((DEBUG_INFO, "Calling RepublishSecPpi instance %d.\n", Index)); diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h index e20bcf8653..029bee3e7e 100644 --- a/UefiCpuPkg/SecCore/SecMain.h +++ b/UefiCpuPkg/SecCore/SecMain.h @@ -42,8 +42,8 @@ typedef struct _SEC_IDT_TABLE { // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store // EFI_PEI_SERVICES** // - UINT64 PeiService; - UINT64 IdtTable[SEC_IDT_ENTRY_COUNT]; + UINT64 PeiService; + UINT64 IdtTable[SEC_IDT_ENTRY_COUNT]; } SEC_IDT_TABLE; /** @@ -73,9 +73,9 @@ VOID NORETURN EFIAPI SecStartup ( - IN UINT32 SizeOfRam, - IN UINT32 TempRamBase, - IN VOID *BootFirmwareVolume + IN UINT32 SizeOfRam, + IN UINT32 TempRamBase, + IN VOID *BootFirmwareVolume ); /** @@ -92,9 +92,9 @@ SecStartup ( VOID EFIAPI FindAndReportEntryPoints ( - IN EFI_FIRMWARE_VOLUME_HEADER *SecCoreFirmwareVolumePtr, - IN EFI_FIRMWARE_VOLUME_HEADER *PeiCoreFirmwareVolumePtr, - OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + IN EFI_FIRMWARE_VOLUME_HEADER *SecCoreFirmwareVolumePtr, + IN EFI_FIRMWARE_VOLUME_HEADER *PeiCoreFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint ); /** @@ -123,9 +123,9 @@ ProcessLibraryConstructorList ( EFI_STATUS EFIAPI SecPlatformInformationBist ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ); /** @@ -143,9 +143,9 @@ SecPlatformInformationBist ( EFI_STATUS EFIAPI SecPlatformInformation2Bist ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 ); /** diff --git a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c index 4813a06f13..363d44b8ff 100644 --- a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c +++ b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c @@ -19,55 +19,54 @@ #include "SecMigrationPei.h" STATIC REPUBLISH_SEC_PPI_PPI mEdkiiRepublishSecPpiPpi = { - RepublishSecPpis - }; + RepublishSecPpis +}; GLOBAL_REMOVE_IF_UNREFERENCED EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPostMemoryPpi = { - SecPlatformInformationPostMemory - }; + SecPlatformInformationPostMemory +}; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_DONE_PPI mSecTemporaryRamDonePostMemoryPpi = { + SecTemporaryRamDonePostMemory +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_DONE_PPI mSecTemporaryRamDonePostMemoryPpi = { - SecTemporaryRamDonePostMemory - }; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPostMemoryPpi = { + SecTemporaryRamSupportPostMemory +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPostMemoryPpi = { - SecTemporaryRamSupportPostMemory - }; +GLOBAL_REMOVE_IF_UNREFERENCED PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = { + GetPerformancePostMemory +}; -GLOBAL_REMOVE_IF_UNREFERENCED PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = { - GetPerformancePostMemory - }; - -STATIC EFI_PEI_PPI_DESCRIPTOR mEdkiiRepublishSecPpiDescriptor = { +STATIC EFI_PEI_PPI_DESCRIPTOR mEdkiiRepublishSecPpiDescriptor = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gRepublishSecPpiPpiGuid, &mEdkiiRepublishSecPpiPpi - }; +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPlatformInformationPostMemoryDescriptor = { +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPlatformInformationPostMemoryDescriptor = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiSecPlatformInformationPpiGuid, &mSecPlatformInformationPostMemoryPpi - }; +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamDonePostMemoryDescriptor = { +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamDonePostMemoryDescriptor = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiTemporaryRamDonePpiGuid, &mSecTemporaryRamDonePostMemoryPpi - }; +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamSupportPostMemoryDescriptor = { +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamSupportPostMemoryDescriptor = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiTemporaryRamSupportPpiGuid, &mSecTemporaryRamSupportPostMemoryPpi - }; +}; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPerformancePpiDescriptor = { +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPerformancePpiDescriptor = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gPeiSecPerformancePpiGuid, &mSecPerformancePpi - }; +}; /** Disables the use of Temporary RAM. @@ -110,10 +109,10 @@ SecTemporaryRamDonePostMemory ( EFI_STATUS EFIAPI SecTemporaryRamSupportPostMemory ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize ) { // @@ -151,7 +150,7 @@ GetPerformancePostMemory ( { SEC_PLATFORM_INFORMATION_CONTEXT_HOB *SecPlatformInformationContexHob; - if (This == NULL || Performance == NULL) { + if ((This == NULL) || (Performance == NULL)) { return EFI_INVALID_PARAMETER; } @@ -182,9 +181,9 @@ GetPerformancePostMemory ( EFI_STATUS EFIAPI SecPlatformInformationPostMemory ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ) { SEC_PLATFORM_INFORMATION_CONTEXT_HOB *SecPlatformInformationContexHob; @@ -209,9 +208,9 @@ SecPlatformInformationPostMemory ( *StructureSize = SecPlatformInformationContexHob->Context.StructureSize; CopyMem ( - (VOID *) PlatformInformationRecord, - (VOID *) SecPlatformInformationContexHob->Context.PlatformInformationRecord, - (UINTN) SecPlatformInformationContexHob->Context.StructureSize + (VOID *)PlatformInformationRecord, + (VOID *)SecPlatformInformationContexHob->Context.PlatformInformationRecord, + (UINTN)SecPlatformInformationContexHob->Context.StructureSize ); return EFI_SUCCESS; @@ -241,13 +240,13 @@ RepublishSecPpis ( UINT64 SecStructureSize; SecPlatformInformationPtr = NULL; - SecStructureSize = 0; + SecStructureSize = 0; Status = PeiServicesLocatePpi ( &gEfiTemporaryRamDonePpiGuid, 0, &PeiPpiDescriptor, - (VOID **) &PeiPpi + (VOID **)&PeiPpi ); if (!EFI_ERROR (Status)) { Status = PeiServicesReInstallPpi ( @@ -261,7 +260,7 @@ RepublishSecPpis ( &gEfiTemporaryRamSupportPpiGuid, 0, &PeiPpiDescriptor, - (VOID **) &PeiPpi + (VOID **)&PeiPpi ); if (!EFI_ERROR (Status)) { Status = PeiServicesReInstallPpi ( @@ -274,7 +273,7 @@ RepublishSecPpis ( Status = PeiServicesCreateHob ( EFI_HOB_TYPE_GUID_EXTENSION, sizeof (SEC_PLATFORM_INFORMATION_CONTEXT_HOB), - (VOID **) &SecPlatformInformationContextHob + (VOID **)&SecPlatformInformationContextHob ); ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { @@ -289,14 +288,14 @@ RepublishSecPpis ( &gPeiSecPerformancePpiGuid, 0, &PeiPpiDescriptor, - (VOID **) &PeiPpi + (VOID **)&PeiPpi ); if (!EFI_ERROR (Status)) { - Status = ((PEI_SEC_PERFORMANCE_PPI *) PeiPpi)->GetPerformance ( - GetPeiServicesTablePointer (), - (PEI_SEC_PERFORMANCE_PPI *) PeiPpi, - &SecPlatformInformationContextHob->FirmwareSecPerformance - ); + Status = ((PEI_SEC_PERFORMANCE_PPI *)PeiPpi)->GetPerformance ( + GetPeiServicesTablePointer (), + (PEI_SEC_PERFORMANCE_PPI *)PeiPpi, + &SecPlatformInformationContextHob->FirmwareSecPerformance + ); ASSERT_EFI_ERROR (Status); if (!EFI_ERROR (Status)) { Status = PeiServicesReInstallPpi ( @@ -311,32 +310,33 @@ RepublishSecPpis ( &gEfiSecPlatformInformationPpiGuid, 0, &PeiPpiDescriptor, - (VOID **) &PeiPpi + (VOID **)&PeiPpi ); if (!EFI_ERROR (Status)) { - Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *) PeiPpi)->PlatformInformation ( - GetPeiServicesTablePointer (), - &SecStructureSize, - SecPlatformInformationPtr - ); + Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *)PeiPpi)->PlatformInformation ( + GetPeiServicesTablePointer (), + &SecStructureSize, + SecPlatformInformationPtr + ); ASSERT (Status == EFI_BUFFER_TOO_SMALL); if (Status != EFI_BUFFER_TOO_SMALL) { return EFI_NOT_FOUND; } - ZeroMem ((VOID *) &(SecPlatformInformationContextHob->Context), sizeof (SEC_PLATFORM_INFORMATION_CONTEXT)); - SecPlatformInformationContextHob->Context.PlatformInformationRecord = AllocatePool ((UINTN) SecStructureSize); + ZeroMem ((VOID *)&(SecPlatformInformationContextHob->Context), sizeof (SEC_PLATFORM_INFORMATION_CONTEXT)); + SecPlatformInformationContextHob->Context.PlatformInformationRecord = AllocatePool ((UINTN)SecStructureSize); ASSERT (SecPlatformInformationContextHob->Context.PlatformInformationRecord != NULL); if (SecPlatformInformationContextHob->Context.PlatformInformationRecord == NULL) { return EFI_OUT_OF_RESOURCES; } + SecPlatformInformationContextHob->Context.StructureSize = SecStructureSize; - Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *) PeiPpi)->PlatformInformation ( - GetPeiServicesTablePointer (), - &(SecPlatformInformationContextHob->Context.StructureSize), - SecPlatformInformationContextHob->Context.PlatformInformationRecord - ); + Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *)PeiPpi)->PlatformInformation ( + GetPeiServicesTablePointer (), + &(SecPlatformInformationContextHob->Context.StructureSize), + SecPlatformInformationContextHob->Context.PlatformInformationRecord + ); ASSERT_EFI_ERROR (Status); if (!EFI_ERROR (Status)) { Status = PeiServicesReInstallPpi ( diff --git a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h index 2d28490d9e..9919c8af76 100644 --- a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h +++ b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h @@ -36,9 +36,9 @@ EFI_STATUS EFIAPI SecPlatformInformationPostMemory ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN OUT UINT64 *StructureSize, - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord ); /** @@ -55,9 +55,9 @@ SecPlatformInformationPostMemory ( EFI_STATUS EFIAPI SecPlatformInformationPpiNotifyCallback ( - IN EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi ); /** @@ -110,10 +110,10 @@ SecTemporaryRamDonePostMemory ( EFI_STATUS EFIAPI SecTemporaryRamSupportPostMemory ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize ); /** @@ -143,16 +143,16 @@ GetPerformancePostMemory ( ); typedef struct { - UINT64 StructureSize; - EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord; + UINT64 StructureSize; + EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord; } SEC_PLATFORM_INFORMATION_CONTEXT; typedef struct { - EFI_HOB_GUID_TYPE Header; - UINT8 Revision; - UINT8 Reserved[3]; - FIRMWARE_SEC_PERFORMANCE FirmwareSecPerformance; - SEC_PLATFORM_INFORMATION_CONTEXT Context; + EFI_HOB_GUID_TYPE Header; + UINT8 Revision; + UINT8 Reserved[3]; + FIRMWARE_SEC_PERFORMANCE FirmwareSecPerformance; + SEC_PLATFORM_INFORMATION_CONTEXT Context; } SEC_PLATFORM_INFORMATION_CONTEXT_HOB; #endif diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c index 6fa907161a..8419a4e32a 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -58,21 +58,21 @@ #pragma pack(1) typedef union { struct { - UINT32 LimitLow : 16; - UINT32 BaseLow : 16; - UINT32 BaseMid : 8; - UINT32 Type : 4; - UINT32 System : 1; - UINT32 Dpl : 2; - UINT32 Present : 1; - UINT32 LimitHigh : 4; - UINT32 Software : 1; - UINT32 Reserved : 1; - UINT32 DefaultSize : 1; - UINT32 Granularity : 1; - UINT32 BaseHigh : 8; + UINT32 LimitLow : 16; + UINT32 BaseLow : 16; + UINT32 BaseMid : 8; + UINT32 Type : 4; + UINT32 System : 1; + UINT32 Dpl : 2; + UINT32 Present : 1; + UINT32 LimitHigh : 4; + UINT32 Software : 1; + UINT32 Reserved : 1; + UINT32 DefaultSize : 1; + UINT32 Granularity : 1; + UINT32 BaseHigh : 8; } Bits; - UINT64 Uint64; + UINT64 Uint64; } IA32_GDT; // @@ -81,18 +81,18 @@ typedef union { // typedef union { struct { - UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory - UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write - UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User - UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching - UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached - UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) - UINT64 Reserved:1; // Reserved - UINT64 MustBeZero:2; // Must Be Zero - UINT64 Available:3; // Available for use by system software - UINT64 PageTableBaseAddress:40; // Page Table Base Address - UINT64 AvabilableHigh:11; // Available for use by system software - UINT64 Nx:1; // No Execute bit + UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory + UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write + UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User + UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching + UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached + UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) + UINT64 Reserved : 1; // Reserved + UINT64 MustBeZero : 2; // Must Be Zero + UINT64 Available : 3; // Available for use by system software + UINT64 PageTableBaseAddress : 40; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system software + UINT64 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } PAGE_MAP_AND_DIRECTORY_POINTER; @@ -102,21 +102,21 @@ typedef union { // typedef union { struct { - UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory - UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write - UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User - UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching - UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached - UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) - UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page - UINT64 MustBe1:1; // Must be 1 - UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write - UINT64 Available:3; // Available for use by system software - UINT64 PAT:1; // - UINT64 MustBeZero:8; // Must be zero; - UINT64 PageTableBaseAddress:31; // Page Table Base Address - UINT64 AvabilableHigh:11; // Available for use by system software - UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution + UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory + UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write + UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User + UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching + UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached + UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) + UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page + UINT64 MustBe1 : 1; // Must be 1 + UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write + UINT64 Available : 3; // Available for use by system software + UINT64 PAT : 1; // + UINT64 MustBeZero : 8; // Must be zero; + UINT64 PageTableBaseAddress : 31; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system software + UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution } Bits; UINT64 Uint64; } PAGE_TABLE_ENTRY; @@ -126,21 +126,21 @@ typedef union { // typedef union { struct { - UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory - UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write - UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User - UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching - UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached - UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) - UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page - UINT64 MustBe1:1; // Must be 1 - UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write - UINT64 Available:3; // Available for use by system software - UINT64 PAT:1; // - UINT64 MustBeZero:17; // Must be zero; - UINT64 PageTableBaseAddress:22; // Page Table Base Address - UINT64 AvabilableHigh:11; // Available for use by system software - UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution + UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory + UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write + UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User + UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching + UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached + UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) + UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page + UINT64 MustBe1 : 1; // Must be 1 + UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write + UINT64 Available : 3; // Available for use by system software + UINT64 PAT : 1; // + UINT64 MustBeZero : 17; // Must be zero; + UINT64 PageTableBaseAddress : 22; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system software + UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution } Bits; UINT64 Uint64; } PAGE_TABLE_1G_ENTRY; @@ -150,15 +150,15 @@ typedef union { // One for 32 bits PEI + 64 bits DXE, the other for 32 bits PEI + 32 bits DXE case. // typedef struct { - EFI_GUID HeaderGuid; - UINT32 MessageLength; - UINT8 Data[1]; + EFI_GUID HeaderGuid; + UINT32 MessageLength; + UINT8 Data[1]; } SMM_COMMUNICATE_HEADER_32; typedef struct { - EFI_GUID HeaderGuid; - UINT64 MessageLength; - UINT8 Data[1]; + EFI_GUID HeaderGuid; + UINT64 MessageLength; + UINT8 Data[1]; } SMM_COMMUNICATE_HEADER_64; #pragma pack() @@ -166,6 +166,7 @@ typedef struct { // // Function prototypes // + /** a ASM function to transfer control to OS. @@ -174,7 +175,7 @@ typedef struct { **/ typedef VOID -(EFIAPI *ASM_TRANSFER_CONTROL) ( +(EFIAPI *ASM_TRANSFER_CONTROL)( IN UINT32 S3WakingVector, IN UINT32 AcpiLowMemoryBase ); @@ -225,33 +226,33 @@ S3RestoreConfig2 ( VOID EFIAPI AsmSetDataSelectors ( - IN UINT16 SelectorValue + IN UINT16 SelectorValue ); // // Globals // -EFI_PEI_S3_RESUME2_PPI mS3ResumePpi = { S3RestoreConfig2 }; +EFI_PEI_S3_RESUME2_PPI mS3ResumePpi = { S3RestoreConfig2 }; -EFI_PEI_PPI_DESCRIPTOR mPpiList = { +EFI_PEI_PPI_DESCRIPTOR mPpiList = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiPeiS3Resume2PpiGuid, &mS3ResumePpi }; -EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable = { +EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gPeiPostScriptTablePpiGuid, 0 }; -EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable = { +EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEfiEndOfPeiSignalPpiGuid, 0 }; -EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = { +EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), &gEdkiiS3SmmInitDoneGuid, 0 @@ -260,29 +261,46 @@ EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = { // // Global Descriptor Table (GDT) // -GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = { -/* selector { Global Segment Descriptor } */ -/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, -/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, -/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, -/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, -/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, -/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, -/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, -/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}}, -/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, +GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = { + /* selector { Global Segment Descriptor } */ + /* 0x00 */ { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + /* 0x08 */ { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + /* 0x10 */ { + { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 } + }, + /* 0x18 */ { + { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 } + }, + /* 0x20 */ { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + /* 0x28 */ { + { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 } + }, + /* 0x30 */ { + { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 } + }, + /* 0x38 */ { + { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0 } + }, + /* 0x40 */ { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, }; -#define DATA_SEGEMENT_SELECTOR 0x18 +#define DATA_SEGEMENT_SELECTOR 0x18 // // IA32 Gdt register // -GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = { +GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = { sizeof (mGdtEntries) - 1, - (UINTN) mGdtEntries - }; - + (UINTN)mGdtEntries +}; /** The function will check if current waking vector is long mode. @@ -294,28 +312,32 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = { **/ BOOLEAN IsLongModeWakingVector ( - IN ACPI_S3_CONTEXT *AcpiS3Context + IN ACPI_S3_CONTEXT *AcpiS3Context ) { EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs; - Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)); + Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)); if ((Facs == NULL) || (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) || - ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) { + ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0))) + { // Something wrong with FACS return FALSE; } + if (Facs->XFirmwareWakingVector != 0) { if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) && ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) && - ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) { + ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) + { // Both BIOS and OS wants 64bit vector if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { return TRUE; } } } + return FALSE; } @@ -327,15 +349,15 @@ IsLongModeWakingVector ( **/ VOID SignalToSmmByCommunication ( - IN EFI_GUID *HandlerType + IN EFI_GUID *HandlerType ) { - EFI_STATUS Status; - EFI_PEI_SMM_COMMUNICATION_PPI *SmmCommunicationPpi; - UINTN CommSize; - SMM_COMMUNICATE_HEADER_32 Header32; - SMM_COMMUNICATE_HEADER_64 Header64; - VOID *CommBuffer; + EFI_STATUS Status; + EFI_PEI_SMM_COMMUNICATION_PPI *SmmCommunicationPpi; + UINTN CommSize; + SMM_COMMUNICATE_HEADER_32 Header32; + SMM_COMMUNICATE_HEADER_64 Header64; + VOID *CommBuffer; DEBUG ((DEBUG_INFO, "Signal %g to SMM - Enter\n", HandlerType)); @@ -345,15 +367,16 @@ SignalToSmmByCommunication ( // if (sizeof(UINTN) == sizeof(UINT64), PEI already 64 bits, assume DXE also 64 bits. // or (FeaturePcdGet (PcdDxeIplSwitchToLongMode)), DXE will switch to 64 bits. // - if ((sizeof(UINTN) == sizeof(UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) { - CommBuffer = &Header64; + if ((sizeof (UINTN) == sizeof (UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) { + CommBuffer = &Header64; Header64.MessageLength = 0; - CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data); + CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data); } else { - CommBuffer = &Header32; + CommBuffer = &Header32; Header32.MessageLength = 0; - CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data); + CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data); } + CopyGuid (CommBuffer, HandlerType); Status = PeiServicesLocatePpi ( @@ -390,8 +413,8 @@ SignalToSmmByCommunication ( VOID EFIAPI S3ResumeBootOs ( - IN ACPI_S3_CONTEXT *AcpiS3Context, - IN PEI_S3_RESUME_STATE *PeiS3ResumeState + IN ACPI_S3_CONTEXT *AcpiS3Context, + IN PEI_S3_RESUME_STATE *PeiS3ResumeState ) { EFI_STATUS Status; @@ -436,11 +459,12 @@ S3ResumeBootOs ( // // Get ACPI Table Address // - Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)); + Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)); if ((Facs == NULL) || (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) || - ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) { + ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0))) + { // // Report Status code that no valid vector is found // @@ -449,20 +473,20 @@ S3ResumeBootOs ( (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR) ); CpuDeadLoop (); - return ; + return; } // // Install EndOfPeiPpi // - PERF_INMODULE_BEGIN("EndOfPeiPpi"); + PERF_INMODULE_BEGIN ("EndOfPeiPpi"); Status = PeiServicesInstallPpi (&mPpiListEndOfPeiTable); ASSERT_EFI_ERROR (Status); - PERF_INMODULE_END("EndOfPeiPpi"); + PERF_INMODULE_END ("EndOfPeiPpi"); - PERF_INMODULE_BEGIN("EndOfS3Resume"); + PERF_INMODULE_BEGIN ("EndOfS3Resume"); DEBUG ((DEBUG_INFO, "Signal EndOfS3Resume\n")); // @@ -482,7 +506,7 @@ S3ResumeBootOs ( // // Switch to native waking vector // - TempStackTop = (UINTN)&TempStack + sizeof(TempStack); + TempStackTop = (UINTN)&TempStack + sizeof (TempStack); DEBUG (( DEBUG_INFO, "%a() Stack Base: 0x%x, Stack Size: 0x%x\n", @@ -492,7 +516,8 @@ S3ResumeBootOs ( )); if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) && ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) && - ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) { + ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) + { // // X64 long mode waking vector // @@ -513,10 +538,10 @@ S3ResumeBootOs ( EFI_ERROR_CODE | EFI_ERROR_MAJOR, (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR) ); - DEBUG (( DEBUG_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n")); + DEBUG ((DEBUG_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n")); ASSERT (FALSE); CpuDeadLoop (); - return ; + return; } } else { // @@ -524,7 +549,7 @@ S3ResumeBootOs ( // DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n", (UINTN)Facs->XFirmwareWakingVector)); SwitchStack ( - (SWITCH_STACK_ENTRY_POINT) (UINTN) Facs->XFirmwareWakingVector, + (SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector, NULL, NULL, (VOID *)(UINTN)TempStackTop @@ -549,7 +574,7 @@ S3ResumeBootOs ( // // Never run to here // - CpuDeadLoop(); + CpuDeadLoop (); } /** @@ -561,28 +586,28 @@ S3ResumeBootOs ( **/ VOID RestoreS3PageTables ( - IN UINTN S3NvsPageTableAddress, - IN BOOLEAN Build4GPageTableOnly + IN UINTN S3NvsPageTableAddress, + IN BOOLEAN Build4GPageTableOnly ) { if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { - UINT32 RegEax; - UINT32 RegEdx; - UINT8 PhysicalAddressBits; - EFI_PHYSICAL_ADDRESS PageAddress; - UINTN IndexOfPml4Entries; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT32 NumberOfPml4EntriesNeeded; - UINT32 NumberOfPdpEntriesNeeded; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; - PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; - PAGE_TABLE_ENTRY *PageDirectoryEntry; - VOID *Hob; - BOOLEAN Page1GSupport; - PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; - UINT64 AddressEncMask; + UINT32 RegEax; + UINT32 RegEdx; + UINT8 PhysicalAddressBits; + EFI_PHYSICAL_ADDRESS PageAddress; + UINTN IndexOfPml4Entries; + UINTN IndexOfPdpEntries; + UINTN IndexOfPageDirectoryEntries; + UINT32 NumberOfPml4EntriesNeeded; + UINT32 NumberOfPdpEntriesNeeded; + PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; + PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; + PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; + PAGE_TABLE_ENTRY *PageDirectoryEntry; + VOID *Hob; + BOOLEAN Page1GSupport; + PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressEncMask; // // Make sure AddressEncMask is contained to smallest supported address field @@ -600,11 +625,11 @@ RestoreS3PageTables ( // // By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // - PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress; + PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress; S3NvsPageTableAddress += SIZE_4KB; Page1GSupport = FALSE; - if (PcdGetBool(PcdUse1GPageTable)) { + if (PcdGetBool (PcdUse1GPageTable)) { AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000001) { AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); @@ -619,12 +644,12 @@ RestoreS3PageTables ( // Hob = GetFirstHob (EFI_HOB_TYPE_CPU); if (Hob != NULL) { - PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; + PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; } else { AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >= 0x80000008) { AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits = (UINT8) RegEax; + PhysicalAddressBits = (UINT8)RegEax; } else { PhysicalAddressBits = 36; } @@ -644,17 +669,18 @@ RestoreS3PageTables ( // if (Build4GPageTableOnly) { PhysicalAddressBits = 32; - ZeroMem (PageMap, EFI_PAGES_TO_SIZE(2)); + ZeroMem (PageMap, EFI_PAGES_TO_SIZE (2)); } + // // Calculate the table entries needed. // if (PhysicalAddressBits <= 39) { NumberOfPml4EntriesNeeded = 1; - NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30)); + NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30)); } else { NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39)); - NumberOfPdpEntriesNeeded = 512; + NumberOfPdpEntriesNeeded = 512; } PageMapLevel4Entry = PageMap; @@ -665,26 +691,26 @@ RestoreS3PageTables ( // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop. // PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress; - S3NvsPageTableAddress += SIZE_4KB; + S3NvsPageTableAddress += SIZE_4KB; // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask; + PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask; PageMapLevel4Entry->Bits.ReadWrite = 1; - PageMapLevel4Entry->Bits.Present = 1; + PageMapLevel4Entry->Bits.Present = 1; if (Page1GSupport) { - PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry; + PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry; for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) { // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; + PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; PageDirectory1GEntry->Bits.ReadWrite = 1; - PageDirectory1GEntry->Bits.Present = 1; - PageDirectory1GEntry->Bits.MustBe1 = 1; + PageDirectory1GEntry->Bits.Present = 1; + PageDirectory1GEntry->Bits.MustBe1 = 1; } } else { for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) { @@ -692,34 +718,35 @@ RestoreS3PageTables ( // Each Directory Pointer entries points to a page of Page Directory entires. // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop. // - PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress; + PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress; S3NvsPageTableAddress += SIZE_4KB; // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask; + PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask; PageDirectoryPointerEntry->Bits.ReadWrite = 1; - PageDirectoryPointerEntry->Bits.Present = 1; + PageDirectoryPointerEntry->Bits.Present = 1; for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) { // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; + PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; PageDirectoryEntry->Bits.ReadWrite = 1; - PageDirectoryEntry->Bits.Present = 1; - PageDirectoryEntry->Bits.MustBe1 = 1; + PageDirectoryEntry->Bits.Present = 1; + PageDirectoryEntry->Bits.MustBe1 = 1; } } } } - return ; + + return; } else { // // If DXE is running 32-bit mode, no need to establish page table. // - return ; + return; } } @@ -739,12 +766,12 @@ S3ResumeExecuteBootScript ( IN BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable ) { - EFI_STATUS Status; - PEI_SMM_ACCESS_PPI *SmmAccess; - UINTN Index; - VOID *GuidHob; - PEI_S3_RESUME_STATE *PeiS3ResumeState; - BOOLEAN InterruptStatus; + EFI_STATUS Status; + PEI_SMM_ACCESS_PPI *SmmAccess; + UINTN Index; + VOID *GuidHob; + PEI_S3_RESUME_STATE *PeiS3ResumeState; + BOOLEAN InterruptStatus; DEBUG ((DEBUG_INFO, "S3ResumeExecuteBootScript()\n")); @@ -767,11 +794,11 @@ S3ResumeExecuteBootScript ( SendSmiIpi (GetApicId ()); Status = PeiServicesLocatePpi ( - &gPeiSmmAccessPpiGuid, - 0, - NULL, - (VOID **) &SmmAccess - ); + &gPeiSmmAccessPpiGuid, + 0, + NULL, + (VOID **)&SmmAccess + ); if (!EFI_ERROR (Status)) { DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot script\n")); @@ -819,7 +846,7 @@ S3ResumeExecuteBootScript ( // // Prepare data for return back // - PeiS3ResumeState = AllocatePool (sizeof(*PeiS3ResumeState)); + PeiS3ResumeState = AllocatePool (sizeof (*PeiS3ResumeState)); if (PeiS3ResumeState == NULL) { REPORT_STATUS_CODE ( EFI_ERROR_CODE | EFI_ERROR_MAJOR, @@ -827,6 +854,7 @@ S3ResumeExecuteBootScript ( ); ASSERT (FALSE); } + DEBUG ((DEBUG_INFO, "PeiS3ResumeState - %x\r\n", PeiS3ResumeState)); PeiS3ResumeState->ReturnCs = 0x10; PeiS3ResumeState->ReturnEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)S3ResumeBootOs; @@ -865,7 +893,7 @@ S3ResumeExecuteBootScript ( // DEBUG ((DEBUG_INFO, "transfer control to Standalone Boot Script Executor\r\n")); SwitchStack ( - (SWITCH_STACK_ENTRY_POINT) (UINTN) EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint, + (SWITCH_STACK_ENTRY_POINT)(UINTN)EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint, (VOID *)AcpiS3Context, (VOID *)PeiS3ResumeState, (VOID *)(UINTN)(AcpiS3Context->BootScriptStackBase + AcpiS3Context->BootScriptStackSize) @@ -875,8 +903,9 @@ S3ResumeExecuteBootScript ( // // Never run to here // - CpuDeadLoop(); + CpuDeadLoop (); } + /** Restores the platform to its preboot configuration for an S3 resume and jumps to the OS waking vector. @@ -914,32 +943,32 @@ S3RestoreConfig2 ( IN EFI_PEI_S3_RESUME2_PPI *This ) { - EFI_STATUS Status; - PEI_SMM_ACCESS_PPI *SmmAccess; - UINTN Index; - ACPI_S3_CONTEXT *AcpiS3Context; - EFI_PHYSICAL_ADDRESS TempEfiBootScriptExecutorVariable; - EFI_PHYSICAL_ADDRESS TempAcpiS3Context; - BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable; - UINTN VarSize; - EFI_SMRAM_DESCRIPTOR *SmramDescriptor; - SMM_S3_RESUME_STATE *SmmS3ResumeState; - VOID *GuidHob; - BOOLEAN Build4GPageTableOnly; - BOOLEAN InterruptStatus; - IA32_CR0 Cr0; - - TempAcpiS3Context = 0; + EFI_STATUS Status; + PEI_SMM_ACCESS_PPI *SmmAccess; + UINTN Index; + ACPI_S3_CONTEXT *AcpiS3Context; + EFI_PHYSICAL_ADDRESS TempEfiBootScriptExecutorVariable; + EFI_PHYSICAL_ADDRESS TempAcpiS3Context; + BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable; + UINTN VarSize; + EFI_SMRAM_DESCRIPTOR *SmramDescriptor; + SMM_S3_RESUME_STATE *SmmS3ResumeState; + VOID *GuidHob; + BOOLEAN Build4GPageTableOnly; + BOOLEAN InterruptStatus; + IA32_CR0 Cr0; + + TempAcpiS3Context = 0; TempEfiBootScriptExecutorVariable = 0; DEBUG ((DEBUG_INFO, "Enter S3 PEIM\r\n")); VarSize = sizeof (EFI_PHYSICAL_ADDRESS); - Status = RestoreLockBox ( - &gEfiAcpiVariableGuid, - &TempAcpiS3Context, - &VarSize - ); + Status = RestoreLockBox ( + &gEfiAcpiVariableGuid, + &TempAcpiS3Context, + &VarSize + ); ASSERT_EFI_ERROR (Status); Status = RestoreLockBox ( @@ -952,12 +981,12 @@ S3RestoreConfig2 ( AcpiS3Context = (ACPI_S3_CONTEXT *)(UINTN)TempAcpiS3Context; ASSERT (AcpiS3Context != NULL); - VarSize = sizeof (EFI_PHYSICAL_ADDRESS); - Status = RestoreLockBox ( - &gEfiBootScriptExecutorVariableGuid, - &TempEfiBootScriptExecutorVariable, - &VarSize - ); + VarSize = sizeof (EFI_PHYSICAL_ADDRESS); + Status = RestoreLockBox ( + &gEfiBootScriptExecutorVariableGuid, + &TempEfiBootScriptExecutorVariable, + &VarSize + ); ASSERT_EFI_ERROR (Status); Status = RestoreLockBox ( @@ -967,18 +996,18 @@ S3RestoreConfig2 ( ); ASSERT_EFI_ERROR (Status); - EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *) (UINTN) TempEfiBootScriptExecutorVariable; + EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)TempEfiBootScriptExecutorVariable; ASSERT (EfiBootScriptExecutorVariable != NULL); - DEBUG (( DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context)); - DEBUG (( DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase)); - DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackSize = %x\n", AcpiS3Context->BootScriptStackSize)); - DEBUG (( DEBUG_INFO, "EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = %x\n", EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint)); + DEBUG ((DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context)); + DEBUG ((DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase)); + DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackSize = %x\n", AcpiS3Context->BootScriptStackSize)); + DEBUG ((DEBUG_INFO, "EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = %x\n", EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint)); // // Additional step for BootScript integrity - we only handle BootScript and BootScriptExecutor. @@ -1001,6 +1030,7 @@ S3RestoreConfig2 ( } else { Build4GPageTableOnly = TRUE; } + RestoreS3PageTables ((UINTN)AcpiS3Context->S3NvsPageTableAddress, Build4GPageTableOnly); } @@ -1014,19 +1044,19 @@ S3RestoreConfig2 ( // assumption that it's in 32 bits mode now. // Add ASSERT code to indicate this assumption. // - ASSERT(sizeof (UINTN) == sizeof (UINT32)); + ASSERT (sizeof (UINTN) == sizeof (UINT32)); Status = PeiServicesLocatePpi ( - &gPeiSmmAccessPpiGuid, - 0, - NULL, - (VOID **) &SmmAccess - ); + &gPeiSmmAccessPpiGuid, + 0, + NULL, + (VOID **)&SmmAccess + ); for (Index = 0; !EFI_ERROR (Status); Index++) { Status = SmmAccess->Open ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index); } - SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); + SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob); SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart; SmmS3ResumeState->ReturnCs = AsmReadCs (); @@ -1035,19 +1065,19 @@ S3RestoreConfig2 ( SmmS3ResumeState->ReturnContext2 = (EFI_PHYSICAL_ADDRESS)(UINTN)EfiBootScriptExecutorVariable; SmmS3ResumeState->ReturnStackPointer = (EFI_PHYSICAL_ADDRESS)STACK_ALIGN_DOWN (&Status); - DEBUG (( DEBUG_INFO, "SMM S3 Signature = %x\n", SmmS3ResumeState->Signature)); - DEBUG (( DEBUG_INFO, "SMM S3 Stack Base = %x\n", SmmS3ResumeState->SmmS3StackBase)); - DEBUG (( DEBUG_INFO, "SMM S3 Stack Size = %x\n", SmmS3ResumeState->SmmS3StackSize)); - DEBUG (( DEBUG_INFO, "SMM S3 Resume Entry Point = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint)); - DEBUG (( DEBUG_INFO, "SMM S3 CR0 = %x\n", SmmS3ResumeState->SmmS3Cr0)); - DEBUG (( DEBUG_INFO, "SMM S3 CR3 = %x\n", SmmS3ResumeState->SmmS3Cr3)); - DEBUG (( DEBUG_INFO, "SMM S3 CR4 = %x\n", SmmS3ResumeState->SmmS3Cr4)); - DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); - DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); - DEBUG (( DEBUG_INFO, "SMM S3 Smst = %x\n", SmmS3ResumeState->Smst)); + DEBUG ((DEBUG_INFO, "SMM S3 Signature = %x\n", SmmS3ResumeState->Signature)); + DEBUG ((DEBUG_INFO, "SMM S3 Stack Base = %x\n", SmmS3ResumeState->SmmS3StackBase)); + DEBUG ((DEBUG_INFO, "SMM S3 Stack Size = %x\n", SmmS3ResumeState->SmmS3StackSize)); + DEBUG ((DEBUG_INFO, "SMM S3 Resume Entry Point = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint)); + DEBUG ((DEBUG_INFO, "SMM S3 CR0 = %x\n", SmmS3ResumeState->SmmS3Cr0)); + DEBUG ((DEBUG_INFO, "SMM S3 CR3 = %x\n", SmmS3ResumeState->SmmS3Cr3)); + DEBUG ((DEBUG_INFO, "SMM S3 CR4 = %x\n", SmmS3ResumeState->SmmS3Cr4)); + DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); + DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); + DEBUG ((DEBUG_INFO, "SMM S3 Smst = %x\n", SmmS3ResumeState->Smst)); if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) { SwitchStack ( @@ -1057,6 +1087,7 @@ S3RestoreConfig2 ( (VOID *)(UINTN)(SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize) ); } + if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) { // // Switch to long mode to complete resume. @@ -1085,6 +1116,7 @@ S3RestoreConfig2 ( Cr0.Bits.PG = 0; AsmWriteCr0 (Cr0.UintN); } + AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3); // @@ -1102,12 +1134,12 @@ S3RestoreConfig2 ( SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize ); } - } - S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable ); + S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable); return EFI_SUCCESS; } + /** Main entry for S3 Resume PEIM. @@ -1122,8 +1154,8 @@ S3RestoreConfig2 ( EFI_STATUS EFIAPI PeimS3ResumeEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices ) { EFI_STATUS Status; -- 2.39.2