From bc252e8ea4fbf56f0899c923d08bf72153b8e2eb Mon Sep 17 00:00:00 2001 From: geekboy15a Date: Tue, 2 Feb 2010 17:56:00 +0000 Subject: [PATCH] Adding files from OvmfPkg to common location. This is so multiple packages can use pre-built reset vector code. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9911 6f19259b-4bc3-4df7-8a09-765794883524 --- .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 0 -> 500 bytes .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 0 -> 484 bytes .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 0 -> 884 bytes .../ResetVector/Vtf0/Bin/ResetVector.inf | 35 ++++ .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 0 -> 28676 bytes .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 0 -> 28676 bytes .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 0 -> 28676 bytes UefiCpuPkg/ResetVector/Vtf0/Build.py | 53 +++++ UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc | 31 +++ UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm | 26 +++ .../ResetVector/Vtf0/Ia16/16RealTo32Flat.asm | 133 ++++++++++++ UefiCpuPkg/ResetVector/Vtf0/Ia16/Init16.asm | 48 +++++ .../ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 57 +++++ .../ResetVector/Vtf0/Ia32/32FlatTo64Flat.asm | 46 ++++ .../Vtf0/Ia32/SearchForBfvBase.asm | 86 ++++++++ .../Vtf0/Ia32/SearchForSecEntry.asm | 196 ++++++++++++++++++ UefiCpuPkg/ResetVector/Vtf0/Main.asm | 106 ++++++++++ UefiCpuPkg/ResetVector/Vtf0/Makefile | 42 ++++ UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm | 28 +++ UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc | 25 +++ .../ResetVector/Vtf0/ResetVectorCode.asm | 52 +++++ UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm | 132 ++++++++++++ .../Vtf0/Tools/FixupForRawSection.py | 110 ++++++++++ 23 files changed, 1206 insertions(+) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.port80.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.serial.raw create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Build.py create mode 100644 UefiCpuPkg/ResetVector/Vtf0/CommonMacros.inc create mode 100644 UefiCpuPkg/ResetVector/Vtf0/DebugDisabled.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia16/16RealTo32Flat.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia16/Init16.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/32FlatTo64Flat.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Main.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Makefile create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc create mode 100644 UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw new file mode 100644 index 0000000000000000000000000000000000000000..3a8a46d17265364917572a83248743cf60d1c301 GIT binary patch literal 500 zcmX9*%}X0W6o2cw+XN3A{7NVuB+Wq&O4B0vmEs3V4~jVy35o?TTfA;}V2?Y{9LC5J z(2MP*f5P_Uf`@Dyzj{(ALP|bu`AZl@~eYVRiEZEvc~nXtZRHyS}@j!;t#n@^sdrnH1abM`Wq`DbZpe5pGK2@ zzGb$_B*Z(AnRQ8s9q~ORBwY3@dq43bBiYg?uqHahY#`qx*&p0kSI zQ=f`I^GkeEnh~*zMn~qBNkA=TK1&Evi_4^4o(w9zm{p4_fxasLh#^g-r*O!iJlV?? z#10sVGf?KOrDu@A1m7??d@Z+6!oGAD74P1^*`a+=~!=7cW*9*S?HbdlU0D O78j;L4SDuCcSR4P&xrO!xEkXg5G&p&K}$w2)fy!XBQ?|a|(|L<9rWfiw@ z;jUNwi3`XpHgSRT{FQc(9>XN}wB zwXSvN%6+fMny#fF8Ic!88E2Ekp%Z}Q;x_*BIH~@Sef}9Qi2FmhGlV-ly98mZ&@IN8 zu@c-JW|Km@_p{OKZ3sy<NjaZlAYWqnRNjEO)WKxWP%f>EK*AVG4B=eZ4%4hob*g8pq+-T6Die^{L5 zd}Zn#J^>O3E3>!eG#pcp zTtZ*X+LFai$s!k*?Gw-svB!}=p8;_(WRFBZKut@4T zqiK+B#nB@;10KR&_+I>gIw5p#b$5KYic0B>d#H3d;|j8|Oe-z8H1s>82N_*&F-D(k a!{w~APnKKTCGt5YZ;T^RaF>5``{OTLqqwX9 literal 0 HcmV?d00001 diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf new file mode 100644 index 0000000000..a1a0e78cb1 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf @@ -0,0 +1,35 @@ +#/** @file +# Reset Vector binary +# +# Copyright (c) 2006 - 2009, Intel Corporation. +# +# All rights reserved. This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ResetVector + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.1 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Binaries.Ia32] + RAW|ResetVector.ia32.raw|* + +[Binaries.X64] + RAW|ResetVector.x64.raw|* + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.port80.raw b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.x64.port80.raw new file mode 100644 index 0000000000000000000000000000000000000000..487d815670e1d693df6736e6a746a08830345932 GIT binary patch literal 28676 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*)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + + ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize); + add eax, [ebx + 0x8] + add eax, 0x28 + movzx ebx, word [ebx + 0x6] + sub eax, ebx + jmp getEntryPointOfFfsFileReturn + +thereIsNoVzSignature: + + ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) + cmp dword [ebx], `PE\x00\x00` + jne getEntryPointOfFfsFileErrorReturn + + ; *EntryPoint = (VOID *)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff)); + add eax, [ebx + 0x4 + 0x14 + 0x10] + jmp getEntryPointOfFfsFileReturn + +getEntryPointOfFfsFileErrorReturn: + mov eax, 0 + +getEntryPointOfFfsFileReturn: + OneTimeCallRet GetEntryPointOfFfsFile + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Main.asm b/UefiCpuPkg/ResetVector/Vtf0/Main.asm new file mode 100644 index 0000000000..bc2a3b168a --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Main.asm @@ -0,0 +1,106 @@ +;------------------------------------------------------------------------------ +; @file +; Main routine of the pre-SEC code up through the jump into SEC +; +; Copyright (c) 2008 - 2009, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + +BITS 16 + +; +; Modified: EBX, ECX, EDX, EBP +; +; @param[in,out] RAX/EAX Initial value of the EAX register +; (BIST: Built-in Self Test) +; @param[in,out] DI 'BP': boot-strap processor, or +; 'AP': application processor +; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV) +; +; @return None This routine jumps to SEC and does not return +; +Main16: + OneTimeCall EarlyInit16 + + ; + ; Transition the processor from 16-bit real mode to 32-bit flat mode + ; + OneTimeCall TransitionFromReal16To32BitFlat + +BITS 32 + + ; + ; Search for the Boot Firmware Volume (BFV) + ; + OneTimeCall Flat32SearchForBfvBase + + ; + ; EBP - Start of BFV + ; + + ; + ; Search for the SEC entry point + ; + OneTimeCall Flat32SearchForSecEntryPoint + + ; + ; ESI - SEC Core entry point + ; EBP - Start of BFV + ; + +%ifdef ARCH_IA32 + + ; + ; Restore initial EAX value into the EAX register + ; + mov eax, esp + + ; + ; Jump to the 32-bit SEC entry point + ; + jmp esi + +%else + + ; + ; Transition the processor from 32-bit flat mode to 64-bit flat mode + ; + OneTimeCall Transition32FlatTo64Flat + +BITS 64 + + ; + ; Some values were calculated in 32-bit mode. Make sure the upper + ; 32-bits of 64-bit registers are zero for these values. + ; + mov rax, 0x00000000ffffffff + and rsi, rax + and rbp, rax + and rsp, rax + + ; + ; RSI - SEC Core entry point + ; RBP - Start of BFV + ; + + ; + ; Restore initial EAX value into the RAX register + ; + mov rax, rsp + + ; + ; Jump to the 64-bit SEC entry point + ; + jmp rsi + +%endif + + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Makefile b/UefiCpuPkg/ResetVector/Vtf0/Makefile new file mode 100644 index 0000000000..a4c3f789d1 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Makefile @@ -0,0 +1,42 @@ +## @file +# Makefile to create FFS Raw sections for VTF images. +# +# Copyright (c) 2008, Intel Corporation +# +# All rights reserved. This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +TARGETS = Bin/ResetVector.ia32.raw Bin/ResetVector.x64.raw +ASM = nasm + +COMMON_DEPS = \ + Ia16/16RealTo32Flat.asm \ + Ia32/32FlatTo64Flat.asm \ + JumpToSec.asm \ + Ia16/ResetVectorVtf0.asm \ + Ia32/SearchForBfvBase.asm \ + Ia32/SearchForSecAndPeiEntries.asm \ + SerialDebug.asm \ + Makefile \ + Tools/FixupForRawSection.py + +.PHONY: all +all: $(TARGETS) + +Bin/ResetVector.ia32.raw: $(COMMON_DEPS) ResetVectorCode.asm + nasm -D ARCH_IA32 -o $@ ResetVectorCode.asm + python Tools/FixupForRawSection.py $@ + +Bin/ResetVector.x64.raw: $(COMMON_DEPS) ResetVectorCode.asm + nasm -D ARCH_X64 -o $@ ResetVectorCode.asm + python Tools/FixupForRawSection.py $@ + +clean: + -rm $(TARGETS) + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm b/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm new file mode 100644 index 0000000000..2f9d0862e8 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Port80Debug.asm @@ -0,0 +1,28 @@ +;------------------------------------------------------------------------------ +; @file +; Port 0x80 debug support macros +; +; Copyright (c) 2009, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 + mov al, %1 + out 0x80, al +%endmacro + diff --git a/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc b/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc new file mode 100644 index 0000000000..2556aed873 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc @@ -0,0 +1,25 @@ +;------------------------------------------------------------------------------ +; @file +; Definitions of POST CODES for the reset vector module +; +; Copyright (c) 2009, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +%define POSTCODE_16BIT_MODE 0x16 +%define POSTCODE_32BIT_MODE 0x32 +%define POSTCODE_64BIT_MODE 0x64 + +%define POSTCODE_BFV_NOT_FOUND 0xb0 +%define POSTCODE_BFV_FOUND 0xb1 + +%define POSTCODE_SEC_NOT_FOUND 0xf0 +%define POSTCODE_SEC_FOUND 0xf1 + diff --git a/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm b/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm new file mode 100644 index 0000000000..8b13942304 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm @@ -0,0 +1,52 @@ +;------------------------------------------------------------------------------ +; @file +; This file includes all other code files to assemble the reset vector code +; +; Copyright (c) 2008 - 2009, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +%ifdef ARCH_IA32 + %ifdef ARCH_X64 + %error "Only one of ARCH_IA32 or ARCH_X64 can be defined." + %endif +%elifdef ARCH_X64 +%else + %error "Either ARCH_IA32 or ARCH_X64 must be defined." +%endif + +%include "CommonMacros.inc" + +%include "PostCodes.inc" + +%ifdef DEBUG_NONE + %include "DebugDisabled.asm" +%elifdef DEBUG_PORT80 + %include "Port80Debug.asm" +%elifdef DEBUG_SERIAL + %include "SerialDebug.asm" +%else + %error "No debug type was specified." +%endif + +%include "Ia32/SearchForBfvBase.asm" +%include "Ia32/SearchForSecEntry.asm" + +%ifdef ARCH_X64 +%include "Ia32/32FlatTo64Flat.asm" +%endif + +%include "Ia16/16RealTo32Flat.asm" +%include "Ia16/Init16.asm" + +%include "Main.asm" + +%include "Ia16/ResetVectorVtf0.asm" + diff --git a/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm b/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm new file mode 100644 index 0000000000..8c2ffc66d3 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm @@ -0,0 +1,132 @@ +;------------------------------------------------------------------------------ +; @file +; Serial port debug support macros +; +; Copyright (c) 2008 - 2009, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +;//--------------------------------------------- +;// UART Register Offsets +;//--------------------------------------------- +%define BAUD_LOW_OFFSET 0x00 +%define BAUD_HIGH_OFFSET 0x01 +%define IER_OFFSET 0x01 +%define LCR_SHADOW_OFFSET 0x01 +%define FCR_SHADOW_OFFSET 0x02 +%define IR_CONTROL_OFFSET 0x02 +%define FCR_OFFSET 0x02 +%define EIR_OFFSET 0x02 +%define BSR_OFFSET 0x03 +%define LCR_OFFSET 0x03 +%define MCR_OFFSET 0x04 +%define LSR_OFFSET 0x05 +%define MSR_OFFSET 0x06 + +;//--------------------------------------------- +;// UART Register Bit Defines +;//--------------------------------------------- +%define LSR_TXRDY 0x20 +%define LSR_RXDA 0x01 +%define DLAB 0x01 + +; UINT16 gComBase = 0x3f8; +; UINTN gBps = 115200; +; UINT8 gData = 8; +; UINT8 gStop = 1; +; UINT8 gParity = 0; +; UINT8 gBreakSet = 0; + +%define DEFAULT_COM_BASE 0x3f8 +%define DEFAULT_BPS 115200 +%define DEFAULT_DATA 8 +%define DEFAULT_STOP 1 +%define DEFAULT_PARITY 0 +%define DEFAULT_BREAK_SET 0 + +%define SERIAL_DEFAULT_LCR ( \ + (DEFAULT_BREAK_SET << 6) | \ + (DEFAULT_PARITY << 3) | \ + (DEFAULT_STOP << 2) | \ + (DEFAULT_DATA - 5) \ + ) + +%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE + +%macro inFromSerialPort 1 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + in al, dx +%endmacro + +%macro waitForSerialTxReady 0 + +%%waitingForTx: + inFromSerialPort LSR_OFFSET + test al, LSR_TXRDY + jz %%waitingForTx + +%endmacro + +%macro outToSerialPort 2 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + mov al, %2 + out dx, al +%endmacro + +%macro debugShowCharacter 1 + waitForSerialTxReady + outToSerialPort 0, %1 +%endmacro + +%macro debugShowHexDigit 1 + %if (%1 < 0xa) + debugShowCharacter BYTE ('0' + (%1)) + %else + debugShowCharacter BYTE ('a' + ((%1) - 0xa)) + %endif +%endmacro + +%macro debugNewline 0 + debugShowCharacter `\r` + debugShowCharacter `\n` +%endmacro + +%macro debugShowPostCode 1 + debugShowHexDigit (((%1) >> 4) & 0xf) + debugShowHexDigit ((%1) & 0xf) + debugNewline +%endmacro + +BITS 16 + +%macro debugInitialize 0 + jmp real16InitDebug +real16InitDebugReturn: +%endmacro + +real16InitDebug: + ; + ; Set communications format + ; + outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR) + + ; + ; Configure baud rate + ; + outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8) + outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff) + + ; + ; Switch back to bank 0 + ; + outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR + + jmp real16InitDebugReturn + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py new file mode 100644 index 0000000000..a4c3799640 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py @@ -0,0 +1,110 @@ +## @file +# Apply fixup to VTF binary image for FFS Raw section +# +# Copyright (c) 2008, Intel Corporation +# +# All rights reserved. This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +import sys + +filename = sys.argv[1] + +if filename.lower().find('ia32') >= 0: + d = open(sys.argv[1], 'rb').read() + c = ((len(d) + 4 + 7) & ~7) - 4 + if c > len(d): + c -= len(d) + f = open(sys.argv[1], 'wb') + f.write('\x90' * c) + f.write(d) + f.close() +else: + from struct import pack + + PAGE_PRESENT = 0x01 + PAGE_READ_WRITE = 0x02 + PAGE_USER_SUPERVISOR = 0x04 + PAGE_WRITE_THROUGH = 0x08 + PAGE_CACHE_DISABLE = 0x010 + PAGE_ACCESSED = 0x020 + PAGE_DIRTY = 0x040 + PAGE_PAT = 0x080 + PAGE_GLOBAL = 0x0100 + PAGE_2M_MBO = 0x080 + PAGE_2M_PAT = 0x01000 + + def NopAlign4k(s): + c = ((len(s) + 0xfff) & ~0xfff) - len(s) + return ('\x90' * c) + s + + def PageDirectoryEntries4GbOf2MbPages(baseAddress): + + s = '' + for i in range(0x800): + i = ( + baseAddress + long(i << 21) + + PAGE_2M_MBO + + PAGE_CACHE_DISABLE + + PAGE_ACCESSED + + PAGE_DIRTY + + PAGE_READ_WRITE + + PAGE_PRESENT + ) + s += pack('Q', i) + return s + + def PageDirectoryPointerTable4GbOf2MbPages(pdeBase): + s = '' + for i in range(0x200): + i = ( + pdeBase + + (min(i, 3) << 12) + + PAGE_CACHE_DISABLE + + PAGE_ACCESSED + + PAGE_READ_WRITE + + PAGE_PRESENT + ) + s += pack('Q', i) + return s + + def PageMapLevel4Table4GbOf2MbPages(pdptBase): + s = '' + for i in range(0x200): + i = ( + pdptBase + + (min(i, 0) << 12) + + PAGE_CACHE_DISABLE + + PAGE_ACCESSED + + PAGE_READ_WRITE + + PAGE_PRESENT + ) + s += pack('Q', i) + return s + + def First4GbPageEntries(topAddress): + PDE = PageDirectoryEntries4GbOf2MbPages(0L) + pml4tBase = topAddress - 0x1000 + pdptBase = pml4tBase - 0x1000 + pdeBase = pdptBase - len(PDE) + PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase) + PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase) + return PDE + PDPT + PML4T + + def AlignAndAddPageTables(): + d = open(sys.argv[1], 'rb').read() + code = NopAlign4k(d) + topAddress = 0x100000000 - len(code) + d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code + f = open(sys.argv[1], 'wb') + f.write(d) + f.close() + + AlignAndAddPageTables() + -- 2.39.2