From 16b918bbaf51211a32ae04d9d8a5ba6ccca25a6a Mon Sep 17 00:00:00 2001 From: Jian J Wang Date: Thu, 9 Aug 2018 16:17:19 +0800 Subject: [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler Once the #PF handler has set the page to be 'present', there should be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used for this purpose. 'TF' bit will be set in interrupted function context so that it can be triggered once the cpu control returns back to the instruction causing #PF and re-execute it. This is an necessary step to implement non-stop mode for Heap Guard and NULL Pointer Detection feature. Cc: Eric Dong Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Eric Dong Acked-by: Laszlo Ersek --- .../CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 7 +++++++ .../CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 4 +--- .../CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 4 ++++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 45d6474091..6fcf5fb23f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm @@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack: pop dword [ebp - 4] mov esp, ebp pop ebp + +; Enable TF bit after page fault handler runs + cmp dword [esp], 14 ; #PF? + jne .5 + bts dword [esp + 16], 8 ; EFLAGS + +.5: add esp, 8 cmp dword [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler jz DoReturn diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index 62bcedea1a..7aac29c7e7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm @@ -355,10 +355,8 @@ o16 mov [ecx + IA32_TSS._SS], ax movzx ebx, word [ecx + IA32_TSS._CS] mov [eax - 0x8], ebx ; create CS in old stack mov ebx, dword [ecx + IA32_TSS.EFLAGS] - bts ebx, 8 + bts ebx, 8 ; Set TF mov [eax - 0x4], ebx ; create eflags in old stack - mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS - mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer sub eax, 0xc ; minus 12 byte mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 7b97810d10..f842af2336 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -336,6 +336,10 @@ HasErrorCode: pop r15 mov rsp, rbp + cmp qword [rbp + 8], 14 ; #PF? + jne .1 + bts qword [rsp + 40], 8 ; RFLAGS.TF +.1: pop rbp add rsp, 16 cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler -- 2.39.2