From 1fd376d979221e9765dbec215916f5a6ab92879f Mon Sep 17 00:00:00 2001 From: jljusten Date: Fri, 1 Jun 2012 17:07:00 +0000 Subject: [PATCH] PcAtChipsetPkg/PciHostBridgeDxe: Improve KVM FIFO I/O read/write performance KVM can substantially boost the speed of the rep insb/insw/insl and rep outsb/outsw/outsl instructions by transferring up to a page of data per VM trap. This change adds assembly handling of the PCI Host Bridge I/O FIFO Reads and Writes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen Reviewed-by: Ruiyu Ni git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13424 6f19259b-4bc3-4df7-8a09-765794883524 --- PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.S | 133 +++++++++++++ .../PciHostBridgeDxe/Ia32/IoFifo.asm | 139 ++++++++++++++ PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h | 175 ++++++++++++++++++ .../PciHostBridgeDxe/PciHostBridgeDxe.inf | 8 + .../PciHostBridgeDxe/PciRootBridgeIo.c | 46 +++++ PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.S | 121 ++++++++++++ .../PciHostBridgeDxe/X64/IoFifo.asm | 125 +++++++++++++ 7 files changed, 747 insertions(+) create mode 100644 PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.S create mode 100644 PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.asm create mode 100644 PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h create mode 100644 PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.S create mode 100644 PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.asm diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.S b/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.S new file mode 100644 index 0000000000..6b9c0966ba --- /dev/null +++ b/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.S @@ -0,0 +1,133 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo8 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo8) +ASM_PFX(IoReadFifo8): + push %edi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %edi +rep insb + pop %edi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo16 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo16) +ASM_PFX(IoReadFifo16): + push %edi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %edi +rep insw + pop %edi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo32 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo32) +ASM_PFX(IoReadFifo32): + push %edi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %edi +rep insl + pop %edi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo8 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo8) +ASM_PFX(IoWriteFifo8): + push %esi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %esi +rep outsb + pop %esi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo16 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo16) +ASM_PFX(IoWriteFifo16): + push %esi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %esi +rep outsw + pop %esi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo32 ( +# IN UINTN Port, +# IN UINTN Count, +# IN VOID *Buffer +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo32) +ASM_PFX(IoWriteFifo32): + push %esi + cld + movw 8(%esp), %dx + mov 12(%esp), %ecx + mov 16(%esp), %esi +rep outsl + pop %esi + ret + diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.asm b/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.asm new file mode 100644 index 0000000000..4b147cbeb9 --- /dev/null +++ b/PcAtChipsetPkg/PciHostBridgeDxe/Ia32/IoFifo.asm @@ -0,0 +1,139 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + .586P + .model flat,C + .code + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo8 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoReadFifo8 PROC + push edi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov edi, [esp + 16] +rep insb + pop edi + ret +IoReadFifo8 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo16 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoReadFifo16 PROC + push edi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov edi, [esp + 16] +rep insw + pop edi + ret +IoReadFifo16 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo32 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoReadFifo32 PROC + push edi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov edi, [esp + 16] +rep insd + pop edi + ret +IoReadFifo32 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo8 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoWriteFifo8 PROC + push esi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov esi, [esp + 16] +rep outsb + pop esi + ret +IoWriteFifo8 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo16 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoWriteFifo16 PROC + push esi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov esi, [esp + 16] +rep outsw + pop esi + ret +IoWriteFifo16 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo32 ( +; IN UINTN Port, +; IN UINTN Size, +; IN VOID *Buffer +; ); +;------------------------------------------------------------------------------ +IoWriteFifo32 PROC + push esi + cld + mov dx, [esp + 8] + mov ecx, [esp + 12] + mov esi, [esp + 16] +rep outsd + pop esi + ret +IoWriteFifo32 ENDP + + END + diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h b/PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h new file mode 100644 index 0000000000..c4eb2081a9 --- /dev/null +++ b/PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h @@ -0,0 +1,175 @@ +/** @file + I/O FIFO routines + + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IO_FIFO_H_INCLUDED_ +#define _IO_FIFO_H_INCLUDED_ + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +#endif + diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf index c5fe0fa61a..ca136a0020 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf @@ -43,6 +43,14 @@ PciRootBridgeIo.c PciHostBridge.h +[Sources.IA32] + Ia32/IoFifo.asm + Ia32/IoFifo.S + +[Sources.X64] + X64/IoFifo.asm + X64/IoFifo.S + [Protocols] gEfiPciHostBridgeResourceAllocationProtocolGuid gEfiPciRootBridgeIoProtocolGuid diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c index 512a5049c1..b4da52eefe 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -13,6 +13,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ #include "PciHostBridge.h" +#include "IoFifo.h" typedef struct { EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax]; @@ -994,6 +995,51 @@ RootBridgeIoIoRW ( InStride = mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + if (InStride == 0) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoWriteFifo8 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint16: + IoWriteFifo16 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint32: + IoWriteFifo32 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoReadFifo8 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint16: + IoReadFifo16 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint32: + IoReadFifo32 ((UINTN) Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } +#endif + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (Write) { switch (OperationWidth) { diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.S b/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.S new file mode 100644 index 0000000000..ca484f5610 --- /dev/null +++ b/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.S @@ -0,0 +1,121 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo8 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo8) +ASM_PFX(IoReadFifo8): + cld + xchg %rcx, %rdx + xchg %r8, %rdi # rdi: buffer address; r8: save register +rep insb + mov %r8, %rdi # restore rdi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo16 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo16) +ASM_PFX(IoReadFifo16): + cld + xchg %rcx, %rdx + xchg %r8, %rdi # rdi: buffer address; r8: save register +rep insw + mov %r8, %rdi # restore rdi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoReadFifo32 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoReadFifo32) +ASM_PFX(IoReadFifo32): + cld + xchg %rcx, %rdx + xchg %r8, %rdi # rdi: buffer address; r8: save register +rep insl + mov %r8, %rdi # restore rdi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo8 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo8) +ASM_PFX(IoWriteFifo8): + cld + xchg %rcx, %rdx + xchg %r8, %rsi # rsi: buffer address; r8: save register +rep outsb + mov %r8, %rsi # restore rsi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo16 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo16) +ASM_PFX(IoWriteFifo16): + cld + xchg %rcx, %rdx + xchg %r8, %rsi # rsi: buffer address; r8: save register +rep outsw + mov %r8, %rsi # restore rsi + ret + +#------------------------------------------------------------------------------ +# VOID +# EFIAPI +# IoWriteFifo32 ( +# IN UINTN Port, // rcx +# IN UINTN Count, // rdx +# IN VOID *Buffer // r8 +# ); +#------------------------------------------------------------------------------ +ASM_GLOBAL ASM_PFX(IoWriteFifo32) +ASM_PFX(IoWriteFifo32): + cld + xchg %rcx, %rdx + xchg %r8, %rsi # rsi: buffer address; r8: save register +rep outsl + mov %r8, %rsi # restore rsi + ret + diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.asm b/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.asm new file mode 100644 index 0000000000..d16f0249d7 --- /dev/null +++ b/PcAtChipsetPkg/PciHostBridgeDxe/X64/IoFifo.asm @@ -0,0 +1,125 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + .code + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo8 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoReadFifo8 PROC + cld + xchg rcx, rdx + xchg rdi, r8 ; rdi: buffer address; r8: save rdi +rep insb + mov rdi, r8 ; restore rdi + ret +IoReadFifo8 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo16 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoReadFifo16 PROC + cld + xchg rcx, rdx + xchg rdi, r8 ; rdi: buffer address; r8: save rdi +rep insw + mov rdi, r8 ; restore rdi + ret +IoReadFifo16 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoReadFifo32 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoReadFifo32 PROC + cld + xchg rcx, rdx + xchg rdi, r8 ; rdi: buffer address; r8: save rdi +rep insd + mov rdi, r8 ; restore rdi + ret +IoReadFifo32 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo8 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoWriteFifo8 PROC + cld + xchg rcx, rdx + xchg rsi, r8 ; rsi: buffer address; r8: save rsi +rep outsb + mov rsi, r8 ; restore rsi + ret +IoWriteFifo8 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo16 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoWriteFifo16 PROC + cld + xchg rcx, rdx + xchg rsi, r8 ; rsi: buffer address; r8: save rsi +rep outsw + mov rsi, r8 ; restore rsi + ret +IoWriteFifo16 ENDP + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; IoWriteFifo32 ( +; IN UINTN Port, // rcx +; IN UINTN Size, // rdx +; IN VOID *Buffer // r8 +; ); +;------------------------------------------------------------------------------ +IoWriteFifo32 PROC + cld + xchg rcx, rdx + xchg rsi, r8 ; rsi: buffer address; r8: save rsi +rep outsd + mov rsi, r8 ; restore rsi + ret +IoWriteFifo32 ENDP + + END + -- 2.39.2