From 22327b5a1b8bedc2625689275bd483a7ca454180 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Mon, 30 May 2016 18:51:59 -0700 Subject: [PATCH] MdePkg BaseLib: Convert Ia32/EnableCache.asm to NASM The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/EnableCache.asm to Ia32/EnableCache.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen --- MdePkg/Library/BaseLib/BaseLib.inf | 2 + MdePkg/Library/BaseLib/Ia32/EnableCache.nasm | 42 ++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/EnableCache.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3062b8bbe9..61b49a68c8 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -344,6 +344,7 @@ Ia32/Thunk16.asm | INTEL Ia32/EnablePaging64.nasm| INTEL Ia32/EnablePaging64.asm | INTEL + Ia32/EnableCache.nasm| INTEL Ia32/EnableCache.asm | INTEL Ia32/DisableCache.asm | INTEL Ia32/RdRand.nasm| INTEL @@ -395,6 +396,7 @@ Ia32/RShiftU64.S | GCC Ia32/LShiftU64.nasm| GCC Ia32/LShiftU64.S | GCC + Ia32/EnableCache.nasm| GCC Ia32/EnableCache.S | GCC Ia32/DisableCache.S | GCC Ia32/RdRand.nasm| GCC diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm b/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm new file mode 100644 index 0000000000..de61a05e19 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm @@ -0,0 +1,42 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; EnableCache.Asm +; +; Abstract: +; +; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear +; the NW bit of CR0 to 0 +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmEnableCache ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmEnableCache) +ASM_PFX(AsmEnableCache): + wbinvd + mov eax, cr0 + btr eax, 29 + btr eax, 30 + mov cr0, eax + ret + -- 2.39.2