From 2af2988f3a0268b02d87a97d5b6d7b65b17c0b03 Mon Sep 17 00:00:00 2001 From: Jian J Wang Date: Thu, 23 Aug 2018 15:58:31 +0800 Subject: [PATCH] MdeModulePkg/DxeIpl: disable paging before creating new page table PEI Stack Guard needs to enable paging before DxeIpl. This might cause #GP in the transition from 32-bit PEI to 64-bit DXE due to the code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. There's no such issue for 64-bit PEI so this change applies only to 32-bit code. Cc: Star Zeng Cc: Ruiyu Ni Cc: Jiewen Yao Cc: "Ware, Ryan R" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Regression-tested-by: Laszlo Ersek Reviewed-by: Eric Dong --- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 8a939b6c24..d28baa3615 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -325,6 +325,11 @@ HandOffToDxeCore ( PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid); ASSERT_EFI_ERROR (Status); + // + // Paging might be already enabled. To avoid conflict configuration, + // disable paging first anyway. + // + AsmWriteCr0 (AsmReadCr0 () & (~BIT31)); AsmWriteCr3 (PageTables); // @@ -445,6 +450,11 @@ HandOffToDxeCore ( ASSERT_EFI_ERROR (Status); if (BuildPageTablesIa32Pae) { + // + // Paging might be already enabled. To avoid conflict configuration, + // disable paging first anyway. + // + AsmWriteCr0 (AsmReadCr0 () & (~BIT31)); AsmWriteCr3 (PageTables); // // Set Physical Address Extension (bit 5 of CR4). -- 2.39.2